LXR linux/drivers/net/ethernet/stmicro/stmmac/dwmac1000

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*******************************************************************************
   3  This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   5  developing this code.
   6
   7  This only implements the mac core functions for this chip.
   8
   9  Copyright (C) 2007-2009  STMicroelectronics Ltd
  10
  11
  12  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  13*******************************************************************************/
  14
  15#include <linux/crc32.h>
  16#include <linux/slab.h>
  17#include <linux/ethtool.h>
  18#include <net/dsa.h>
  19#include <asm/io.h>
  20#include "stmmac.h"
  21#include "stmmac_pcs.h"
  22#include "dwmac1000.h"
  23
  24static void dwmac1000_core_init(struct mac_device_info *hw,
  25                                struct net_device *dev)
  26{
  27        struct stmmac_priv *priv = netdev_priv(dev);
  28        void __iomem *ioaddr = hw->pcsr;
  29        u32 value = readl(ioaddr + GMAC_CONTROL);
  30        int mtu = dev->mtu;
  31
  32        /* Configure GMAC core */
  33        value |= GMAC_CORE_INIT;
  34
  35        /* Clear ACS bit because Ethernet switch tagging formats such as
  36         * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  37         * hardware to truncate packets on reception.
  38         */
  39        if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
  40                value &= ~GMAC_CONTROL_ACS;
  41
  42        if (mtu > 1500)
  43                value |= GMAC_CONTROL_2K;
  44        if (mtu > 2000)
  45                value |= GMAC_CONTROL_JE;
  46
  47        if (hw->ps) {
  48                value |= GMAC_CONTROL_TE;
  49
  50                value &= ~hw->link.speed_mask;
  51                switch (hw->ps) {
  52                case SPEED_1000:
  53                        value |= hw->link.speed1000;
  54                        break;
  55                case SPEED_100:
  56                        value |= hw->link.speed100;
  57                        break;
  58                case SPEED_10:
  59                        value |= hw->link.speed10;
  60                        break;
  61                }
  62        }
  63
  64        writel(value, ioaddr + GMAC_CONTROL);
  65
  66        /* Mask GMAC interrupts */
  67        value = GMAC_INT_DEFAULT_MASK;
  68
  69        if (hw->pcs)
  70                value &= ~GMAC_INT_DISABLE_PCS;
  71
  72        writel(value, ioaddr + GMAC_INT_MASK);
  73
  74#ifdef STMMAC_VLAN_TAG_USED
  75        /* Tag detection without filtering */
  76        writel(0x0, ioaddr + GMAC_VLAN_TAG);
  77#endif
  78}
  79
  80static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  81{
  82        void __iomem *ioaddr = hw->pcsr;
  83        u32 value = readl(ioaddr + GMAC_CONTROL);
  84
  85        if (hw->rx_csum)
  86                value |= GMAC_CONTROL_IPC;
  87        else
  88                value &= ~GMAC_CONTROL_IPC;
  89
  90        writel(value, ioaddr + GMAC_CONTROL);
  91
  92        value = readl(ioaddr + GMAC_CONTROL);
  93
  94        return !!(value & GMAC_CONTROL_IPC);
  95}
  96
  97static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
  98{
  99        void __iomem *ioaddr = hw->pcsr;
 100        int i;
 101
 102        for (i = 0; i < 55; i++)
 103                reg_space[i] = readl(ioaddr + i * 4);
 104}
 105
 106static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 107                                    unsigned char *addr,
 108                                    unsigned int reg_n)
 109{
 110        void __iomem *ioaddr = hw->pcsr;
 111        stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 112                            GMAC_ADDR_LOW(reg_n));
 113}
 114
 115static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
 116                                    unsigned char *addr,
 117                                    unsigned int reg_n)
 118{
 119        void __iomem *ioaddr = hw->pcsr;
 120        stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 121                            GMAC_ADDR_LOW(reg_n));
 122}
 123
 124static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 125                                 int mcbitslog2)
 126{
 127        int numhashregs, regs;
 128
 129        switch (mcbitslog2) {
 130        case 6:
 131                writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 132                writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 133                return;
 134        case 7:
 135                numhashregs = 4;
 136                break;
 137        case 8:
 138                numhashregs = 8;
 139                break;
 140        default:
 141                pr_debug("STMMAC: err in setting multicast filter\n");
 142                return;
 143        }
 144        for (regs = 0; regs < numhashregs; regs++)
 145                writel(mcfilterbits[regs],
 146                       ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 147}
 148
 149static void dwmac1000_set_filter(struct mac_device_info *hw,
 150                                 struct net_device *dev)
 151{
 152        void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 153        unsigned int value = 0;
 154        unsigned int perfect_addr_number = hw->unicast_filter_entries;
 155        u32 mc_filter[8];
 156        int mcbitslog2 = hw->mcast_bits_log2;
 157
 158        pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 159                 netdev_mc_count(dev), netdev_uc_count(dev));
 160
 161        memset(mc_filter, 0, sizeof(mc_filter));
 162
 163        if (dev->flags & IFF_PROMISC) {
 164                value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
 165        } else if (dev->flags & IFF_ALLMULTI) {
 166                value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 167        } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
 168                /* Fall back to all multicast if we've no filter */
 169                value = GMAC_FRAME_FILTER_PM;
 170        } else if (!netdev_mc_empty(dev)) {
 171                struct netdev_hw_addr *ha;
 172
 173                /* Hash filter for multicast */
 174                value = GMAC_FRAME_FILTER_HMC;
 175
 176                netdev_for_each_mc_addr(ha, dev) {
 177                        /* The upper n bits of the calculated CRC are used to
 178                         * index the contents of the hash table. The number of
 179                         * bits used depends on the hardware configuration
 180                         * selected at core configuration time.
 181                         */
 182                        int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 183                                              ETH_ALEN)) >>
 184                                              (32 - mcbitslog2);
 185                        /* The most significant bit determines the register to
 186                         * use (H/L) while the other 5 bits determine the bit
 187                         * within the register.
 188                         */
 189                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 190                }
 191        }
 192
 193        value |= GMAC_FRAME_FILTER_HPF;
 194        dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 195
 196        /* Handle multiple unicast addresses (perfect filtering) */
 197        if (netdev_uc_count(dev) > perfect_addr_number)
 198                /* Switch to promiscuous mode if more than unicast
 199                 * addresses are requested than supported by hardware.
 200                 */
 201                value |= GMAC_FRAME_FILTER_PR;
 202        else {
 203                int reg = 1;
 204                struct netdev_hw_addr *ha;
 205
 206                netdev_for_each_uc_addr(ha, dev) {
 207                        stmmac_set_mac_addr(ioaddr, ha->addr,
 208                                            GMAC_ADDR_HIGH(reg),
 209                                            GMAC_ADDR_LOW(reg));
 210                        reg++;
 211                }
 212
 213                while (reg < perfect_addr_number) {
 214                        writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 215                        writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 216                        reg++;
 217                }
 218        }
 219
 220#ifdef FRAME_FILTER_DEBUG
 221        /* Enable Receive all mode (to debug filtering_fail errors) */
 222        value |= GMAC_FRAME_FILTER_RA;
 223#endif
 224        writel(value, ioaddr + GMAC_FRAME_FILTER);
 225}
 226
 227
 228static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 229                                unsigned int fc, unsigned int pause_time,
 230                                u32 tx_cnt)
 231{
 232        void __iomem *ioaddr = hw->pcsr;
 233        /* Set flow such that DZPQ in Mac Register 6 is 0,
 234         * and unicast pause detect is enabled.
 235         */
 236        unsigned int flow = GMAC_FLOW_CTRL_UP;
 237
 238        pr_debug("GMAC Flow-Control:\n");
 239        if (fc & FLOW_RX) {
 240                pr_debug("\tReceive Flow-Control ON\n");
 241                flow |= GMAC_FLOW_CTRL_RFE;
 242        }
 243        if (fc & FLOW_TX) {
 244                pr_debug("\tTransmit Flow-Control ON\n");
 245                flow |= GMAC_FLOW_CTRL_TFE;
 246        }
 247
 248        if (duplex) {
 249                pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 250                flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 251        }
 252
 253        writel(flow, ioaddr + GMAC_FLOW_CTRL);
 254}
 255
 256static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 257{
 258        void __iomem *ioaddr = hw->pcsr;
 259        unsigned int pmt = 0;
 260
 261        if (mode & WAKE_MAGIC) {
 262                pr_debug("GMAC: WOL Magic frame\n");
 263                pmt |= power_down | magic_pkt_en;
 264        }
 265        if (mode & WAKE_UCAST) {
 266                pr_debug("GMAC: WOL on global unicast\n");
 267                pmt |= power_down | global_unicast | wake_up_frame_en;
 268        }
 269
 270        writel(pmt, ioaddr + GMAC_PMT);
 271}
 272
 273/* RGMII or SMII interface */
 274static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 275{
 276        u32 status;
 277
 278        status = readl(ioaddr + GMAC_RGSMIIIS);
 279        x->irq_rgmii_n++;
 280
 281        /* Check the link status */
 282        if (status & GMAC_RGSMIIIS_LNKSTS) {
 283                int speed_value;
 284
 285                x->pcs_link = 1;
 286
 287                speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
 288                               GMAC_RGSMIIIS_SPEED_SHIFT);
 289                if (speed_value == GMAC_RGSMIIIS_SPEED_125)
 290                        x->pcs_speed = SPEED_1000;
 291                else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
 292                        x->pcs_speed = SPEED_100;
 293                else
 294                        x->pcs_speed = SPEED_10;
 295
 296                x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
 297
 298                pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 299                        x->pcs_duplex ? "Full" : "Half");
 300        } else {
 301                x->pcs_link = 0;
 302                pr_info("Link is Down\n");
 303        }
 304}
 305
 306static int dwmac1000_irq_status(struct mac_device_info *hw,
 307                                struct stmmac_extra_stats *x)
 308{
 309        void __iomem *ioaddr = hw->pcsr;
 310        u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 311        u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
 312        int ret = 0;
 313
 314        /* Discard masked bits */
 315        intr_status &= ~intr_mask;
 316
 317        /* Not used events (e.g. MMC interrupts) are not handled. */
 318        if ((intr_status & GMAC_INT_STATUS_MMCTIS))
 319                x->mmc_tx_irq_n++;
 320        if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
 321                x->mmc_rx_irq_n++;
 322        if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
 323                x->mmc_rx_csum_offload_irq_n++;
 324        if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
 325                /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 326                readl(ioaddr + GMAC_PMT);
 327                x->irq_receive_pmt_irq_n++;
 328        }
 329
 330        /* MAC tx/rx EEE LPI entry/exit interrupts */
 331        if (intr_status & GMAC_INT_STATUS_LPIIS) {
 332                /* Clean LPI interrupt by reading the Reg 12 */
 333                ret = readl(ioaddr + LPI_CTRL_STATUS);
 334
 335                if (ret & LPI_CTRL_STATUS_TLPIEN)
 336                        x->irq_tx_path_in_lpi_mode_n++;
 337                if (ret & LPI_CTRL_STATUS_TLPIEX)
 338                        x->irq_tx_path_exit_lpi_mode_n++;
 339                if (ret & LPI_CTRL_STATUS_RLPIEN)
 340                        x->irq_rx_path_in_lpi_mode_n++;
 341                if (ret & LPI_CTRL_STATUS_RLPIEX)
 342                        x->irq_rx_path_exit_lpi_mode_n++;
 343        }
 344
 345        dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 346
 347        if (intr_status & PCS_RGSMIIIS_IRQ)
 348                dwmac1000_rgsmii(ioaddr, x);
 349
 350        return ret;
 351}
 352
 353static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
 354                                   bool en_tx_lpi_clockgating)
 355{
 356        void __iomem *ioaddr = hw->pcsr;
 357        u32 value;
 358
 359        /*TODO - en_tx_lpi_clockgating treatment */
 360
 361        /* Enable the link status receive on RGMII, SGMII ore SMII
 362         * receive path and instruct the transmit to enter in LPI
 363         * state.
 364         */
 365        value = readl(ioaddr + LPI_CTRL_STATUS);
 366        value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 367        writel(value, ioaddr + LPI_CTRL_STATUS);
 368}
 369
 370static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 371{
 372        void __iomem *ioaddr = hw->pcsr;
 373        u32 value;
 374
 375        value = readl(ioaddr + LPI_CTRL_STATUS);
 376        value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 377        writel(value, ioaddr + LPI_CTRL_STATUS);
 378}
 379
 380static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 381{
 382        void __iomem *ioaddr = hw->pcsr;
 383        u32 value;
 384
 385        value = readl(ioaddr + LPI_CTRL_STATUS);
 386
 387        if (link)
 388                value |= LPI_CTRL_STATUS_PLS;
 389        else
 390                value &= ~LPI_CTRL_STATUS_PLS;
 391
 392        writel(value, ioaddr + LPI_CTRL_STATUS);
 393}
 394
 395static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 396{
 397        void __iomem *ioaddr = hw->pcsr;
 398        int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 399
 400        /* Program the timers in the LPI timer control register:
 401         * LS: minimum time (ms) for which the link
 402         *  status from PHY should be ok before transmitting
 403         *  the LPI pattern.
 404         * TW: minimum time (us) for which the core waits
 405         *  after it has stopped transmitting the LPI pattern.
 406         */
 407        writel(value, ioaddr + LPI_TIMER_CTRL);
 408}
 409
 410static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 411                               bool loopback)
 412{
 413        dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 414}
 415
 416static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
 417{
 418        dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 419}
 420
 421static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 422{
 423        dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 424}
 425
 426static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 427                            u32 rx_queues, u32 tx_queues)
 428{
 429        u32 value = readl(ioaddr + GMAC_DEBUG);
 430
 431        if (value & GMAC_DEBUG_TXSTSFSTS)
 432                x->mtl_tx_status_fifo_full++;
 433        if (value & GMAC_DEBUG_TXFSTS)
 434                x->mtl_tx_fifo_not_empty++;
 435        if (value & GMAC_DEBUG_TWCSTS)
 436                x->mmtl_fifo_ctrl++;
 437        if (value & GMAC_DEBUG_TRCSTS_MASK) {
 438                u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
 439                             >> GMAC_DEBUG_TRCSTS_SHIFT;
 440                if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
 441                        x->mtl_tx_fifo_read_ctrl_write++;
 442                else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
 443                        x->mtl_tx_fifo_read_ctrl_wait++;
 444                else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
 445                        x->mtl_tx_fifo_read_ctrl_read++;
 446                else
 447                        x->mtl_tx_fifo_read_ctrl_idle++;
 448        }
 449        if (value & GMAC_DEBUG_TXPAUSED)
 450                x->mac_tx_in_pause++;
 451        if (value & GMAC_DEBUG_TFCSTS_MASK) {
 452                u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 453                              >> GMAC_DEBUG_TFCSTS_SHIFT;
 454
 455                if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 456                        x->mac_tx_frame_ctrl_xfer++;
 457                else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 458                        x->mac_tx_frame_ctrl_pause++;
 459                else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 460                        x->mac_tx_frame_ctrl_wait++;
 461                else
 462                        x->mac_tx_frame_ctrl_idle++;
 463        }
 464        if (value & GMAC_DEBUG_TPESTS)
 465                x->mac_gmii_tx_proto_engine++;
 466        if (value & GMAC_DEBUG_RXFSTS_MASK) {
 467                u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
 468                             >> GMAC_DEBUG_RRCSTS_SHIFT;
 469
 470                if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
 471                        x->mtl_rx_fifo_fill_level_full++;
 472                else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
 473                        x->mtl_rx_fifo_fill_above_thresh++;
 474                else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
 475                        x->mtl_rx_fifo_fill_below_thresh++;
 476                else
 477                        x->mtl_rx_fifo_fill_level_empty++;
 478        }
 479        if (value & GMAC_DEBUG_RRCSTS_MASK) {
 480                u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
 481                             GMAC_DEBUG_RRCSTS_SHIFT;
 482
 483                if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
 484                        x->mtl_rx_fifo_read_ctrl_flush++;
 485                else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
 486                        x->mtl_rx_fifo_read_ctrl_read_data++;
 487                else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
 488                        x->mtl_rx_fifo_read_ctrl_status++;
 489                else
 490                        x->mtl_rx_fifo_read_ctrl_idle++;
 491        }
 492        if (value & GMAC_DEBUG_RWCSTS)
 493                x->mtl_rx_fifo_ctrl_active++;
 494        if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 495                x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 496                                            >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 497        if (value & GMAC_DEBUG_RPESTS)
 498                x->mac_gmii_rx_proto_engine++;
 499}
 500
 501static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
 502{
 503        u32 value = readl(ioaddr + GMAC_CONTROL);
 504
 505        if (enable)
 506                value |= GMAC_CONTROL_LM;
 507        else
 508                value &= ~GMAC_CONTROL_LM;
 509
 510        writel(value, ioaddr + GMAC_CONTROL);
 511}
 512
 513const struct stmmac_ops dwmac1000_ops = {
 514        .core_init = dwmac1000_core_init,
 515        .set_mac = stmmac_set_mac,
 516        .rx_ipc = dwmac1000_rx_ipc_enable,
 517        .dump_regs = dwmac1000_dump_regs,
 518        .host_irq_status = dwmac1000_irq_status,
 519        .set_filter = dwmac1000_set_filter,
 520        .flow_ctrl = dwmac1000_flow_ctrl,
 521        .pmt = dwmac1000_pmt,
 522        .set_umac_addr = dwmac1000_set_umac_addr,
 523        .get_umac_addr = dwmac1000_get_umac_addr,
 524        .set_eee_mode = dwmac1000_set_eee_mode,
 525        .reset_eee_mode = dwmac1000_reset_eee_mode,
 526        .set_eee_timer = dwmac1000_set_eee_timer,
 527        .set_eee_pls = dwmac1000_set_eee_pls,
 528        .debug = dwmac1000_debug,
 529        .pcs_ctrl_ane = dwmac1000_ctrl_ane,
 530        .pcs_rane = dwmac1000_rane,
 531        .pcs_get_adv_lp = dwmac1000_get_adv_lp,
 532        .set_mac_loopback = dwmac1000_set_mac_loopback,
 533};
 534
 535int dwmac1000_setup(struct stmmac_priv *priv)
 536{
 537        struct mac_device_info *mac = priv->hw;
 538
 539        dev_info(priv->device, "\tDWMAC1000\n");
 540
 541        priv->dev->priv_flags |= IFF_UNICAST_FLT;
 542        mac->pcsr = priv->ioaddr;
 543        mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
 544        mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
 545        mac->mcast_bits_log2 = 0;
 546
 547        if (mac->multicast_filter_bins)
 548                mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 549
 550        mac->link.duplex = GMAC_CONTROL_DM;
 551        mac->link.speed10 = GMAC_CONTROL_PS;
 552        mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 553        mac->link.speed1000 = 0;
 554        mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 555        mac->mii.addr = GMAC_MII_ADDR;
 556        mac->mii.data = GMAC_MII_DATA;
 557        mac->mii.addr_shift = 11;
 558        mac->mii.addr_mask = 0x0000F800;
 559        mac->mii.reg_shift = 6;
 560        mac->mii.reg_mask = 0x000007C0;
 561        mac->mii.clk_csr_shift = 2;
 562        mac->mii.clk_csr_mask = GENMASK(5, 2);
 563
 564        return 0;
 565}
 566