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60
61#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
62
63#include "tehuti.h"
64
65static const struct pci_device_id bdx_pci_tbl[] = {
66 { PCI_VDEVICE(TEHUTI, 0x3009), },
67 { PCI_VDEVICE(TEHUTI, 0x3010), },
68 { PCI_VDEVICE(TEHUTI, 0x3014), },
69 { 0 }
70};
71
72MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
73
74
75static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
76static void bdx_tx_cleanup(struct bdx_priv *priv);
77static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
78
79
80static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
81
82
83static int bdx_tx_init(struct bdx_priv *priv);
84static int bdx_rx_init(struct bdx_priv *priv);
85
86
87static void bdx_rx_free(struct bdx_priv *priv);
88static void bdx_tx_free(struct bdx_priv *priv);
89
90
91static void bdx_set_ethtool_ops(struct net_device *netdev);
92
93
94
95
96
97static void print_hw_id(struct pci_dev *pdev)
98{
99 struct pci_nic *nic = pci_get_drvdata(pdev);
100 u16 pci_link_status = 0;
101 u16 pci_ctrl = 0;
102
103 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
104 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
105
106 pr_info("%s%s\n", BDX_NIC_NAME,
107 nic->port_num == 1 ? "" : ", 2-Port");
108 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
109 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
110 readl(nic->regs + FPGA_SEED),
111 GET_LINK_STATUS_LANES(pci_link_status),
112 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
113}
114
115static void print_fw_id(struct pci_nic *nic)
116{
117 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
118}
119
120static void print_eth_id(struct net_device *ndev)
121{
122 netdev_info(ndev, "%s, Port %c\n",
123 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
124
125}
126
127
128
129
130
131#define bdx_enable_interrupts(priv) \
132 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
133#define bdx_disable_interrupts(priv) \
134 do { WRITE_REG(priv, regIMR, 0); } while (0)
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152static int
153bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
154 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
155{
156 u16 memsz = FIFO_SIZE * (1 << fsz_type);
157
158 memset(f, 0, sizeof(struct fifo));
159
160 f->va = dma_alloc_coherent(&priv->pdev->dev, memsz + FIFO_EXTRA_SPACE,
161 &f->da, GFP_ATOMIC);
162 if (!f->va) {
163 pr_err("dma_alloc_coherent failed\n");
164 RET(-ENOMEM);
165 }
166 f->reg_CFG0 = reg_CFG0;
167 f->reg_CFG1 = reg_CFG1;
168 f->reg_RPTR = reg_RPTR;
169 f->reg_WPTR = reg_WPTR;
170 f->rptr = 0;
171 f->wptr = 0;
172 f->memsz = memsz;
173 f->size_mask = memsz - 1;
174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
175 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
176
177 RET(0);
178}
179
180
181
182
183
184
185static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
186{
187 ENTER;
188 if (f->va) {
189 dma_free_coherent(&priv->pdev->dev,
190 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
191 f->va = NULL;
192 }
193 RET();
194}
195
196
197
198
199
200static void bdx_link_changed(struct bdx_priv *priv)
201{
202 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
203
204 if (!link) {
205 if (netif_carrier_ok(priv->ndev)) {
206 netif_stop_queue(priv->ndev);
207 netif_carrier_off(priv->ndev);
208 netdev_err(priv->ndev, "Link Down\n");
209 }
210 } else {
211 if (!netif_carrier_ok(priv->ndev)) {
212 netif_wake_queue(priv->ndev);
213 netif_carrier_on(priv->ndev);
214 netdev_err(priv->ndev, "Link Up\n");
215 }
216 }
217}
218
219static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
220{
221 if (isr & IR_RX_FREE_0) {
222 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
223 DBG("RX_FREE_0\n");
224 }
225
226 if (isr & IR_LNKCHG0)
227 bdx_link_changed(priv);
228
229 if (isr & IR_PCIE_LINK)
230 netdev_err(priv->ndev, "PCI-E Link Fault\n");
231
232 if (isr & IR_PCIE_TOUT)
233 netdev_err(priv->ndev, "PCI-E Time Out\n");
234
235}
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251static irqreturn_t bdx_isr_napi(int irq, void *dev)
252{
253 struct net_device *ndev = dev;
254 struct bdx_priv *priv = netdev_priv(ndev);
255 u32 isr;
256
257 ENTER;
258 isr = (READ_REG(priv, regISR) & IR_RUN);
259 if (unlikely(!isr)) {
260 bdx_enable_interrupts(priv);
261 return IRQ_NONE;
262 }
263
264 if (isr & IR_EXTRA)
265 bdx_isr_extra(priv, isr);
266
267 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
268 if (likely(napi_schedule_prep(&priv->napi))) {
269 __napi_schedule(&priv->napi);
270 RET(IRQ_HANDLED);
271 } else {
272
273
274
275
276
277
278
279
280 READ_REG(priv, regTXF_WPTR_0);
281 READ_REG(priv, regRXD_WPTR_0);
282 }
283 }
284
285 bdx_enable_interrupts(priv);
286 RET(IRQ_HANDLED);
287}
288
289static int bdx_poll(struct napi_struct *napi, int budget)
290{
291 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
292 int work_done;
293
294 ENTER;
295 bdx_tx_cleanup(priv);
296 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
297 if ((work_done < budget) ||
298 (priv->napi_stop++ >= 30)) {
299 DBG("rx poll is done. backing to isr-driven\n");
300
301
302
303 priv->napi_stop = 0;
304
305 napi_complete_done(napi, work_done);
306 bdx_enable_interrupts(priv);
307 }
308 return work_done;
309}
310
311
312
313
314
315
316
317
318
319
320
321static int bdx_fw_load(struct bdx_priv *priv)
322{
323 const struct firmware *fw = NULL;
324 int master, i;
325 int rc;
326
327 ENTER;
328 master = READ_REG(priv, regINIT_SEMAPHORE);
329 if (!READ_REG(priv, regINIT_STATUS) && master) {
330 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
331 if (rc)
332 goto out;
333 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
334 mdelay(100);
335 }
336 for (i = 0; i < 200; i++) {
337 if (READ_REG(priv, regINIT_STATUS)) {
338 rc = 0;
339 goto out;
340 }
341 mdelay(2);
342 }
343 rc = -EIO;
344out:
345 if (master)
346 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
347
348 release_firmware(fw);
349
350 if (rc) {
351 netdev_err(priv->ndev, "firmware loading failed\n");
352 if (rc == -EIO)
353 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
354 READ_REG(priv, regVPC),
355 READ_REG(priv, regVIC),
356 READ_REG(priv, regINIT_STATUS), i);
357 RET(rc);
358 } else {
359 DBG("%s: firmware loading success\n", priv->ndev->name);
360 RET(0);
361 }
362}
363
364static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
365{
366 u32 val;
367
368 ENTER;
369 DBG("mac0=%x mac1=%x mac2=%x\n",
370 READ_REG(priv, regUNC_MAC0_A),
371 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
372
373 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
374 WRITE_REG(priv, regUNC_MAC2_A, val);
375 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
376 WRITE_REG(priv, regUNC_MAC1_A, val);
377 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
378 WRITE_REG(priv, regUNC_MAC0_A, val);
379
380 DBG("mac0=%x mac1=%x mac2=%x\n",
381 READ_REG(priv, regUNC_MAC0_A),
382 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
383 RET();
384}
385
386
387
388
389
390static int bdx_hw_start(struct bdx_priv *priv)
391{
392 int rc = -EIO;
393 struct net_device *ndev = priv->ndev;
394
395 ENTER;
396 bdx_link_changed(priv);
397
398
399 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
400 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
401 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
402 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
403 WRITE_REG(priv, regRX_FULLNESS, 0);
404 WRITE_REG(priv, regTX_FULLNESS, 0);
405 WRITE_REG(priv, regCTRLST,
406 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
407
408 WRITE_REG(priv, regVGLB, 0);
409 WRITE_REG(priv, regMAX_FRAME_A,
410 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
411
412 DBG("RDINTCM=%08x\n", priv->rdintcm);
413 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
414 WRITE_REG(priv, regRDINTCM2, 0);
415
416 DBG("TDINTCM=%08x\n", priv->tdintcm);
417 WRITE_REG(priv, regTDINTCM0, priv->tdintcm);
418
419
420
421 bdx_restore_mac(priv->ndev, priv);
422
423 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
424 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
425
426#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
427
428 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
429 ndev->name, ndev);
430 if (rc)
431 goto err_irq;
432 bdx_enable_interrupts(priv);
433
434 RET(0);
435
436err_irq:
437 RET(rc);
438}
439
440static void bdx_hw_stop(struct bdx_priv *priv)
441{
442 ENTER;
443 bdx_disable_interrupts(priv);
444 free_irq(priv->pdev->irq, priv->ndev);
445
446 netif_carrier_off(priv->ndev);
447 netif_stop_queue(priv->ndev);
448
449 RET();
450}
451
452static int bdx_hw_reset_direct(void __iomem *regs)
453{
454 u32 val, i;
455 ENTER;
456
457
458 val = readl(regs + regCLKPLL);
459 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
460 udelay(50);
461 val = readl(regs + regCLKPLL);
462 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
463
464
465 for (i = 0; i < 70; i++, mdelay(10))
466 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
467
468 readl(regs + regRXD_CFG0_0);
469 return 0;
470 }
471 pr_err("HW reset failed\n");
472 return 1;
473}
474
475static int bdx_hw_reset(struct bdx_priv *priv)
476{
477 u32 val, i;
478 ENTER;
479
480 if (priv->port == 0) {
481
482 val = READ_REG(priv, regCLKPLL);
483 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
484 udelay(50);
485 val = READ_REG(priv, regCLKPLL);
486 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
487 }
488
489 for (i = 0; i < 70; i++, mdelay(10))
490 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
491
492 READ_REG(priv, regRXD_CFG0_0);
493 return 0;
494 }
495 pr_err("HW reset failed\n");
496 return 1;
497}
498
499static int bdx_sw_reset(struct bdx_priv *priv)
500{
501 int i;
502
503 ENTER;
504
505
506 WRITE_REG(priv, regGMAC_RXF_A, 0);
507 mdelay(100);
508
509 WRITE_REG(priv, regDIS_PORT, 1);
510
511 WRITE_REG(priv, regDIS_QU, 1);
512
513 for (i = 0; i < 50; i++) {
514 if (READ_REG(priv, regRST_PORT) & 1)
515 break;
516 mdelay(10);
517 }
518 if (i == 50)
519 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
520
521
522 WRITE_REG(priv, regRDINTCM0, 0);
523 WRITE_REG(priv, regTDINTCM0, 0);
524 WRITE_REG(priv, regIMR, 0);
525 READ_REG(priv, regISR);
526
527
528 WRITE_REG(priv, regRST_QU, 1);
529
530 WRITE_REG(priv, regRST_PORT, 1);
531
532 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
533 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
534 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
535 WRITE_REG(priv, i, 0);
536
537 WRITE_REG(priv, regDIS_PORT, 0);
538
539 WRITE_REG(priv, regDIS_QU, 0);
540
541 WRITE_REG(priv, regRST_QU, 0);
542
543 WRITE_REG(priv, regRST_PORT, 0);
544
545
546
547 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
548 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
549
550 RET(0);
551}
552
553
554static int bdx_reset(struct bdx_priv *priv)
555{
556 ENTER;
557 RET((priv->pdev->device == 0x3009)
558 ? bdx_hw_reset(priv)
559 : bdx_sw_reset(priv));
560}
561
562
563
564
565
566
567
568
569
570
571
572
573static int bdx_close(struct net_device *ndev)
574{
575 struct bdx_priv *priv = NULL;
576
577 ENTER;
578 priv = netdev_priv(ndev);
579
580 napi_disable(&priv->napi);
581
582 bdx_reset(priv);
583 bdx_hw_stop(priv);
584 bdx_rx_free(priv);
585 bdx_tx_free(priv);
586 RET(0);
587}
588
589
590
591
592
593
594
595
596
597
598
599
600
601static int bdx_open(struct net_device *ndev)
602{
603 struct bdx_priv *priv;
604 int rc;
605
606 ENTER;
607 priv = netdev_priv(ndev);
608 bdx_reset(priv);
609 if (netif_running(ndev))
610 netif_stop_queue(priv->ndev);
611
612 if ((rc = bdx_tx_init(priv)) ||
613 (rc = bdx_rx_init(priv)) ||
614 (rc = bdx_fw_load(priv)))
615 goto err;
616
617 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
618
619 rc = bdx_hw_start(priv);
620 if (rc)
621 goto err;
622
623 napi_enable(&priv->napi);
624
625 print_fw_id(priv->nic);
626
627 RET(0);
628
629err:
630 bdx_close(ndev);
631 RET(rc);
632}
633
634static int bdx_range_check(struct bdx_priv *priv, u32 offset)
635{
636 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
637 -EINVAL : 0;
638}
639
640static int bdx_siocdevprivate(struct net_device *ndev, struct ifreq *ifr,
641 void __user *udata, int cmd)
642{
643 struct bdx_priv *priv = netdev_priv(ndev);
644 u32 data[3];
645 int error;
646
647 ENTER;
648
649 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
650 if (cmd != SIOCDEVPRIVATE) {
651 error = copy_from_user(data, udata, sizeof(data));
652 if (error) {
653 pr_err("can't copy from user\n");
654 RET(-EFAULT);
655 }
656 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
657 } else {
658 return -EOPNOTSUPP;
659 }
660
661 if (!capable(CAP_SYS_RAWIO))
662 return -EPERM;
663
664 switch (data[0]) {
665
666 case BDX_OP_READ:
667 error = bdx_range_check(priv, data[1]);
668 if (error < 0)
669 return error;
670 data[2] = READ_REG(priv, data[1]);
671 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
672 data[2]);
673 error = copy_to_user(udata, data, sizeof(data));
674 if (error)
675 RET(-EFAULT);
676 break;
677
678 case BDX_OP_WRITE:
679 error = bdx_range_check(priv, data[1]);
680 if (error < 0)
681 return error;
682 WRITE_REG(priv, data[1], data[2]);
683 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
684 break;
685
686 default:
687 RET(-EOPNOTSUPP);
688 }
689 return 0;
690}
691
692
693
694
695
696
697
698
699
700static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
701{
702 struct bdx_priv *priv = netdev_priv(ndev);
703 u32 reg, bit, val;
704
705 ENTER;
706 DBG2("vid=%d value=%d\n", (int)vid, enable);
707 if (unlikely(vid >= 4096)) {
708 pr_err("invalid VID: %u (> 4096)\n", vid);
709 RET();
710 }
711 reg = regVLAN_0 + (vid / 32) * 4;
712 bit = 1 << vid % 32;
713 val = READ_REG(priv, reg);
714 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
715 if (enable)
716 val |= bit;
717 else
718 val &= ~bit;
719 DBG2("new val %x\n", val);
720 WRITE_REG(priv, reg, val);
721 RET();
722}
723
724
725
726
727
728
729
730static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
731{
732 __bdx_vlan_rx_vid(ndev, vid, 1);
733 return 0;
734}
735
736
737
738
739
740
741
742static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
743{
744 __bdx_vlan_rx_vid(ndev, vid, 0);
745 return 0;
746}
747
748
749
750
751
752
753
754
755static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
756{
757 ENTER;
758
759 ndev->mtu = new_mtu;
760 if (netif_running(ndev)) {
761 bdx_close(ndev);
762 bdx_open(ndev);
763 }
764 RET(0);
765}
766
767static void bdx_setmulti(struct net_device *ndev)
768{
769 struct bdx_priv *priv = netdev_priv(ndev);
770
771 u32 rxf_val =
772 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
773 int i;
774
775 ENTER;
776
777
778
779
780 if (ndev->flags & IFF_PROMISC) {
781 rxf_val |= GMAC_RX_FILTER_PRM;
782 } else if (ndev->flags & IFF_ALLMULTI) {
783
784 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
785 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
786 } else if (!netdev_mc_empty(ndev)) {
787 u8 hash;
788 struct netdev_hw_addr *ha;
789 u32 reg, val;
790
791
792 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
793 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
794
795 for (i = 0; i < MAC_MCST_NUM; i++) {
796 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
797 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
798 }
799
800
801
802
803
804
805 netdev_for_each_mc_addr(ha, ndev) {
806 hash = 0;
807 for (i = 0; i < ETH_ALEN; i++)
808 hash ^= ha->addr[i];
809 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
810 val = READ_REG(priv, reg);
811 val |= (1 << (hash % 32));
812 WRITE_REG(priv, reg, val);
813 }
814
815 } else {
816 DBG("only own mac %d\n", netdev_mc_count(ndev));
817 rxf_val |= GMAC_RX_FILTER_AB;
818 }
819 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
820
821
822 RET();
823}
824
825static int bdx_set_mac(struct net_device *ndev, void *p)
826{
827 struct bdx_priv *priv = netdev_priv(ndev);
828 struct sockaddr *addr = p;
829
830 ENTER;
831
832
833
834
835 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
836 bdx_restore_mac(ndev, priv);
837 RET(0);
838}
839
840static int bdx_read_mac(struct bdx_priv *priv)
841{
842 u16 macAddress[3], i;
843 ENTER;
844
845 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
846 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
847 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
848 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
849 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
850 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
851 for (i = 0; i < 3; i++) {
852 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
853 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
854 }
855 RET(0);
856}
857
858static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
859{
860 u64 val;
861
862 val = READ_REG(priv, reg);
863 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
864 return val;
865}
866
867
868static void bdx_update_stats(struct bdx_priv *priv)
869{
870 struct bdx_stats *stats = &priv->hw_stats;
871 u64 *stats_vector = (u64 *) stats;
872 int i;
873 int addr;
874
875
876 addr = 0x7200;
877
878 for (i = 0; i < 12; i++) {
879 stats_vector[i] = bdx_read_l2stat(priv, addr);
880 addr += 0x10;
881 }
882 BDX_ASSERT(addr != 0x72C0);
883
884 addr = 0x72F0;
885 for (; i < 16; i++) {
886 stats_vector[i] = bdx_read_l2stat(priv, addr);
887 addr += 0x10;
888 }
889 BDX_ASSERT(addr != 0x7330);
890
891 addr = 0x7370;
892 for (; i < 19; i++) {
893 stats_vector[i] = bdx_read_l2stat(priv, addr);
894 addr += 0x10;
895 }
896 BDX_ASSERT(addr != 0x73A0);
897
898 addr = 0x73C0;
899 for (; i < 23; i++) {
900 stats_vector[i] = bdx_read_l2stat(priv, addr);
901 addr += 0x10;
902 }
903 BDX_ASSERT(addr != 0x7400);
904 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
905}
906
907static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
908 u16 rxd_vlan);
909static void print_rxfd(struct rxf_desc *rxfd);
910
911
912
913
914
915static void bdx_rxdb_destroy(struct rxdb *db)
916{
917 vfree(db);
918}
919
920static struct rxdb *bdx_rxdb_create(int nelem)
921{
922 struct rxdb *db;
923 int i;
924
925 db = vmalloc(sizeof(struct rxdb)
926 + (nelem * sizeof(int))
927 + (nelem * sizeof(struct rx_map)));
928 if (likely(db != NULL)) {
929 db->stack = (int *)(db + 1);
930 db->elems = (void *)(db->stack + nelem);
931 db->nelem = nelem;
932 db->top = nelem;
933 for (i = 0; i < nelem; i++)
934 db->stack[i] = nelem - i - 1;
935
936 }
937
938 return db;
939}
940
941static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
942{
943 BDX_ASSERT(db->top <= 0);
944 return db->stack[--(db->top)];
945}
946
947static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
948{
949 BDX_ASSERT((n < 0) || (n >= db->nelem));
950 return db->elems + n;
951}
952
953static inline int bdx_rxdb_available(struct rxdb *db)
954{
955 return db->top;
956}
957
958static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
959{
960 BDX_ASSERT((n >= db->nelem) || (n < 0));
961 db->stack[(db->top)++] = n;
962}
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986static int bdx_rx_init(struct bdx_priv *priv)
987{
988 ENTER;
989
990 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
991 regRXD_CFG0_0, regRXD_CFG1_0,
992 regRXD_RPTR_0, regRXD_WPTR_0))
993 goto err_mem;
994 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
995 regRXF_CFG0_0, regRXF_CFG1_0,
996 regRXF_RPTR_0, regRXF_WPTR_0))
997 goto err_mem;
998 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
999 sizeof(struct rxf_desc));
1000 if (!priv->rxdb)
1001 goto err_mem;
1002
1003 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1004 return 0;
1005
1006err_mem:
1007 netdev_err(priv->ndev, "Rx init failed\n");
1008 return -ENOMEM;
1009}
1010
1011
1012
1013
1014
1015
1016static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1017{
1018 struct rx_map *dm;
1019 struct rxdb *db = priv->rxdb;
1020 u16 i;
1021
1022 ENTER;
1023 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1024 db->nelem - bdx_rxdb_available(db));
1025 while (bdx_rxdb_available(db) > 0) {
1026 i = bdx_rxdb_alloc_elem(db);
1027 dm = bdx_rxdb_addr_elem(db, i);
1028 dm->dma = 0;
1029 }
1030 for (i = 0; i < db->nelem; i++) {
1031 dm = bdx_rxdb_addr_elem(db, i);
1032 if (dm->dma) {
1033 dma_unmap_single(&priv->pdev->dev, dm->dma,
1034 f->m.pktsz, DMA_FROM_DEVICE);
1035 dev_kfree_skb(dm->skb);
1036 }
1037 }
1038}
1039
1040
1041
1042
1043
1044
1045
1046static void bdx_rx_free(struct bdx_priv *priv)
1047{
1048 ENTER;
1049 if (priv->rxdb) {
1050 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1051 bdx_rxdb_destroy(priv->rxdb);
1052 priv->rxdb = NULL;
1053 }
1054 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1055 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1056
1057 RET();
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1078{
1079 struct sk_buff *skb;
1080 struct rxf_desc *rxfd;
1081 struct rx_map *dm;
1082 int dno, delta, idx;
1083 struct rxdb *db = priv->rxdb;
1084
1085 ENTER;
1086 dno = bdx_rxdb_available(db) - 1;
1087 while (dno > 0) {
1088 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
1089 if (!skb)
1090 break;
1091
1092 skb_reserve(skb, NET_IP_ALIGN);
1093
1094 idx = bdx_rxdb_alloc_elem(db);
1095 dm = bdx_rxdb_addr_elem(db, idx);
1096 dm->dma = dma_map_single(&priv->pdev->dev, skb->data,
1097 f->m.pktsz, DMA_FROM_DEVICE);
1098 dm->skb = skb;
1099 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1100 rxfd->info = CPU_CHIP_SWAP32(0x10003);
1101 rxfd->va_lo = idx;
1102 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1103 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1104 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1105 print_rxfd(rxfd);
1106
1107 f->m.wptr += sizeof(struct rxf_desc);
1108 delta = f->m.wptr - f->m.memsz;
1109 if (unlikely(delta >= 0)) {
1110 f->m.wptr = delta;
1111 if (delta > 0) {
1112 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1113 DBG("wrapped descriptor\n");
1114 }
1115 }
1116 dno--;
1117 }
1118
1119 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1120 RET();
1121}
1122
1123static inline void
1124NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1125 struct sk_buff *skb)
1126{
1127 ENTER;
1128 DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1129 if (GET_RXD_VTAG(rxd_val1)) {
1130 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1131 priv->ndev->name,
1132 GET_RXD_VLAN_ID(rxd_vlan),
1133 GET_RXD_VTAG(rxd_val1));
1134 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1135 }
1136 netif_receive_skb(skb);
1137}
1138
1139static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1140{
1141 struct rxf_desc *rxfd;
1142 struct rx_map *dm;
1143 struct rxf_fifo *f;
1144 struct rxdb *db;
1145 int delta;
1146
1147 ENTER;
1148 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1149 f = &priv->rxf_fifo0;
1150 db = priv->rxdb;
1151 DBG("db=%p f=%p\n", db, f);
1152 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1153 DBG("dm=%p\n", dm);
1154 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1155 rxfd->info = CPU_CHIP_SWAP32(0x10003);
1156 rxfd->va_lo = rxdd->va_lo;
1157 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1158 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1159 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1160 print_rxfd(rxfd);
1161
1162 f->m.wptr += sizeof(struct rxf_desc);
1163 delta = f->m.wptr - f->m.memsz;
1164 if (unlikely(delta >= 0)) {
1165 f->m.wptr = delta;
1166 if (delta > 0) {
1167 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1168 DBG("wrapped descriptor\n");
1169 }
1170 }
1171 RET();
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1188{
1189 struct net_device *ndev = priv->ndev;
1190 struct sk_buff *skb, *skb2;
1191 struct rxd_desc *rxdd;
1192 struct rx_map *dm;
1193 struct rxf_fifo *rxf_fifo;
1194 int tmp_len, size;
1195 int done = 0;
1196 int max_done = BDX_MAX_RX_DONE;
1197 struct rxdb *db = NULL;
1198
1199 u32 rxd_val1;
1200 u16 len;
1201 u16 rxd_vlan;
1202
1203 ENTER;
1204 max_done = budget;
1205
1206 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1207
1208 size = f->m.wptr - f->m.rptr;
1209 if (size < 0)
1210 size = f->m.memsz + size;
1211
1212 while (size > 0) {
1213
1214 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1215 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1216
1217 len = CPU_CHIP_SWAP16(rxdd->len);
1218
1219 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1220
1221 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1222
1223 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1224 BDX_ASSERT(tmp_len <= 0);
1225 size -= tmp_len;
1226 if (size < 0)
1227 break;
1228
1229 f->m.rptr += tmp_len;
1230
1231 tmp_len = f->m.rptr - f->m.memsz;
1232 if (unlikely(tmp_len >= 0)) {
1233 f->m.rptr = tmp_len;
1234 if (tmp_len > 0) {
1235 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1236 f->m.rptr, tmp_len);
1237 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1238 }
1239 }
1240
1241 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1242 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1243 ndev->stats.rx_errors++;
1244 bdx_recycle_skb(priv, rxdd);
1245 continue;
1246 }
1247
1248 rxf_fifo = &priv->rxf_fifo0;
1249 db = priv->rxdb;
1250 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1251 skb = dm->skb;
1252
1253 if (len < BDX_COPYBREAK &&
1254 (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1255 skb_reserve(skb2, NET_IP_ALIGN);
1256
1257 dma_sync_single_for_cpu(&priv->pdev->dev, dm->dma,
1258 rxf_fifo->m.pktsz,
1259 DMA_FROM_DEVICE);
1260 memcpy(skb2->data, skb->data, len);
1261 bdx_recycle_skb(priv, rxdd);
1262 skb = skb2;
1263 } else {
1264 dma_unmap_single(&priv->pdev->dev, dm->dma,
1265 rxf_fifo->m.pktsz, DMA_FROM_DEVICE);
1266 bdx_rxdb_free_elem(db, rxdd->va_lo);
1267 }
1268
1269 ndev->stats.rx_bytes += len;
1270
1271 skb_put(skb, len);
1272 skb->protocol = eth_type_trans(skb, ndev);
1273
1274
1275 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1276 skb_checksum_none_assert(skb);
1277 else
1278 skb->ip_summed = CHECKSUM_UNNECESSARY;
1279
1280 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1281
1282 if (++done >= max_done)
1283 break;
1284 }
1285
1286 ndev->stats.rx_packets += done;
1287
1288
1289 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1290
1291 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1292
1293 RET(done);
1294}
1295
1296
1297
1298
1299static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1300 u16 rxd_vlan)
1301{
1302 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1303 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1304 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1305 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1306 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1307 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1308 rxdd->va_hi);
1309}
1310
1311static void print_rxfd(struct rxf_desc *rxfd)
1312{
1313 DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1314 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1315 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1316}
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1365{
1366 BDX_ASSERT(db == NULL || pptr == NULL);
1367
1368 BDX_ASSERT(*pptr != db->rptr &&
1369 *pptr != db->wptr);
1370
1371 BDX_ASSERT(*pptr < db->start ||
1372 *pptr >= db->end);
1373
1374 ++*pptr;
1375 if (unlikely(*pptr == db->end))
1376 *pptr = db->start;
1377}
1378
1379
1380
1381
1382
1383static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1384{
1385 BDX_ASSERT(db->rptr == db->wptr);
1386 __bdx_tx_db_ptr_next(db, &db->rptr);
1387}
1388
1389
1390
1391
1392
1393static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1394{
1395 __bdx_tx_db_ptr_next(db, &db->wptr);
1396 BDX_ASSERT(db->rptr == db->wptr);
1397
1398}
1399
1400
1401
1402
1403
1404
1405
1406
1407static int bdx_tx_db_init(struct txdb *d, int sz_type)
1408{
1409 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1410
1411 d->start = vmalloc(memsz);
1412 if (!d->start)
1413 return -ENOMEM;
1414
1415
1416
1417
1418
1419
1420 d->size = memsz / sizeof(struct tx_map) - 1;
1421 d->end = d->start + d->size + 1;
1422
1423
1424 d->rptr = d->start;
1425 d->wptr = d->start;
1426
1427 return 0;
1428}
1429
1430
1431
1432
1433
1434static void bdx_tx_db_close(struct txdb *d)
1435{
1436 BDX_ASSERT(d == NULL);
1437
1438 vfree(d->start);
1439 d->start = NULL;
1440}
1441
1442
1443
1444
1445
1446
1447
1448static struct {
1449 u16 bytes;
1450 u16 qwords;
1451} txd_sizes[MAX_SKB_FRAGS + 1];
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465static inline void
1466bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1467 struct txd_desc *txdd)
1468{
1469 struct txdb *db = &priv->txdb;
1470 struct pbl *pbl = &txdd->pbl[0];
1471 int nr_frags = skb_shinfo(skb)->nr_frags;
1472 int i;
1473
1474 db->wptr->len = skb_headlen(skb);
1475 db->wptr->addr.dma = dma_map_single(&priv->pdev->dev, skb->data,
1476 db->wptr->len, DMA_TO_DEVICE);
1477 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1478 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1479 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1480 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1481 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1482 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1483 bdx_tx_db_inc_wptr(db);
1484
1485 for (i = 0; i < nr_frags; i++) {
1486 const skb_frag_t *frag;
1487
1488 frag = &skb_shinfo(skb)->frags[i];
1489 db->wptr->len = skb_frag_size(frag);
1490 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1491 0, skb_frag_size(frag),
1492 DMA_TO_DEVICE);
1493
1494 pbl++;
1495 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1496 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1497 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1498 bdx_tx_db_inc_wptr(db);
1499 }
1500
1501
1502 db->wptr->len = -txd_sizes[nr_frags].bytes;
1503 db->wptr->addr.skb = skb;
1504 bdx_tx_db_inc_wptr(db);
1505}
1506
1507
1508
1509
1510static void __init init_txd_sizes(void)
1511{
1512 int i, lwords;
1513
1514
1515
1516 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1517 lwords = 7 + (i * 3);
1518 if (lwords & 1)
1519 lwords++;
1520 txd_sizes[i].qwords = lwords >> 1;
1521 txd_sizes[i].bytes = lwords << 2;
1522 }
1523}
1524
1525
1526
1527static int bdx_tx_init(struct bdx_priv *priv)
1528{
1529 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1530 regTXD_CFG0_0,
1531 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1532 goto err_mem;
1533 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1534 regTXF_CFG0_0,
1535 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1536 goto err_mem;
1537
1538
1539
1540 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1541 goto err_mem;
1542
1543 priv->tx_level = BDX_MAX_TX_LEVEL;
1544#ifdef BDX_DELAY_WPTR
1545 priv->tx_update_mark = priv->tx_level - 1024;
1546#endif
1547 return 0;
1548
1549err_mem:
1550 netdev_err(priv->ndev, "Tx init failed\n");
1551 return -ENOMEM;
1552}
1553
1554
1555
1556
1557
1558
1559
1560static inline int bdx_tx_space(struct bdx_priv *priv)
1561{
1562 struct txd_fifo *f = &priv->txd_fifo0;
1563 int fsize;
1564
1565 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1566 fsize = f->m.rptr - f->m.wptr;
1567 if (fsize <= 0)
1568 fsize = f->m.memsz + fsize;
1569 return fsize;
1570}
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1583 struct net_device *ndev)
1584{
1585 struct bdx_priv *priv = netdev_priv(ndev);
1586 struct txd_fifo *f = &priv->txd_fifo0;
1587 int txd_checksum = 7;
1588 int txd_lgsnd = 0;
1589 int txd_vlan_id = 0;
1590 int txd_vtag = 0;
1591 int txd_mss = 0;
1592
1593 int nr_frags = skb_shinfo(skb)->nr_frags;
1594 struct txd_desc *txdd;
1595 int len;
1596 unsigned long flags;
1597
1598 ENTER;
1599 local_irq_save(flags);
1600 spin_lock(&priv->tx_lock);
1601
1602
1603 BDX_ASSERT(f->m.wptr >= f->m.memsz);
1604 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1605 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1606 txd_checksum = 0;
1607
1608 if (skb_shinfo(skb)->gso_size) {
1609 txd_mss = skb_shinfo(skb)->gso_size;
1610 txd_lgsnd = 1;
1611 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1612 txd_mss);
1613 }
1614
1615 if (skb_vlan_tag_present(skb)) {
1616
1617 txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1618 txd_vtag = 1;
1619 }
1620
1621 txdd->length = CPU_CHIP_SWAP16(skb->len);
1622 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1623 txdd->txd_val1 =
1624 CPU_CHIP_SWAP32(TXD_W1_VAL
1625 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1626 txd_lgsnd, txd_vlan_id));
1627 DBG("=== TxD desc =====================\n");
1628 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1629 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1630
1631 bdx_tx_map_skb(priv, skb, txdd);
1632
1633
1634
1635
1636 f->m.wptr += txd_sizes[nr_frags].bytes;
1637 len = f->m.wptr - f->m.memsz;
1638 if (unlikely(len >= 0)) {
1639 f->m.wptr = len;
1640 if (len > 0) {
1641 BDX_ASSERT(len > f->m.memsz);
1642 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1643 }
1644 }
1645 BDX_ASSERT(f->m.wptr >= f->m.memsz);
1646
1647 priv->tx_level -= txd_sizes[nr_frags].bytes;
1648 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1649#ifdef BDX_DELAY_WPTR
1650 if (priv->tx_level > priv->tx_update_mark) {
1651
1652
1653
1654
1655 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1656 } else {
1657 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1658 priv->tx_noupd = 0;
1659 WRITE_REG(priv, f->m.reg_WPTR,
1660 f->m.wptr & TXF_WPTR_WR_PTR);
1661 }
1662 }
1663#else
1664
1665
1666
1667
1668 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1669
1670#endif
1671#ifdef BDX_LLTX
1672 netif_trans_update(ndev);
1673#endif
1674 ndev->stats.tx_packets++;
1675 ndev->stats.tx_bytes += skb->len;
1676
1677 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1678 DBG("%s: %s: TX Q STOP level %d\n",
1679 BDX_DRV_NAME, ndev->name, priv->tx_level);
1680 netif_stop_queue(ndev);
1681 }
1682
1683 spin_unlock_irqrestore(&priv->tx_lock, flags);
1684 return NETDEV_TX_OK;
1685}
1686
1687
1688
1689
1690
1691
1692
1693
1694static void bdx_tx_cleanup(struct bdx_priv *priv)
1695{
1696 struct txf_fifo *f = &priv->txf_fifo0;
1697 struct txdb *db = &priv->txdb;
1698 int tx_level = 0;
1699
1700 ENTER;
1701 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1702 BDX_ASSERT(f->m.rptr >= f->m.memsz);
1703
1704 while (f->m.wptr != f->m.rptr) {
1705 f->m.rptr += BDX_TXF_DESC_SZ;
1706 f->m.rptr &= f->m.size_mask;
1707
1708
1709
1710 BDX_ASSERT(db->rptr->len == 0);
1711 do {
1712 BDX_ASSERT(db->rptr->addr.dma == 0);
1713 dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
1714 db->rptr->len, DMA_TO_DEVICE);
1715 bdx_tx_db_inc_rptr(db);
1716 } while (db->rptr->len > 0);
1717 tx_level -= db->rptr->len;
1718
1719
1720 dev_consume_skb_irq(db->rptr->addr.skb);
1721 bdx_tx_db_inc_rptr(db);
1722 }
1723
1724
1725 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1726 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1727
1728
1729
1730 spin_lock(&priv->tx_lock);
1731 priv->tx_level += tx_level;
1732 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1733#ifdef BDX_DELAY_WPTR
1734 if (priv->tx_noupd) {
1735 priv->tx_noupd = 0;
1736 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1737 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1738 }
1739#endif
1740
1741 if (unlikely(netif_queue_stopped(priv->ndev) &&
1742 netif_carrier_ok(priv->ndev) &&
1743 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1744 DBG("%s: %s: TX Q WAKE level %d\n",
1745 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1746 netif_wake_queue(priv->ndev);
1747 }
1748 spin_unlock(&priv->tx_lock);
1749}
1750
1751
1752
1753
1754
1755
1756
1757static void bdx_tx_free_skbs(struct bdx_priv *priv)
1758{
1759 struct txdb *db = &priv->txdb;
1760
1761 ENTER;
1762 while (db->rptr != db->wptr) {
1763 if (likely(db->rptr->len))
1764 dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
1765 db->rptr->len, DMA_TO_DEVICE);
1766 else
1767 dev_kfree_skb(db->rptr->addr.skb);
1768 bdx_tx_db_inc_rptr(db);
1769 }
1770 RET();
1771}
1772
1773
1774static void bdx_tx_free(struct bdx_priv *priv)
1775{
1776 ENTER;
1777 bdx_tx_free_skbs(priv);
1778 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1779 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1780 bdx_tx_db_close(&priv->txdb);
1781}
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1795{
1796 struct txd_fifo *f = &priv->txd_fifo0;
1797 int i = f->m.memsz - f->m.wptr;
1798
1799 if (size == 0)
1800 return;
1801
1802 if (i > size) {
1803 memcpy(f->m.va + f->m.wptr, data, size);
1804 f->m.wptr += size;
1805 } else {
1806 memcpy(f->m.va + f->m.wptr, data, i);
1807 f->m.wptr = size - i;
1808 memcpy(f->m.va, data + i, f->m.wptr);
1809 }
1810 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1811}
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1823{
1824 int timer = 0;
1825 ENTER;
1826
1827 while (size > 0) {
1828
1829
1830
1831 int avail = bdx_tx_space(priv) - 8;
1832 if (avail <= 0) {
1833 if (timer++ > 300) {
1834 DBG("timeout while writing desc to TxD fifo\n");
1835 break;
1836 }
1837 udelay(50);
1838 continue;
1839 }
1840 avail = min(avail, size);
1841 DBG("about to push %d bytes starting %p size %d\n", avail,
1842 data, size);
1843 bdx_tx_push_desc(priv, data, avail);
1844 size -= avail;
1845 data += avail;
1846 }
1847 RET();
1848}
1849
1850static const struct net_device_ops bdx_netdev_ops = {
1851 .ndo_open = bdx_open,
1852 .ndo_stop = bdx_close,
1853 .ndo_start_xmit = bdx_tx_transmit,
1854 .ndo_validate_addr = eth_validate_addr,
1855 .ndo_siocdevprivate = bdx_siocdevprivate,
1856 .ndo_set_rx_mode = bdx_setmulti,
1857 .ndo_change_mtu = bdx_change_mtu,
1858 .ndo_set_mac_address = bdx_set_mac,
1859 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1860 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1861};
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880static int
1881bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1882{
1883 struct net_device *ndev;
1884 struct bdx_priv *priv;
1885 int err, pci_using_dac, port;
1886 unsigned long pciaddr;
1887 u32 regionSize;
1888 struct pci_nic *nic;
1889
1890 ENTER;
1891
1892 nic = vmalloc(sizeof(*nic));
1893 if (!nic)
1894 RET(-ENOMEM);
1895
1896
1897 err = pci_enable_device(pdev);
1898 if (err)
1899 goto err_pci;
1900
1901 if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) &&
1902 !(err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
1903 pci_using_dac = 1;
1904 } else {
1905 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) ||
1906 (err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
1907 pr_err("No usable DMA configuration, aborting\n");
1908 goto err_dma;
1909 }
1910 pci_using_dac = 0;
1911 }
1912
1913 err = pci_request_regions(pdev, BDX_DRV_NAME);
1914 if (err)
1915 goto err_dma;
1916
1917 pci_set_master(pdev);
1918
1919 pciaddr = pci_resource_start(pdev, 0);
1920 if (!pciaddr) {
1921 err = -EIO;
1922 pr_err("no MMIO resource\n");
1923 goto err_out_res;
1924 }
1925 regionSize = pci_resource_len(pdev, 0);
1926 if (regionSize < BDX_REGS_SIZE) {
1927 err = -EIO;
1928 pr_err("MMIO resource (%x) too small\n", regionSize);
1929 goto err_out_res;
1930 }
1931
1932 nic->regs = ioremap(pciaddr, regionSize);
1933 if (!nic->regs) {
1934 err = -EIO;
1935 pr_err("ioremap failed\n");
1936 goto err_out_res;
1937 }
1938
1939 if (pdev->irq < 2) {
1940 err = -EIO;
1941 pr_err("invalid irq (%d)\n", pdev->irq);
1942 goto err_out_iomap;
1943 }
1944 pci_set_drvdata(pdev, nic);
1945
1946 if (pdev->device == 0x3014)
1947 nic->port_num = 2;
1948 else
1949 nic->port_num = 1;
1950
1951 print_hw_id(pdev);
1952
1953 bdx_hw_reset_direct(nic->regs);
1954
1955 nic->irq_type = IRQ_INTX;
1956#ifdef BDX_MSI
1957 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1958 err = pci_enable_msi(pdev);
1959 if (err)
1960 pr_err("Can't enable msi. error is %d\n", err);
1961 else
1962 nic->irq_type = IRQ_MSI;
1963 } else
1964 DBG("HW does not support MSI\n");
1965#endif
1966
1967
1968 for (port = 0; port < nic->port_num; port++) {
1969 ndev = alloc_etherdev(sizeof(struct bdx_priv));
1970 if (!ndev) {
1971 err = -ENOMEM;
1972 goto err_out_iomap;
1973 }
1974
1975 ndev->netdev_ops = &bdx_netdev_ops;
1976 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1977
1978 bdx_set_ethtool_ops(ndev);
1979
1980
1981
1982 ndev->if_port = port;
1983 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
1984 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1985 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
1986 ;
1987 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1988 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
1989
1990 if (pci_using_dac)
1991 ndev->features |= NETIF_F_HIGHDMA;
1992
1993
1994 priv = nic->priv[port] = netdev_priv(ndev);
1995
1996 priv->pBdxRegs = nic->regs + port * 0x8000;
1997 priv->port = port;
1998 priv->pdev = pdev;
1999 priv->ndev = ndev;
2000 priv->nic = nic;
2001 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2002
2003 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2004
2005 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2006 DBG("HW statistics not supported\n");
2007 priv->stats_flag = 0;
2008 } else {
2009 priv->stats_flag = 1;
2010 }
2011
2012
2013 priv->txd_size = 2;
2014 priv->txf_size = 2;
2015 priv->rxd_size = 2;
2016 priv->rxf_size = 3;
2017
2018
2019 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2020 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2021
2022
2023
2024
2025
2026
2027#ifdef BDX_LLTX
2028 ndev->features |= NETIF_F_LLTX;
2029#endif
2030
2031 ndev->min_mtu = ETH_ZLEN;
2032 ndev->max_mtu = BDX_MAX_MTU;
2033
2034 spin_lock_init(&priv->tx_lock);
2035
2036
2037 if (bdx_read_mac(priv)) {
2038 pr_err("load MAC address failed\n");
2039 err = -EFAULT;
2040 goto err_out_iomap;
2041 }
2042 SET_NETDEV_DEV(ndev, &pdev->dev);
2043 err = register_netdev(ndev);
2044 if (err) {
2045 pr_err("register_netdev failed\n");
2046 goto err_out_free;
2047 }
2048 netif_carrier_off(ndev);
2049 netif_stop_queue(ndev);
2050
2051 print_eth_id(ndev);
2052 }
2053 RET(0);
2054
2055err_out_free:
2056 free_netdev(ndev);
2057err_out_iomap:
2058 iounmap(nic->regs);
2059err_out_res:
2060 pci_release_regions(pdev);
2061err_dma:
2062 pci_disable_device(pdev);
2063err_pci:
2064 vfree(nic);
2065
2066 RET(err);
2067}
2068
2069
2070
2071static const char
2072 bdx_stat_names[][ETH_GSTRING_LEN] = {
2073 "InUCast",
2074 "InMCast",
2075 "InBCast",
2076 "InPkts",
2077 "InErrors",
2078 "InDropped",
2079 "FrameTooLong",
2080 "FrameSequenceErrors",
2081 "InVLAN",
2082 "InDroppedDFE",
2083 "InDroppedIntFull",
2084 "InFrameAlignErrors",
2085
2086
2087
2088 "OutUCast",
2089 "OutMCast",
2090 "OutBCast",
2091 "OutPkts",
2092
2093
2094
2095 "OutVLAN",
2096 "InUCastOctects",
2097 "OutUCastOctects",
2098
2099
2100
2101 "InBCastOctects",
2102 "OutBCastOctects",
2103 "InOctects",
2104 "OutOctects",
2105};
2106
2107
2108
2109
2110
2111
2112static int bdx_get_link_ksettings(struct net_device *netdev,
2113 struct ethtool_link_ksettings *ecmd)
2114{
2115 ethtool_link_ksettings_zero_link_mode(ecmd, supported);
2116 ethtool_link_ksettings_add_link_mode(ecmd, supported,
2117 10000baseT_Full);
2118 ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE);
2119 ethtool_link_ksettings_zero_link_mode(ecmd, advertising);
2120 ethtool_link_ksettings_add_link_mode(ecmd, advertising,
2121 10000baseT_Full);
2122 ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE);
2123
2124 ecmd->base.speed = SPEED_10000;
2125 ecmd->base.duplex = DUPLEX_FULL;
2126 ecmd->base.port = PORT_FIBRE;
2127 ecmd->base.autoneg = AUTONEG_DISABLE;
2128
2129 return 0;
2130}
2131
2132
2133
2134
2135
2136
2137static void
2138bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2139{
2140 struct bdx_priv *priv = netdev_priv(netdev);
2141
2142 strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2143 strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2144 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2145 strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
2146 sizeof(drvinfo->bus_info));
2147}
2148
2149
2150
2151
2152
2153
2154static int bdx_get_coalesce(struct net_device *netdev,
2155 struct ethtool_coalesce *ecoal,
2156 struct kernel_ethtool_coalesce *kernel_coal,
2157 struct netlink_ext_ack *extack)
2158{
2159 u32 rdintcm;
2160 u32 tdintcm;
2161 struct bdx_priv *priv = netdev_priv(netdev);
2162
2163 rdintcm = priv->rdintcm;
2164 tdintcm = priv->tdintcm;
2165
2166
2167
2168 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2169 ecoal->rx_max_coalesced_frames =
2170 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2171
2172 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2173 ecoal->tx_max_coalesced_frames =
2174 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2175
2176
2177 return 0;
2178}
2179
2180
2181
2182
2183
2184
2185static int bdx_set_coalesce(struct net_device *netdev,
2186 struct ethtool_coalesce *ecoal,
2187 struct kernel_ethtool_coalesce *kernel_coal,
2188 struct netlink_ext_ack *extack)
2189{
2190 u32 rdintcm;
2191 u32 tdintcm;
2192 struct bdx_priv *priv = netdev_priv(netdev);
2193 int rx_coal;
2194 int tx_coal;
2195 int rx_max_coal;
2196 int tx_max_coal;
2197
2198
2199 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2200 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2201 rx_max_coal = ecoal->rx_max_coalesced_frames;
2202 tx_max_coal = ecoal->tx_max_coalesced_frames;
2203
2204
2205 rx_max_coal =
2206 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2207 / PCK_TH_MULT);
2208 tx_max_coal =
2209 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2210 / PCK_TH_MULT);
2211
2212 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2213 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2214 return -EINVAL;
2215
2216 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2217 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2218 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2219 tx_max_coal);
2220
2221 priv->rdintcm = rdintcm;
2222 priv->tdintcm = tdintcm;
2223
2224 WRITE_REG(priv, regRDINTCM0, rdintcm);
2225 WRITE_REG(priv, regTDINTCM0, tdintcm);
2226
2227 return 0;
2228}
2229
2230
2231static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2232{
2233 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
2234}
2235
2236
2237static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2238{
2239 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
2240}
2241
2242
2243
2244
2245
2246
2247static void
2248bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2249{
2250 struct bdx_priv *priv = netdev_priv(netdev);
2251
2252
2253 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2254 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2255 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2256 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2257}
2258
2259
2260
2261
2262
2263
2264static int
2265bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2266{
2267 struct bdx_priv *priv = netdev_priv(netdev);
2268 int rx_size = 0;
2269 int tx_size = 0;
2270
2271 for (; rx_size < 4; rx_size++) {
2272 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2273 break;
2274 }
2275 if (rx_size == 4)
2276 rx_size = 3;
2277
2278 for (; tx_size < 4; tx_size++) {
2279 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2280 break;
2281 }
2282 if (tx_size == 4)
2283 tx_size = 3;
2284
2285
2286 if ((rx_size == priv->rxf_size) &&
2287 (tx_size == priv->txd_size))
2288 return 0;
2289
2290 priv->rxf_size = rx_size;
2291 if (rx_size > 1)
2292 priv->rxd_size = rx_size - 1;
2293 else
2294 priv->rxd_size = rx_size;
2295
2296 priv->txf_size = priv->txd_size = tx_size;
2297
2298 if (netif_running(netdev)) {
2299 bdx_close(netdev);
2300 bdx_open(netdev);
2301 }
2302 return 0;
2303}
2304
2305
2306
2307
2308
2309
2310static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2311{
2312 switch (stringset) {
2313 case ETH_SS_STATS:
2314 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2315 break;
2316 }
2317}
2318
2319
2320
2321
2322
2323static int bdx_get_sset_count(struct net_device *netdev, int stringset)
2324{
2325 struct bdx_priv *priv = netdev_priv(netdev);
2326
2327 switch (stringset) {
2328 case ETH_SS_STATS:
2329 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2330 != sizeof(struct bdx_stats) / sizeof(u64));
2331 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
2332 }
2333
2334 return -EINVAL;
2335}
2336
2337
2338
2339
2340
2341
2342
2343static void bdx_get_ethtool_stats(struct net_device *netdev,
2344 struct ethtool_stats *stats, u64 *data)
2345{
2346 struct bdx_priv *priv = netdev_priv(netdev);
2347
2348 if (priv->stats_flag) {
2349
2350
2351 bdx_update_stats(priv);
2352
2353
2354 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2355 }
2356}
2357
2358
2359
2360
2361
2362static void bdx_set_ethtool_ops(struct net_device *netdev)
2363{
2364 static const struct ethtool_ops bdx_ethtool_ops = {
2365 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2366 ETHTOOL_COALESCE_MAX_FRAMES,
2367 .get_drvinfo = bdx_get_drvinfo,
2368 .get_link = ethtool_op_get_link,
2369 .get_coalesce = bdx_get_coalesce,
2370 .set_coalesce = bdx_set_coalesce,
2371 .get_ringparam = bdx_get_ringparam,
2372 .set_ringparam = bdx_set_ringparam,
2373 .get_strings = bdx_get_strings,
2374 .get_sset_count = bdx_get_sset_count,
2375 .get_ethtool_stats = bdx_get_ethtool_stats,
2376 .get_link_ksettings = bdx_get_link_ksettings,
2377 };
2378
2379 netdev->ethtool_ops = &bdx_ethtool_ops;
2380}
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391static void bdx_remove(struct pci_dev *pdev)
2392{
2393 struct pci_nic *nic = pci_get_drvdata(pdev);
2394 struct net_device *ndev;
2395 int port;
2396
2397 for (port = 0; port < nic->port_num; port++) {
2398 ndev = nic->priv[port]->ndev;
2399 unregister_netdev(ndev);
2400 free_netdev(ndev);
2401 }
2402
2403
2404#ifdef BDX_MSI
2405 if (nic->irq_type == IRQ_MSI)
2406 pci_disable_msi(pdev);
2407#endif
2408
2409 iounmap(nic->regs);
2410 pci_release_regions(pdev);
2411 pci_disable_device(pdev);
2412 vfree(nic);
2413
2414 RET();
2415}
2416
2417static struct pci_driver bdx_pci_driver = {
2418 .name = BDX_DRV_NAME,
2419 .id_table = bdx_pci_tbl,
2420 .probe = bdx_probe,
2421 .remove = bdx_remove,
2422};
2423
2424
2425
2426
2427static void __init print_driver_id(void)
2428{
2429 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2430 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
2431}
2432
2433static int __init bdx_module_init(void)
2434{
2435 ENTER;
2436 init_txd_sizes();
2437 print_driver_id();
2438 RET(pci_register_driver(&bdx_pci_driver));
2439}
2440
2441module_init(bdx_module_init);
2442
2443static void __exit bdx_module_exit(void)
2444{
2445 ENTER;
2446 pci_unregister_driver(&bdx_pci_driver);
2447 RET();
2448}
2449
2450module_exit(bdx_module_exit);
2451
2452MODULE_LICENSE("GPL");
2453MODULE_AUTHOR(DRIVER_AUTHOR);
2454MODULE_DESCRIPTION(BDX_DRV_DESC);
2455MODULE_FIRMWARE("tehuti/bdx.bin");
2456