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18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/sched.h>
21#include <linux/string.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/in.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/mm.h>
28#include <linux/interrupt.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/highmem.h>
35#include <linux/proc_fs.h>
36#include <linux/ctype.h>
37#include <linux/spinlock.h>
38#include <linux/dma-mapping.h>
39#include <linux/clk.h>
40#include <linux/platform_device.h>
41#include <linux/regmap.h>
42#include <linux/semaphore.h>
43#include <linux/phy.h>
44#include <linux/bitops.h>
45#include <linux/io.h>
46#include <linux/uaccess.h>
47#include <linux/pm_runtime.h>
48#include <linux/davinci_emac.h>
49#include <linux/of.h>
50#include <linux/of_address.h>
51#include <linux/of_device.h>
52#include <linux/of_mdio.h>
53#include <linux/of_irq.h>
54#include <linux/of_net.h>
55#include <linux/mfd/syscon.h>
56
57#include <asm/irq.h>
58#include <asm/page.h>
59
60#include "cpsw.h"
61#include "davinci_cpdma.h"
62
63static int debug_level;
64module_param(debug_level, int, 0);
65MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
66
67
68#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK | \
71 NETIF_MSG_TIMER | \
72 NETIF_MSG_IFDOWN | \
73 NETIF_MSG_IFUP | \
74 NETIF_MSG_RX_ERR | \
75 NETIF_MSG_TX_ERR | \
76 NETIF_MSG_TX_QUEUED | \
77 NETIF_MSG_INTR | \
78 NETIF_MSG_TX_DONE | \
79 NETIF_MSG_RX_STATUS | \
80 NETIF_MSG_PKTDATA | \
81 NETIF_MSG_HW | \
82 NETIF_MSG_WOL)
83
84
85#define EMAC_MAJOR_VERSION 6
86#define EMAC_MINOR_VERSION 1
87#define EMAC_MODULE_VERSION "6.1"
88MODULE_VERSION(EMAC_MODULE_VERSION);
89static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
90
91
92#define EMAC_DEF_PASS_CRC (0)
93#define EMAC_DEF_QOS_EN (0)
94#define EMAC_DEF_NO_BUFF_CHAIN (0)
95#define EMAC_DEF_MACCTRL_FRAME_EN (0)
96#define EMAC_DEF_SHORT_FRAME_EN (0)
97#define EMAC_DEF_ERROR_FRAME_EN (0)
98#define EMAC_DEF_PROM_EN (0)
99#define EMAC_DEF_PROM_CH (0)
100#define EMAC_DEF_BCAST_EN (1)
101#define EMAC_DEF_BCAST_CH (0)
102#define EMAC_DEF_MCAST_EN (1)
103#define EMAC_DEF_MCAST_CH (0)
104
105#define EMAC_DEF_TXPRIO_FIXED (1)
106#define EMAC_DEF_TXPACING_EN (0)
107
108#define EMAC_DEF_BUFFER_OFFSET (0)
109#define EMAC_DEF_MIN_ETHPKTSIZE (60)
110#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
111#define EMAC_DEF_TX_CH (0)
112#define EMAC_DEF_RX_CH (0)
113#define EMAC_DEF_RX_NUM_DESC (128)
114#define EMAC_DEF_MAX_TX_CH (1)
115#define EMAC_DEF_MAX_RX_CH (1)
116#define EMAC_POLL_WEIGHT (64)
117
118
119#define EMAC_DEF_TX_MAX_SERVICE (32)
120#define EMAC_DEF_RX_MAX_SERVICE (64)
121
122
123#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
124#define EMAC_NUM_MULTICAST_BITS (64)
125#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
126#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
127#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
128#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
129#define EMAC_INT_MASK_CLEAR (0xFF)
130
131
132#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
133#define EMAC_RXMBP_QOSEN_MASK BIT(29)
134#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
135#define EMAC_RXMBP_CMFEN_MASK BIT(24)
136#define EMAC_RXMBP_CSFEN_MASK BIT(23)
137#define EMAC_RXMBP_CEFEN_MASK BIT(22)
138#define EMAC_RXMBP_CAFEN_MASK BIT(21)
139#define EMAC_RXMBP_PROMCH_SHIFT (16)
140#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
141#define EMAC_RXMBP_BROADEN_MASK BIT(13)
142#define EMAC_RXMBP_BROADCH_SHIFT (8)
143#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
144#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
145#define EMAC_RXMBP_MULTICH_SHIFT (0)
146#define EMAC_RXMBP_MULTICH_MASK (0x7)
147#define EMAC_RXMBP_CHMASK (0x7)
148
149
150# define EMAC_MBP_RXPROMISC (0x00200000)
151# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
152# define EMAC_MBP_RXBCAST (0x00002000)
153# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
154# define EMAC_MBP_RXMCAST (0x00000020)
155# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
156
157
158#define EMAC_MACCONTROL_TXPTYPE BIT(9)
159#define EMAC_MACCONTROL_TXPACEEN BIT(6)
160#define EMAC_MACCONTROL_GMIIEN BIT(5)
161#define EMAC_MACCONTROL_GIGABITEN BIT(7)
162#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
163#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
164
165
166#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
167#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
168
169
170#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
171#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
172#define EMAC_MACSTATUS_TXERRCH_MASK (0x70000)
173#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
174#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
175#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
176#define EMAC_MACSTATUS_RXERRCH_MASK (0x700)
177#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
178
179
180#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
181#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
182
183
184#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
185#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
186#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
187#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
188
189
190#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
191#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
192#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
193#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
194
195
196#define EMAC_CPPI_SOP_BIT BIT(31)
197#define EMAC_CPPI_EOP_BIT BIT(30)
198#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
199#define EMAC_CPPI_EOQ_BIT BIT(28)
200#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
201#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
202#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
203#define EMAC_BD_LENGTH_FOR_CACHE (16)
204#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
205
206
207#define EMAC_MAX_TXRX_CHANNELS (8)
208#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64)
209
210
211#define EMAC_MACINVECTOR 0x90
212
213#define EMAC_DM646X_MACEOIVECTOR 0x94
214
215#define EMAC_MACINTSTATRAW 0xB0
216#define EMAC_MACINTSTATMASKED 0xB4
217#define EMAC_MACINTMASKSET 0xB8
218#define EMAC_MACINTMASKCLEAR 0xBC
219
220#define EMAC_RXMBPENABLE 0x100
221#define EMAC_RXUNICASTSET 0x104
222#define EMAC_RXUNICASTCLEAR 0x108
223#define EMAC_RXMAXLEN 0x10C
224#define EMAC_RXBUFFEROFFSET 0x110
225#define EMAC_RXFILTERLOWTHRESH 0x114
226
227#define EMAC_MACCONTROL 0x160
228#define EMAC_MACSTATUS 0x164
229#define EMAC_EMCONTROL 0x168
230#define EMAC_FIFOCONTROL 0x16C
231#define EMAC_MACCONFIG 0x170
232#define EMAC_SOFTRESET 0x174
233#define EMAC_MACSRCADDRLO 0x1D0
234#define EMAC_MACSRCADDRHI 0x1D4
235#define EMAC_MACHASH1 0x1D8
236#define EMAC_MACHASH2 0x1DC
237#define EMAC_MACADDRLO 0x500
238#define EMAC_MACADDRHI 0x504
239#define EMAC_MACINDEX 0x508
240
241
242#define EMAC_RXGOODFRAMES 0x200
243#define EMAC_RXBCASTFRAMES 0x204
244#define EMAC_RXMCASTFRAMES 0x208
245#define EMAC_RXPAUSEFRAMES 0x20C
246#define EMAC_RXCRCERRORS 0x210
247#define EMAC_RXALIGNCODEERRORS 0x214
248#define EMAC_RXOVERSIZED 0x218
249#define EMAC_RXJABBER 0x21C
250#define EMAC_RXUNDERSIZED 0x220
251#define EMAC_RXFRAGMENTS 0x224
252#define EMAC_RXFILTERED 0x228
253#define EMAC_RXQOSFILTERED 0x22C
254#define EMAC_RXOCTETS 0x230
255#define EMAC_TXGOODFRAMES 0x234
256#define EMAC_TXBCASTFRAMES 0x238
257#define EMAC_TXMCASTFRAMES 0x23C
258#define EMAC_TXPAUSEFRAMES 0x240
259#define EMAC_TXDEFERRED 0x244
260#define EMAC_TXCOLLISION 0x248
261#define EMAC_TXSINGLECOLL 0x24C
262#define EMAC_TXMULTICOLL 0x250
263#define EMAC_TXEXCESSIVECOLL 0x254
264#define EMAC_TXLATECOLL 0x258
265#define EMAC_TXUNDERRUN 0x25C
266#define EMAC_TXCARRIERSENSE 0x260
267#define EMAC_TXOCTETS 0x264
268#define EMAC_NETOCTETS 0x280
269#define EMAC_RXSOFOVERRUNS 0x284
270#define EMAC_RXMOFOVERRUNS 0x288
271#define EMAC_RXDMAOVERRUNS 0x28C
272
273
274#define EMAC_CTRL_EWCTL (0x4)
275#define EMAC_CTRL_EWINTTCNT (0x8)
276
277
278#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
279#define EMAC_DM644X_INTMIN_INTVL 0x1
280#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
281
282
283#define EMAC_DM646X_CMINTCTRL 0x0C
284#define EMAC_DM646X_CMRXINTEN 0x14
285#define EMAC_DM646X_CMTXINTEN 0x18
286#define EMAC_DM646X_CMRXINTMAX 0x70
287#define EMAC_DM646X_CMTXINTMAX 0x74
288
289
290#define EMAC_DM646X_INTPACEEN (0x3 << 16)
291#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
292#define EMAC_DM646X_CMINTMAX_CNT 63
293#define EMAC_DM646X_CMINTMIN_CNT 2
294#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
295#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
296
297
298
299#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
300#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
301
302
303#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
304
305
306
307
308
309struct emac_priv {
310 u32 msg_enable;
311 struct net_device *ndev;
312 struct platform_device *pdev;
313 struct napi_struct napi;
314 char mac_addr[6];
315 void __iomem *remap_addr;
316 u32 emac_base_phys;
317 void __iomem *emac_base;
318 void __iomem *ctrl_base;
319 struct cpdma_ctlr *dma;
320 struct cpdma_chan *txchan;
321 struct cpdma_chan *rxchan;
322 u32 link;
323 u32 speed;
324 u32 duplex;
325 u32 rx_buf_size;
326 u32 isr_count;
327 u32 coal_intvl;
328 u32 bus_freq_mhz;
329 u8 rmii_en;
330 u8 version;
331 u32 mac_hash1;
332 u32 mac_hash2;
333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
334 u32 rx_addr_type;
335 const char *phy_id;
336 struct device_node *phy_node;
337 spinlock_t lock;
338
339 void (*int_enable) (void);
340 void (*int_disable) (void);
341};
342
343
344static char *emac_txhost_errcodes[16] = {
345 "No error", "SOP error", "Ownership bit not set in SOP buffer",
346 "Zero Next Buffer Descriptor Pointer Without EOP",
347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
349 "Reserved", "Reserved", "Reserved", "Reserved"
350};
351
352
353static char *emac_rxhost_errcodes[16] = {
354 "No error", "Reserved", "Ownership bit not set in input buffer",
355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
357 "Reserved", "Reserved", "Reserved", "Reserved"
358};
359
360
361#define emac_read(reg) ioread32(priv->emac_base + (reg))
362#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
363
364#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
365#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
366
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372
373
374
375static void emac_get_drvinfo(struct net_device *ndev,
376 struct ethtool_drvinfo *info)
377{
378 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
380}
381
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389
390
391
392static int emac_get_coalesce(struct net_device *ndev,
393 struct ethtool_coalesce *coal,
394 struct kernel_ethtool_coalesce *kernel_coal,
395 struct netlink_ext_ack *extack)
396{
397 struct emac_priv *priv = netdev_priv(ndev);
398
399 coal->rx_coalesce_usecs = priv->coal_intvl;
400 return 0;
401
402}
403
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412
413
414static int emac_set_coalesce(struct net_device *ndev,
415 struct ethtool_coalesce *coal,
416 struct kernel_ethtool_coalesce *kernel_coal,
417 struct netlink_ext_ack *extack)
418{
419 struct emac_priv *priv = netdev_priv(ndev);
420 u32 int_ctrl, num_interrupts = 0;
421 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
422
423 if (!coal->rx_coalesce_usecs)
424 return -EINVAL;
425
426 coal_intvl = coal->rx_coalesce_usecs;
427
428 switch (priv->version) {
429 case EMAC_VERSION_2:
430 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
431 prescale = priv->bus_freq_mhz * 4;
432
433 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
434 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
435
436 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
437
438
439
440
441 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
442
443 if (addnl_dvdr > 1) {
444 prescale *= addnl_dvdr;
445 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
446 * addnl_dvdr))
447 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
448 * addnl_dvdr);
449 } else {
450 addnl_dvdr = 1;
451 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
452 }
453 }
454
455 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
456
457 int_ctrl |= EMAC_DM646X_INTPACEEN;
458 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
459 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
460 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
461
462 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
463 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
464
465 break;
466 default:
467 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
468 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
469 prescale = coal_intvl * priv->bus_freq_mhz;
470 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
471 prescale = EMAC_DM644X_EWINTCNT_MASK;
472 coal_intvl = prescale / priv->bus_freq_mhz;
473 }
474 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
475
476 break;
477 }
478
479 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
480 priv->coal_intvl = coal_intvl;
481
482 return 0;
483
484}
485
486
487
488
489
490
491static const struct ethtool_ops ethtool_ops = {
492 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
493 .get_drvinfo = emac_get_drvinfo,
494 .get_link = ethtool_op_get_link,
495 .get_coalesce = emac_get_coalesce,
496 .set_coalesce = emac_set_coalesce,
497 .get_ts_info = ethtool_op_get_ts_info,
498 .get_link_ksettings = phy_ethtool_get_link_ksettings,
499 .set_link_ksettings = phy_ethtool_set_link_ksettings,
500};
501
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508
509
510static void emac_update_phystatus(struct emac_priv *priv)
511{
512 u32 mac_control;
513 u32 new_duplex;
514 u32 cur_duplex;
515 struct net_device *ndev = priv->ndev;
516
517 mac_control = emac_read(EMAC_MACCONTROL);
518 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
519 DUPLEX_FULL : DUPLEX_HALF;
520 if (ndev->phydev)
521 new_duplex = ndev->phydev->duplex;
522 else
523 new_duplex = DUPLEX_FULL;
524
525
526 if ((priv->link) && (new_duplex != cur_duplex)) {
527 priv->duplex = new_duplex;
528 if (DUPLEX_FULL == priv->duplex)
529 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
530 else
531 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
532 }
533
534 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
535 mac_control = emac_read(EMAC_MACCONTROL);
536 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
537 EMAC_DM646X_MACCONTORL_GIGFORCE);
538 } else {
539
540 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
541 EMAC_DM646X_MACCONTORL_GIG);
542
543 if (priv->rmii_en && (priv->speed == SPEED_100))
544 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
545 else
546 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
547 }
548
549
550 emac_write(EMAC_MACCONTROL, mac_control);
551
552 if (priv->link) {
553
554 if (!netif_carrier_ok(ndev))
555 netif_carrier_on(ndev);
556
557 if (netif_running(ndev) && netif_queue_stopped(ndev))
558 netif_wake_queue(ndev);
559 } else {
560
561 if (netif_carrier_ok(ndev))
562 netif_carrier_off(ndev);
563 if (!netif_queue_stopped(ndev))
564 netif_stop_queue(ndev);
565 }
566}
567
568
569
570
571
572
573
574
575static u32 hash_get(u8 *addr)
576{
577 u32 hash;
578 u8 tmpval;
579 int cnt;
580 hash = 0;
581
582 for (cnt = 0; cnt < 2; cnt++) {
583 tmpval = *addr++;
584 hash ^= (tmpval >> 2) ^ (tmpval << 4);
585 tmpval = *addr++;
586 hash ^= (tmpval >> 4) ^ (tmpval << 2);
587 tmpval = *addr++;
588 hash ^= (tmpval >> 6) ^ (tmpval);
589 }
590
591 return hash & 0x3F;
592}
593
594
595
596
597
598
599
600
601
602static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
603{
604 struct device *emac_dev = &priv->ndev->dev;
605 u32 rc = 0;
606 u32 hash_bit;
607 u32 hash_value = hash_get(mac_addr);
608
609 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
610 if (netif_msg_drv(priv)) {
611 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
612 "Hash %08x, should not be greater than %08x",
613 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
614 }
615 return -1;
616 }
617
618
619 if (priv->multicast_hash_cnt[hash_value] == 0) {
620 rc = 1;
621 if (hash_value < 32) {
622 hash_bit = BIT(hash_value);
623 priv->mac_hash1 |= hash_bit;
624 } else {
625 hash_bit = BIT((hash_value - 32));
626 priv->mac_hash2 |= hash_bit;
627 }
628 }
629
630
631 ++priv->multicast_hash_cnt[hash_value];
632
633 return rc;
634}
635
636
637
638
639
640
641
642
643
644static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
645{
646 u32 hash_value;
647 u32 hash_bit;
648
649 hash_value = hash_get(mac_addr);
650 if (priv->multicast_hash_cnt[hash_value] > 0) {
651
652 --priv->multicast_hash_cnt[hash_value];
653 }
654
655
656
657 if (priv->multicast_hash_cnt[hash_value] > 0)
658 return 0;
659
660 if (hash_value < 32) {
661 hash_bit = BIT(hash_value);
662 priv->mac_hash1 &= ~hash_bit;
663 } else {
664 hash_bit = BIT((hash_value - 32));
665 priv->mac_hash2 &= ~hash_bit;
666 }
667
668
669 return 1;
670}
671
672
673#define EMAC_MULTICAST_ADD 0
674#define EMAC_MULTICAST_DEL 1
675#define EMAC_ALL_MULTI_SET 2
676#define EMAC_ALL_MULTI_CLR 3
677
678
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685
686
687static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
688{
689 struct device *emac_dev = &priv->ndev->dev;
690 int update = -1;
691
692 switch (action) {
693 case EMAC_MULTICAST_ADD:
694 update = emac_hash_add(priv, mac_addr);
695 break;
696 case EMAC_MULTICAST_DEL:
697 update = emac_hash_del(priv, mac_addr);
698 break;
699 case EMAC_ALL_MULTI_SET:
700 update = 1;
701 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
702 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
703 break;
704 case EMAC_ALL_MULTI_CLR:
705 update = 1;
706 priv->mac_hash1 = 0;
707 priv->mac_hash2 = 0;
708 memset(&(priv->multicast_hash_cnt[0]), 0,
709 sizeof(priv->multicast_hash_cnt[0]) *
710 EMAC_NUM_MULTICAST_BITS);
711 break;
712 default:
713 if (netif_msg_drv(priv))
714 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
715 ": bad operation %d", action);
716 break;
717 }
718
719
720 if (update > 0) {
721 emac_write(EMAC_MACHASH1, priv->mac_hash1);
722 emac_write(EMAC_MACHASH2, priv->mac_hash2);
723 }
724}
725
726
727
728
729
730
731
732
733static void emac_dev_mcast_set(struct net_device *ndev)
734{
735 u32 mbp_enable;
736 struct emac_priv *priv = netdev_priv(ndev);
737
738 mbp_enable = emac_read(EMAC_RXMBPENABLE);
739 if (ndev->flags & IFF_PROMISC) {
740 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
741 mbp_enable |= (EMAC_MBP_RXPROMISC);
742 } else {
743 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
744 if ((ndev->flags & IFF_ALLMULTI) ||
745 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
746 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
747 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
748 } else if (!netdev_mc_empty(ndev)) {
749 struct netdev_hw_addr *ha;
750
751 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
752 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
753
754 netdev_for_each_mc_addr(ha, ndev) {
755 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
756 (u8 *) ha->addr);
757 }
758 } else {
759 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
760 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
761 }
762 }
763
764 emac_write(EMAC_RXMBPENABLE, mbp_enable);
765}
766
767
768
769
770
771
772
773
774
775
776
777
778static void emac_int_disable(struct emac_priv *priv)
779{
780 if (priv->version == EMAC_VERSION_2) {
781 unsigned long flags;
782
783 local_irq_save(flags);
784
785
786
787 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
788 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
789
790 if (priv->int_disable)
791 priv->int_disable();
792
793
794
795
796 emac_write(EMAC_DM646X_MACEOIVECTOR,
797 EMAC_DM646X_MAC_EOI_C0_RXEN);
798
799
800 emac_write(EMAC_DM646X_MACEOIVECTOR,
801 EMAC_DM646X_MAC_EOI_C0_TXEN);
802
803 local_irq_restore(flags);
804
805 } else {
806
807 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
808 }
809}
810
811
812
813
814
815
816
817
818static void emac_int_enable(struct emac_priv *priv)
819{
820 if (priv->version == EMAC_VERSION_2) {
821 if (priv->int_enable)
822 priv->int_enable();
823
824 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
825 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
826
827
828
829
830
831
832 } else {
833
834 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
835 }
836}
837
838
839
840
841
842
843
844
845
846
847
848static irqreturn_t emac_irq(int irq, void *dev_id)
849{
850 struct net_device *ndev = (struct net_device *)dev_id;
851 struct emac_priv *priv = netdev_priv(ndev);
852
853 ++priv->isr_count;
854 if (likely(netif_running(priv->ndev))) {
855 emac_int_disable(priv);
856 napi_schedule(&priv->napi);
857 } else {
858
859 }
860 return IRQ_HANDLED;
861}
862
863static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
864{
865 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
866 if (WARN_ON(!skb))
867 return NULL;
868 skb_reserve(skb, NET_IP_ALIGN);
869 return skb;
870}
871
872static void emac_rx_handler(void *token, int len, int status)
873{
874 struct sk_buff *skb = token;
875 struct net_device *ndev = skb->dev;
876 struct emac_priv *priv = netdev_priv(ndev);
877 struct device *emac_dev = &ndev->dev;
878 int ret;
879
880
881 if (unlikely(!netif_running(ndev))) {
882 dev_kfree_skb_any(skb);
883 return;
884 }
885
886
887 if (status < 0) {
888 ndev->stats.rx_errors++;
889 goto recycle;
890 }
891
892
893 skb_put(skb, len);
894 skb->protocol = eth_type_trans(skb, ndev);
895 netif_receive_skb(skb);
896 ndev->stats.rx_bytes += len;
897 ndev->stats.rx_packets++;
898
899
900 skb = emac_rx_alloc(priv);
901 if (!skb) {
902 if (netif_msg_rx_err(priv) && net_ratelimit())
903 dev_err(emac_dev, "failed rx buffer alloc\n");
904 return;
905 }
906
907recycle:
908 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
909 skb_tailroom(skb), 0);
910
911 WARN_ON(ret == -ENOMEM);
912 if (unlikely(ret < 0))
913 dev_kfree_skb_any(skb);
914}
915
916static void emac_tx_handler(void *token, int len, int status)
917{
918 struct sk_buff *skb = token;
919 struct net_device *ndev = skb->dev;
920
921
922
923
924 if (unlikely(netif_queue_stopped(ndev)))
925 netif_wake_queue(ndev);
926 ndev->stats.tx_packets++;
927 ndev->stats.tx_bytes += len;
928 dev_kfree_skb_any(skb);
929}
930
931
932
933
934
935
936
937
938
939
940
941static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
942{
943 struct device *emac_dev = &ndev->dev;
944 int ret_code;
945 struct emac_priv *priv = netdev_priv(ndev);
946
947
948 if (unlikely(!priv->link)) {
949 if (netif_msg_tx_err(priv) && net_ratelimit())
950 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
951 goto fail_tx;
952 }
953
954 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
955 if (unlikely(ret_code < 0)) {
956 if (netif_msg_tx_err(priv) && net_ratelimit())
957 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
958 goto fail_tx;
959 }
960
961 skb_tx_timestamp(skb);
962
963 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
964 0);
965 if (unlikely(ret_code != 0)) {
966 if (netif_msg_tx_err(priv) && net_ratelimit())
967 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
968 goto fail_tx;
969 }
970
971
972
973
974 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
975 netif_stop_queue(ndev);
976
977 return NETDEV_TX_OK;
978
979fail_tx:
980 ndev->stats.tx_dropped++;
981 netif_stop_queue(ndev);
982 return NETDEV_TX_BUSY;
983}
984
985
986
987
988
989
990
991
992
993
994
995
996static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
997{
998 struct emac_priv *priv = netdev_priv(ndev);
999 struct device *emac_dev = &ndev->dev;
1000
1001 if (netif_msg_tx_err(priv))
1002 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1003
1004 ndev->stats.tx_errors++;
1005 emac_int_disable(priv);
1006 cpdma_chan_stop(priv->txchan);
1007 cpdma_chan_start(priv->txchan);
1008 emac_int_enable(priv);
1009}
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1022{
1023 u32 val;
1024 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1025 emac_write(EMAC_MACSRCADDRLO, val);
1026
1027 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1028 (mac_addr[1] << 8) | (mac_addr[0]));
1029 emac_write(EMAC_MACSRCADDRHI, val);
1030 val = emac_read(EMAC_RXUNICASTSET);
1031 val |= BIT(ch);
1032 emac_write(EMAC_RXUNICASTSET, val);
1033 val = emac_read(EMAC_RXUNICASTCLEAR);
1034 val &= ~BIT(ch);
1035 emac_write(EMAC_RXUNICASTCLEAR, val);
1036}
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1049{
1050 u32 val;
1051 emac_write(EMAC_MACINDEX, ch);
1052 val = ((mac_addr[5] << 8) | mac_addr[4]);
1053 emac_write(EMAC_MACADDRLO, val);
1054 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1055 (mac_addr[1] << 8) | (mac_addr[0]));
1056 emac_write(EMAC_MACADDRHI, val);
1057 emac_set_type0addr(priv, ch, mac_addr);
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1073 char *mac_addr, int index, int match)
1074{
1075 u32 val;
1076 emac_write(EMAC_MACINDEX, index);
1077 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1078 (mac_addr[1] << 8) | (mac_addr[0]));
1079 emac_write(EMAC_MACADDRHI, val);
1080 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1081 (match << 19) | BIT(20));
1082 emac_write(EMAC_MACADDRLO, val);
1083 emac_set_type0addr(priv, ch, mac_addr);
1084}
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1097{
1098 struct device *emac_dev = &priv->ndev->dev;
1099
1100 if (priv->rx_addr_type == 0) {
1101 emac_set_type0addr(priv, ch, mac_addr);
1102 } else if (priv->rx_addr_type == 1) {
1103 u32 cnt;
1104 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1105 emac_set_type1addr(priv, ch, mac_addr);
1106 } else if (priv->rx_addr_type == 2) {
1107 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1108 emac_set_type0addr(priv, ch, mac_addr);
1109 } else {
1110 if (netif_msg_drv(priv))
1111 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1112 }
1113}
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1125{
1126 struct emac_priv *priv = netdev_priv(ndev);
1127 struct device *emac_dev = &priv->ndev->dev;
1128 struct sockaddr *sa = addr;
1129
1130 if (!is_valid_ether_addr(sa->sa_data))
1131 return -EADDRNOTAVAIL;
1132
1133
1134 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1135 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1136
1137
1138 if (netif_running(ndev)) {
1139 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1140 }
1141
1142 if (netif_msg_drv(priv))
1143 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1144 priv->mac_addr);
1145
1146 return 0;
1147}
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158static int emac_hw_enable(struct emac_priv *priv)
1159{
1160 u32 val, mbp_enable, mac_control;
1161
1162
1163 emac_write(EMAC_SOFTRESET, 1);
1164 while (emac_read(EMAC_SOFTRESET))
1165 cpu_relax();
1166
1167
1168 emac_int_disable(priv);
1169
1170
1171 mac_control =
1172 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1173 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1174 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1175 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1176 emac_write(EMAC_MACCONTROL, mac_control);
1177
1178 mbp_enable =
1179 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1180 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1181 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1182 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1183 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1184 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1185 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1186 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1187 EMAC_RXMBP_PROMCH_SHIFT) |
1188 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1189 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1190 EMAC_RXMBP_BROADCH_SHIFT) |
1191 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1192 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1193 EMAC_RXMBP_MULTICH_SHIFT));
1194 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1195 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1196 EMAC_RX_MAX_LEN_MASK));
1197 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1198 EMAC_RX_BUFFER_OFFSET_MASK));
1199 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1200 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1201 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1202
1203 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1204
1205 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1206
1207
1208 val = emac_read(EMAC_MACCONTROL);
1209 val |= (EMAC_MACCONTROL_GMIIEN);
1210 emac_write(EMAC_MACCONTROL, val);
1211
1212
1213 napi_enable(&priv->napi);
1214 emac_int_enable(priv);
1215 return 0;
1216
1217}
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232static int emac_poll(struct napi_struct *napi, int budget)
1233{
1234 unsigned int mask;
1235 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1236 struct net_device *ndev = priv->ndev;
1237 struct device *emac_dev = &ndev->dev;
1238 u32 status = 0;
1239 u32 num_rx_pkts = 0;
1240
1241
1242 status = emac_read(EMAC_MACINVECTOR);
1243
1244 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1245
1246 if (priv->version == EMAC_VERSION_2)
1247 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1248
1249 if (status & mask) {
1250 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE);
1251 }
1252
1253 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1254
1255 if (priv->version == EMAC_VERSION_2)
1256 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1257
1258 if (status & mask) {
1259 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1260 }
1261
1262 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1263 if (priv->version == EMAC_VERSION_2)
1264 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1265
1266 if (unlikely(status & mask)) {
1267 u32 ch, cause;
1268 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1269 netif_stop_queue(ndev);
1270 napi_disable(&priv->napi);
1271
1272 status = emac_read(EMAC_MACSTATUS);
1273 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1274 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1275 if (cause) {
1276 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1277 EMAC_MACSTATUS_TXERRCH_SHIFT);
1278 if (net_ratelimit()) {
1279 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1280 &emac_txhost_errcodes[cause][0], ch);
1281 }
1282 }
1283 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1284 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1285 if (cause) {
1286 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1287 EMAC_MACSTATUS_RXERRCH_SHIFT);
1288 if (netif_msg_hw(priv) && net_ratelimit())
1289 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1290 &emac_rxhost_errcodes[cause][0], ch);
1291 }
1292 } else if (num_rx_pkts < budget) {
1293 napi_complete_done(napi, num_rx_pkts);
1294 emac_int_enable(priv);
1295 }
1296
1297 return num_rx_pkts;
1298}
1299
1300#ifdef CONFIG_NET_POLL_CONTROLLER
1301
1302
1303
1304
1305
1306
1307
1308static void emac_poll_controller(struct net_device *ndev)
1309{
1310 struct emac_priv *priv = netdev_priv(ndev);
1311
1312 emac_int_disable(priv);
1313 emac_irq(ndev->irq, ndev);
1314 emac_int_enable(priv);
1315}
1316#endif
1317
1318static void emac_adjust_link(struct net_device *ndev)
1319{
1320 struct emac_priv *priv = netdev_priv(ndev);
1321 struct phy_device *phydev = ndev->phydev;
1322 unsigned long flags;
1323 int new_state = 0;
1324
1325 spin_lock_irqsave(&priv->lock, flags);
1326
1327 if (phydev->link) {
1328
1329 if (phydev->duplex != priv->duplex) {
1330 new_state = 1;
1331 priv->duplex = phydev->duplex;
1332 }
1333 if (phydev->speed != priv->speed) {
1334 new_state = 1;
1335 priv->speed = phydev->speed;
1336 }
1337 if (!priv->link) {
1338 new_state = 1;
1339 priv->link = 1;
1340 }
1341
1342 } else if (priv->link) {
1343 new_state = 1;
1344 priv->link = 0;
1345 priv->speed = 0;
1346 priv->duplex = ~0;
1347 }
1348 if (new_state) {
1349 emac_update_phystatus(priv);
1350 phy_print_status(ndev->phydev);
1351 }
1352
1353 spin_unlock_irqrestore(&priv->lock, flags);
1354}
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1371{
1372 if (!(netif_running(ndev)))
1373 return -EINVAL;
1374
1375
1376
1377 if (ndev->phydev)
1378 return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1379 else
1380 return -EOPNOTSUPP;
1381}
1382
1383static int match_first_device(struct device *dev, const void *data)
1384{
1385 if (dev->parent && dev->parent->of_node)
1386 return of_device_is_compatible(dev->parent->of_node,
1387 "ti,davinci_mdio");
1388
1389 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1390}
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402static int emac_dev_open(struct net_device *ndev)
1403{
1404 struct device *emac_dev = &ndev->dev;
1405 u32 cnt;
1406 struct resource *res;
1407 int q, m, ret;
1408 int res_num = 0, irq_num = 0;
1409 int i = 0;
1410 struct emac_priv *priv = netdev_priv(ndev);
1411 struct phy_device *phydev = NULL;
1412 struct device *phy = NULL;
1413
1414 ret = pm_runtime_get_sync(&priv->pdev->dev);
1415 if (ret < 0) {
1416 pm_runtime_put_noidle(&priv->pdev->dev);
1417 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1418 __func__, ret);
1419 return ret;
1420 }
1421
1422 netif_carrier_off(ndev);
1423 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1424 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1425
1426
1427 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1428
1429 priv->mac_hash1 = 0;
1430 priv->mac_hash2 = 0;
1431 emac_write(EMAC_MACHASH1, 0);
1432 emac_write(EMAC_MACHASH2, 0);
1433
1434 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1435 struct sk_buff *skb = emac_rx_alloc(priv);
1436
1437 if (!skb)
1438 break;
1439
1440 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
1441 skb_tailroom(skb), 0);
1442 if (WARN_ON(ret < 0))
1443 break;
1444 }
1445
1446
1447 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1448 res_num))) {
1449 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1450 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1451 ndev)) {
1452 dev_err(emac_dev,
1453 "DaVinci EMAC: request_irq() failed\n");
1454 ret = -EBUSY;
1455
1456 goto rollback;
1457 }
1458 }
1459 res_num++;
1460 }
1461
1462 res_num--;
1463 irq_num--;
1464
1465
1466 emac_hw_enable(priv);
1467
1468
1469 if (priv->coal_intvl != 0) {
1470 struct ethtool_coalesce coal;
1471
1472 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1473 emac_set_coalesce(ndev, &coal, NULL, NULL);
1474 }
1475
1476 cpdma_ctlr_start(priv->dma);
1477
1478 if (priv->phy_node) {
1479 phydev = of_phy_connect(ndev, priv->phy_node,
1480 &emac_adjust_link, 0, 0);
1481 if (!phydev) {
1482 dev_err(emac_dev, "could not connect to phy %pOF\n",
1483 priv->phy_node);
1484 ret = -ENODEV;
1485 goto err;
1486 }
1487 }
1488
1489
1490 if (!phydev && !priv->phy_id) {
1491
1492
1493
1494
1495
1496
1497 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1498 match_first_device);
1499 if (phy) {
1500 priv->phy_id = dev_name(phy);
1501 if (!priv->phy_id || !*priv->phy_id)
1502 put_device(phy);
1503 }
1504 }
1505
1506 if (!phydev && priv->phy_id && *priv->phy_id) {
1507 phydev = phy_connect(ndev, priv->phy_id,
1508 &emac_adjust_link,
1509 PHY_INTERFACE_MODE_MII);
1510 put_device(phy);
1511 if (IS_ERR(phydev)) {
1512 dev_err(emac_dev, "could not connect to phy %s\n",
1513 priv->phy_id);
1514 ret = PTR_ERR(phydev);
1515 goto err;
1516 }
1517
1518 priv->link = 0;
1519 priv->speed = 0;
1520 priv->duplex = ~0;
1521
1522 phy_attached_info(phydev);
1523 }
1524
1525 if (!phydev) {
1526
1527 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1528 priv->link = 1;
1529 priv->speed = SPEED_100;
1530 priv->duplex = DUPLEX_FULL;
1531 emac_update_phystatus(priv);
1532 }
1533
1534 if (netif_msg_drv(priv))
1535 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1536
1537 if (phydev)
1538 phy_start(phydev);
1539
1540 return 0;
1541
1542err:
1543 emac_int_disable(priv);
1544 napi_disable(&priv->napi);
1545
1546rollback:
1547 for (q = res_num; q >= 0; q--) {
1548 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1549
1550
1551
1552 if (q != res_num)
1553 irq_num = res->end;
1554
1555 for (m = irq_num; m >= res->start; m--)
1556 free_irq(m, ndev);
1557 }
1558 cpdma_ctlr_stop(priv->dma);
1559 pm_runtime_put(&priv->pdev->dev);
1560 return ret;
1561}
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572static int emac_dev_stop(struct net_device *ndev)
1573{
1574 struct resource *res;
1575 int i = 0;
1576 int irq_num;
1577 struct emac_priv *priv = netdev_priv(ndev);
1578 struct device *emac_dev = &ndev->dev;
1579
1580
1581 netif_stop_queue(ndev);
1582 napi_disable(&priv->napi);
1583
1584 netif_carrier_off(ndev);
1585 emac_int_disable(priv);
1586 cpdma_ctlr_stop(priv->dma);
1587 emac_write(EMAC_SOFTRESET, 1);
1588
1589 if (ndev->phydev)
1590 phy_disconnect(ndev->phydev);
1591
1592
1593 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1594 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1595 free_irq(irq_num, priv->ndev);
1596 i++;
1597 }
1598
1599 if (netif_msg_drv(priv))
1600 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1601
1602 pm_runtime_put(&priv->pdev->dev);
1603 return 0;
1604}
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1615{
1616 struct emac_priv *priv = netdev_priv(ndev);
1617 u32 mac_control;
1618 u32 stats_clear_mask;
1619 int err;
1620
1621 err = pm_runtime_get_sync(&priv->pdev->dev);
1622 if (err < 0) {
1623 pm_runtime_put_noidle(&priv->pdev->dev);
1624 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1625 __func__, err);
1626 return &ndev->stats;
1627 }
1628
1629
1630
1631 mac_control = emac_read(EMAC_MACCONTROL);
1632
1633 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1634 stats_clear_mask = EMAC_STATS_CLR_MASK;
1635 else
1636 stats_clear_mask = 0;
1637
1638 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1639 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1640
1641 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1642 emac_read(EMAC_TXSINGLECOLL) +
1643 emac_read(EMAC_TXMULTICOLL));
1644 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1645 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1646 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1647
1648 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1649 emac_read(EMAC_RXJABBER) +
1650 emac_read(EMAC_RXUNDERSIZED));
1651 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1652 emac_write(EMAC_RXJABBER, stats_clear_mask);
1653 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1654
1655 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1656 emac_read(EMAC_RXMOFOVERRUNS));
1657 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1658 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1659
1660 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1661 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1662
1663 ndev->stats.tx_carrier_errors +=
1664 emac_read(EMAC_TXCARRIERSENSE);
1665 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1666
1667 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1668 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1669
1670 pm_runtime_put(&priv->pdev->dev);
1671
1672 return &ndev->stats;
1673}
1674
1675static const struct net_device_ops emac_netdev_ops = {
1676 .ndo_open = emac_dev_open,
1677 .ndo_stop = emac_dev_stop,
1678 .ndo_start_xmit = emac_dev_xmit,
1679 .ndo_set_rx_mode = emac_dev_mcast_set,
1680 .ndo_set_mac_address = emac_dev_setmac_addr,
1681 .ndo_eth_ioctl = emac_devioctl,
1682 .ndo_tx_timeout = emac_dev_tx_timeout,
1683 .ndo_get_stats = emac_dev_getnetstats,
1684#ifdef CONFIG_NET_POLL_CONTROLLER
1685 .ndo_poll_controller = emac_poll_controller,
1686#endif
1687};
1688
1689static const struct of_device_id davinci_emac_of_match[];
1690
1691static struct emac_platform_data *
1692davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1693{
1694 struct device_node *np;
1695 const struct of_device_id *match;
1696 const struct emac_platform_data *auxdata;
1697 struct emac_platform_data *pdata = NULL;
1698
1699 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1700 return dev_get_platdata(&pdev->dev);
1701
1702 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1703 if (!pdata)
1704 return NULL;
1705
1706 np = pdev->dev.of_node;
1707 pdata->version = EMAC_VERSION_2;
1708
1709 if (!is_valid_ether_addr(pdata->mac_addr))
1710 of_get_mac_address(np, pdata->mac_addr);
1711
1712 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1713 &pdata->ctrl_reg_offset);
1714
1715 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1716 &pdata->ctrl_mod_reg_offset);
1717
1718 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1719 &pdata->ctrl_ram_offset);
1720
1721 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1722 &pdata->ctrl_ram_size);
1723
1724 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1725
1726 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1727
1728 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1729 if (!priv->phy_node) {
1730 if (!of_phy_is_fixed_link(np))
1731 pdata->phy_id = NULL;
1732 else if (of_phy_register_fixed_link(np) >= 0)
1733 priv->phy_node = of_node_get(np);
1734 }
1735
1736 auxdata = pdev->dev.platform_data;
1737 if (auxdata) {
1738 pdata->interrupt_enable = auxdata->interrupt_enable;
1739 pdata->interrupt_disable = auxdata->interrupt_disable;
1740 }
1741
1742 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1743 if (match && match->data) {
1744 auxdata = match->data;
1745 pdata->version = auxdata->version;
1746 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1747 }
1748
1749 return pdata;
1750}
1751
1752static int davinci_emac_try_get_mac(struct platform_device *pdev,
1753 int instance, u8 *mac_addr)
1754{
1755 if (!pdev->dev.of_node)
1756 return -EINVAL;
1757
1758 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1759}
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769static int davinci_emac_probe(struct platform_device *pdev)
1770{
1771 struct device_node *np = pdev->dev.of_node;
1772 int rc = 0;
1773 struct resource *res, *res_ctrl;
1774 struct net_device *ndev;
1775 struct emac_priv *priv;
1776 unsigned long hw_ram_addr;
1777 struct emac_platform_data *pdata;
1778 struct cpdma_params dma_params;
1779 struct clk *emac_clk;
1780 unsigned long emac_bus_frequency;
1781
1782
1783
1784 emac_clk = devm_clk_get(&pdev->dev, NULL);
1785 if (IS_ERR(emac_clk)) {
1786 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1787 return -EBUSY;
1788 }
1789 emac_bus_frequency = clk_get_rate(emac_clk);
1790 devm_clk_put(&pdev->dev, emac_clk);
1791
1792
1793
1794 ndev = alloc_etherdev(sizeof(struct emac_priv));
1795 if (!ndev)
1796 return -ENOMEM;
1797
1798 platform_set_drvdata(pdev, ndev);
1799 priv = netdev_priv(ndev);
1800 priv->pdev = pdev;
1801 priv->ndev = ndev;
1802 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1803
1804 spin_lock_init(&priv->lock);
1805
1806 pdata = davinci_emac_of_get_pdata(pdev, priv);
1807 if (!pdata) {
1808 dev_err(&pdev->dev, "no platform data\n");
1809 rc = -ENODEV;
1810 goto err_free_netdev;
1811 }
1812
1813
1814 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1815 priv->phy_id = pdata->phy_id;
1816 priv->rmii_en = pdata->rmii_en;
1817 priv->version = pdata->version;
1818 priv->int_enable = pdata->interrupt_enable;
1819 priv->int_disable = pdata->interrupt_disable;
1820
1821 priv->coal_intvl = 0;
1822 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1823
1824
1825 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1826 if (IS_ERR(priv->remap_addr)) {
1827 rc = PTR_ERR(priv->remap_addr);
1828 goto no_pdata;
1829 }
1830 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1831
1832 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1833 if (res_ctrl) {
1834 priv->ctrl_base =
1835 devm_ioremap_resource(&pdev->dev, res_ctrl);
1836 if (IS_ERR(priv->ctrl_base)) {
1837 rc = PTR_ERR(priv->ctrl_base);
1838 goto no_pdata;
1839 }
1840 } else {
1841 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1842 }
1843
1844 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1845 ndev->base_addr = (unsigned long)priv->remap_addr;
1846
1847 hw_ram_addr = pdata->hw_ram_addr;
1848 if (!hw_ram_addr)
1849 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1850
1851 memset(&dma_params, 0, sizeof(dma_params));
1852 dma_params.dev = &pdev->dev;
1853 dma_params.dmaregs = priv->emac_base;
1854 dma_params.rxthresh = priv->emac_base + 0x120;
1855 dma_params.rxfree = priv->emac_base + 0x140;
1856 dma_params.txhdp = priv->emac_base + 0x600;
1857 dma_params.rxhdp = priv->emac_base + 0x620;
1858 dma_params.txcp = priv->emac_base + 0x640;
1859 dma_params.rxcp = priv->emac_base + 0x660;
1860 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1861 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1862 dma_params.desc_hw_addr = hw_ram_addr;
1863 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1864 dma_params.desc_align = 16;
1865
1866 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1867 (u32 __force)res->start + pdata->ctrl_ram_offset;
1868
1869 priv->dma = cpdma_ctlr_create(&dma_params);
1870 if (!priv->dma) {
1871 dev_err(&pdev->dev, "error initializing DMA\n");
1872 rc = -ENOMEM;
1873 goto no_pdata;
1874 }
1875
1876 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1877 emac_tx_handler, 0);
1878 if (IS_ERR(priv->txchan)) {
1879 dev_err(&pdev->dev, "error initializing tx dma channel\n");
1880 rc = PTR_ERR(priv->txchan);
1881 goto err_free_dma;
1882 }
1883
1884 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1885 emac_rx_handler, 1);
1886 if (IS_ERR(priv->rxchan)) {
1887 dev_err(&pdev->dev, "error initializing rx dma channel\n");
1888 rc = PTR_ERR(priv->rxchan);
1889 goto err_free_txchan;
1890 }
1891
1892 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1893 if (!res) {
1894 dev_err(&pdev->dev, "error getting irq res\n");
1895 rc = -ENOENT;
1896 goto err_free_rxchan;
1897 }
1898 ndev->irq = res->start;
1899
1900 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1901 if (!rc)
1902 ether_addr_copy(ndev->dev_addr, priv->mac_addr);
1903
1904 if (!is_valid_ether_addr(priv->mac_addr)) {
1905
1906 eth_hw_addr_random(ndev);
1907 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1908 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1909 priv->mac_addr);
1910 }
1911
1912 ndev->netdev_ops = &emac_netdev_ops;
1913 ndev->ethtool_ops = ðtool_ops;
1914 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1915
1916 pm_runtime_enable(&pdev->dev);
1917 rc = pm_runtime_get_sync(&pdev->dev);
1918 if (rc < 0) {
1919 pm_runtime_put_noidle(&pdev->dev);
1920 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1921 __func__, rc);
1922 goto err_napi_del;
1923 }
1924
1925
1926 SET_NETDEV_DEV(ndev, &pdev->dev);
1927 rc = register_netdev(ndev);
1928 if (rc) {
1929 dev_err(&pdev->dev, "error in register_netdev\n");
1930 rc = -ENODEV;
1931 pm_runtime_put(&pdev->dev);
1932 goto err_napi_del;
1933 }
1934
1935
1936 if (netif_msg_probe(priv)) {
1937 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1938 "(regs: %pa, irq: %d)\n",
1939 &priv->emac_base_phys, ndev->irq);
1940 }
1941 pm_runtime_put(&pdev->dev);
1942
1943 return 0;
1944
1945err_napi_del:
1946 netif_napi_del(&priv->napi);
1947err_free_rxchan:
1948 cpdma_chan_destroy(priv->rxchan);
1949err_free_txchan:
1950 cpdma_chan_destroy(priv->txchan);
1951err_free_dma:
1952 cpdma_ctlr_destroy(priv->dma);
1953no_pdata:
1954 if (of_phy_is_fixed_link(np))
1955 of_phy_deregister_fixed_link(np);
1956 of_node_put(priv->phy_node);
1957err_free_netdev:
1958 free_netdev(ndev);
1959 return rc;
1960}
1961
1962
1963
1964
1965
1966
1967
1968
1969static int davinci_emac_remove(struct platform_device *pdev)
1970{
1971 struct net_device *ndev = platform_get_drvdata(pdev);
1972 struct emac_priv *priv = netdev_priv(ndev);
1973 struct device_node *np = pdev->dev.of_node;
1974
1975 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1976
1977 if (priv->txchan)
1978 cpdma_chan_destroy(priv->txchan);
1979 if (priv->rxchan)
1980 cpdma_chan_destroy(priv->rxchan);
1981 cpdma_ctlr_destroy(priv->dma);
1982
1983 unregister_netdev(ndev);
1984 of_node_put(priv->phy_node);
1985 pm_runtime_disable(&pdev->dev);
1986 if (of_phy_is_fixed_link(np))
1987 of_phy_deregister_fixed_link(np);
1988 free_netdev(ndev);
1989
1990 return 0;
1991}
1992
1993static int davinci_emac_suspend(struct device *dev)
1994{
1995 struct net_device *ndev = dev_get_drvdata(dev);
1996
1997 if (netif_running(ndev))
1998 emac_dev_stop(ndev);
1999
2000 return 0;
2001}
2002
2003static int davinci_emac_resume(struct device *dev)
2004{
2005 struct net_device *ndev = dev_get_drvdata(dev);
2006
2007 if (netif_running(ndev))
2008 emac_dev_open(ndev);
2009
2010 return 0;
2011}
2012
2013static const struct dev_pm_ops davinci_emac_pm_ops = {
2014 .suspend = davinci_emac_suspend,
2015 .resume = davinci_emac_resume,
2016};
2017
2018static const struct emac_platform_data am3517_emac_data = {
2019 .version = EMAC_VERSION_2,
2020 .hw_ram_addr = 0x01e20000,
2021};
2022
2023static const struct emac_platform_data dm816_emac_data = {
2024 .version = EMAC_VERSION_2,
2025};
2026
2027static const struct of_device_id davinci_emac_of_match[] = {
2028 {.compatible = "ti,davinci-dm6467-emac", },
2029 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2030 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2031 {},
2032};
2033MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2034
2035
2036static struct platform_driver davinci_emac_driver = {
2037 .driver = {
2038 .name = "davinci_emac",
2039 .pm = &davinci_emac_pm_ops,
2040 .of_match_table = davinci_emac_of_match,
2041 },
2042 .probe = davinci_emac_probe,
2043 .remove = davinci_emac_remove,
2044};
2045
2046
2047
2048
2049
2050
2051
2052static int __init davinci_emac_init(void)
2053{
2054 return platform_driver_register(&davinci_emac_driver);
2055}
2056late_initcall(davinci_emac_init);
2057
2058
2059
2060
2061
2062
2063
2064static void __exit davinci_emac_exit(void)
2065{
2066 platform_driver_unregister(&davinci_emac_driver);
2067}
2068module_exit(davinci_emac_exit);
2069
2070MODULE_LICENSE("GPL");
2071MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2072MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2073MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2074