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11#ifndef _HWM_
12#define _HWM_
13
14#include "mbuf.h"
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29#ifndef DRV_BUF_FLUSH
30#define DRV_BUF_FLUSH(desc,flag)
31#define DDI_DMA_SYNC_FORCPU
32#define DDI_DMA_SYNC_FORDEV
33#endif
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38#define RX_ENABLE_PASS_SMT 21
39#define RX_DISABLE_PASS_SMT 22
40#define RX_ENABLE_PASS_NSA 23
41#define RX_DISABLE_PASS_NSA 24
42#define RX_ENABLE_PASS_DB 25
43#define RX_DISABLE_PASS_DB 26
44#define RX_DISABLE_PASS_ALL 27
45#define RX_DISABLE_LLC_PROMISC 28
46#define RX_ENABLE_LLC_PROMISC 29
47
48
49#ifndef DMA_RD
50#define DMA_RD 1
51#endif
52#ifndef DMA_WR
53#define DMA_WR 2
54#endif
55#define SMT_BUF 0x80
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60#define EN_IRQ_EOF 0x02
61#define LOC_TX 0x04
62#define LAST_FRAG 0x08
63#define FIRST_FRAG 0x10
64#define LAN_TX 0x20
65#define RING_DOWN 0x40
66#define OUT_OF_TXD 0x80
67
68
69#ifndef NULL
70#define NULL 0
71#endif
72
73#define C_INDIC (1L<<25)
74#define A_INDIC (1L<<26)
75#define RD_FS_LOCAL 0x80
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79
80#define DEBUG_SMTF 1
81#define DEBUG_SMT 2
82#define DEBUG_ECM 3
83#define DEBUG_RMT 4
84#define DEBUG_CFM 5
85#define DEBUG_PCM 6
86#define DEBUG_SBA 7
87#define DEBUG_ESS 8
88
89#define DB_HWM_RX 10
90#define DB_HWM_TX 11
91#define DB_HWM_GEN 12
92
93struct s_mbuf_pool {
94#ifndef MB_OUTSIDE_SMC
95 SMbuf mb[MAX_MBUF] ;
96#endif
97 SMbuf *mb_start ;
98 SMbuf *mb_free ;
99} ;
100
101struct hwm_r {
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105 u_int len ;
106 char *mb_pos ;
107} ;
108
109struct hw_modul {
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113 struct s_mbuf_pool mbuf_pool ;
114 struct hwm_r r ;
115
116 union s_fp_descr volatile *descr_p ;
117
118 u_short pass_SMT ;
119 u_short pass_NSA ;
120 u_short pass_DB ;
121 u_short pass_llc_promisc ;
122
123 SMbuf *llc_rx_pipe ;
124 SMbuf *llc_rx_tail ;
125 int queued_rx_frames ;
126
127 SMbuf *txd_tx_pipe ;
128 SMbuf *txd_tx_tail ;
129 int queued_txd_mb ;
130
131 int rx_break ;
132 int leave_isr ;
133 int isr_flag ;
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137 struct s_smt_tx_queue *tx_p ;
138 u_long tx_descr ;
139 int tx_len ;
140 SMbuf *tx_mb ;
141 char *tx_data ;
142
143 int detec_count ;
144 u_long rx_len_error ;
145} ;
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151
152#ifdef DEBUG
153struct os_debug {
154 int hwm_rx ;
155 int hwm_tx ;
156 int hwm_gen ;
157} ;
158#endif
159
160#ifdef DEBUG
161#ifdef DEBUG_BRD
162#define DB_P smc->debug
163#else
164#define DB_P debug
165#endif
166
167#define DB_RX(lev, fmt, ...) \
168do { \
169 if (DB_P.d_os.hwm_rx >= (lev)) \
170 printf(fmt "\n", ##__VA_ARGS__); \
171} while (0)
172#define DB_TX(lev, fmt, ...) \
173do { \
174 if (DB_P.d_os.hwm_tx >= (lev)) \
175 printf(fmt "\n", ##__VA_ARGS__); \
176} while (0)
177#define DB_GEN(lev, fmt, ...) \
178do { \
179 if (DB_P.d_os.hwm_gen >= (lev)) \
180 printf(fmt "\n", ##__VA_ARGS__); \
181} while (0)
182#else
183#define DB_RX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
184#define DB_TX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
185#define DB_GEN(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
186#endif
187
188#ifndef SK_BREAK
189#define SK_BREAK()
190#endif
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209#define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
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225#define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
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242#define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
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260#define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
261 (smc)->hw.fp.tx_q[queue].tx_curr_put
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277#define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
278 RD_LENGTH)
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294#define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
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311#define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
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325#define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
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340#define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
341 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
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357#ifndef HWM_NO_FLOW_CTL
358#define HWM_RX_CHECK(smc,low_water) {\
359 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
360 mac_drv_fill_rxd(smc) ;\
361 }\
362}
363#else
364#define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
365#endif
366
367#ifndef HWM_EBASE
368#define HWM_EBASE 500
369#endif
370
371#define HWM_E0001 HWM_EBASE + 1
372#define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
373#define HWM_E0002 HWM_EBASE + 2
374#define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
375#define HWM_E0003 HWM_EBASE + 3
376#define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
377#define HWM_E0004 HWM_EBASE + 4
378#define HWM_E0004_MSG "HWM: Parity error rx queue 1"
379#define HWM_E0005 HWM_EBASE + 5
380#define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
381#define HWM_E0006 HWM_EBASE + 6
382#define HWM_E0006_MSG "HWM: Encoding error async tx queue"
383#define HWM_E0007 HWM_EBASE + 7
384#define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
385#define HWM_E0008 HWM_EBASE + 8
386#define HWM_E0008_MSG ""
387#define HWM_E0009 HWM_EBASE + 9
388#define HWM_E0009_MSG "HWM: Out of RxD condition detected"
389#define HWM_E0010 HWM_EBASE + 10
390#define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
391#define HWM_E0011 HWM_EBASE + 11
392#define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
393#define HWM_E0012 HWM_EBASE + 12
394#define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
395#define HWM_E0013 HWM_EBASE + 13
396#define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
397
398#endif
399