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7#include <linux/types.h>
8#include <linux/device.h>
9#include <linux/slab.h>
10#include <linux/bitfield.h>
11#include <linux/dma-direction.h>
12
13#include "gsi.h"
14#include "gsi_trans.h"
15#include "ipa.h"
16#include "ipa_endpoint.h"
17#include "ipa_table.h"
18#include "ipa_cmd.h"
19#include "ipa_mem.h"
20
21
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27
28
29
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37
38
39
40enum pipeline_clear_options {
41 pipeline_clear_hps = 0x0,
42 pipeline_clear_src_grp = 0x1,
43 pipeline_clear_full = 0x2,
44};
45
46
47
48struct ipa_cmd_hw_ip_fltrt_init {
49 __le64 hash_rules_addr;
50 __le64 flags;
51 __le64 nhash_rules_addr;
52};
53
54
55#define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0)
56#define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12)
57#define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28)
58#define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40)
59
60
61
62struct ipa_cmd_hw_hdr_init_local {
63 __le64 hdr_table_addr;
64 __le32 flags;
65 __le32 reserved;
66};
67
68
69#define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0)
70#define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12)
71
72
73
74
75#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
76#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
77
78struct ipa_cmd_register_write {
79 __le16 flags;
80 __le16 offset;
81 __le32 value;
82 __le32 value_mask;
83 __le32 clear_options;
84};
85
86
87
88#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11)
89
90#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15)
91
92
93#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0)
94
95
96
97struct ipa_cmd_ip_packet_init {
98 u8 dest_endpoint;
99 u8 reserved[7];
100};
101
102
103#define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0)
104
105
106
107
108
109#define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
110#define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
111
112struct ipa_cmd_hw_dma_mem_mem {
113 __le16 clear_after_read;
114 __le16 size;
115 __le16 local_addr;
116 __le16 flags;
117 __le64 system_addr;
118};
119
120
121#define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15)
122
123
124#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0)
125
126#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1)
127#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2)
128
129
130
131struct ipa_cmd_ip_packet_tag_status {
132 __le64 tag;
133};
134
135#define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16)
136
137
138union ipa_cmd_payload {
139 struct ipa_cmd_hw_ip_fltrt_init table_init;
140 struct ipa_cmd_hw_hdr_init_local hdr_init_local;
141 struct ipa_cmd_register_write register_write;
142 struct ipa_cmd_ip_packet_init ip_packet_init;
143 struct ipa_cmd_hw_dma_mem_mem dma_shared_mem;
144 struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status;
145};
146
147static void ipa_cmd_validate_build(void)
148{
149
150
151
152
153
154
155
156#define TABLE_SIZE (TABLE_COUNT_MAX * sizeof(__le64))
157#define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX)
158 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK));
159 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));
160#undef TABLE_COUNT_MAX
161#undef TABLE_SIZE
162
163
164 BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK) !=
165 field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));
166 BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) !=
167 field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK));
168
169
170 BUILD_BUG_ON(field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK) <
171 IPA_ENDPOINT_MAX - 1);
172}
173
174
175bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, bool route)
176{
177 u32 offset_max = field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
178 u32 size_max = field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK);
179 const char *table = route ? "route" : "filter";
180 struct device *dev = &ipa->pdev->dev;
181
182
183 if (mem->size > size_max) {
184 dev_err(dev, "%s table region size too large\n", table);
185 dev_err(dev, " (0x%04x > 0x%04x)\n",
186 mem->size, size_max);
187
188 return false;
189 }
190
191
192 if (mem->offset > offset_max ||
193 ipa->mem_offset > offset_max - mem->offset) {
194 dev_err(dev, "%s table region offset too large\n", table);
195 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
196 ipa->mem_offset, mem->offset, offset_max);
197
198 return false;
199 }
200
201
202 if (mem->offset > ipa->mem_size ||
203 mem->size > ipa->mem_size - mem->offset) {
204 dev_err(dev, "%s table region out of range\n", table);
205 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
206 mem->offset, mem->size, ipa->mem_size);
207
208 return false;
209 }
210
211 return true;
212}
213
214
215static bool ipa_cmd_header_valid(struct ipa *ipa)
216{
217 struct device *dev = &ipa->pdev->dev;
218 const struct ipa_mem *mem;
219 u32 offset_max;
220 u32 size_max;
221 u32 offset;
222 u32 size;
223
224
225
226
227
228
229 offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
230 size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
231
232
233
234
235 mem = ipa_mem_find(ipa, IPA_MEM_MODEM_HEADER);
236 offset = mem->offset;
237 size = mem->size;
238
239
240 if (offset > offset_max || ipa->mem_offset > offset_max - offset) {
241 dev_err(dev, "header table region offset too large\n");
242 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
243 ipa->mem_offset, offset, offset_max);
244
245 return false;
246 }
247
248
249 mem = ipa_mem_find(ipa, IPA_MEM_AP_HEADER);
250 if (mem)
251 size += mem->size;
252
253
254 if (size > size_max) {
255 dev_err(dev, "header table region size too large\n");
256 dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max);
257
258 return false;
259 }
260
261
262 if (size > ipa->mem_size || offset > ipa->mem_size - size) {
263 dev_err(dev, "header table region out of range\n");
264 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
265 offset, size, ipa->mem_size);
266
267 return false;
268 }
269
270 return true;
271}
272
273
274static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa,
275 const char *name, u32 offset)
276{
277 struct ipa_cmd_register_write *payload;
278 struct device *dev = &ipa->pdev->dev;
279 u32 offset_max;
280 u32 bit_count;
281
282
283
284
285
286
287 bit_count = BITS_PER_BYTE * sizeof(payload->offset);
288 if (ipa->version >= IPA_VERSION_4_0)
289 bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
290 BUILD_BUG_ON(bit_count > 32);
291 offset_max = ~0U >> (32 - bit_count);
292
293
294
295
296
297 if (offset > offset_max || ipa->mem_offset > offset_max - offset) {
298 dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n",
299 name, ipa->mem_offset, offset, offset_max);
300 return false;
301 }
302
303 return true;
304}
305
306
307static bool ipa_cmd_register_write_valid(struct ipa *ipa)
308{
309 const char *name;
310 u32 offset;
311
312
313
314
315 if (ipa_table_hash_support(ipa)) {
316 offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version);
317 name = "filter/route hash flush";
318 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
319 return false;
320 }
321
322
323
324
325
326
327
328
329 offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1);
330 name = "maximal endpoint status";
331 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
332 return false;
333
334 return true;
335}
336
337bool ipa_cmd_data_valid(struct ipa *ipa)
338{
339 if (!ipa_cmd_header_valid(ipa))
340 return false;
341
342 if (!ipa_cmd_register_write_valid(ipa))
343 return false;
344
345 return true;
346}
347
348
349int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max)
350{
351 struct gsi_trans_info *trans_info = &channel->trans_info;
352 struct device *dev = channel->gsi->dev;
353 int ret;
354
355
356 ipa_cmd_validate_build();
357
358
359
360
361
362 ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool,
363 sizeof(union ipa_cmd_payload),
364 tre_max, channel->tlv_count);
365 if (ret)
366 return ret;
367
368
369 ret = gsi_trans_pool_init(&trans_info->info_pool,
370 sizeof(struct ipa_cmd_info),
371 tre_max, channel->tlv_count);
372 if (ret)
373 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
374
375 return ret;
376}
377
378void ipa_cmd_pool_exit(struct gsi_channel *channel)
379{
380 struct gsi_trans_info *trans_info = &channel->trans_info;
381 struct device *dev = channel->gsi->dev;
382
383 gsi_trans_pool_exit(&trans_info->info_pool);
384 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
385}
386
387static union ipa_cmd_payload *
388ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr)
389{
390 struct gsi_trans_info *trans_info;
391 struct ipa_endpoint *endpoint;
392
393 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
394 trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info;
395
396 return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr);
397}
398
399
400void ipa_cmd_table_init_add(struct gsi_trans *trans,
401 enum ipa_cmd_opcode opcode, u16 size, u32 offset,
402 dma_addr_t addr, u16 hash_size, u32 hash_offset,
403 dma_addr_t hash_addr)
404{
405 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
406 enum dma_data_direction direction = DMA_TO_DEVICE;
407 struct ipa_cmd_hw_ip_fltrt_init *payload;
408 union ipa_cmd_payload *cmd_payload;
409 dma_addr_t payload_addr;
410 u64 val;
411
412
413 offset += ipa->mem_offset;
414 val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
415 val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK);
416
417
418 if (hash_size) {
419
420 hash_offset += ipa->mem_offset;
421 val |= u64_encode_bits(hash_offset,
422 IP_FLTRT_FLAGS_HASH_ADDR_FMASK);
423 val |= u64_encode_bits(hash_size,
424 IP_FLTRT_FLAGS_HASH_SIZE_FMASK);
425 }
426
427 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
428 payload = &cmd_payload->table_init;
429
430
431 if (hash_size)
432 payload->hash_rules_addr = cpu_to_le64(hash_addr);
433 payload->flags = cpu_to_le64(val);
434 payload->nhash_rules_addr = cpu_to_le64(addr);
435
436 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
437 direction, opcode);
438}
439
440
441void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size,
442 dma_addr_t addr)
443{
444 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
445 enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL;
446 enum dma_data_direction direction = DMA_TO_DEVICE;
447 struct ipa_cmd_hw_hdr_init_local *payload;
448 union ipa_cmd_payload *cmd_payload;
449 dma_addr_t payload_addr;
450 u32 flags;
451
452 offset += ipa->mem_offset;
453
454
455
456
457
458
459 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
460 payload = &cmd_payload->hdr_init_local;
461
462 payload->hdr_table_addr = cpu_to_le64(addr);
463 flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
464 flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
465 payload->flags = cpu_to_le32(flags);
466
467 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
468 direction, opcode);
469}
470
471void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value,
472 u32 mask, bool clear_full)
473{
474 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
475 struct ipa_cmd_register_write *payload;
476 union ipa_cmd_payload *cmd_payload;
477 u32 opcode = IPA_CMD_REGISTER_WRITE;
478 dma_addr_t payload_addr;
479 u32 clear_option;
480 u32 options;
481 u16 flags;
482
483
484 clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps;
485
486
487
488
489
490 if (ipa->version >= IPA_VERSION_4_0) {
491 u16 offset_high;
492 u32 val;
493
494
495
496 val = u16_encode_bits(clear_option,
497 REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK);
498 opcode |= val;
499
500
501 offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16));
502 offset &= (1 << 16) - 1;
503
504
505 flags = u16_encode_bits(offset_high,
506 REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
507 options = 0;
508
509 } else {
510 flags = 0;
511 options = u16_encode_bits(clear_option,
512 REGISTER_WRITE_CLEAR_OPTIONS_FMASK);
513 }
514
515 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
516 payload = &cmd_payload->register_write;
517
518 payload->flags = cpu_to_le16(flags);
519 payload->offset = cpu_to_le16((u16)offset);
520 payload->value = cpu_to_le32(value);
521 payload->value_mask = cpu_to_le32(mask);
522 payload->clear_options = cpu_to_le32(options);
523
524 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
525 DMA_NONE, opcode);
526}
527
528
529static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id)
530{
531 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
532 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT;
533 enum dma_data_direction direction = DMA_TO_DEVICE;
534 struct ipa_cmd_ip_packet_init *payload;
535 union ipa_cmd_payload *cmd_payload;
536 dma_addr_t payload_addr;
537
538 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
539 payload = &cmd_payload->ip_packet_init;
540
541 payload->dest_endpoint = u8_encode_bits(endpoint_id,
542 IPA_PACKET_INIT_DEST_ENDPOINT_FMASK);
543
544 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
545 direction, opcode);
546}
547
548
549void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size,
550 dma_addr_t addr, bool toward_ipa)
551{
552 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
553 enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM;
554 struct ipa_cmd_hw_dma_mem_mem *payload;
555 union ipa_cmd_payload *cmd_payload;
556 enum dma_data_direction direction;
557 dma_addr_t payload_addr;
558 u16 flags;
559
560
561 WARN_ON(!size);
562 WARN_ON(size > U16_MAX);
563 WARN_ON(offset > U16_MAX || ipa->mem_offset > U16_MAX - offset);
564
565 offset += ipa->mem_offset;
566
567 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
568 payload = &cmd_payload->dma_shared_mem;
569
570
571
572
573 payload->size = cpu_to_le16(size);
574 payload->local_addr = cpu_to_le16(offset);
575
576
577
578
579
580
581
582
583 flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK;
584 payload->flags = cpu_to_le16(flags);
585 payload->system_addr = cpu_to_le64(addr);
586
587 direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
588
589 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
590 direction, opcode);
591}
592
593static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans)
594{
595 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
596 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS;
597 enum dma_data_direction direction = DMA_TO_DEVICE;
598 struct ipa_cmd_ip_packet_tag_status *payload;
599 union ipa_cmd_payload *cmd_payload;
600 dma_addr_t payload_addr;
601
602 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
603 payload = &cmd_payload->ip_packet_tag_status;
604
605 payload->tag = le64_encode_bits(0, IP_PACKET_TAG_STATUS_TAG_FMASK);
606
607 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
608 direction, opcode);
609}
610
611
612static void ipa_cmd_transfer_add(struct gsi_trans *trans)
613{
614 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
615 enum dma_data_direction direction = DMA_TO_DEVICE;
616 enum ipa_cmd_opcode opcode = IPA_CMD_NONE;
617 union ipa_cmd_payload *payload;
618 dma_addr_t payload_addr;
619
620
621 payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
622
623 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
624 direction, opcode);
625}
626
627
628void ipa_cmd_pipeline_clear_add(struct gsi_trans *trans)
629{
630 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
631 struct ipa_endpoint *endpoint;
632
633
634 reinit_completion(&ipa->completion);
635
636
637 ipa_cmd_register_write_add(trans, 0, 0, 0, true);
638
639
640
641
642
643
644
645
646
647 endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX];
648 ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id);
649 ipa_cmd_ip_tag_status_add(trans);
650 ipa_cmd_transfer_add(trans);
651}
652
653
654u32 ipa_cmd_pipeline_clear_count(void)
655{
656 return 4;
657}
658
659void ipa_cmd_pipeline_clear_wait(struct ipa *ipa)
660{
661 wait_for_completion(&ipa->completion);
662}
663
664void ipa_cmd_pipeline_clear(struct ipa *ipa)
665{
666 u32 count = ipa_cmd_pipeline_clear_count();
667 struct gsi_trans *trans;
668
669 trans = ipa_cmd_trans_alloc(ipa, count);
670 if (trans) {
671 ipa_cmd_pipeline_clear_add(trans);
672 gsi_trans_commit_wait(trans);
673 ipa_cmd_pipeline_clear_wait(ipa);
674 } else {
675 dev_err(&ipa->pdev->dev,
676 "error allocating %u entry tag transaction\n", count);
677 }
678}
679
680static struct ipa_cmd_info *
681ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count)
682{
683 struct gsi_channel *channel;
684
685 channel = &endpoint->ipa->gsi.channel[endpoint->channel_id];
686
687 return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count);
688}
689
690
691struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count)
692{
693 struct ipa_endpoint *endpoint;
694 struct gsi_trans *trans;
695
696 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
697
698 trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id,
699 tre_count, DMA_NONE);
700 if (trans)
701 trans->info = ipa_cmd_info_alloc(endpoint, tre_count);
702
703 return trans;
704}
705