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22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31
32
33#define MII_KSZPHY_OMSO 0x16
34#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
35#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
36#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
37#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
38#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39
40
41#define MII_KSZPHY_INTCS 0x1B
42#define KSZPHY_INTCS_JABBER BIT(15)
43#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
44#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
45#define KSZPHY_INTCS_PARELLEL BIT(12)
46#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
47#define KSZPHY_INTCS_LINK_DOWN BIT(10)
48#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
49#define KSZPHY_INTCS_LINK_UP BIT(8)
50#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
51 KSZPHY_INTCS_LINK_DOWN)
52#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
53#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
54#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
55 KSZPHY_INTCS_LINK_UP_STATUS)
56
57
58#define KSZ8081_LMD 0x1d
59#define KSZ8081_LMD_ENABLE_TEST BIT(15)
60#define KSZ8081_LMD_STAT_NORMAL 0
61#define KSZ8081_LMD_STAT_OPEN 1
62#define KSZ8081_LMD_STAT_SHORT 2
63#define KSZ8081_LMD_STAT_FAIL 3
64#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
65
66#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
67#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
68
69
70#define MII_KSZPHY_CTRL_1 0x1e
71#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
72
73
74#define MII_KSZPHY_CTRL_2 0x1f
75#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
76
77#define KSZ8081_CTRL2_HP_MDIX BIT(15)
78#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
79#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
80#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
81#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
82#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
83#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
84
85
86#define MII_KSZPHY_EXTREG 0x0b
87#define KSZPHY_EXTREG_WRITE 0x8000
88
89#define MII_KSZPHY_EXTREG_WRITE 0x0c
90#define MII_KSZPHY_EXTREG_READ 0x0d
91
92
93#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
94#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
95#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
96
97#define PS_TO_REG 200
98
99struct kszphy_hw_stat {
100 const char *string;
101 u8 reg;
102 u8 bits;
103};
104
105static struct kszphy_hw_stat kszphy_hw_stats[] = {
106 { "phy_receive_errors", 21, 16},
107 { "phy_idle_errors", 10, 8 },
108};
109
110struct kszphy_type {
111 u32 led_mode_reg;
112 u16 interrupt_level_mask;
113 bool has_broadcast_disable;
114 bool has_nand_tree_disable;
115 bool has_rmii_ref_clk_sel;
116};
117
118struct kszphy_priv {
119 const struct kszphy_type *type;
120 int led_mode;
121 bool rmii_ref_clk_sel;
122 bool rmii_ref_clk_sel_val;
123 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
124};
125
126static const struct kszphy_type ksz8021_type = {
127 .led_mode_reg = MII_KSZPHY_CTRL_2,
128 .has_broadcast_disable = true,
129 .has_nand_tree_disable = true,
130 .has_rmii_ref_clk_sel = true,
131};
132
133static const struct kszphy_type ksz8041_type = {
134 .led_mode_reg = MII_KSZPHY_CTRL_1,
135};
136
137static const struct kszphy_type ksz8051_type = {
138 .led_mode_reg = MII_KSZPHY_CTRL_2,
139 .has_nand_tree_disable = true,
140};
141
142static const struct kszphy_type ksz8081_type = {
143 .led_mode_reg = MII_KSZPHY_CTRL_2,
144 .has_broadcast_disable = true,
145 .has_nand_tree_disable = true,
146 .has_rmii_ref_clk_sel = true,
147};
148
149static const struct kszphy_type ks8737_type = {
150 .interrupt_level_mask = BIT(14),
151};
152
153static const struct kszphy_type ksz9021_type = {
154 .interrupt_level_mask = BIT(14),
155};
156
157static int kszphy_extended_write(struct phy_device *phydev,
158 u32 regnum, u16 val)
159{
160 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
161 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
162}
163
164static int kszphy_extended_read(struct phy_device *phydev,
165 u32 regnum)
166{
167 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
168 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
169}
170
171static int kszphy_ack_interrupt(struct phy_device *phydev)
172{
173
174 int rc;
175
176 rc = phy_read(phydev, MII_KSZPHY_INTCS);
177
178 return (rc < 0) ? rc : 0;
179}
180
181static int kszphy_config_intr(struct phy_device *phydev)
182{
183 const struct kszphy_type *type = phydev->drv->driver_data;
184 int temp, err;
185 u16 mask;
186
187 if (type && type->interrupt_level_mask)
188 mask = type->interrupt_level_mask;
189 else
190 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
191
192
193 temp = phy_read(phydev, MII_KSZPHY_CTRL);
194 if (temp < 0)
195 return temp;
196 temp &= ~mask;
197 phy_write(phydev, MII_KSZPHY_CTRL, temp);
198
199
200 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
201 err = kszphy_ack_interrupt(phydev);
202 if (err)
203 return err;
204
205 temp = KSZPHY_INTCS_ALL;
206 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
207 } else {
208 temp = 0;
209 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
210 if (err)
211 return err;
212
213 err = kszphy_ack_interrupt(phydev);
214 }
215
216 return err;
217}
218
219static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
220{
221 int irq_status;
222
223 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
224 if (irq_status < 0) {
225 phy_error(phydev);
226 return IRQ_NONE;
227 }
228
229 if (!(irq_status & KSZPHY_INTCS_STATUS))
230 return IRQ_NONE;
231
232 phy_trigger_machine(phydev);
233
234 return IRQ_HANDLED;
235}
236
237static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
238{
239 int ctrl;
240
241 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
242 if (ctrl < 0)
243 return ctrl;
244
245 if (val)
246 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
247 else
248 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
249
250 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
251}
252
253static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
254{
255 int rc, temp, shift;
256
257 switch (reg) {
258 case MII_KSZPHY_CTRL_1:
259 shift = 14;
260 break;
261 case MII_KSZPHY_CTRL_2:
262 shift = 4;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 temp = phy_read(phydev, reg);
269 if (temp < 0) {
270 rc = temp;
271 goto out;
272 }
273
274 temp &= ~(3 << shift);
275 temp |= val << shift;
276 rc = phy_write(phydev, reg, temp);
277out:
278 if (rc < 0)
279 phydev_err(phydev, "failed to set led mode\n");
280
281 return rc;
282}
283
284
285
286
287static int kszphy_broadcast_disable(struct phy_device *phydev)
288{
289 int ret;
290
291 ret = phy_read(phydev, MII_KSZPHY_OMSO);
292 if (ret < 0)
293 goto out;
294
295 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
296out:
297 if (ret)
298 phydev_err(phydev, "failed to disable broadcast address\n");
299
300 return ret;
301}
302
303static int kszphy_nand_tree_disable(struct phy_device *phydev)
304{
305 int ret;
306
307 ret = phy_read(phydev, MII_KSZPHY_OMSO);
308 if (ret < 0)
309 goto out;
310
311 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
312 return 0;
313
314 ret = phy_write(phydev, MII_KSZPHY_OMSO,
315 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
316out:
317 if (ret)
318 phydev_err(phydev, "failed to disable NAND tree mode\n");
319
320 return ret;
321}
322
323
324static int kszphy_config_reset(struct phy_device *phydev)
325{
326 struct kszphy_priv *priv = phydev->priv;
327 int ret;
328
329 if (priv->rmii_ref_clk_sel) {
330 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
331 if (ret) {
332 phydev_err(phydev,
333 "failed to set rmii reference clock\n");
334 return ret;
335 }
336 }
337
338 if (priv->led_mode >= 0)
339 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
340
341 return 0;
342}
343
344static int kszphy_config_init(struct phy_device *phydev)
345{
346 struct kszphy_priv *priv = phydev->priv;
347 const struct kszphy_type *type;
348
349 if (!priv)
350 return 0;
351
352 type = priv->type;
353
354 if (type->has_broadcast_disable)
355 kszphy_broadcast_disable(phydev);
356
357 if (type->has_nand_tree_disable)
358 kszphy_nand_tree_disable(phydev);
359
360 return kszphy_config_reset(phydev);
361}
362
363static int ksz8041_fiber_mode(struct phy_device *phydev)
364{
365 struct device_node *of_node = phydev->mdio.dev.of_node;
366
367 return of_property_read_bool(of_node, "micrel,fiber-mode");
368}
369
370static int ksz8041_config_init(struct phy_device *phydev)
371{
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374
375 if (ksz8041_fiber_mode(phydev)) {
376 phydev->dev_flags |= MICREL_PHY_FXEN;
377 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
378 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
379
380 linkmode_and(phydev->supported, phydev->supported, mask);
381 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
382 phydev->supported);
383 linkmode_and(phydev->advertising, phydev->advertising, mask);
384 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
385 phydev->advertising);
386 phydev->autoneg = AUTONEG_DISABLE;
387 }
388
389 return kszphy_config_init(phydev);
390}
391
392static int ksz8041_config_aneg(struct phy_device *phydev)
393{
394
395 if (phydev->dev_flags & MICREL_PHY_FXEN) {
396 phydev->speed = SPEED_100;
397 return 0;
398 }
399
400 return genphy_config_aneg(phydev);
401}
402
403static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
404 const bool ksz_8051)
405{
406 int ret;
407
408 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
409 return 0;
410
411 ret = phy_read(phydev, MII_BMSR);
412 if (ret < 0)
413 return ret;
414
415
416
417
418
419
420 ret &= BMSR_ERCAP;
421 if (ksz_8051)
422 return ret;
423 else
424 return !ret;
425}
426
427static int ksz8051_match_phy_device(struct phy_device *phydev)
428{
429 return ksz8051_ksz8795_match_phy_device(phydev, true);
430}
431
432static int ksz8081_config_init(struct phy_device *phydev)
433{
434
435
436
437
438
439 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
440
441 return kszphy_config_init(phydev);
442}
443
444static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
445{
446 u16 val;
447
448 switch (ctrl) {
449 case ETH_TP_MDI:
450 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
451 break;
452 case ETH_TP_MDI_X:
453 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
454 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
455 break;
456 case ETH_TP_MDI_AUTO:
457 val = 0;
458 break;
459 default:
460 return 0;
461 }
462
463 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
464 KSZ8081_CTRL2_HP_MDIX |
465 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
466 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
467 KSZ8081_CTRL2_HP_MDIX | val);
468}
469
470static int ksz8081_config_aneg(struct phy_device *phydev)
471{
472 int ret;
473
474 ret = genphy_config_aneg(phydev);
475 if (ret)
476 return ret;
477
478
479
480
481
482 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
483}
484
485static int ksz8081_mdix_update(struct phy_device *phydev)
486{
487 int ret;
488
489 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
490 if (ret < 0)
491 return ret;
492
493 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
494 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
495 phydev->mdix_ctrl = ETH_TP_MDI_X;
496 else
497 phydev->mdix_ctrl = ETH_TP_MDI;
498 } else {
499 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
500 }
501
502 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
503 if (ret < 0)
504 return ret;
505
506 if (ret & KSZ8081_CTRL1_MDIX_STAT)
507 phydev->mdix = ETH_TP_MDI;
508 else
509 phydev->mdix = ETH_TP_MDI_X;
510
511 return 0;
512}
513
514static int ksz8081_read_status(struct phy_device *phydev)
515{
516 int ret;
517
518 ret = ksz8081_mdix_update(phydev);
519 if (ret < 0)
520 return ret;
521
522 return genphy_read_status(phydev);
523}
524
525static int ksz8061_config_init(struct phy_device *phydev)
526{
527 int ret;
528
529 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
530 if (ret)
531 return ret;
532
533 return kszphy_config_init(phydev);
534}
535
536static int ksz8795_match_phy_device(struct phy_device *phydev)
537{
538 return ksz8051_ksz8795_match_phy_device(phydev, false);
539}
540
541static int ksz9021_load_values_from_of(struct phy_device *phydev,
542 const struct device_node *of_node,
543 u16 reg,
544 const char *field1, const char *field2,
545 const char *field3, const char *field4)
546{
547 int val1 = -1;
548 int val2 = -2;
549 int val3 = -3;
550 int val4 = -4;
551 int newval;
552 int matches = 0;
553
554 if (!of_property_read_u32(of_node, field1, &val1))
555 matches++;
556
557 if (!of_property_read_u32(of_node, field2, &val2))
558 matches++;
559
560 if (!of_property_read_u32(of_node, field3, &val3))
561 matches++;
562
563 if (!of_property_read_u32(of_node, field4, &val4))
564 matches++;
565
566 if (!matches)
567 return 0;
568
569 if (matches < 4)
570 newval = kszphy_extended_read(phydev, reg);
571 else
572 newval = 0;
573
574 if (val1 != -1)
575 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
576
577 if (val2 != -2)
578 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
579
580 if (val3 != -3)
581 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
582
583 if (val4 != -4)
584 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
585
586 return kszphy_extended_write(phydev, reg, newval);
587}
588
589static int ksz9021_config_init(struct phy_device *phydev)
590{
591 const struct device_node *of_node;
592 const struct device *dev_walker;
593
594
595
596
597
598 dev_walker = &phydev->mdio.dev;
599 do {
600 of_node = dev_walker->of_node;
601 dev_walker = dev_walker->parent;
602
603 } while (!of_node && dev_walker);
604
605 if (of_node) {
606 ksz9021_load_values_from_of(phydev, of_node,
607 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
608 "txen-skew-ps", "txc-skew-ps",
609 "rxdv-skew-ps", "rxc-skew-ps");
610 ksz9021_load_values_from_of(phydev, of_node,
611 MII_KSZPHY_RX_DATA_PAD_SKEW,
612 "rxd0-skew-ps", "rxd1-skew-ps",
613 "rxd2-skew-ps", "rxd3-skew-ps");
614 ksz9021_load_values_from_of(phydev, of_node,
615 MII_KSZPHY_TX_DATA_PAD_SKEW,
616 "txd0-skew-ps", "txd1-skew-ps",
617 "txd2-skew-ps", "txd3-skew-ps");
618 }
619 return 0;
620}
621
622#define KSZ9031_PS_TO_REG 60
623
624
625
626#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
627#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
628
629
630#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
631#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
632#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
633
634#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
635#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
636#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
637#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
638#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
639
640#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
641#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
642#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
643#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
644#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
645
646#define MII_KSZ9031RN_CLK_PAD_SKEW 8
647#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
648#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
649
650
651
652
653
654
655
656
657#define RX_ID 0x7
658#define RX_CLK_ID 0x19
659
660
661
662
663#define RX_ND 0xc
664#define RX_CLK_ND 0x0
665
666
667#define TX_ID 0x0
668#define TX_CLK_ID 0x1f
669
670
671
672
673#define TX_ND 0x7
674#define TX_CLK_ND 0xf
675
676
677#define MII_KSZ9031RN_EDPD 0x23
678#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
679
680static int ksz9031_of_load_skew_values(struct phy_device *phydev,
681 const struct device_node *of_node,
682 u16 reg, size_t field_sz,
683 const char *field[], u8 numfields,
684 bool *update)
685{
686 int val[4] = {-1, -2, -3, -4};
687 int matches = 0;
688 u16 mask;
689 u16 maxval;
690 u16 newval;
691 int i;
692
693 for (i = 0; i < numfields; i++)
694 if (!of_property_read_u32(of_node, field[i], val + i))
695 matches++;
696
697 if (!matches)
698 return 0;
699
700 *update |= true;
701
702 if (matches < numfields)
703 newval = phy_read_mmd(phydev, 2, reg);
704 else
705 newval = 0;
706
707 maxval = (field_sz == 4) ? 0xf : 0x1f;
708 for (i = 0; i < numfields; i++)
709 if (val[i] != -(i + 1)) {
710 mask = 0xffff;
711 mask ^= maxval << (field_sz * i);
712 newval = (newval & mask) |
713 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
714 << (field_sz * i));
715 }
716
717 return phy_write_mmd(phydev, 2, reg, newval);
718}
719
720
721static int ksz9031_center_flp_timing(struct phy_device *phydev)
722{
723 int result;
724
725 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
726 0x0006);
727 if (result)
728 return result;
729
730 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
731 0x1A80);
732 if (result)
733 return result;
734
735 return genphy_restart_aneg(phydev);
736}
737
738
739static int ksz9031_enable_edpd(struct phy_device *phydev)
740{
741 int reg;
742
743 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
744 if (reg < 0)
745 return reg;
746 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
747 reg | MII_KSZ9031RN_EDPD_ENABLE);
748}
749
750static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
751{
752 u16 rx, tx, rx_clk, tx_clk;
753 int ret;
754
755 switch (phydev->interface) {
756 case PHY_INTERFACE_MODE_RGMII:
757 tx = TX_ND;
758 tx_clk = TX_CLK_ND;
759 rx = RX_ND;
760 rx_clk = RX_CLK_ND;
761 break;
762 case PHY_INTERFACE_MODE_RGMII_ID:
763 tx = TX_ID;
764 tx_clk = TX_CLK_ID;
765 rx = RX_ID;
766 rx_clk = RX_CLK_ID;
767 break;
768 case PHY_INTERFACE_MODE_RGMII_RXID:
769 tx = TX_ND;
770 tx_clk = TX_CLK_ND;
771 rx = RX_ID;
772 rx_clk = RX_CLK_ID;
773 break;
774 case PHY_INTERFACE_MODE_RGMII_TXID:
775 tx = TX_ID;
776 tx_clk = TX_CLK_ID;
777 rx = RX_ND;
778 rx_clk = RX_CLK_ND;
779 break;
780 default:
781 return 0;
782 }
783
784 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
785 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
786 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
787 if (ret < 0)
788 return ret;
789
790 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
791 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
792 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
793 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
794 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
795 if (ret < 0)
796 return ret;
797
798 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
799 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
800 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
801 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
802 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
803 if (ret < 0)
804 return ret;
805
806 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
807 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
808 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
809}
810
811static int ksz9031_config_init(struct phy_device *phydev)
812{
813 const struct device_node *of_node;
814 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
815 static const char *rx_data_skews[4] = {
816 "rxd0-skew-ps", "rxd1-skew-ps",
817 "rxd2-skew-ps", "rxd3-skew-ps"
818 };
819 static const char *tx_data_skews[4] = {
820 "txd0-skew-ps", "txd1-skew-ps",
821 "txd2-skew-ps", "txd3-skew-ps"
822 };
823 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
824 const struct device *dev_walker;
825 int result;
826
827 result = ksz9031_enable_edpd(phydev);
828 if (result < 0)
829 return result;
830
831
832
833
834
835 dev_walker = &phydev->mdio.dev;
836 do {
837 of_node = dev_walker->of_node;
838 dev_walker = dev_walker->parent;
839 } while (!of_node && dev_walker);
840
841 if (of_node) {
842 bool update = false;
843
844 if (phy_interface_is_rgmii(phydev)) {
845 result = ksz9031_config_rgmii_delay(phydev);
846 if (result < 0)
847 return result;
848 }
849
850 ksz9031_of_load_skew_values(phydev, of_node,
851 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
852 clk_skews, 2, &update);
853
854 ksz9031_of_load_skew_values(phydev, of_node,
855 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
856 control_skews, 2, &update);
857
858 ksz9031_of_load_skew_values(phydev, of_node,
859 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
860 rx_data_skews, 4, &update);
861
862 ksz9031_of_load_skew_values(phydev, of_node,
863 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
864 tx_data_skews, 4, &update);
865
866 if (update && phydev->interface != PHY_INTERFACE_MODE_RGMII)
867 phydev_warn(phydev,
868 "*-skew-ps values should be used only with phy-mode = \"rgmii\"\n");
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885 if (of_property_read_bool(of_node, "micrel,force-master")) {
886 result = phy_read(phydev, MII_CTRL1000);
887 if (result < 0)
888 goto err_force_master;
889
890
891 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
892 result = phy_write(phydev, MII_CTRL1000, result);
893 if (result < 0)
894 goto err_force_master;
895 }
896 }
897
898 return ksz9031_center_flp_timing(phydev);
899
900err_force_master:
901 phydev_err(phydev, "failed to force the phy to master mode\n");
902 return result;
903}
904
905#define KSZ9131_SKEW_5BIT_MAX 2400
906#define KSZ9131_SKEW_4BIT_MAX 800
907#define KSZ9131_OFFSET 700
908#define KSZ9131_STEP 100
909
910static int ksz9131_of_load_skew_values(struct phy_device *phydev,
911 struct device_node *of_node,
912 u16 reg, size_t field_sz,
913 char *field[], u8 numfields)
914{
915 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
916 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
917 int skewval, skewmax = 0;
918 int matches = 0;
919 u16 maxval;
920 u16 newval;
921 u16 mask;
922 int i;
923
924
925 if (field_sz == 5)
926 skewmax = KSZ9131_SKEW_5BIT_MAX;
927 else
928 skewmax = KSZ9131_SKEW_4BIT_MAX;
929
930 for (i = 0; i < numfields; i++)
931 if (!of_property_read_s32(of_node, field[i], &skewval)) {
932 if (skewval < -KSZ9131_OFFSET)
933 skewval = -KSZ9131_OFFSET;
934 else if (skewval > skewmax)
935 skewval = skewmax;
936
937 val[i] = skewval + KSZ9131_OFFSET;
938 matches++;
939 }
940
941 if (!matches)
942 return 0;
943
944 if (matches < numfields)
945 newval = phy_read_mmd(phydev, 2, reg);
946 else
947 newval = 0;
948
949 maxval = (field_sz == 4) ? 0xf : 0x1f;
950 for (i = 0; i < numfields; i++)
951 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
952 mask = 0xffff;
953 mask ^= maxval << (field_sz * i);
954 newval = (newval & mask) |
955 (((val[i] / KSZ9131_STEP) & maxval)
956 << (field_sz * i));
957 }
958
959 return phy_write_mmd(phydev, 2, reg, newval);
960}
961
962#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
963#define KSZ9131RN_RXC_DLL_CTRL 76
964#define KSZ9131RN_TXC_DLL_CTRL 77
965#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
966#define KSZ9131RN_DLL_ENABLE_DELAY 0
967#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
968
969static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
970{
971 u16 rxcdll_val, txcdll_val;
972 int ret;
973
974 switch (phydev->interface) {
975 case PHY_INTERFACE_MODE_RGMII:
976 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
977 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
978 break;
979 case PHY_INTERFACE_MODE_RGMII_ID:
980 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
981 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
982 break;
983 case PHY_INTERFACE_MODE_RGMII_RXID:
984 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
985 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
986 break;
987 case PHY_INTERFACE_MODE_RGMII_TXID:
988 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
989 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
990 break;
991 default:
992 return 0;
993 }
994
995 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
996 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
997 rxcdll_val);
998 if (ret < 0)
999 return ret;
1000
1001 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1002 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1003 txcdll_val);
1004}
1005
1006static int ksz9131_config_init(struct phy_device *phydev)
1007{
1008 struct device_node *of_node;
1009 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1010 char *rx_data_skews[4] = {
1011 "rxd0-skew-psec", "rxd1-skew-psec",
1012 "rxd2-skew-psec", "rxd3-skew-psec"
1013 };
1014 char *tx_data_skews[4] = {
1015 "txd0-skew-psec", "txd1-skew-psec",
1016 "txd2-skew-psec", "txd3-skew-psec"
1017 };
1018 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1019 const struct device *dev_walker;
1020 int ret;
1021
1022 dev_walker = &phydev->mdio.dev;
1023 do {
1024 of_node = dev_walker->of_node;
1025 dev_walker = dev_walker->parent;
1026 } while (!of_node && dev_walker);
1027
1028 if (!of_node)
1029 return 0;
1030
1031 if (phy_interface_is_rgmii(phydev)) {
1032 ret = ksz9131_config_rgmii_delay(phydev);
1033 if (ret < 0)
1034 return ret;
1035 }
1036
1037 ret = ksz9131_of_load_skew_values(phydev, of_node,
1038 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1039 clk_skews, 2);
1040 if (ret < 0)
1041 return ret;
1042
1043 ret = ksz9131_of_load_skew_values(phydev, of_node,
1044 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1045 control_skews, 2);
1046 if (ret < 0)
1047 return ret;
1048
1049 ret = ksz9131_of_load_skew_values(phydev, of_node,
1050 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1051 rx_data_skews, 4);
1052 if (ret < 0)
1053 return ret;
1054
1055 ret = ksz9131_of_load_skew_values(phydev, of_node,
1056 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1057 tx_data_skews, 4);
1058 if (ret < 0)
1059 return ret;
1060
1061 return 0;
1062}
1063
1064#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1065#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1066#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1067static int ksz8873mll_read_status(struct phy_device *phydev)
1068{
1069 int regval;
1070
1071
1072 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1073
1074 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1075
1076 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1077 phydev->duplex = DUPLEX_HALF;
1078 else
1079 phydev->duplex = DUPLEX_FULL;
1080
1081 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1082 phydev->speed = SPEED_10;
1083 else
1084 phydev->speed = SPEED_100;
1085
1086 phydev->link = 1;
1087 phydev->pause = phydev->asym_pause = 0;
1088
1089 return 0;
1090}
1091
1092static int ksz9031_get_features(struct phy_device *phydev)
1093{
1094 int ret;
1095
1096 ret = genphy_read_abilities(phydev);
1097 if (ret < 0)
1098 return ret;
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1110
1111
1112
1113
1114 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1115
1116 return 0;
1117}
1118
1119static int ksz9031_read_status(struct phy_device *phydev)
1120{
1121 int err;
1122 int regval;
1123
1124 err = genphy_read_status(phydev);
1125 if (err)
1126 return err;
1127
1128
1129
1130
1131 regval = phy_read(phydev, MII_STAT1000);
1132 if ((regval & 0xFF) == 0xFF) {
1133 phy_init_hw(phydev);
1134 phydev->link = 0;
1135 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1136 phydev->drv->config_intr(phydev);
1137 return genphy_config_aneg(phydev);
1138 }
1139
1140 return 0;
1141}
1142
1143static int ksz8873mll_config_aneg(struct phy_device *phydev)
1144{
1145 return 0;
1146}
1147
1148static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1149{
1150 u16 val;
1151
1152 switch (ctrl) {
1153 case ETH_TP_MDI:
1154 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1155 break;
1156 case ETH_TP_MDI_X:
1157
1158
1159
1160
1161
1162
1163 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1164 break;
1165 case ETH_TP_MDI_AUTO:
1166 val = 0;
1167 break;
1168 default:
1169 return 0;
1170 }
1171
1172 return phy_modify(phydev, MII_BMCR,
1173 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1174 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1175 KSZ886X_BMCR_HP_MDIX | val);
1176}
1177
1178static int ksz886x_config_aneg(struct phy_device *phydev)
1179{
1180 int ret;
1181
1182 ret = genphy_config_aneg(phydev);
1183 if (ret)
1184 return ret;
1185
1186
1187
1188
1189
1190 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1191}
1192
1193static int ksz886x_mdix_update(struct phy_device *phydev)
1194{
1195 int ret;
1196
1197 ret = phy_read(phydev, MII_BMCR);
1198 if (ret < 0)
1199 return ret;
1200
1201 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1202 if (ret & KSZ886X_BMCR_FORCE_MDI)
1203 phydev->mdix_ctrl = ETH_TP_MDI_X;
1204 else
1205 phydev->mdix_ctrl = ETH_TP_MDI;
1206 } else {
1207 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1208 }
1209
1210 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1211 if (ret < 0)
1212 return ret;
1213
1214
1215 if (ret & KSZ886X_CTRL_MDIX_STAT)
1216 phydev->mdix = ETH_TP_MDI_X;
1217 else
1218 phydev->mdix = ETH_TP_MDI;
1219
1220 return 0;
1221}
1222
1223static int ksz886x_read_status(struct phy_device *phydev)
1224{
1225 int ret;
1226
1227 ret = ksz886x_mdix_update(phydev);
1228 if (ret < 0)
1229 return ret;
1230
1231 return genphy_read_status(phydev);
1232}
1233
1234static int kszphy_get_sset_count(struct phy_device *phydev)
1235{
1236 return ARRAY_SIZE(kszphy_hw_stats);
1237}
1238
1239static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1240{
1241 int i;
1242
1243 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1244 strlcpy(data + i * ETH_GSTRING_LEN,
1245 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1246 }
1247}
1248
1249static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1250{
1251 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1252 struct kszphy_priv *priv = phydev->priv;
1253 int val;
1254 u64 ret;
1255
1256 val = phy_read(phydev, stat.reg);
1257 if (val < 0) {
1258 ret = U64_MAX;
1259 } else {
1260 val = val & ((1 << stat.bits) - 1);
1261 priv->stats[i] += val;
1262 ret = priv->stats[i];
1263 }
1264
1265 return ret;
1266}
1267
1268static void kszphy_get_stats(struct phy_device *phydev,
1269 struct ethtool_stats *stats, u64 *data)
1270{
1271 int i;
1272
1273 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1274 data[i] = kszphy_get_stat(phydev, i);
1275}
1276
1277static int kszphy_suspend(struct phy_device *phydev)
1278{
1279
1280 if (phy_interrupt_is_valid(phydev)) {
1281 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1282 if (phydev->drv->config_intr)
1283 phydev->drv->config_intr(phydev);
1284 }
1285
1286 return genphy_suspend(phydev);
1287}
1288
1289static int kszphy_resume(struct phy_device *phydev)
1290{
1291 int ret;
1292
1293 genphy_resume(phydev);
1294
1295
1296
1297
1298
1299 usleep_range(1000, 2000);
1300
1301 ret = kszphy_config_reset(phydev);
1302 if (ret)
1303 return ret;
1304
1305
1306 if (phy_interrupt_is_valid(phydev)) {
1307 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1308 if (phydev->drv->config_intr)
1309 phydev->drv->config_intr(phydev);
1310 }
1311
1312 return 0;
1313}
1314
1315static int kszphy_probe(struct phy_device *phydev)
1316{
1317 const struct kszphy_type *type = phydev->drv->driver_data;
1318 const struct device_node *np = phydev->mdio.dev.of_node;
1319 struct kszphy_priv *priv;
1320 struct clk *clk;
1321 int ret;
1322
1323 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1324 if (!priv)
1325 return -ENOMEM;
1326
1327 phydev->priv = priv;
1328
1329 priv->type = type;
1330
1331 if (type->led_mode_reg) {
1332 ret = of_property_read_u32(np, "micrel,led-mode",
1333 &priv->led_mode);
1334 if (ret)
1335 priv->led_mode = -1;
1336
1337 if (priv->led_mode > 3) {
1338 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1339 priv->led_mode);
1340 priv->led_mode = -1;
1341 }
1342 } else {
1343 priv->led_mode = -1;
1344 }
1345
1346 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1347
1348 if (!IS_ERR_OR_NULL(clk)) {
1349 unsigned long rate = clk_get_rate(clk);
1350 bool rmii_ref_clk_sel_25_mhz;
1351
1352 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1353 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1354 "micrel,rmii-reference-clock-select-25-mhz");
1355
1356 if (rate > 24500000 && rate < 25500000) {
1357 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1358 } else if (rate > 49500000 && rate < 50500000) {
1359 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1360 } else {
1361 phydev_err(phydev, "Clock rate out of range: %ld\n",
1362 rate);
1363 return -EINVAL;
1364 }
1365 }
1366
1367 if (ksz8041_fiber_mode(phydev))
1368 phydev->port = PORT_FIBRE;
1369
1370
1371 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1372 priv->rmii_ref_clk_sel = true;
1373 priv->rmii_ref_clk_sel_val = true;
1374 }
1375
1376 return 0;
1377}
1378
1379static int ksz886x_cable_test_start(struct phy_device *phydev)
1380{
1381 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1382 return -EOPNOTSUPP;
1383
1384
1385
1386
1387
1388
1389 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1390}
1391
1392static int ksz886x_cable_test_result_trans(u16 status)
1393{
1394 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1395 case KSZ8081_LMD_STAT_NORMAL:
1396 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1397 case KSZ8081_LMD_STAT_SHORT:
1398 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1399 case KSZ8081_LMD_STAT_OPEN:
1400 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1401 case KSZ8081_LMD_STAT_FAIL:
1402 fallthrough;
1403 default:
1404 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1405 }
1406}
1407
1408static bool ksz886x_cable_test_failed(u16 status)
1409{
1410 return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1411 KSZ8081_LMD_STAT_FAIL;
1412}
1413
1414static bool ksz886x_cable_test_fault_length_valid(u16 status)
1415{
1416 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1417 case KSZ8081_LMD_STAT_OPEN:
1418 fallthrough;
1419 case KSZ8081_LMD_STAT_SHORT:
1420 return true;
1421 }
1422 return false;
1423}
1424
1425static int ksz886x_cable_test_fault_length(u16 status)
1426{
1427 int dt;
1428
1429
1430
1431
1432 dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1433
1434 return (dt * 400) / 10;
1435}
1436
1437static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1438{
1439 int val, ret;
1440
1441 ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1442 !(val & KSZ8081_LMD_ENABLE_TEST),
1443 30000, 100000, true);
1444
1445 return ret < 0 ? ret : 0;
1446}
1447
1448static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1449{
1450 static const int ethtool_pair[] = {
1451 ETHTOOL_A_CABLE_PAIR_A,
1452 ETHTOOL_A_CABLE_PAIR_B,
1453 };
1454 int ret, val, mdix;
1455
1456
1457
1458
1459 if (pair == 0)
1460 mdix = ETH_TP_MDI;
1461 else
1462 mdix = ETH_TP_MDI_X;
1463
1464 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1465 case PHY_ID_KSZ8081:
1466 ret = ksz8081_config_mdix(phydev, mdix);
1467 break;
1468 case PHY_ID_KSZ886X:
1469 ret = ksz886x_config_mdix(phydev, mdix);
1470 break;
1471 default:
1472 ret = -ENODEV;
1473 }
1474
1475 if (ret)
1476 return ret;
1477
1478
1479
1480
1481 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1482 if (ret)
1483 return ret;
1484
1485 ret = ksz886x_cable_test_wait_for_completion(phydev);
1486 if (ret)
1487 return ret;
1488
1489 val = phy_read(phydev, KSZ8081_LMD);
1490 if (val < 0)
1491 return val;
1492
1493 if (ksz886x_cable_test_failed(val))
1494 return -EAGAIN;
1495
1496 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1497 ksz886x_cable_test_result_trans(val));
1498 if (ret)
1499 return ret;
1500
1501 if (!ksz886x_cable_test_fault_length_valid(val))
1502 return 0;
1503
1504 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1505 ksz886x_cable_test_fault_length(val));
1506}
1507
1508static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1509 bool *finished)
1510{
1511 unsigned long pair_mask = 0x3;
1512 int retries = 20;
1513 int pair, ret;
1514
1515 *finished = false;
1516
1517
1518 while (pair_mask && retries--) {
1519 for_each_set_bit(pair, &pair_mask, 4) {
1520 ret = ksz886x_cable_test_one_pair(phydev, pair);
1521 if (ret == -EAGAIN)
1522 continue;
1523 if (ret < 0)
1524 return ret;
1525 clear_bit(pair, &pair_mask);
1526 }
1527
1528
1529
1530
1531 if (pair_mask)
1532 msleep(2);
1533 }
1534
1535 *finished = true;
1536
1537 return ret;
1538}
1539
1540static struct phy_driver ksphy_driver[] = {
1541{
1542 .phy_id = PHY_ID_KS8737,
1543 .phy_id_mask = MICREL_PHY_ID_MASK,
1544 .name = "Micrel KS8737",
1545
1546 .driver_data = &ks8737_type,
1547 .config_init = kszphy_config_init,
1548 .config_intr = kszphy_config_intr,
1549 .handle_interrupt = kszphy_handle_interrupt,
1550 .suspend = genphy_suspend,
1551 .resume = genphy_resume,
1552}, {
1553 .phy_id = PHY_ID_KSZ8021,
1554 .phy_id_mask = 0x00ffffff,
1555 .name = "Micrel KSZ8021 or KSZ8031",
1556
1557 .driver_data = &ksz8021_type,
1558 .probe = kszphy_probe,
1559 .config_init = kszphy_config_init,
1560 .config_intr = kszphy_config_intr,
1561 .handle_interrupt = kszphy_handle_interrupt,
1562 .get_sset_count = kszphy_get_sset_count,
1563 .get_strings = kszphy_get_strings,
1564 .get_stats = kszphy_get_stats,
1565 .suspend = genphy_suspend,
1566 .resume = genphy_resume,
1567}, {
1568 .phy_id = PHY_ID_KSZ8031,
1569 .phy_id_mask = 0x00ffffff,
1570 .name = "Micrel KSZ8031",
1571
1572 .driver_data = &ksz8021_type,
1573 .probe = kszphy_probe,
1574 .config_init = kszphy_config_init,
1575 .config_intr = kszphy_config_intr,
1576 .handle_interrupt = kszphy_handle_interrupt,
1577 .get_sset_count = kszphy_get_sset_count,
1578 .get_strings = kszphy_get_strings,
1579 .get_stats = kszphy_get_stats,
1580 .suspend = genphy_suspend,
1581 .resume = genphy_resume,
1582}, {
1583 .phy_id = PHY_ID_KSZ8041,
1584 .phy_id_mask = MICREL_PHY_ID_MASK,
1585 .name = "Micrel KSZ8041",
1586
1587 .driver_data = &ksz8041_type,
1588 .probe = kszphy_probe,
1589 .config_init = ksz8041_config_init,
1590 .config_aneg = ksz8041_config_aneg,
1591 .config_intr = kszphy_config_intr,
1592 .handle_interrupt = kszphy_handle_interrupt,
1593 .get_sset_count = kszphy_get_sset_count,
1594 .get_strings = kszphy_get_strings,
1595 .get_stats = kszphy_get_stats,
1596 .suspend = genphy_suspend,
1597 .resume = genphy_resume,
1598}, {
1599 .phy_id = PHY_ID_KSZ8041RNLI,
1600 .phy_id_mask = MICREL_PHY_ID_MASK,
1601 .name = "Micrel KSZ8041RNLI",
1602
1603 .driver_data = &ksz8041_type,
1604 .probe = kszphy_probe,
1605 .config_init = kszphy_config_init,
1606 .config_intr = kszphy_config_intr,
1607 .handle_interrupt = kszphy_handle_interrupt,
1608 .get_sset_count = kszphy_get_sset_count,
1609 .get_strings = kszphy_get_strings,
1610 .get_stats = kszphy_get_stats,
1611 .suspend = genphy_suspend,
1612 .resume = genphy_resume,
1613}, {
1614 .name = "Micrel KSZ8051",
1615
1616 .driver_data = &ksz8051_type,
1617 .probe = kszphy_probe,
1618 .config_init = kszphy_config_init,
1619 .config_intr = kszphy_config_intr,
1620 .handle_interrupt = kszphy_handle_interrupt,
1621 .get_sset_count = kszphy_get_sset_count,
1622 .get_strings = kszphy_get_strings,
1623 .get_stats = kszphy_get_stats,
1624 .match_phy_device = ksz8051_match_phy_device,
1625 .suspend = genphy_suspend,
1626 .resume = genphy_resume,
1627}, {
1628 .phy_id = PHY_ID_KSZ8001,
1629 .name = "Micrel KSZ8001 or KS8721",
1630 .phy_id_mask = 0x00fffffc,
1631
1632 .driver_data = &ksz8041_type,
1633 .probe = kszphy_probe,
1634 .config_init = kszphy_config_init,
1635 .config_intr = kszphy_config_intr,
1636 .handle_interrupt = kszphy_handle_interrupt,
1637 .get_sset_count = kszphy_get_sset_count,
1638 .get_strings = kszphy_get_strings,
1639 .get_stats = kszphy_get_stats,
1640 .suspend = genphy_suspend,
1641 .resume = genphy_resume,
1642}, {
1643 .phy_id = PHY_ID_KSZ8081,
1644 .name = "Micrel KSZ8081 or KSZ8091",
1645 .phy_id_mask = MICREL_PHY_ID_MASK,
1646 .flags = PHY_POLL_CABLE_TEST,
1647
1648 .driver_data = &ksz8081_type,
1649 .probe = kszphy_probe,
1650 .config_init = ksz8081_config_init,
1651 .soft_reset = genphy_soft_reset,
1652 .config_aneg = ksz8081_config_aneg,
1653 .read_status = ksz8081_read_status,
1654 .config_intr = kszphy_config_intr,
1655 .handle_interrupt = kszphy_handle_interrupt,
1656 .get_sset_count = kszphy_get_sset_count,
1657 .get_strings = kszphy_get_strings,
1658 .get_stats = kszphy_get_stats,
1659 .suspend = kszphy_suspend,
1660 .resume = kszphy_resume,
1661 .cable_test_start = ksz886x_cable_test_start,
1662 .cable_test_get_status = ksz886x_cable_test_get_status,
1663}, {
1664 .phy_id = PHY_ID_KSZ8061,
1665 .name = "Micrel KSZ8061",
1666 .phy_id_mask = MICREL_PHY_ID_MASK,
1667
1668 .config_init = ksz8061_config_init,
1669 .config_intr = kszphy_config_intr,
1670 .handle_interrupt = kszphy_handle_interrupt,
1671 .suspend = genphy_suspend,
1672 .resume = genphy_resume,
1673}, {
1674 .phy_id = PHY_ID_KSZ9021,
1675 .phy_id_mask = 0x000ffffe,
1676 .name = "Micrel KSZ9021 Gigabit PHY",
1677
1678 .driver_data = &ksz9021_type,
1679 .probe = kszphy_probe,
1680 .get_features = ksz9031_get_features,
1681 .config_init = ksz9021_config_init,
1682 .config_intr = kszphy_config_intr,
1683 .handle_interrupt = kszphy_handle_interrupt,
1684 .get_sset_count = kszphy_get_sset_count,
1685 .get_strings = kszphy_get_strings,
1686 .get_stats = kszphy_get_stats,
1687 .suspend = genphy_suspend,
1688 .resume = genphy_resume,
1689 .read_mmd = genphy_read_mmd_unsupported,
1690 .write_mmd = genphy_write_mmd_unsupported,
1691}, {
1692 .phy_id = PHY_ID_KSZ9031,
1693 .phy_id_mask = MICREL_PHY_ID_MASK,
1694 .name = "Micrel KSZ9031 Gigabit PHY",
1695 .driver_data = &ksz9021_type,
1696 .probe = kszphy_probe,
1697 .get_features = ksz9031_get_features,
1698 .config_init = ksz9031_config_init,
1699 .soft_reset = genphy_soft_reset,
1700 .read_status = ksz9031_read_status,
1701 .config_intr = kszphy_config_intr,
1702 .handle_interrupt = kszphy_handle_interrupt,
1703 .get_sset_count = kszphy_get_sset_count,
1704 .get_strings = kszphy_get_strings,
1705 .get_stats = kszphy_get_stats,
1706 .suspend = genphy_suspend,
1707 .resume = kszphy_resume,
1708}, {
1709 .phy_id = PHY_ID_LAN8814,
1710 .phy_id_mask = MICREL_PHY_ID_MASK,
1711 .name = "Microchip INDY Gigabit Quad PHY",
1712 .driver_data = &ksz9021_type,
1713 .probe = kszphy_probe,
1714 .soft_reset = genphy_soft_reset,
1715 .read_status = ksz9031_read_status,
1716 .get_sset_count = kszphy_get_sset_count,
1717 .get_strings = kszphy_get_strings,
1718 .get_stats = kszphy_get_stats,
1719 .suspend = genphy_suspend,
1720 .resume = kszphy_resume,
1721}, {
1722 .phy_id = PHY_ID_KSZ9131,
1723 .phy_id_mask = MICREL_PHY_ID_MASK,
1724 .name = "Microchip KSZ9131 Gigabit PHY",
1725
1726 .driver_data = &ksz9021_type,
1727 .probe = kszphy_probe,
1728 .config_init = ksz9131_config_init,
1729 .config_intr = kszphy_config_intr,
1730 .handle_interrupt = kszphy_handle_interrupt,
1731 .get_sset_count = kszphy_get_sset_count,
1732 .get_strings = kszphy_get_strings,
1733 .get_stats = kszphy_get_stats,
1734 .suspend = genphy_suspend,
1735 .resume = kszphy_resume,
1736}, {
1737 .phy_id = PHY_ID_KSZ8873MLL,
1738 .phy_id_mask = MICREL_PHY_ID_MASK,
1739 .name = "Micrel KSZ8873MLL Switch",
1740
1741 .config_init = kszphy_config_init,
1742 .config_aneg = ksz8873mll_config_aneg,
1743 .read_status = ksz8873mll_read_status,
1744 .suspend = genphy_suspend,
1745 .resume = genphy_resume,
1746}, {
1747 .phy_id = PHY_ID_KSZ886X,
1748 .phy_id_mask = MICREL_PHY_ID_MASK,
1749 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
1750
1751 .flags = PHY_POLL_CABLE_TEST,
1752 .config_init = kszphy_config_init,
1753 .config_aneg = ksz886x_config_aneg,
1754 .read_status = ksz886x_read_status,
1755 .suspend = genphy_suspend,
1756 .resume = genphy_resume,
1757 .cable_test_start = ksz886x_cable_test_start,
1758 .cable_test_get_status = ksz886x_cable_test_get_status,
1759}, {
1760 .name = "Micrel KSZ87XX Switch",
1761
1762 .config_init = kszphy_config_init,
1763 .match_phy_device = ksz8795_match_phy_device,
1764 .suspend = genphy_suspend,
1765 .resume = genphy_resume,
1766}, {
1767 .phy_id = PHY_ID_KSZ9477,
1768 .phy_id_mask = MICREL_PHY_ID_MASK,
1769 .name = "Microchip KSZ9477",
1770
1771 .config_init = kszphy_config_init,
1772 .suspend = genphy_suspend,
1773 .resume = genphy_resume,
1774} };
1775
1776module_phy_driver(ksphy_driver);
1777
1778MODULE_DESCRIPTION("Micrel PHY driver");
1779MODULE_AUTHOR("David J. Choi");
1780MODULE_LICENSE("GPL");
1781
1782static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1783 { PHY_ID_KSZ9021, 0x000ffffe },
1784 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1785 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1786 { PHY_ID_KSZ8001, 0x00fffffc },
1787 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1788 { PHY_ID_KSZ8021, 0x00ffffff },
1789 { PHY_ID_KSZ8031, 0x00ffffff },
1790 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1791 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1792 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1793 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1794 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1795 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1796 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
1797 { }
1798};
1799
1800MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1801
