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2
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4
5
6#include <linux/delay.h>
7#include <linux/ethtool.h>
8#include <linux/ethtool_netlink.h>
9#include <linux/kernel.h>
10#include <linux/mdio.h>
11#include <linux/mii.h>
12#include <linux/module.h>
13#include <linux/phy.h>
14#include <linux/hwmon.h>
15#include <linux/bitfield.h>
16#include <linux/of_mdio.h>
17#include <linux/of_irq.h>
18
19#define PHY_ID_MASK 0xfffffff0
20#define PHY_ID_TJA1100 0x0180dc40
21#define PHY_ID_TJA1101 0x0180dd00
22#define PHY_ID_TJA1102 0x0180dc80
23
24#define MII_ECTRL 17
25#define MII_ECTRL_LINK_CONTROL BIT(15)
26#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
27#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
28#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
29#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
30#define MII_ECTRL_CABLE_TEST BIT(5)
31#define MII_ECTRL_CONFIG_EN BIT(2)
32#define MII_ECTRL_WAKE_REQUEST BIT(0)
33
34#define MII_CFG1 18
35#define MII_CFG1_MASTER_SLAVE BIT(15)
36#define MII_CFG1_AUTO_OP BIT(14)
37#define MII_CFG1_SLEEP_CONFIRM BIT(6)
38#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
39#define MII_CFG1_LED_MODE_LINKUP 0
40#define MII_CFG1_LED_ENABLE BIT(3)
41
42#define MII_CFG2 19
43#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
44#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
45
46#define MII_INTSRC 21
47#define MII_INTSRC_LINK_FAIL BIT(10)
48#define MII_INTSRC_LINK_UP BIT(9)
49#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
50#define MII_INTSRC_UV_ERR BIT(3)
51#define MII_INTSRC_TEMP_ERR BIT(1)
52
53#define MII_INTEN 22
54#define MII_INTEN_LINK_FAIL BIT(10)
55#define MII_INTEN_LINK_UP BIT(9)
56#define MII_INTEN_UV_ERR BIT(3)
57#define MII_INTEN_TEMP_ERR BIT(1)
58
59#define MII_COMMSTAT 23
60#define MII_COMMSTAT_LINK_UP BIT(15)
61#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
62#define MII_COMMSTAT_SQI_MAX 7
63
64#define MII_GENSTAT 24
65#define MII_GENSTAT_PLL_LOCKED BIT(14)
66
67#define MII_EXTSTAT 25
68#define MII_EXTSTAT_SHORT_DETECT BIT(8)
69#define MII_EXTSTAT_OPEN_DETECT BIT(7)
70#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
71
72#define MII_COMMCFG 27
73#define MII_COMMCFG_AUTO_OP BIT(15)
74
75struct tja11xx_priv {
76 char *hwmon_name;
77 struct device *hwmon_dev;
78 struct phy_device *phydev;
79 struct work_struct phy_register_work;
80};
81
82struct tja11xx_phy_stats {
83 const char *string;
84 u8 reg;
85 u8 off;
86 u16 mask;
87};
88
89static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
90 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
91 { "phy_polarity_detect", 25, 6, BIT(6) },
92 { "phy_open_detect", 25, 7, BIT(7) },
93 { "phy_short_detect", 25, 8, BIT(8) },
94 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
95 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
96};
97
98static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
99{
100 int val;
101
102 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
103 150, 30000, false);
104}
105
106static int phy_modify_check(struct phy_device *phydev, u8 reg,
107 u16 mask, u16 set)
108{
109 int ret;
110
111 ret = phy_modify(phydev, reg, mask, set);
112 if (ret)
113 return ret;
114
115 return tja11xx_check(phydev, reg, mask, set);
116}
117
118static int tja11xx_enable_reg_write(struct phy_device *phydev)
119{
120 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
121}
122
123static int tja11xx_enable_link_control(struct phy_device *phydev)
124{
125 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
126}
127
128static int tja11xx_disable_link_control(struct phy_device *phydev)
129{
130 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
131}
132
133static int tja11xx_wakeup(struct phy_device *phydev)
134{
135 int ret;
136
137 ret = phy_read(phydev, MII_ECTRL);
138 if (ret < 0)
139 return ret;
140
141 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
142 case MII_ECTRL_POWER_MODE_NO_CHANGE:
143 break;
144 case MII_ECTRL_POWER_MODE_NORMAL:
145 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
146 if (ret)
147 return ret;
148
149 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
150 if (ret)
151 return ret;
152 break;
153 case MII_ECTRL_POWER_MODE_STANDBY:
154 ret = phy_modify_check(phydev, MII_ECTRL,
155 MII_ECTRL_POWER_MODE_MASK,
156 MII_ECTRL_POWER_MODE_STANDBY);
157 if (ret)
158 return ret;
159
160 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
161 MII_ECTRL_POWER_MODE_NORMAL);
162 if (ret)
163 return ret;
164
165 ret = phy_modify_check(phydev, MII_GENSTAT,
166 MII_GENSTAT_PLL_LOCKED,
167 MII_GENSTAT_PLL_LOCKED);
168 if (ret)
169 return ret;
170
171 return tja11xx_enable_link_control(phydev);
172 default:
173 break;
174 }
175
176 return 0;
177}
178
179static int tja11xx_soft_reset(struct phy_device *phydev)
180{
181 int ret;
182
183 ret = tja11xx_enable_reg_write(phydev);
184 if (ret)
185 return ret;
186
187 return genphy_soft_reset(phydev);
188}
189
190static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
191{
192 bool finished = false;
193 int ret;
194
195 if (phydev->link)
196 return 0;
197
198 if (!phydev->drv->cable_test_start ||
199 !phydev->drv->cable_test_get_status)
200 return 0;
201
202 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
203 if (ret)
204 return ret;
205
206 ret = phydev->drv->cable_test_start(phydev);
207 if (ret)
208 return ret;
209
210
211 usleep_range(100, 200);
212
213 ret = phydev->drv->cable_test_get_status(phydev, &finished);
214 if (ret)
215 return ret;
216
217 if (finished)
218 ethnl_cable_test_finished(phydev);
219
220 return 0;
221}
222
223static int tja11xx_config_aneg(struct phy_device *phydev)
224{
225 int ret, changed = 0;
226 u16 ctl = 0;
227
228 switch (phydev->master_slave_set) {
229 case MASTER_SLAVE_CFG_MASTER_FORCE:
230 ctl |= MII_CFG1_MASTER_SLAVE;
231 break;
232 case MASTER_SLAVE_CFG_SLAVE_FORCE:
233 break;
234 case MASTER_SLAVE_CFG_UNKNOWN:
235 case MASTER_SLAVE_CFG_UNSUPPORTED:
236 goto do_test;
237 default:
238 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
239 return -ENOTSUPP;
240 }
241
242 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
243 if (changed < 0)
244 return changed;
245
246do_test:
247 ret = tja11xx_config_aneg_cable_test(phydev);
248 if (ret)
249 return ret;
250
251 return __genphy_config_aneg(phydev, changed);
252}
253
254static int tja11xx_config_init(struct phy_device *phydev)
255{
256 int ret;
257
258 ret = tja11xx_enable_reg_write(phydev);
259 if (ret)
260 return ret;
261
262 phydev->autoneg = AUTONEG_DISABLE;
263 phydev->speed = SPEED_100;
264 phydev->duplex = DUPLEX_FULL;
265
266 switch (phydev->phy_id & PHY_ID_MASK) {
267 case PHY_ID_TJA1100:
268 ret = phy_modify(phydev, MII_CFG1,
269 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
270 MII_CFG1_LED_ENABLE,
271 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
272 MII_CFG1_LED_ENABLE);
273 if (ret)
274 return ret;
275 break;
276 case PHY_ID_TJA1101:
277 case PHY_ID_TJA1102:
278 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
279 if (ret)
280 return ret;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
287 if (ret)
288 return ret;
289
290 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
291 MII_CFG2_SLEEP_REQUEST_TO_16MS);
292 if (ret)
293 return ret;
294
295 ret = tja11xx_wakeup(phydev);
296 if (ret < 0)
297 return ret;
298
299
300 ret = phy_read(phydev, MII_INTSRC);
301 if (ret < 0)
302 return ret;
303
304 return 0;
305}
306
307static int tja11xx_read_status(struct phy_device *phydev)
308{
309 int ret;
310
311 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
312 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
313
314 ret = genphy_update_link(phydev);
315 if (ret)
316 return ret;
317
318 ret = phy_read(phydev, MII_CFG1);
319 if (ret < 0)
320 return ret;
321
322 if (ret & MII_CFG1_MASTER_SLAVE)
323 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
324 else
325 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
326
327 if (phydev->link) {
328 ret = phy_read(phydev, MII_COMMSTAT);
329 if (ret < 0)
330 return ret;
331
332 if (!(ret & MII_COMMSTAT_LINK_UP))
333 phydev->link = 0;
334 }
335
336 return 0;
337}
338
339static int tja11xx_get_sqi(struct phy_device *phydev)
340{
341 int ret;
342
343 ret = phy_read(phydev, MII_COMMSTAT);
344 if (ret < 0)
345 return ret;
346
347 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
348}
349
350static int tja11xx_get_sqi_max(struct phy_device *phydev)
351{
352 return MII_COMMSTAT_SQI_MAX;
353}
354
355static int tja11xx_get_sset_count(struct phy_device *phydev)
356{
357 return ARRAY_SIZE(tja11xx_hw_stats);
358}
359
360static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
361{
362 int i;
363
364 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
365 strncpy(data + i * ETH_GSTRING_LEN,
366 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
367 }
368}
369
370static void tja11xx_get_stats(struct phy_device *phydev,
371 struct ethtool_stats *stats, u64 *data)
372{
373 int i, ret;
374
375 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
376 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
377 if (ret < 0)
378 data[i] = U64_MAX;
379 else {
380 data[i] = ret & tja11xx_hw_stats[i].mask;
381 data[i] >>= tja11xx_hw_stats[i].off;
382 }
383 }
384}
385
386static int tja11xx_hwmon_read(struct device *dev,
387 enum hwmon_sensor_types type,
388 u32 attr, int channel, long *value)
389{
390 struct phy_device *phydev = dev_get_drvdata(dev);
391 int ret;
392
393 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
394 ret = phy_read(phydev, MII_INTSRC);
395 if (ret < 0)
396 return ret;
397
398 *value = !!(ret & MII_INTSRC_TEMP_ERR);
399 return 0;
400 }
401
402 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
403 ret = phy_read(phydev, MII_INTSRC);
404 if (ret < 0)
405 return ret;
406
407 *value = !!(ret & MII_INTSRC_UV_ERR);
408 return 0;
409 }
410
411 return -EOPNOTSUPP;
412}
413
414static umode_t tja11xx_hwmon_is_visible(const void *data,
415 enum hwmon_sensor_types type,
416 u32 attr, int channel)
417{
418 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
419 return 0444;
420
421 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
422 return 0444;
423
424 return 0;
425}
426
427static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
428 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
429 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
430 NULL
431};
432
433static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
434 .is_visible = tja11xx_hwmon_is_visible,
435 .read = tja11xx_hwmon_read,
436};
437
438static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
439 .ops = &tja11xx_hwmon_hwmon_ops,
440 .info = tja11xx_hwmon_info,
441};
442
443static int tja11xx_hwmon_register(struct phy_device *phydev,
444 struct tja11xx_priv *priv)
445{
446 struct device *dev = &phydev->mdio.dev;
447 int i;
448
449 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
450 if (!priv->hwmon_name)
451 return -ENOMEM;
452
453 for (i = 0; priv->hwmon_name[i]; i++)
454 if (hwmon_is_bad_char(priv->hwmon_name[i]))
455 priv->hwmon_name[i] = '_';
456
457 priv->hwmon_dev =
458 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
459 phydev,
460 &tja11xx_hwmon_chip_info,
461 NULL);
462
463 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
464}
465
466static int tja11xx_probe(struct phy_device *phydev)
467{
468 struct device *dev = &phydev->mdio.dev;
469 struct tja11xx_priv *priv;
470
471 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
472 if (!priv)
473 return -ENOMEM;
474
475 priv->phydev = phydev;
476
477 return tja11xx_hwmon_register(phydev, priv);
478}
479
480static void tja1102_p1_register(struct work_struct *work)
481{
482 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
483 phy_register_work);
484 struct phy_device *phydev_phy0 = priv->phydev;
485 struct mii_bus *bus = phydev_phy0->mdio.bus;
486 struct device *dev = &phydev_phy0->mdio.dev;
487 struct device_node *np = dev->of_node;
488 struct device_node *child;
489 int ret;
490
491 for_each_available_child_of_node(np, child) {
492 struct phy_device *phy;
493 int addr;
494
495 addr = of_mdio_parse_addr(dev, child);
496 if (addr < 0) {
497 dev_err(dev, "Can't parse addr\n");
498 continue;
499 } else if (addr != phydev_phy0->mdio.addr + 1) {
500
501
502
503
504 dev_err(dev, "Unexpected address. Should be: %i\n",
505 phydev_phy0->mdio.addr + 1);
506 continue;
507 }
508
509 if (mdiobus_is_registered_device(bus, addr)) {
510 dev_err(dev, "device is already registered\n");
511 continue;
512 }
513
514
515 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
516 if (IS_ERR(phy)) {
517 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
518 addr);
519 continue;
520 }
521
522
523
524
525 phy->mdio.dev.parent = dev;
526
527 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
528 if (ret) {
529
530
531
532
533
534 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
535 ret);
536 phy_device_free(phy);
537 }
538 }
539}
540
541static int tja1102_p0_probe(struct phy_device *phydev)
542{
543 struct device *dev = &phydev->mdio.dev;
544 struct tja11xx_priv *priv;
545 int ret;
546
547 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
548 if (!priv)
549 return -ENOMEM;
550
551 priv->phydev = phydev;
552 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
553
554 ret = tja11xx_hwmon_register(phydev, priv);
555 if (ret)
556 return ret;
557
558 schedule_work(&priv->phy_register_work);
559
560 return 0;
561}
562
563static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
564{
565 int ret;
566
567 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
568 return 0;
569
570 ret = phy_read(phydev, MII_PHYSID2);
571 if (ret < 0)
572 return ret;
573
574
575
576
577 if (port0)
578 return ret ? 1 : 0;
579
580 return !ret;
581}
582
583static int tja1102_p0_match_phy_device(struct phy_device *phydev)
584{
585 return tja1102_match_phy_device(phydev, true);
586}
587
588static int tja1102_p1_match_phy_device(struct phy_device *phydev)
589{
590 return tja1102_match_phy_device(phydev, false);
591}
592
593static int tja11xx_ack_interrupt(struct phy_device *phydev)
594{
595 int ret;
596
597 ret = phy_read(phydev, MII_INTSRC);
598
599 return (ret < 0) ? ret : 0;
600}
601
602static int tja11xx_config_intr(struct phy_device *phydev)
603{
604 int value = 0;
605 int err;
606
607 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
608 err = tja11xx_ack_interrupt(phydev);
609 if (err)
610 return err;
611
612 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP |
613 MII_INTEN_UV_ERR | MII_INTEN_TEMP_ERR;
614 err = phy_write(phydev, MII_INTEN, value);
615 } else {
616 err = phy_write(phydev, MII_INTEN, value);
617 if (err)
618 return err;
619
620 err = tja11xx_ack_interrupt(phydev);
621 }
622
623 return err;
624}
625
626static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
627{
628 struct device *dev = &phydev->mdio.dev;
629 int irq_status;
630
631 irq_status = phy_read(phydev, MII_INTSRC);
632 if (irq_status < 0) {
633 phy_error(phydev);
634 return IRQ_NONE;
635 }
636
637 if (irq_status & MII_INTSRC_TEMP_ERR)
638 dev_warn(dev, "Overtemperature error detected (temp > 155C°).\n");
639 if (irq_status & MII_INTSRC_UV_ERR)
640 dev_warn(dev, "Undervoltage error detected.\n");
641
642 if (!(irq_status & MII_INTSRC_MASK))
643 return IRQ_NONE;
644
645 phy_trigger_machine(phydev);
646
647 return IRQ_HANDLED;
648}
649
650static int tja11xx_cable_test_start(struct phy_device *phydev)
651{
652 int ret;
653
654 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
655 if (ret)
656 return ret;
657
658 ret = tja11xx_wakeup(phydev);
659 if (ret < 0)
660 return ret;
661
662 ret = tja11xx_disable_link_control(phydev);
663 if (ret < 0)
664 return ret;
665
666 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
667}
668
669
670
671
672
673
674
675
676
677
678
679
680
681static int tja11xx_cable_test_report_trans(u32 result)
682{
683 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
684
685 if ((result & mask) == mask) {
686
687 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
688 } else if ((result & mask) == 0) {
689 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
690 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
691 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
692 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
693 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
694 } else {
695 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
696 }
697}
698
699static int tja11xx_cable_test_report(struct phy_device *phydev)
700{
701 int ret;
702
703 ret = phy_read(phydev, MII_EXTSTAT);
704 if (ret < 0)
705 return ret;
706
707 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
708 tja11xx_cable_test_report_trans(ret));
709
710 return 0;
711}
712
713static int tja11xx_cable_test_get_status(struct phy_device *phydev,
714 bool *finished)
715{
716 int ret;
717
718 *finished = false;
719
720 ret = phy_read(phydev, MII_ECTRL);
721 if (ret < 0)
722 return ret;
723
724 if (!(ret & MII_ECTRL_CABLE_TEST)) {
725 *finished = true;
726
727 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
728 if (ret)
729 return ret;
730
731 return tja11xx_cable_test_report(phydev);
732 }
733
734 return 0;
735}
736
737static struct phy_driver tja11xx_driver[] = {
738 {
739 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
740 .name = "NXP TJA1100",
741 .features = PHY_BASIC_T1_FEATURES,
742 .probe = tja11xx_probe,
743 .soft_reset = tja11xx_soft_reset,
744 .config_aneg = tja11xx_config_aneg,
745 .config_init = tja11xx_config_init,
746 .read_status = tja11xx_read_status,
747 .get_sqi = tja11xx_get_sqi,
748 .get_sqi_max = tja11xx_get_sqi_max,
749 .suspend = genphy_suspend,
750 .resume = genphy_resume,
751 .set_loopback = genphy_loopback,
752
753 .get_sset_count = tja11xx_get_sset_count,
754 .get_strings = tja11xx_get_strings,
755 .get_stats = tja11xx_get_stats,
756 }, {
757 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
758 .name = "NXP TJA1101",
759 .features = PHY_BASIC_T1_FEATURES,
760 .probe = tja11xx_probe,
761 .soft_reset = tja11xx_soft_reset,
762 .config_aneg = tja11xx_config_aneg,
763 .config_init = tja11xx_config_init,
764 .read_status = tja11xx_read_status,
765 .get_sqi = tja11xx_get_sqi,
766 .get_sqi_max = tja11xx_get_sqi_max,
767 .suspend = genphy_suspend,
768 .resume = genphy_resume,
769 .set_loopback = genphy_loopback,
770
771 .get_sset_count = tja11xx_get_sset_count,
772 .get_strings = tja11xx_get_strings,
773 .get_stats = tja11xx_get_stats,
774 }, {
775 .name = "NXP TJA1102 Port 0",
776 .features = PHY_BASIC_T1_FEATURES,
777 .flags = PHY_POLL_CABLE_TEST,
778 .probe = tja1102_p0_probe,
779 .soft_reset = tja11xx_soft_reset,
780 .config_aneg = tja11xx_config_aneg,
781 .config_init = tja11xx_config_init,
782 .read_status = tja11xx_read_status,
783 .get_sqi = tja11xx_get_sqi,
784 .get_sqi_max = tja11xx_get_sqi_max,
785 .match_phy_device = tja1102_p0_match_phy_device,
786 .suspend = genphy_suspend,
787 .resume = genphy_resume,
788 .set_loopback = genphy_loopback,
789
790 .get_sset_count = tja11xx_get_sset_count,
791 .get_strings = tja11xx_get_strings,
792 .get_stats = tja11xx_get_stats,
793 .config_intr = tja11xx_config_intr,
794 .handle_interrupt = tja11xx_handle_interrupt,
795 .cable_test_start = tja11xx_cable_test_start,
796 .cable_test_get_status = tja11xx_cable_test_get_status,
797 }, {
798 .name = "NXP TJA1102 Port 1",
799 .features = PHY_BASIC_T1_FEATURES,
800 .flags = PHY_POLL_CABLE_TEST,
801
802 .soft_reset = tja11xx_soft_reset,
803 .config_aneg = tja11xx_config_aneg,
804 .config_init = tja11xx_config_init,
805 .read_status = tja11xx_read_status,
806 .get_sqi = tja11xx_get_sqi,
807 .get_sqi_max = tja11xx_get_sqi_max,
808 .match_phy_device = tja1102_p1_match_phy_device,
809 .suspend = genphy_suspend,
810 .resume = genphy_resume,
811 .set_loopback = genphy_loopback,
812
813 .get_sset_count = tja11xx_get_sset_count,
814 .get_strings = tja11xx_get_strings,
815 .get_stats = tja11xx_get_stats,
816 .config_intr = tja11xx_config_intr,
817 .handle_interrupt = tja11xx_handle_interrupt,
818 .cable_test_start = tja11xx_cable_test_start,
819 .cable_test_get_status = tja11xx_cable_test_get_status,
820 }
821};
822
823module_phy_driver(tja11xx_driver);
824
825static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
826 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
827 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
828 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
829 { }
830};
831
832MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
833
834MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
835MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
836MODULE_LICENSE("GPL");
837
