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8#include <linux/acpi.h>
9#include <linux/ethtool.h>
10#include <linux/export.h>
11#include <linux/gpio/consumer.h>
12#include <linux/netdevice.h>
13#include <linux/of.h>
14#include <linux/of_mdio.h>
15#include <linux/phy.h>
16#include <linux/phy_fixed.h>
17#include <linux/phylink.h>
18#include <linux/rtnetlink.h>
19#include <linux/spinlock.h>
20#include <linux/timer.h>
21#include <linux/workqueue.h>
22
23#include "sfp.h"
24#include "swphy.h"
25
26#define SUPPORTED_INTERFACES \
27 (SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE | \
28 SUPPORTED_BNC | SUPPORTED_AUI | SUPPORTED_Backplane)
29#define ADVERTISED_INTERFACES \
30 (ADVERTISED_TP | ADVERTISED_MII | ADVERTISED_FIBRE | \
31 ADVERTISED_BNC | ADVERTISED_AUI | ADVERTISED_Backplane)
32
33enum {
34 PHYLINK_DISABLE_STOPPED,
35 PHYLINK_DISABLE_LINK,
36 PHYLINK_DISABLE_MAC_WOL,
37};
38
39
40
41
42struct phylink {
43
44 struct net_device *netdev;
45 const struct phylink_mac_ops *mac_ops;
46 const struct phylink_pcs_ops *pcs_ops;
47 struct phylink_config *config;
48 struct phylink_pcs *pcs;
49 struct device *dev;
50 unsigned int old_link_state:1;
51
52 unsigned long phylink_disable_state;
53 struct phy_device *phydev;
54 phy_interface_t link_interface;
55 u8 cfg_link_an_mode;
56 u8 cur_link_an_mode;
57 u8 link_port;
58 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
59
60
61 struct phylink_link_state link_config;
62
63
64 phy_interface_t cur_interface;
65
66 struct gpio_desc *link_gpio;
67 unsigned int link_irq;
68 struct timer_list link_poll;
69 void (*get_fixed_state)(struct net_device *dev,
70 struct phylink_link_state *s);
71
72 struct mutex state_mutex;
73 struct phylink_link_state phy_state;
74 struct work_struct resolve;
75
76 bool mac_link_dropped;
77
78 struct sfp_bus *sfp_bus;
79 bool sfp_may_have_phy;
80 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
81 u8 sfp_port;
82};
83
84#define phylink_printk(level, pl, fmt, ...) \
85 do { \
86 if ((pl)->config->type == PHYLINK_NETDEV) \
87 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
88 else if ((pl)->config->type == PHYLINK_DEV) \
89 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
90 } while (0)
91
92#define phylink_err(pl, fmt, ...) \
93 phylink_printk(KERN_ERR, pl, fmt, ##__VA_ARGS__)
94#define phylink_warn(pl, fmt, ...) \
95 phylink_printk(KERN_WARNING, pl, fmt, ##__VA_ARGS__)
96#define phylink_info(pl, fmt, ...) \
97 phylink_printk(KERN_INFO, pl, fmt, ##__VA_ARGS__)
98#if defined(CONFIG_DYNAMIC_DEBUG)
99#define phylink_dbg(pl, fmt, ...) \
100do { \
101 if ((pl)->config->type == PHYLINK_NETDEV) \
102 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
103 else if ((pl)->config->type == PHYLINK_DEV) \
104 dev_dbg((pl)->dev, fmt, ##__VA_ARGS__); \
105} while (0)
106#elif defined(DEBUG)
107#define phylink_dbg(pl, fmt, ...) \
108 phylink_printk(KERN_DEBUG, pl, fmt, ##__VA_ARGS__)
109#else
110#define phylink_dbg(pl, fmt, ...) \
111({ \
112 if (0) \
113 phylink_printk(KERN_DEBUG, pl, fmt, ##__VA_ARGS__); \
114})
115#endif
116
117
118
119
120
121
122
123
124void phylink_set_port_modes(unsigned long *mask)
125{
126 phylink_set(mask, TP);
127 phylink_set(mask, AUI);
128 phylink_set(mask, MII);
129 phylink_set(mask, FIBRE);
130 phylink_set(mask, BNC);
131 phylink_set(mask, Backplane);
132}
133EXPORT_SYMBOL_GPL(phylink_set_port_modes);
134
135static int phylink_is_empty_linkmode(const unsigned long *linkmode)
136{
137 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp) = { 0, };
138
139 phylink_set_port_modes(tmp);
140 phylink_set(tmp, Autoneg);
141 phylink_set(tmp, Pause);
142 phylink_set(tmp, Asym_Pause);
143
144 return linkmode_subset(linkmode, tmp);
145}
146
147static const char *phylink_an_mode_str(unsigned int mode)
148{
149 static const char *modestr[] = {
150 [MLO_AN_PHY] = "phy",
151 [MLO_AN_FIXED] = "fixed",
152 [MLO_AN_INBAND] = "inband",
153 };
154
155 return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
156}
157
158static int phylink_validate(struct phylink *pl, unsigned long *supported,
159 struct phylink_link_state *state)
160{
161 pl->mac_ops->validate(pl->config, supported, state);
162
163 return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
164}
165
166static int phylink_parse_fixedlink(struct phylink *pl,
167 struct fwnode_handle *fwnode)
168{
169 struct fwnode_handle *fixed_node;
170 const struct phy_setting *s;
171 struct gpio_desc *desc;
172 u32 speed;
173 int ret;
174
175 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
176 if (fixed_node) {
177 ret = fwnode_property_read_u32(fixed_node, "speed", &speed);
178
179 pl->link_config.speed = speed;
180 pl->link_config.duplex = DUPLEX_HALF;
181
182 if (fwnode_property_read_bool(fixed_node, "full-duplex"))
183 pl->link_config.duplex = DUPLEX_FULL;
184
185
186
187
188 if (fwnode_property_read_bool(fixed_node, "pause"))
189 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
190 pl->link_config.lp_advertising);
191 if (fwnode_property_read_bool(fixed_node, "asym-pause"))
192 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
193 pl->link_config.lp_advertising);
194
195 if (ret == 0) {
196 desc = fwnode_gpiod_get_index(fixed_node, "link", 0,
197 GPIOD_IN, "?");
198
199 if (!IS_ERR(desc))
200 pl->link_gpio = desc;
201 else if (desc == ERR_PTR(-EPROBE_DEFER))
202 ret = -EPROBE_DEFER;
203 }
204 fwnode_handle_put(fixed_node);
205
206 if (ret)
207 return ret;
208 } else {
209 u32 prop[5];
210
211 ret = fwnode_property_read_u32_array(fwnode, "fixed-link",
212 NULL, 0);
213 if (ret != ARRAY_SIZE(prop)) {
214 phylink_err(pl, "broken fixed-link?\n");
215 return -EINVAL;
216 }
217
218 ret = fwnode_property_read_u32_array(fwnode, "fixed-link",
219 prop, ARRAY_SIZE(prop));
220 if (!ret) {
221 pl->link_config.duplex = prop[1] ?
222 DUPLEX_FULL : DUPLEX_HALF;
223 pl->link_config.speed = prop[2];
224 if (prop[3])
225 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
226 pl->link_config.lp_advertising);
227 if (prop[4])
228 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
229 pl->link_config.lp_advertising);
230 }
231 }
232
233 if (pl->link_config.speed > SPEED_1000 &&
234 pl->link_config.duplex != DUPLEX_FULL)
235 phylink_warn(pl, "fixed link specifies half duplex for %dMbps link?\n",
236 pl->link_config.speed);
237
238 bitmap_fill(pl->supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
239 linkmode_copy(pl->link_config.advertising, pl->supported);
240 phylink_validate(pl, pl->supported, &pl->link_config);
241
242 s = phy_lookup_setting(pl->link_config.speed, pl->link_config.duplex,
243 pl->supported, true);
244 linkmode_zero(pl->supported);
245 phylink_set(pl->supported, MII);
246 phylink_set(pl->supported, Pause);
247 phylink_set(pl->supported, Asym_Pause);
248 phylink_set(pl->supported, Autoneg);
249 if (s) {
250 __set_bit(s->bit, pl->supported);
251 __set_bit(s->bit, pl->link_config.lp_advertising);
252 } else {
253 phylink_warn(pl, "fixed link %s duplex %dMbps not recognised\n",
254 pl->link_config.duplex == DUPLEX_FULL ? "full" : "half",
255 pl->link_config.speed);
256 }
257
258 linkmode_and(pl->link_config.advertising, pl->link_config.advertising,
259 pl->supported);
260
261 pl->link_config.link = 1;
262 pl->link_config.an_complete = 1;
263
264 return 0;
265}
266
267static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
268{
269 struct fwnode_handle *dn;
270 const char *managed;
271
272 dn = fwnode_get_named_child_node(fwnode, "fixed-link");
273 if (dn || fwnode_property_present(fwnode, "fixed-link"))
274 pl->cfg_link_an_mode = MLO_AN_FIXED;
275 fwnode_handle_put(dn);
276
277 if ((fwnode_property_read_string(fwnode, "managed", &managed) == 0 &&
278 strcmp(managed, "in-band-status") == 0) ||
279 pl->config->ovr_an_inband) {
280 if (pl->cfg_link_an_mode == MLO_AN_FIXED) {
281 phylink_err(pl,
282 "can't use both fixed-link and in-band-status\n");
283 return -EINVAL;
284 }
285
286 linkmode_zero(pl->supported);
287 phylink_set(pl->supported, MII);
288 phylink_set(pl->supported, Autoneg);
289 phylink_set(pl->supported, Asym_Pause);
290 phylink_set(pl->supported, Pause);
291 pl->link_config.an_enabled = true;
292 pl->cfg_link_an_mode = MLO_AN_INBAND;
293
294 switch (pl->link_config.interface) {
295 case PHY_INTERFACE_MODE_SGMII:
296 case PHY_INTERFACE_MODE_QSGMII:
297 phylink_set(pl->supported, 10baseT_Half);
298 phylink_set(pl->supported, 10baseT_Full);
299 phylink_set(pl->supported, 100baseT_Half);
300 phylink_set(pl->supported, 100baseT_Full);
301 phylink_set(pl->supported, 1000baseT_Half);
302 phylink_set(pl->supported, 1000baseT_Full);
303 break;
304
305 case PHY_INTERFACE_MODE_1000BASEX:
306 phylink_set(pl->supported, 1000baseX_Full);
307 break;
308
309 case PHY_INTERFACE_MODE_2500BASEX:
310 phylink_set(pl->supported, 2500baseX_Full);
311 break;
312
313 case PHY_INTERFACE_MODE_5GBASER:
314 phylink_set(pl->supported, 5000baseT_Full);
315 break;
316
317 case PHY_INTERFACE_MODE_25GBASER:
318 phylink_set(pl->supported, 25000baseCR_Full);
319 phylink_set(pl->supported, 25000baseKR_Full);
320 phylink_set(pl->supported, 25000baseSR_Full);
321 fallthrough;
322 case PHY_INTERFACE_MODE_USXGMII:
323 case PHY_INTERFACE_MODE_10GKR:
324 case PHY_INTERFACE_MODE_10GBASER:
325 phylink_set(pl->supported, 10baseT_Half);
326 phylink_set(pl->supported, 10baseT_Full);
327 phylink_set(pl->supported, 100baseT_Half);
328 phylink_set(pl->supported, 100baseT_Full);
329 phylink_set(pl->supported, 1000baseT_Half);
330 phylink_set(pl->supported, 1000baseT_Full);
331 phylink_set(pl->supported, 1000baseX_Full);
332 phylink_set(pl->supported, 1000baseKX_Full);
333 phylink_set(pl->supported, 2500baseT_Full);
334 phylink_set(pl->supported, 2500baseX_Full);
335 phylink_set(pl->supported, 5000baseT_Full);
336 phylink_set(pl->supported, 10000baseT_Full);
337 phylink_set(pl->supported, 10000baseKR_Full);
338 phylink_set(pl->supported, 10000baseKX4_Full);
339 phylink_set(pl->supported, 10000baseCR_Full);
340 phylink_set(pl->supported, 10000baseSR_Full);
341 phylink_set(pl->supported, 10000baseLR_Full);
342 phylink_set(pl->supported, 10000baseLRM_Full);
343 phylink_set(pl->supported, 10000baseER_Full);
344 break;
345
346 case PHY_INTERFACE_MODE_XLGMII:
347 phylink_set(pl->supported, 25000baseCR_Full);
348 phylink_set(pl->supported, 25000baseKR_Full);
349 phylink_set(pl->supported, 25000baseSR_Full);
350 phylink_set(pl->supported, 40000baseKR4_Full);
351 phylink_set(pl->supported, 40000baseCR4_Full);
352 phylink_set(pl->supported, 40000baseSR4_Full);
353 phylink_set(pl->supported, 40000baseLR4_Full);
354 phylink_set(pl->supported, 50000baseCR2_Full);
355 phylink_set(pl->supported, 50000baseKR2_Full);
356 phylink_set(pl->supported, 50000baseSR2_Full);
357 phylink_set(pl->supported, 50000baseKR_Full);
358 phylink_set(pl->supported, 50000baseSR_Full);
359 phylink_set(pl->supported, 50000baseCR_Full);
360 phylink_set(pl->supported, 50000baseLR_ER_FR_Full);
361 phylink_set(pl->supported, 50000baseDR_Full);
362 phylink_set(pl->supported, 100000baseKR4_Full);
363 phylink_set(pl->supported, 100000baseSR4_Full);
364 phylink_set(pl->supported, 100000baseCR4_Full);
365 phylink_set(pl->supported, 100000baseLR4_ER4_Full);
366 phylink_set(pl->supported, 100000baseKR2_Full);
367 phylink_set(pl->supported, 100000baseSR2_Full);
368 phylink_set(pl->supported, 100000baseCR2_Full);
369 phylink_set(pl->supported, 100000baseLR2_ER2_FR2_Full);
370 phylink_set(pl->supported, 100000baseDR2_Full);
371 break;
372
373 default:
374 phylink_err(pl,
375 "incorrect link mode %s for in-band status\n",
376 phy_modes(pl->link_config.interface));
377 return -EINVAL;
378 }
379
380 linkmode_copy(pl->link_config.advertising, pl->supported);
381
382 if (phylink_validate(pl, pl->supported, &pl->link_config)) {
383 phylink_err(pl,
384 "failed to validate link configuration for in-band status\n");
385 return -EINVAL;
386 }
387
388
389 pl->link_config.an_enabled = phylink_test(pl->supported, Autoneg);
390 }
391
392 return 0;
393}
394
395static void phylink_apply_manual_flow(struct phylink *pl,
396 struct phylink_link_state *state)
397{
398
399 if (!state->an_enabled)
400 state->pause &= ~MLO_PAUSE_AN;
401
402
403 if (!(pl->link_config.pause & MLO_PAUSE_AN))
404 state->pause = pl->link_config.pause;
405}
406
407static void phylink_resolve_flow(struct phylink_link_state *state)
408{
409 bool tx_pause, rx_pause;
410
411 state->pause = MLO_PAUSE_NONE;
412 if (state->duplex == DUPLEX_FULL) {
413 linkmode_resolve_pause(state->advertising,
414 state->lp_advertising,
415 &tx_pause, &rx_pause);
416 if (tx_pause)
417 state->pause |= MLO_PAUSE_TX;
418 if (rx_pause)
419 state->pause |= MLO_PAUSE_RX;
420 }
421}
422
423static void phylink_mac_config(struct phylink *pl,
424 const struct phylink_link_state *state)
425{
426 phylink_dbg(pl,
427 "%s: mode=%s/%s/%s/%s adv=%*pb pause=%02x link=%u an=%u\n",
428 __func__, phylink_an_mode_str(pl->cur_link_an_mode),
429 phy_modes(state->interface),
430 phy_speed_to_str(state->speed),
431 phy_duplex_to_str(state->duplex),
432 __ETHTOOL_LINK_MODE_MASK_NBITS, state->advertising,
433 state->pause, state->link, state->an_enabled);
434
435 pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, state);
436}
437
438static void phylink_mac_pcs_an_restart(struct phylink *pl)
439{
440 if (pl->link_config.an_enabled &&
441 phy_interface_mode_is_8023z(pl->link_config.interface) &&
442 phylink_autoneg_inband(pl->cur_link_an_mode)) {
443 if (pl->pcs_ops)
444 pl->pcs_ops->pcs_an_restart(pl->pcs);
445 else
446 pl->mac_ops->mac_an_restart(pl->config);
447 }
448}
449
450static void phylink_major_config(struct phylink *pl, bool restart,
451 const struct phylink_link_state *state)
452{
453 int err;
454
455 phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
456
457 if (pl->mac_ops->mac_prepare) {
458 err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode,
459 state->interface);
460 if (err < 0) {
461 phylink_err(pl, "mac_prepare failed: %pe\n",
462 ERR_PTR(err));
463 return;
464 }
465 }
466
467 phylink_mac_config(pl, state);
468
469 if (pl->pcs_ops) {
470 err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
471 state->interface,
472 state->advertising,
473 !!(pl->link_config.pause &
474 MLO_PAUSE_AN));
475 if (err < 0)
476 phylink_err(pl, "pcs_config failed: %pe\n",
477 ERR_PTR(err));
478 if (err > 0)
479 restart = true;
480 }
481 if (restart)
482 phylink_mac_pcs_an_restart(pl);
483
484 if (pl->mac_ops->mac_finish) {
485 err = pl->mac_ops->mac_finish(pl->config, pl->cur_link_an_mode,
486 state->interface);
487 if (err < 0)
488 phylink_err(pl, "mac_finish failed: %pe\n",
489 ERR_PTR(err));
490 }
491}
492
493
494
495
496
497
498
499static int phylink_change_inband_advert(struct phylink *pl)
500{
501 int ret;
502
503 if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state))
504 return 0;
505
506 if (!pl->pcs_ops) {
507
508 phylink_mac_config(pl, &pl->link_config);
509 phylink_mac_pcs_an_restart(pl);
510 return 0;
511 }
512
513 phylink_dbg(pl, "%s: mode=%s/%s adv=%*pb pause=%02x\n", __func__,
514 phylink_an_mode_str(pl->cur_link_an_mode),
515 phy_modes(pl->link_config.interface),
516 __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising,
517 pl->link_config.pause);
518
519
520
521
522
523 ret = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
524 pl->link_config.interface,
525 pl->link_config.advertising,
526 !!(pl->link_config.pause & MLO_PAUSE_AN));
527 if (ret < 0)
528 return ret;
529
530 if (ret > 0)
531 phylink_mac_pcs_an_restart(pl);
532
533 return 0;
534}
535
536static void phylink_mac_pcs_get_state(struct phylink *pl,
537 struct phylink_link_state *state)
538{
539 linkmode_copy(state->advertising, pl->link_config.advertising);
540 linkmode_zero(state->lp_advertising);
541 state->interface = pl->link_config.interface;
542 state->an_enabled = pl->link_config.an_enabled;
543 state->speed = SPEED_UNKNOWN;
544 state->duplex = DUPLEX_UNKNOWN;
545 state->pause = MLO_PAUSE_NONE;
546 state->an_complete = 0;
547 state->link = 1;
548
549 if (pl->pcs_ops)
550 pl->pcs_ops->pcs_get_state(pl->pcs, state);
551 else if (pl->mac_ops->mac_pcs_get_state)
552 pl->mac_ops->mac_pcs_get_state(pl->config, state);
553 else
554 state->link = 0;
555}
556
557
558
559
560static void phylink_get_fixed_state(struct phylink *pl,
561 struct phylink_link_state *state)
562{
563 *state = pl->link_config;
564 if (pl->config->get_fixed_state)
565 pl->config->get_fixed_state(pl->config, state);
566 else if (pl->link_gpio)
567 state->link = !!gpiod_get_value_cansleep(pl->link_gpio);
568
569 phylink_resolve_flow(state);
570}
571
572static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
573{
574 struct phylink_link_state link_state;
575
576 switch (pl->cur_link_an_mode) {
577 case MLO_AN_PHY:
578 link_state = pl->phy_state;
579 break;
580
581 case MLO_AN_FIXED:
582 phylink_get_fixed_state(pl, &link_state);
583 break;
584
585 case MLO_AN_INBAND:
586 link_state = pl->link_config;
587 if (link_state.interface == PHY_INTERFACE_MODE_SGMII)
588 link_state.pause = MLO_PAUSE_NONE;
589 break;
590
591 default:
592 return;
593 }
594
595 link_state.link = false;
596
597 phylink_apply_manual_flow(pl, &link_state);
598 phylink_major_config(pl, force_restart, &link_state);
599}
600
601static const char *phylink_pause_to_str(int pause)
602{
603 switch (pause & MLO_PAUSE_TXRX_MASK) {
604 case MLO_PAUSE_TX | MLO_PAUSE_RX:
605 return "rx/tx";
606 case MLO_PAUSE_TX:
607 return "tx";
608 case MLO_PAUSE_RX:
609 return "rx";
610 default:
611 return "off";
612 }
613}
614
615static void phylink_link_up(struct phylink *pl,
616 struct phylink_link_state link_state)
617{
618 struct net_device *ndev = pl->netdev;
619
620 pl->cur_interface = link_state.interface;
621
622 if (pl->pcs_ops && pl->pcs_ops->pcs_link_up)
623 pl->pcs_ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode,
624 pl->cur_interface,
625 link_state.speed, link_state.duplex);
626
627 pl->mac_ops->mac_link_up(pl->config, pl->phydev,
628 pl->cur_link_an_mode, pl->cur_interface,
629 link_state.speed, link_state.duplex,
630 !!(link_state.pause & MLO_PAUSE_TX),
631 !!(link_state.pause & MLO_PAUSE_RX));
632
633 if (ndev)
634 netif_carrier_on(ndev);
635
636 phylink_info(pl,
637 "Link is Up - %s/%s - flow control %s\n",
638 phy_speed_to_str(link_state.speed),
639 phy_duplex_to_str(link_state.duplex),
640 phylink_pause_to_str(link_state.pause));
641}
642
643static void phylink_link_down(struct phylink *pl)
644{
645 struct net_device *ndev = pl->netdev;
646
647 if (ndev)
648 netif_carrier_off(ndev);
649 pl->mac_ops->mac_link_down(pl->config, pl->cur_link_an_mode,
650 pl->cur_interface);
651 phylink_info(pl, "Link is Down\n");
652}
653
654static void phylink_resolve(struct work_struct *w)
655{
656 struct phylink *pl = container_of(w, struct phylink, resolve);
657 struct phylink_link_state link_state;
658 struct net_device *ndev = pl->netdev;
659 bool mac_config = false;
660 bool cur_link_state;
661
662 mutex_lock(&pl->state_mutex);
663 if (pl->netdev)
664 cur_link_state = netif_carrier_ok(ndev);
665 else
666 cur_link_state = pl->old_link_state;
667
668 if (pl->phylink_disable_state) {
669 pl->mac_link_dropped = false;
670 link_state.link = false;
671 } else if (pl->mac_link_dropped) {
672 link_state.link = false;
673 } else {
674 switch (pl->cur_link_an_mode) {
675 case MLO_AN_PHY:
676 link_state = pl->phy_state;
677 phylink_apply_manual_flow(pl, &link_state);
678 mac_config = link_state.link;
679 break;
680
681 case MLO_AN_FIXED:
682 phylink_get_fixed_state(pl, &link_state);
683 mac_config = link_state.link;
684 break;
685
686 case MLO_AN_INBAND:
687 phylink_mac_pcs_get_state(pl, &link_state);
688
689
690
691
692 if (pl->phydev)
693 link_state.link &= pl->phy_state.link;
694
695
696 if (pl->phydev && pl->phy_state.link) {
697 link_state.interface = pl->phy_state.interface;
698
699
700
701
702 link_state.pause = pl->phy_state.pause;
703 mac_config = true;
704 }
705 phylink_apply_manual_flow(pl, &link_state);
706 break;
707 }
708 }
709
710 if (mac_config) {
711 if (link_state.interface != pl->link_config.interface) {
712
713
714
715 if (cur_link_state) {
716 phylink_link_down(pl);
717 cur_link_state = false;
718 }
719 phylink_major_config(pl, false, &link_state);
720 pl->link_config.interface = link_state.interface;
721 } else if (!pl->pcs_ops) {
722
723
724
725
726
727
728 phylink_mac_config(pl, &link_state);
729 }
730 }
731
732 if (link_state.link != cur_link_state) {
733 pl->old_link_state = link_state.link;
734 if (!link_state.link)
735 phylink_link_down(pl);
736 else
737 phylink_link_up(pl, link_state);
738 }
739 if (!link_state.link && pl->mac_link_dropped) {
740 pl->mac_link_dropped = false;
741 queue_work(system_power_efficient_wq, &pl->resolve);
742 }
743 mutex_unlock(&pl->state_mutex);
744}
745
746static void phylink_run_resolve(struct phylink *pl)
747{
748 if (!pl->phylink_disable_state)
749 queue_work(system_power_efficient_wq, &pl->resolve);
750}
751
752static void phylink_run_resolve_and_disable(struct phylink *pl, int bit)
753{
754 unsigned long state = pl->phylink_disable_state;
755
756 set_bit(bit, &pl->phylink_disable_state);
757 if (state == 0) {
758 queue_work(system_power_efficient_wq, &pl->resolve);
759 flush_work(&pl->resolve);
760 }
761}
762
763static void phylink_fixed_poll(struct timer_list *t)
764{
765 struct phylink *pl = container_of(t, struct phylink, link_poll);
766
767 mod_timer(t, jiffies + HZ);
768
769 phylink_run_resolve(pl);
770}
771
772static const struct sfp_upstream_ops sfp_phylink_ops;
773
774static int phylink_register_sfp(struct phylink *pl,
775 struct fwnode_handle *fwnode)
776{
777 struct sfp_bus *bus;
778 int ret;
779
780 if (!fwnode)
781 return 0;
782
783 bus = sfp_bus_find_fwnode(fwnode);
784 if (IS_ERR(bus)) {
785 ret = PTR_ERR(bus);
786 phylink_err(pl, "unable to attach SFP bus: %d\n", ret);
787 return ret;
788 }
789
790 pl->sfp_bus = bus;
791
792 ret = sfp_bus_add_upstream(bus, pl, &sfp_phylink_ops);
793 sfp_bus_put(bus);
794
795 return ret;
796}
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814struct phylink *phylink_create(struct phylink_config *config,
815 struct fwnode_handle *fwnode,
816 phy_interface_t iface,
817 const struct phylink_mac_ops *mac_ops)
818{
819 struct phylink *pl;
820 int ret;
821
822 pl = kzalloc(sizeof(*pl), GFP_KERNEL);
823 if (!pl)
824 return ERR_PTR(-ENOMEM);
825
826 mutex_init(&pl->state_mutex);
827 INIT_WORK(&pl->resolve, phylink_resolve);
828
829 pl->config = config;
830 if (config->type == PHYLINK_NETDEV) {
831 pl->netdev = to_net_dev(config->dev);
832 } else if (config->type == PHYLINK_DEV) {
833 pl->dev = config->dev;
834 } else {
835 kfree(pl);
836 return ERR_PTR(-EINVAL);
837 }
838
839 pl->phy_state.interface = iface;
840 pl->link_interface = iface;
841 if (iface == PHY_INTERFACE_MODE_MOCA)
842 pl->link_port = PORT_BNC;
843 else
844 pl->link_port = PORT_MII;
845 pl->link_config.interface = iface;
846 pl->link_config.pause = MLO_PAUSE_AN;
847 pl->link_config.speed = SPEED_UNKNOWN;
848 pl->link_config.duplex = DUPLEX_UNKNOWN;
849 pl->link_config.an_enabled = true;
850 pl->mac_ops = mac_ops;
851 __set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
852 timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
853
854 bitmap_fill(pl->supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
855 linkmode_copy(pl->link_config.advertising, pl->supported);
856 phylink_validate(pl, pl->supported, &pl->link_config);
857
858 ret = phylink_parse_mode(pl, fwnode);
859 if (ret < 0) {
860 kfree(pl);
861 return ERR_PTR(ret);
862 }
863
864 if (pl->cfg_link_an_mode == MLO_AN_FIXED) {
865 ret = phylink_parse_fixedlink(pl, fwnode);
866 if (ret < 0) {
867 kfree(pl);
868 return ERR_PTR(ret);
869 }
870 }
871
872 pl->cur_link_an_mode = pl->cfg_link_an_mode;
873
874 ret = phylink_register_sfp(pl, fwnode);
875 if (ret < 0) {
876 kfree(pl);
877 return ERR_PTR(ret);
878 }
879
880 return pl;
881}
882EXPORT_SYMBOL_GPL(phylink_create);
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898void phylink_set_pcs(struct phylink *pl, struct phylink_pcs *pcs)
899{
900 pl->pcs = pcs;
901 pl->pcs_ops = pcs->ops;
902}
903EXPORT_SYMBOL_GPL(phylink_set_pcs);
904
905
906
907
908
909
910
911
912
913
914void phylink_destroy(struct phylink *pl)
915{
916 sfp_bus_del_upstream(pl->sfp_bus);
917 if (pl->link_gpio)
918 gpiod_put(pl->link_gpio);
919
920 cancel_work_sync(&pl->resolve);
921 kfree(pl);
922}
923EXPORT_SYMBOL_GPL(phylink_destroy);
924
925static void phylink_phy_change(struct phy_device *phydev, bool up)
926{
927 struct phylink *pl = phydev->phylink;
928 bool tx_pause, rx_pause;
929
930 phy_get_pause(phydev, &tx_pause, &rx_pause);
931
932 mutex_lock(&pl->state_mutex);
933 pl->phy_state.speed = phydev->speed;
934 pl->phy_state.duplex = phydev->duplex;
935 pl->phy_state.pause = MLO_PAUSE_NONE;
936 if (tx_pause)
937 pl->phy_state.pause |= MLO_PAUSE_TX;
938 if (rx_pause)
939 pl->phy_state.pause |= MLO_PAUSE_RX;
940 pl->phy_state.interface = phydev->interface;
941 pl->phy_state.link = up;
942 mutex_unlock(&pl->state_mutex);
943
944 phylink_run_resolve(pl);
945
946 phylink_dbg(pl, "phy link %s %s/%s/%s/%s\n", up ? "up" : "down",
947 phy_modes(phydev->interface),
948 phy_speed_to_str(phydev->speed),
949 phy_duplex_to_str(phydev->duplex),
950 phylink_pause_to_str(pl->phy_state.pause));
951}
952
953static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
954 phy_interface_t interface)
955{
956 struct phylink_link_state config;
957 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
958 char *irq_str;
959 int ret;
960
961
962
963
964
965
966
967
968 phy_support_asym_pause(phy);
969
970 memset(&config, 0, sizeof(config));
971 linkmode_copy(supported, phy->supported);
972 linkmode_copy(config.advertising, phy->advertising);
973
974
975
976
977
978
979 if (phy->is_c45 &&
980 interface != PHY_INTERFACE_MODE_RXAUI &&
981 interface != PHY_INTERFACE_MODE_XAUI &&
982 interface != PHY_INTERFACE_MODE_USXGMII)
983 config.interface = PHY_INTERFACE_MODE_NA;
984 else
985 config.interface = interface;
986
987 ret = phylink_validate(pl, supported, &config);
988 if (ret) {
989 phylink_warn(pl, "validation of %s with support %*pb and advertisement %*pb failed: %d\n",
990 phy_modes(config.interface),
991 __ETHTOOL_LINK_MODE_MASK_NBITS, phy->supported,
992 __ETHTOOL_LINK_MODE_MASK_NBITS, config.advertising,
993 ret);
994 return ret;
995 }
996
997 phy->phylink = pl;
998 phy->phy_link_change = phylink_phy_change;
999
1000 irq_str = phy_attached_info_irq(phy);
1001 phylink_info(pl,
1002 "PHY [%s] driver [%s] (irq=%s)\n",
1003 dev_name(&phy->mdio.dev), phy->drv->name, irq_str);
1004 kfree(irq_str);
1005
1006 mutex_lock(&phy->lock);
1007 mutex_lock(&pl->state_mutex);
1008 pl->phydev = phy;
1009 pl->phy_state.interface = interface;
1010 pl->phy_state.pause = MLO_PAUSE_NONE;
1011 pl->phy_state.speed = SPEED_UNKNOWN;
1012 pl->phy_state.duplex = DUPLEX_UNKNOWN;
1013 linkmode_copy(pl->supported, supported);
1014 linkmode_copy(pl->link_config.advertising, config.advertising);
1015
1016
1017 linkmode_copy(phy->advertising, config.advertising);
1018 mutex_unlock(&pl->state_mutex);
1019 mutex_unlock(&phy->lock);
1020
1021 phylink_dbg(pl,
1022 "phy: setting supported %*pb advertising %*pb\n",
1023 __ETHTOOL_LINK_MODE_MASK_NBITS, pl->supported,
1024 __ETHTOOL_LINK_MODE_MASK_NBITS, phy->advertising);
1025
1026 if (phy_interrupt_is_valid(phy))
1027 phy_request_interrupt(phy);
1028
1029 return 0;
1030}
1031
1032static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy,
1033 phy_interface_t interface)
1034{
1035 if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED ||
1036 (pl->cfg_link_an_mode == MLO_AN_INBAND &&
1037 phy_interface_mode_is_8023z(interface))))
1038 return -EINVAL;
1039
1040 if (pl->phydev)
1041 return -EBUSY;
1042
1043 return phy_attach_direct(pl->netdev, phy, 0, interface);
1044}
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061int phylink_connect_phy(struct phylink *pl, struct phy_device *phy)
1062{
1063 int ret;
1064
1065
1066 if (pl->link_interface == PHY_INTERFACE_MODE_NA) {
1067 pl->link_interface = phy->interface;
1068 pl->link_config.interface = pl->link_interface;
1069 }
1070
1071 ret = phylink_attach_phy(pl, phy, pl->link_interface);
1072 if (ret < 0)
1073 return ret;
1074
1075 ret = phylink_bringup_phy(pl, phy, pl->link_config.interface);
1076 if (ret)
1077 phy_detach(phy);
1078
1079 return ret;
1080}
1081EXPORT_SYMBOL_GPL(phylink_connect_phy);
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095int phylink_of_phy_connect(struct phylink *pl, struct device_node *dn,
1096 u32 flags)
1097{
1098 return phylink_fwnode_phy_connect(pl, of_fwnode_handle(dn), flags);
1099}
1100EXPORT_SYMBOL_GPL(phylink_of_phy_connect);
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113int phylink_fwnode_phy_connect(struct phylink *pl,
1114 struct fwnode_handle *fwnode,
1115 u32 flags)
1116{
1117 struct fwnode_handle *phy_fwnode;
1118 struct phy_device *phy_dev;
1119 int ret;
1120
1121
1122 if (pl->cfg_link_an_mode == MLO_AN_FIXED ||
1123 (pl->cfg_link_an_mode == MLO_AN_INBAND &&
1124 phy_interface_mode_is_8023z(pl->link_interface)))
1125 return 0;
1126
1127 phy_fwnode = fwnode_get_phy_node(fwnode);
1128 if (IS_ERR(phy_fwnode)) {
1129 if (pl->cfg_link_an_mode == MLO_AN_PHY)
1130 return -ENODEV;
1131 return 0;
1132 }
1133
1134 phy_dev = fwnode_phy_find_device(phy_fwnode);
1135
1136 fwnode_handle_put(phy_fwnode);
1137 if (!phy_dev)
1138 return -ENODEV;
1139
1140 ret = phy_attach_direct(pl->netdev, phy_dev, flags,
1141 pl->link_interface);
1142 if (ret) {
1143 phy_device_free(phy_dev);
1144 return ret;
1145 }
1146
1147 ret = phylink_bringup_phy(pl, phy_dev, pl->link_config.interface);
1148 if (ret)
1149 phy_detach(phy_dev);
1150
1151 return ret;
1152}
1153EXPORT_SYMBOL_GPL(phylink_fwnode_phy_connect);
1154
1155
1156
1157
1158
1159
1160
1161
1162void phylink_disconnect_phy(struct phylink *pl)
1163{
1164 struct phy_device *phy;
1165
1166 ASSERT_RTNL();
1167
1168 phy = pl->phydev;
1169 if (phy) {
1170 mutex_lock(&phy->lock);
1171 mutex_lock(&pl->state_mutex);
1172 pl->phydev = NULL;
1173 mutex_unlock(&pl->state_mutex);
1174 mutex_unlock(&phy->lock);
1175 flush_work(&pl->resolve);
1176
1177 phy_disconnect(phy);
1178 }
1179}
1180EXPORT_SYMBOL_GPL(phylink_disconnect_phy);
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190void phylink_mac_change(struct phylink *pl, bool up)
1191{
1192 if (!up)
1193 pl->mac_link_dropped = true;
1194 phylink_run_resolve(pl);
1195 phylink_dbg(pl, "mac link %s\n", up ? "up" : "down");
1196}
1197EXPORT_SYMBOL_GPL(phylink_mac_change);
1198
1199static irqreturn_t phylink_link_handler(int irq, void *data)
1200{
1201 struct phylink *pl = data;
1202
1203 phylink_run_resolve(pl);
1204
1205 return IRQ_HANDLED;
1206}
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216void phylink_start(struct phylink *pl)
1217{
1218 bool poll = false;
1219
1220 ASSERT_RTNL();
1221
1222 phylink_info(pl, "configuring for %s/%s link mode\n",
1223 phylink_an_mode_str(pl->cur_link_an_mode),
1224 phy_modes(pl->link_config.interface));
1225
1226
1227 if (pl->netdev)
1228 netif_carrier_off(pl->netdev);
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238 phylink_mac_initial_config(pl, true);
1239
1240 clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
1241 phylink_run_resolve(pl);
1242
1243 if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
1244 int irq = gpiod_to_irq(pl->link_gpio);
1245
1246 if (irq > 0) {
1247 if (!request_irq(irq, phylink_link_handler,
1248 IRQF_TRIGGER_RISING |
1249 IRQF_TRIGGER_FALLING,
1250 "netdev link", pl))
1251 pl->link_irq = irq;
1252 else
1253 irq = 0;
1254 }
1255 if (irq <= 0)
1256 poll = true;
1257 }
1258
1259 switch (pl->cfg_link_an_mode) {
1260 case MLO_AN_FIXED:
1261 poll |= pl->config->poll_fixed_state;
1262 break;
1263 case MLO_AN_INBAND:
1264 poll |= pl->config->pcs_poll;
1265 if (pl->pcs)
1266 poll |= pl->pcs->poll;
1267 break;
1268 }
1269 if (poll)
1270 mod_timer(&pl->link_poll, jiffies + HZ);
1271 if (pl->phydev)
1272 phy_start(pl->phydev);
1273 if (pl->sfp_bus)
1274 sfp_upstream_start(pl->sfp_bus);
1275}
1276EXPORT_SYMBOL_GPL(phylink_start);
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290void phylink_stop(struct phylink *pl)
1291{
1292 ASSERT_RTNL();
1293
1294 if (pl->sfp_bus)
1295 sfp_upstream_stop(pl->sfp_bus);
1296 if (pl->phydev)
1297 phy_stop(pl->phydev);
1298 del_timer_sync(&pl->link_poll);
1299 if (pl->link_irq) {
1300 free_irq(pl->link_irq, pl);
1301 pl->link_irq = 0;
1302 }
1303
1304 phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
1305}
1306EXPORT_SYMBOL_GPL(phylink_stop);
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321void phylink_suspend(struct phylink *pl, bool mac_wol)
1322{
1323 ASSERT_RTNL();
1324
1325 if (mac_wol && (!pl->netdev || pl->netdev->wol_enabled)) {
1326
1327 mutex_lock(&pl->state_mutex);
1328
1329
1330 __set_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state);
1331
1332
1333
1334
1335
1336 netif_carrier_off(pl->netdev);
1337
1338
1339
1340
1341 mutex_unlock(&pl->state_mutex);
1342 } else {
1343 phylink_stop(pl);
1344 }
1345}
1346EXPORT_SYMBOL_GPL(phylink_suspend);
1347
1348
1349
1350
1351
1352
1353
1354
1355void phylink_resume(struct phylink *pl)
1356{
1357 ASSERT_RTNL();
1358
1359 if (test_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state)) {
1360
1361
1362
1363
1364
1365
1366
1367
1368 mutex_lock(&pl->state_mutex);
1369 phylink_link_down(pl);
1370 mutex_unlock(&pl->state_mutex);
1371
1372
1373
1374
1375 phylink_mac_initial_config(pl, true);
1376
1377
1378 clear_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state);
1379 phylink_run_resolve(pl);
1380 } else {
1381 phylink_start(pl);
1382 }
1383}
1384EXPORT_SYMBOL_GPL(phylink_resume);
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395void phylink_ethtool_get_wol(struct phylink *pl, struct ethtool_wolinfo *wol)
1396{
1397 ASSERT_RTNL();
1398
1399 wol->supported = 0;
1400 wol->wolopts = 0;
1401
1402 if (pl->phydev)
1403 phy_ethtool_get_wol(pl->phydev, wol);
1404}
1405EXPORT_SYMBOL_GPL(phylink_ethtool_get_wol);
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418int phylink_ethtool_set_wol(struct phylink *pl, struct ethtool_wolinfo *wol)
1419{
1420 int ret = -EOPNOTSUPP;
1421
1422 ASSERT_RTNL();
1423
1424 if (pl->phydev)
1425 ret = phy_ethtool_set_wol(pl->phydev, wol);
1426
1427 return ret;
1428}
1429EXPORT_SYMBOL_GPL(phylink_ethtool_set_wol);
1430
1431static void phylink_merge_link_mode(unsigned long *dst, const unsigned long *b)
1432{
1433 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask);
1434
1435 linkmode_zero(mask);
1436 phylink_set_port_modes(mask);
1437
1438 linkmode_and(dst, dst, mask);
1439 linkmode_or(dst, dst, b);
1440}
1441
1442static void phylink_get_ksettings(const struct phylink_link_state *state,
1443 struct ethtool_link_ksettings *kset)
1444{
1445 phylink_merge_link_mode(kset->link_modes.advertising, state->advertising);
1446 linkmode_copy(kset->link_modes.lp_advertising, state->lp_advertising);
1447 kset->base.speed = state->speed;
1448 kset->base.duplex = state->duplex;
1449 kset->base.autoneg = state->an_enabled ? AUTONEG_ENABLE :
1450 AUTONEG_DISABLE;
1451}
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462int phylink_ethtool_ksettings_get(struct phylink *pl,
1463 struct ethtool_link_ksettings *kset)
1464{
1465 struct phylink_link_state link_state;
1466
1467 ASSERT_RTNL();
1468
1469 if (pl->phydev)
1470 phy_ethtool_ksettings_get(pl->phydev, kset);
1471 else
1472 kset->base.port = pl->link_port;
1473
1474 linkmode_copy(kset->link_modes.supported, pl->supported);
1475
1476 switch (pl->cur_link_an_mode) {
1477 case MLO_AN_FIXED:
1478
1479
1480
1481
1482 phylink_get_fixed_state(pl, &link_state);
1483 phylink_get_ksettings(&link_state, kset);
1484 break;
1485
1486 case MLO_AN_INBAND:
1487
1488
1489
1490 if (pl->phydev)
1491 break;
1492
1493 phylink_mac_pcs_get_state(pl, &link_state);
1494
1495
1496
1497
1498
1499 phylink_get_ksettings(&link_state, kset);
1500 break;
1501 }
1502
1503 return 0;
1504}
1505EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get);
1506
1507
1508
1509
1510
1511
1512int phylink_ethtool_ksettings_set(struct phylink *pl,
1513 const struct ethtool_link_ksettings *kset)
1514{
1515 __ETHTOOL_DECLARE_LINK_MODE_MASK(support);
1516 struct phylink_link_state config;
1517 const struct phy_setting *s;
1518
1519 ASSERT_RTNL();
1520
1521 if (pl->phydev) {
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540 return phy_ethtool_ksettings_set(pl->phydev, kset);
1541 }
1542
1543 config = pl->link_config;
1544
1545
1546 linkmode_and(config.advertising, kset->link_modes.advertising,
1547 pl->supported);
1548
1549
1550 switch (kset->base.autoneg) {
1551 case AUTONEG_DISABLE:
1552
1553
1554
1555 s = phy_lookup_setting(kset->base.speed, kset->base.duplex,
1556 pl->supported, false);
1557 if (!s)
1558 return -EINVAL;
1559
1560
1561
1562
1563 if (pl->cur_link_an_mode == MLO_AN_FIXED) {
1564 if (s->speed != pl->link_config.speed ||
1565 s->duplex != pl->link_config.duplex)
1566 return -EINVAL;
1567 return 0;
1568 }
1569
1570 config.speed = s->speed;
1571 config.duplex = s->duplex;
1572 break;
1573
1574 case AUTONEG_ENABLE:
1575
1576
1577
1578
1579 if (pl->cur_link_an_mode == MLO_AN_FIXED) {
1580 if (!linkmode_equal(config.advertising,
1581 pl->link_config.advertising))
1582 return -EINVAL;
1583 return 0;
1584 }
1585
1586 config.speed = SPEED_UNKNOWN;
1587 config.duplex = DUPLEX_UNKNOWN;
1588 break;
1589
1590 default:
1591 return -EINVAL;
1592 }
1593
1594
1595
1596
1597 config.an_enabled = kset->base.autoneg == AUTONEG_ENABLE;
1598 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, config.advertising,
1599 config.an_enabled);
1600
1601
1602 linkmode_copy(support, pl->supported);
1603 if (phylink_validate(pl, support, &config))
1604 return -EINVAL;
1605
1606
1607 if (config.an_enabled && phylink_is_empty_linkmode(config.advertising))
1608 return -EINVAL;
1609
1610
1611
1612
1613
1614 if (pl->sfp_port && pl->sfp_bus) {
1615 config.interface = sfp_select_interface(pl->sfp_bus,
1616 config.advertising);
1617 if (config.interface == PHY_INTERFACE_MODE_NA) {
1618 phylink_err(pl,
1619 "selection of interface failed, advertisement %*pb\n",
1620 __ETHTOOL_LINK_MODE_MASK_NBITS,
1621 config.advertising);
1622 return -EINVAL;
1623 }
1624
1625
1626 linkmode_copy(support, pl->supported);
1627 if (phylink_validate(pl, support, &config)) {
1628 phylink_err(pl, "validation of %s/%s with support %*pb failed\n",
1629 phylink_an_mode_str(pl->cur_link_an_mode),
1630 phy_modes(config.interface),
1631 __ETHTOOL_LINK_MODE_MASK_NBITS, support);
1632 return -EINVAL;
1633 }
1634 }
1635
1636 mutex_lock(&pl->state_mutex);
1637 pl->link_config.speed = config.speed;
1638 pl->link_config.duplex = config.duplex;
1639 pl->link_config.an_enabled = config.an_enabled;
1640
1641 if (pl->link_config.interface != config.interface) {
1642
1643
1644 if (pl->old_link_state) {
1645 phylink_link_down(pl);
1646 pl->old_link_state = false;
1647 }
1648 if (!test_bit(PHYLINK_DISABLE_STOPPED,
1649 &pl->phylink_disable_state))
1650 phylink_major_config(pl, false, &config);
1651 pl->link_config.interface = config.interface;
1652 linkmode_copy(pl->link_config.advertising, config.advertising);
1653 } else if (!linkmode_equal(pl->link_config.advertising,
1654 config.advertising)) {
1655 linkmode_copy(pl->link_config.advertising, config.advertising);
1656 phylink_change_inband_advert(pl);
1657 }
1658 mutex_unlock(&pl->state_mutex);
1659
1660 return 0;
1661}
1662EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_set);
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675int phylink_ethtool_nway_reset(struct phylink *pl)
1676{
1677 int ret = 0;
1678
1679 ASSERT_RTNL();
1680
1681 if (pl->phydev)
1682 ret = phy_restart_aneg(pl->phydev);
1683 phylink_mac_pcs_an_restart(pl);
1684
1685 return ret;
1686}
1687EXPORT_SYMBOL_GPL(phylink_ethtool_nway_reset);
1688
1689
1690
1691
1692
1693
1694void phylink_ethtool_get_pauseparam(struct phylink *pl,
1695 struct ethtool_pauseparam *pause)
1696{
1697 ASSERT_RTNL();
1698
1699 pause->autoneg = !!(pl->link_config.pause & MLO_PAUSE_AN);
1700 pause->rx_pause = !!(pl->link_config.pause & MLO_PAUSE_RX);
1701 pause->tx_pause = !!(pl->link_config.pause & MLO_PAUSE_TX);
1702}
1703EXPORT_SYMBOL_GPL(phylink_ethtool_get_pauseparam);
1704
1705
1706
1707
1708
1709
1710int phylink_ethtool_set_pauseparam(struct phylink *pl,
1711 struct ethtool_pauseparam *pause)
1712{
1713 struct phylink_link_state *config = &pl->link_config;
1714 bool manual_changed;
1715 int pause_state;
1716
1717 ASSERT_RTNL();
1718
1719 if (pl->cur_link_an_mode == MLO_AN_FIXED)
1720 return -EOPNOTSUPP;
1721
1722 if (!phylink_test(pl->supported, Pause) &&
1723 !phylink_test(pl->supported, Asym_Pause))
1724 return -EOPNOTSUPP;
1725
1726 if (!phylink_test(pl->supported, Asym_Pause) &&
1727 !pause->autoneg && pause->rx_pause != pause->tx_pause)
1728 return -EINVAL;
1729
1730 pause_state = 0;
1731 if (pause->autoneg)
1732 pause_state |= MLO_PAUSE_AN;
1733 if (pause->rx_pause)
1734 pause_state |= MLO_PAUSE_RX;
1735 if (pause->tx_pause)
1736 pause_state |= MLO_PAUSE_TX;
1737
1738 mutex_lock(&pl->state_mutex);
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752 linkmode_set_pause(config->advertising, pause->tx_pause,
1753 pause->rx_pause);
1754
1755 manual_changed = (config->pause ^ pause_state) & MLO_PAUSE_AN ||
1756 (!(pause_state & MLO_PAUSE_AN) &&
1757 (config->pause ^ pause_state) & MLO_PAUSE_TXRX_MASK);
1758
1759 config->pause = pause_state;
1760
1761
1762
1763
1764 if (!pl->phydev)
1765 phylink_change_inband_advert(pl);
1766
1767 mutex_unlock(&pl->state_mutex);
1768
1769
1770
1771
1772
1773
1774 if (pl->phydev)
1775 phy_set_asym_pause(pl->phydev, pause->rx_pause,
1776 pause->tx_pause);
1777
1778
1779
1780
1781
1782 if (manual_changed) {
1783 pl->mac_link_dropped = true;
1784 phylink_run_resolve(pl);
1785 }
1786
1787 return 0;
1788}
1789EXPORT_SYMBOL_GPL(phylink_ethtool_set_pauseparam);
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801int phylink_get_eee_err(struct phylink *pl)
1802{
1803 int ret = 0;
1804
1805 ASSERT_RTNL();
1806
1807 if (pl->phydev)
1808 ret = phy_get_eee_err(pl->phydev);
1809
1810 return ret;
1811}
1812EXPORT_SYMBOL_GPL(phylink_get_eee_err);
1813
1814
1815
1816
1817
1818
1819
1820
1821int phylink_init_eee(struct phylink *pl, bool clk_stop_enable)
1822{
1823 int ret = -EOPNOTSUPP;
1824
1825 if (pl->phydev)
1826 ret = phy_init_eee(pl->phydev, clk_stop_enable);
1827
1828 return ret;
1829}
1830EXPORT_SYMBOL_GPL(phylink_init_eee);
1831
1832
1833
1834
1835
1836
1837int phylink_ethtool_get_eee(struct phylink *pl, struct ethtool_eee *eee)
1838{
1839 int ret = -EOPNOTSUPP;
1840
1841 ASSERT_RTNL();
1842
1843 if (pl->phydev)
1844 ret = phy_ethtool_get_eee(pl->phydev, eee);
1845
1846 return ret;
1847}
1848EXPORT_SYMBOL_GPL(phylink_ethtool_get_eee);
1849
1850
1851
1852
1853
1854
1855int phylink_ethtool_set_eee(struct phylink *pl, struct ethtool_eee *eee)
1856{
1857 int ret = -EOPNOTSUPP;
1858
1859 ASSERT_RTNL();
1860
1861 if (pl->phydev)
1862 ret = phy_ethtool_set_eee(pl->phydev, eee);
1863
1864 return ret;
1865}
1866EXPORT_SYMBOL_GPL(phylink_ethtool_set_eee);
1867
1868
1869
1870
1871
1872
1873static int phylink_mii_emul_read(unsigned int reg,
1874 struct phylink_link_state *state)
1875{
1876 struct fixed_phy_status fs;
1877 unsigned long *lpa = state->lp_advertising;
1878 int val;
1879
1880 fs.link = state->link;
1881 fs.speed = state->speed;
1882 fs.duplex = state->duplex;
1883 fs.pause = test_bit(ETHTOOL_LINK_MODE_Pause_BIT, lpa);
1884 fs.asym_pause = test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, lpa);
1885
1886 val = swphy_read_reg(reg, &fs);
1887 if (reg == MII_BMSR) {
1888 if (!state->an_complete)
1889 val &= ~BMSR_ANEGCOMPLETE;
1890 }
1891 return val;
1892}
1893
1894static int phylink_phy_read(struct phylink *pl, unsigned int phy_id,
1895 unsigned int reg)
1896{
1897 struct phy_device *phydev = pl->phydev;
1898 int prtad, devad;
1899
1900 if (mdio_phy_id_is_c45(phy_id)) {
1901 prtad = mdio_phy_id_prtad(phy_id);
1902 devad = mdio_phy_id_devad(phy_id);
1903 devad = mdiobus_c45_addr(devad, reg);
1904 } else if (phydev->is_c45) {
1905 switch (reg) {
1906 case MII_BMCR:
1907 case MII_BMSR:
1908 case MII_PHYSID1:
1909 case MII_PHYSID2:
1910 devad = __ffs(phydev->c45_ids.mmds_present);
1911 break;
1912 case MII_ADVERTISE:
1913 case MII_LPA:
1914 if (!(phydev->c45_ids.mmds_present & MDIO_DEVS_AN))
1915 return -EINVAL;
1916 devad = MDIO_MMD_AN;
1917 if (reg == MII_ADVERTISE)
1918 reg = MDIO_AN_ADVERTISE;
1919 else
1920 reg = MDIO_AN_LPA;
1921 break;
1922 default:
1923 return -EINVAL;
1924 }
1925 prtad = phy_id;
1926 devad = mdiobus_c45_addr(devad, reg);
1927 } else {
1928 prtad = phy_id;
1929 devad = reg;
1930 }
1931 return mdiobus_read(pl->phydev->mdio.bus, prtad, devad);
1932}
1933
1934static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
1935 unsigned int reg, unsigned int val)
1936{
1937 struct phy_device *phydev = pl->phydev;
1938 int prtad, devad;
1939
1940 if (mdio_phy_id_is_c45(phy_id)) {
1941 prtad = mdio_phy_id_prtad(phy_id);
1942 devad = mdio_phy_id_devad(phy_id);
1943 devad = mdiobus_c45_addr(devad, reg);
1944 } else if (phydev->is_c45) {
1945 switch (reg) {
1946 case MII_BMCR:
1947 case MII_BMSR:
1948 case MII_PHYSID1:
1949 case MII_PHYSID2:
1950 devad = __ffs(phydev->c45_ids.mmds_present);
1951 break;
1952 case MII_ADVERTISE:
1953 case MII_LPA:
1954 if (!(phydev->c45_ids.mmds_present & MDIO_DEVS_AN))
1955 return -EINVAL;
1956 devad = MDIO_MMD_AN;
1957 if (reg == MII_ADVERTISE)
1958 reg = MDIO_AN_ADVERTISE;
1959 else
1960 reg = MDIO_AN_LPA;
1961 break;
1962 default:
1963 return -EINVAL;
1964 }
1965 prtad = phy_id;
1966 devad = mdiobus_c45_addr(devad, reg);
1967 } else {
1968 prtad = phy_id;
1969 devad = reg;
1970 }
1971
1972 return mdiobus_write(phydev->mdio.bus, prtad, devad, val);
1973}
1974
1975static int phylink_mii_read(struct phylink *pl, unsigned int phy_id,
1976 unsigned int reg)
1977{
1978 struct phylink_link_state state;
1979 int val = 0xffff;
1980
1981 switch (pl->cur_link_an_mode) {
1982 case MLO_AN_FIXED:
1983 if (phy_id == 0) {
1984 phylink_get_fixed_state(pl, &state);
1985 val = phylink_mii_emul_read(reg, &state);
1986 }
1987 break;
1988
1989 case MLO_AN_PHY:
1990 return -EOPNOTSUPP;
1991
1992 case MLO_AN_INBAND:
1993 if (phy_id == 0) {
1994 phylink_mac_pcs_get_state(pl, &state);
1995 val = phylink_mii_emul_read(reg, &state);
1996 }
1997 break;
1998 }
1999
2000 return val & 0xffff;
2001}
2002
2003static int phylink_mii_write(struct phylink *pl, unsigned int phy_id,
2004 unsigned int reg, unsigned int val)
2005{
2006 switch (pl->cur_link_an_mode) {
2007 case MLO_AN_FIXED:
2008 break;
2009
2010 case MLO_AN_PHY:
2011 return -EOPNOTSUPP;
2012
2013 case MLO_AN_INBAND:
2014 break;
2015 }
2016
2017 return 0;
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038int phylink_mii_ioctl(struct phylink *pl, struct ifreq *ifr, int cmd)
2039{
2040 struct mii_ioctl_data *mii = if_mii(ifr);
2041 int ret;
2042
2043 ASSERT_RTNL();
2044
2045 if (pl->phydev) {
2046
2047 switch (cmd) {
2048 case SIOCGMIIPHY:
2049 mii->phy_id = pl->phydev->mdio.addr;
2050 fallthrough;
2051
2052 case SIOCGMIIREG:
2053 ret = phylink_phy_read(pl, mii->phy_id, mii->reg_num);
2054 if (ret >= 0) {
2055 mii->val_out = ret;
2056 ret = 0;
2057 }
2058 break;
2059
2060 case SIOCSMIIREG:
2061 ret = phylink_phy_write(pl, mii->phy_id, mii->reg_num,
2062 mii->val_in);
2063 break;
2064
2065 default:
2066 ret = phy_mii_ioctl(pl->phydev, ifr, cmd);
2067 break;
2068 }
2069 } else {
2070 switch (cmd) {
2071 case SIOCGMIIPHY:
2072 mii->phy_id = 0;
2073 fallthrough;
2074
2075 case SIOCGMIIREG:
2076 ret = phylink_mii_read(pl, mii->phy_id, mii->reg_num);
2077 if (ret >= 0) {
2078 mii->val_out = ret;
2079 ret = 0;
2080 }
2081 break;
2082
2083 case SIOCSMIIREG:
2084 ret = phylink_mii_write(pl, mii->phy_id, mii->reg_num,
2085 mii->val_in);
2086 break;
2087
2088 default:
2089 ret = -EOPNOTSUPP;
2090 break;
2091 }
2092 }
2093
2094 return ret;
2095}
2096EXPORT_SYMBOL_GPL(phylink_mii_ioctl);
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110int phylink_speed_down(struct phylink *pl, bool sync)
2111{
2112 int ret = 0;
2113
2114 ASSERT_RTNL();
2115
2116 if (!pl->sfp_bus && pl->phydev)
2117 ret = phy_speed_down(pl->phydev, sync);
2118
2119 return ret;
2120}
2121EXPORT_SYMBOL_GPL(phylink_speed_down);
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133int phylink_speed_up(struct phylink *pl)
2134{
2135 int ret = 0;
2136
2137 ASSERT_RTNL();
2138
2139 if (!pl->sfp_bus && pl->phydev)
2140 ret = phy_speed_up(pl->phydev);
2141
2142 return ret;
2143}
2144EXPORT_SYMBOL_GPL(phylink_speed_up);
2145
2146static void phylink_sfp_attach(void *upstream, struct sfp_bus *bus)
2147{
2148 struct phylink *pl = upstream;
2149
2150 pl->netdev->sfp_bus = bus;
2151}
2152
2153static void phylink_sfp_detach(void *upstream, struct sfp_bus *bus)
2154{
2155 struct phylink *pl = upstream;
2156
2157 pl->netdev->sfp_bus = NULL;
2158}
2159
2160static int phylink_sfp_config(struct phylink *pl, u8 mode,
2161 const unsigned long *supported,
2162 const unsigned long *advertising)
2163{
2164 __ETHTOOL_DECLARE_LINK_MODE_MASK(support1);
2165 __ETHTOOL_DECLARE_LINK_MODE_MASK(support);
2166 struct phylink_link_state config;
2167 phy_interface_t iface;
2168 bool changed;
2169 int ret;
2170
2171 linkmode_copy(support, supported);
2172
2173 memset(&config, 0, sizeof(config));
2174 linkmode_copy(config.advertising, advertising);
2175 config.interface = PHY_INTERFACE_MODE_NA;
2176 config.speed = SPEED_UNKNOWN;
2177 config.duplex = DUPLEX_UNKNOWN;
2178 config.pause = MLO_PAUSE_AN;
2179 config.an_enabled = pl->link_config.an_enabled;
2180
2181
2182 ret = phylink_validate(pl, support, &config);
2183 if (ret) {
2184 phylink_err(pl, "validation with support %*pb failed: %d\n",
2185 __ETHTOOL_LINK_MODE_MASK_NBITS, support, ret);
2186 return ret;
2187 }
2188
2189 iface = sfp_select_interface(pl->sfp_bus, config.advertising);
2190 if (iface == PHY_INTERFACE_MODE_NA) {
2191 phylink_err(pl,
2192 "selection of interface failed, advertisement %*pb\n",
2193 __ETHTOOL_LINK_MODE_MASK_NBITS, config.advertising);
2194 return -EINVAL;
2195 }
2196
2197 config.interface = iface;
2198 linkmode_copy(support1, support);
2199 ret = phylink_validate(pl, support1, &config);
2200 if (ret) {
2201 phylink_err(pl, "validation of %s/%s with support %*pb failed: %d\n",
2202 phylink_an_mode_str(mode),
2203 phy_modes(config.interface),
2204 __ETHTOOL_LINK_MODE_MASK_NBITS, support, ret);
2205 return ret;
2206 }
2207
2208 phylink_dbg(pl, "requesting link mode %s/%s with support %*pb\n",
2209 phylink_an_mode_str(mode), phy_modes(config.interface),
2210 __ETHTOOL_LINK_MODE_MASK_NBITS, support);
2211
2212 if (phy_interface_mode_is_8023z(iface) && pl->phydev)
2213 return -EINVAL;
2214
2215 changed = !linkmode_equal(pl->supported, support) ||
2216 !linkmode_equal(pl->link_config.advertising,
2217 config.advertising);
2218 if (changed) {
2219 linkmode_copy(pl->supported, support);
2220 linkmode_copy(pl->link_config.advertising, config.advertising);
2221 }
2222
2223 if (pl->cur_link_an_mode != mode ||
2224 pl->link_config.interface != config.interface) {
2225 pl->link_config.interface = config.interface;
2226 pl->cur_link_an_mode = mode;
2227
2228 changed = true;
2229
2230 phylink_info(pl, "switched to %s/%s link mode\n",
2231 phylink_an_mode_str(mode),
2232 phy_modes(config.interface));
2233 }
2234
2235 pl->link_port = pl->sfp_port;
2236
2237 if (changed && !test_bit(PHYLINK_DISABLE_STOPPED,
2238 &pl->phylink_disable_state))
2239 phylink_mac_initial_config(pl, false);
2240
2241 return ret;
2242}
2243
2244static int phylink_sfp_module_insert(void *upstream,
2245 const struct sfp_eeprom_id *id)
2246{
2247 struct phylink *pl = upstream;
2248 unsigned long *support = pl->sfp_support;
2249
2250 ASSERT_RTNL();
2251
2252 linkmode_zero(support);
2253 sfp_parse_support(pl->sfp_bus, id, support);
2254 pl->sfp_port = sfp_parse_port(pl->sfp_bus, id, support);
2255
2256
2257 pl->sfp_may_have_phy = sfp_may_have_phy(pl->sfp_bus, id);
2258 if (pl->sfp_may_have_phy)
2259 return 0;
2260
2261 return phylink_sfp_config(pl, MLO_AN_INBAND, support, support);
2262}
2263
2264static int phylink_sfp_module_start(void *upstream)
2265{
2266 struct phylink *pl = upstream;
2267
2268
2269 if (pl->phydev) {
2270 phy_start(pl->phydev);
2271 return 0;
2272 }
2273
2274
2275
2276
2277 if (!pl->sfp_may_have_phy)
2278 return 0;
2279
2280 return phylink_sfp_config(pl, MLO_AN_INBAND,
2281 pl->sfp_support, pl->sfp_support);
2282}
2283
2284static void phylink_sfp_module_stop(void *upstream)
2285{
2286 struct phylink *pl = upstream;
2287
2288
2289 if (pl->phydev)
2290 phy_stop(pl->phydev);
2291}
2292
2293static void phylink_sfp_link_down(void *upstream)
2294{
2295 struct phylink *pl = upstream;
2296
2297 ASSERT_RTNL();
2298
2299 phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_LINK);
2300}
2301
2302static void phylink_sfp_link_up(void *upstream)
2303{
2304 struct phylink *pl = upstream;
2305
2306 ASSERT_RTNL();
2307
2308 clear_bit(PHYLINK_DISABLE_LINK, &pl->phylink_disable_state);
2309 phylink_run_resolve(pl);
2310}
2311
2312
2313
2314
2315static bool phylink_phy_no_inband(struct phy_device *phy)
2316{
2317 return phy->is_c45 &&
2318 (phy->c45_ids.device_ids[1] & 0xfffffff0) == 0xae025150;
2319}
2320
2321static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
2322{
2323 struct phylink *pl = upstream;
2324 phy_interface_t interface;
2325 u8 mode;
2326 int ret;
2327
2328
2329
2330
2331
2332
2333
2334
2335 phy_support_asym_pause(phy);
2336
2337 if (phylink_phy_no_inband(phy))
2338 mode = MLO_AN_PHY;
2339 else
2340 mode = MLO_AN_INBAND;
2341
2342
2343 ret = phylink_sfp_config(pl, mode, phy->supported, phy->advertising);
2344 if (ret < 0)
2345 return ret;
2346
2347 interface = pl->link_config.interface;
2348 ret = phylink_attach_phy(pl, phy, interface);
2349 if (ret < 0)
2350 return ret;
2351
2352 ret = phylink_bringup_phy(pl, phy, interface);
2353 if (ret)
2354 phy_detach(phy);
2355
2356 return ret;
2357}
2358
2359static void phylink_sfp_disconnect_phy(void *upstream)
2360{
2361 phylink_disconnect_phy(upstream);
2362}
2363
2364static const struct sfp_upstream_ops sfp_phylink_ops = {
2365 .attach = phylink_sfp_attach,
2366 .detach = phylink_sfp_detach,
2367 .module_insert = phylink_sfp_module_insert,
2368 .module_start = phylink_sfp_module_start,
2369 .module_stop = phylink_sfp_module_stop,
2370 .link_up = phylink_sfp_link_up,
2371 .link_down = phylink_sfp_link_down,
2372 .connect_phy = phylink_sfp_connect_phy,
2373 .disconnect_phy = phylink_sfp_disconnect_phy,
2374};
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388void phylink_helper_basex_speed(struct phylink_link_state *state)
2389{
2390 if (phy_interface_mode_is_8023z(state->interface)) {
2391 bool want_2500 = state->an_enabled ?
2392 phylink_test(state->advertising, 2500baseX_Full) :
2393 state->speed == SPEED_2500;
2394
2395 if (want_2500) {
2396 phylink_clear(state->advertising, 1000baseX_Full);
2397 state->interface = PHY_INTERFACE_MODE_2500BASEX;
2398 } else {
2399 phylink_clear(state->advertising, 2500baseX_Full);
2400 state->interface = PHY_INTERFACE_MODE_1000BASEX;
2401 }
2402 }
2403}
2404EXPORT_SYMBOL_GPL(phylink_helper_basex_speed);
2405
2406static void phylink_decode_c37_word(struct phylink_link_state *state,
2407 uint16_t config_reg, int speed)
2408{
2409 bool tx_pause, rx_pause;
2410 int fd_bit;
2411
2412 if (speed == SPEED_2500)
2413 fd_bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT;
2414 else
2415 fd_bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT;
2416
2417 mii_lpa_mod_linkmode_x(state->lp_advertising, config_reg, fd_bit);
2418
2419 if (linkmode_test_bit(fd_bit, state->advertising) &&
2420 linkmode_test_bit(fd_bit, state->lp_advertising)) {
2421 state->speed = speed;
2422 state->duplex = DUPLEX_FULL;
2423 } else {
2424
2425 state->link = false;
2426 }
2427
2428 linkmode_resolve_pause(state->advertising, state->lp_advertising,
2429 &tx_pause, &rx_pause);
2430
2431 if (tx_pause)
2432 state->pause |= MLO_PAUSE_TX;
2433 if (rx_pause)
2434 state->pause |= MLO_PAUSE_RX;
2435}
2436
2437static void phylink_decode_sgmii_word(struct phylink_link_state *state,
2438 uint16_t config_reg)
2439{
2440 if (!(config_reg & LPA_SGMII_LINK)) {
2441 state->link = false;
2442 return;
2443 }
2444
2445 switch (config_reg & LPA_SGMII_SPD_MASK) {
2446 case LPA_SGMII_10:
2447 state->speed = SPEED_10;
2448 break;
2449 case LPA_SGMII_100:
2450 state->speed = SPEED_100;
2451 break;
2452 case LPA_SGMII_1000:
2453 state->speed = SPEED_1000;
2454 break;
2455 default:
2456 state->link = false;
2457 return;
2458 }
2459 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2460 state->duplex = DUPLEX_FULL;
2461 else
2462 state->duplex = DUPLEX_HALF;
2463}
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474void phylink_decode_usxgmii_word(struct phylink_link_state *state,
2475 uint16_t lpa)
2476{
2477 switch (lpa & MDIO_USXGMII_SPD_MASK) {
2478 case MDIO_USXGMII_10:
2479 state->speed = SPEED_10;
2480 break;
2481 case MDIO_USXGMII_100:
2482 state->speed = SPEED_100;
2483 break;
2484 case MDIO_USXGMII_1000:
2485 state->speed = SPEED_1000;
2486 break;
2487 case MDIO_USXGMII_2500:
2488 state->speed = SPEED_2500;
2489 break;
2490 case MDIO_USXGMII_5000:
2491 state->speed = SPEED_5000;
2492 break;
2493 case MDIO_USXGMII_10G:
2494 state->speed = SPEED_10000;
2495 break;
2496 default:
2497 state->link = false;
2498 return;
2499 }
2500
2501 if (lpa & MDIO_USXGMII_FULL_DUPLEX)
2502 state->duplex = DUPLEX_FULL;
2503 else
2504 state->duplex = DUPLEX_HALF;
2505}
2506EXPORT_SYMBOL_GPL(phylink_decode_usxgmii_word);
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
2523 struct phylink_link_state *state)
2524{
2525 struct mii_bus *bus = pcs->bus;
2526 int addr = pcs->addr;
2527 int bmsr, lpa;
2528
2529 bmsr = mdiobus_read(bus, addr, MII_BMSR);
2530 lpa = mdiobus_read(bus, addr, MII_LPA);
2531 if (bmsr < 0 || lpa < 0) {
2532 state->link = false;
2533 return;
2534 }
2535
2536 state->link = !!(bmsr & BMSR_LSTATUS);
2537 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
2538 if (!state->link)
2539 return;
2540
2541 switch (state->interface) {
2542 case PHY_INTERFACE_MODE_1000BASEX:
2543 phylink_decode_c37_word(state, lpa, SPEED_1000);
2544 break;
2545
2546 case PHY_INTERFACE_MODE_2500BASEX:
2547 phylink_decode_c37_word(state, lpa, SPEED_2500);
2548 break;
2549
2550 case PHY_INTERFACE_MODE_SGMII:
2551 case PHY_INTERFACE_MODE_QSGMII:
2552 phylink_decode_sgmii_word(state, lpa);
2553 break;
2554
2555 default:
2556 state->link = false;
2557 break;
2558 }
2559}
2560EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_get_state);
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579int phylink_mii_c22_pcs_set_advertisement(struct mdio_device *pcs,
2580 phy_interface_t interface,
2581 const unsigned long *advertising)
2582{
2583 struct mii_bus *bus = pcs->bus;
2584 int addr = pcs->addr;
2585 int val, ret;
2586 u16 adv;
2587
2588 switch (interface) {
2589 case PHY_INTERFACE_MODE_1000BASEX:
2590 case PHY_INTERFACE_MODE_2500BASEX:
2591 adv = ADVERTISE_1000XFULL;
2592 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2593 advertising))
2594 adv |= ADVERTISE_1000XPAUSE;
2595 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2596 advertising))
2597 adv |= ADVERTISE_1000XPSE_ASYM;
2598
2599 val = mdiobus_read(bus, addr, MII_ADVERTISE);
2600 if (val < 0)
2601 return val;
2602
2603 if (val == adv)
2604 return 0;
2605
2606 ret = mdiobus_write(bus, addr, MII_ADVERTISE, adv);
2607 if (ret < 0)
2608 return ret;
2609
2610 return 1;
2611
2612 case PHY_INTERFACE_MODE_SGMII:
2613 val = mdiobus_read(bus, addr, MII_ADVERTISE);
2614 if (val < 0)
2615 return val;
2616
2617 if (val == 0x0001)
2618 return 0;
2619
2620 ret = mdiobus_write(bus, addr, MII_ADVERTISE, 0x0001);
2621 if (ret < 0)
2622 return ret;
2623
2624 return 1;
2625
2626 default:
2627
2628 return 0;
2629 }
2630}
2631EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_set_advertisement);
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
2646 phy_interface_t interface,
2647 const unsigned long *advertising)
2648{
2649 bool changed;
2650 u16 bmcr;
2651 int ret;
2652
2653 ret = phylink_mii_c22_pcs_set_advertisement(pcs, interface,
2654 advertising);
2655 if (ret < 0)
2656 return ret;
2657
2658 changed = ret > 0;
2659
2660
2661 bmcr = mode == MLO_AN_INBAND ? BMCR_ANENABLE : 0;
2662 ret = mdiobus_modify(pcs->bus, pcs->addr, MII_BMCR,
2663 BMCR_ANENABLE | BMCR_ISOLATE, bmcr);
2664 if (ret < 0)
2665 return ret;
2666
2667 return changed ? 1 : 0;
2668}
2669EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_config);
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs)
2683{
2684 struct mii_bus *bus = pcs->bus;
2685 int val, addr = pcs->addr;
2686
2687 val = mdiobus_read(bus, addr, MII_BMCR);
2688 if (val >= 0) {
2689 val |= BMCR_ANRESTART;
2690
2691 mdiobus_write(bus, addr, MII_BMCR, val);
2692 }
2693}
2694EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_an_restart);
2695
2696void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
2697 struct phylink_link_state *state)
2698{
2699 struct mii_bus *bus = pcs->bus;
2700 int addr = pcs->addr;
2701 int stat;
2702
2703 stat = mdiobus_c45_read(bus, addr, MDIO_MMD_PCS, MDIO_STAT1);
2704 if (stat < 0) {
2705 state->link = false;
2706 return;
2707 }
2708
2709 state->link = !!(stat & MDIO_STAT1_LSTATUS);
2710 if (!state->link)
2711 return;
2712
2713 switch (state->interface) {
2714 case PHY_INTERFACE_MODE_10GBASER:
2715 state->speed = SPEED_10000;
2716 state->duplex = DUPLEX_FULL;
2717 break;
2718
2719 default:
2720 break;
2721 }
2722}
2723EXPORT_SYMBOL_GPL(phylink_mii_c45_pcs_get_state);
2724
2725MODULE_LICENSE("GPL v2");
2726