LXR linux/drivers/net/usb/asix.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * ASIX AX8817X based USB 2.0 Ethernet Devices
   4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
   5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
   6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
   7 * Copyright (c) 2002-2003 TiVo Inc.
   8 */
   9
  10#ifndef _ASIX_H
  11#define _ASIX_H
  12
  13// #define      DEBUG                   // error path messages, extra info
  14// #define      VERBOSE                 // more; success messages
  15
  16#include <linux/module.h>
  17#include <linux/kmod.h>
  18#include <linux/netdevice.h>
  19#include <linux/etherdevice.h>
  20#include <linux/ethtool.h>
  21#include <linux/workqueue.h>
  22#include <linux/mii.h>
  23#include <linux/usb.h>
  24#include <linux/crc32.h>
  25#include <linux/usb/usbnet.h>
  26#include <linux/slab.h>
  27#include <linux/if_vlan.h>
  28#include <linux/phy.h>
  29#include <net/selftests.h>
  30
  31#define DRIVER_VERSION "22-Dec-2011"
  32#define DRIVER_NAME "asix"
  33
  34/* ASIX AX8817X based USB 2.0 Ethernet Devices */
  35
  36#define AX_CMD_SET_SW_MII               0x06
  37#define AX_CMD_READ_MII_REG             0x07
  38#define AX_CMD_WRITE_MII_REG            0x08
  39#define AX_CMD_STATMNGSTS_REG           0x09
  40#define AX_CMD_SET_HW_MII               0x0a
  41#define AX_CMD_READ_EEPROM              0x0b
  42#define AX_CMD_WRITE_EEPROM             0x0c
  43#define AX_CMD_WRITE_ENABLE             0x0d
  44#define AX_CMD_WRITE_DISABLE            0x0e
  45#define AX_CMD_READ_RX_CTL              0x0f
  46#define AX_CMD_WRITE_RX_CTL             0x10
  47#define AX_CMD_READ_IPG012              0x11
  48#define AX_CMD_WRITE_IPG0               0x12
  49#define AX_CMD_WRITE_IPG1               0x13
  50#define AX_CMD_READ_NODE_ID             0x13
  51#define AX_CMD_WRITE_NODE_ID            0x14
  52#define AX_CMD_WRITE_IPG2               0x14
  53#define AX_CMD_WRITE_MULTI_FILTER       0x16
  54#define AX88172_CMD_READ_NODE_ID        0x17
  55#define AX_CMD_READ_PHY_ID              0x19
  56#define AX_CMD_READ_MEDIUM_STATUS       0x1a
  57#define AX_CMD_WRITE_MEDIUM_MODE        0x1b
  58#define AX_CMD_READ_MONITOR_MODE        0x1c
  59#define AX_CMD_WRITE_MONITOR_MODE       0x1d
  60#define AX_CMD_READ_GPIOS               0x1e
  61#define AX_CMD_WRITE_GPIOS              0x1f
  62#define AX_CMD_SW_RESET                 0x20
  63#define AX_CMD_SW_PHY_STATUS            0x21
  64#define AX_CMD_SW_PHY_SELECT            0x22
  65#define AX_QCTCTRL                      0x2A
  66
  67#define AX_CHIPCODE_MASK                0x70
  68#define AX_AX88772_CHIPCODE             0x00
  69#define AX_AX88772A_CHIPCODE            0x10
  70#define AX_AX88772B_CHIPCODE            0x20
  71#define AX_HOST_EN                      0x01
  72
  73#define AX_PHYSEL_PSEL                  0x01
  74#define AX_PHYSEL_SSMII                 0
  75#define AX_PHYSEL_SSEN                  0x10
  76
  77#define AX_PHY_SELECT_MASK              (BIT(3) | BIT(2))
  78#define AX_PHY_SELECT_INTERNAL          0
  79#define AX_PHY_SELECT_EXTERNAL          BIT(2)
  80
  81#define AX_MONITOR_MODE                 0x01
  82#define AX_MONITOR_LINK                 0x02
  83#define AX_MONITOR_MAGIC                0x04
  84#define AX_MONITOR_HSFS                 0x10
  85
  86/* AX88172 Medium Status Register values */
  87#define AX88172_MEDIUM_FD               0x02
  88#define AX88172_MEDIUM_TX               0x04
  89#define AX88172_MEDIUM_FC               0x10
  90#define AX88172_MEDIUM_DEFAULT \
  91                ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
  92
  93#define AX_MCAST_FILTER_SIZE            8
  94#define AX_MAX_MCAST                    64
  95
  96#define AX_SWRESET_CLEAR                0x00
  97#define AX_SWRESET_RR                   0x01
  98#define AX_SWRESET_RT                   0x02
  99#define AX_SWRESET_PRTE                 0x04
 100#define AX_SWRESET_PRL                  0x08
 101#define AX_SWRESET_BZ                   0x10
 102#define AX_SWRESET_IPRL                 0x20
 103#define AX_SWRESET_IPPD                 0x40
 104
 105#define AX88772_IPG0_DEFAULT            0x15
 106#define AX88772_IPG1_DEFAULT            0x0c
 107#define AX88772_IPG2_DEFAULT            0x12
 108
 109/* AX88772 & AX88178 Medium Mode Register */
 110#define AX_MEDIUM_PF            0x0080
 111#define AX_MEDIUM_JFE           0x0040
 112#define AX_MEDIUM_TFC           0x0020
 113#define AX_MEDIUM_RFC           0x0010
 114#define AX_MEDIUM_ENCK          0x0008
 115#define AX_MEDIUM_AC            0x0004
 116#define AX_MEDIUM_FD            0x0002
 117#define AX_MEDIUM_GM            0x0001
 118#define AX_MEDIUM_SM            0x1000
 119#define AX_MEDIUM_SBP           0x0800
 120#define AX_MEDIUM_PS            0x0200
 121#define AX_MEDIUM_RE            0x0100
 122
 123#define AX88178_MEDIUM_DEFAULT  \
 124        (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
 125         AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
 126         AX_MEDIUM_RE)
 127
 128#define AX88772_MEDIUM_DEFAULT  \
 129        (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
 130         AX_MEDIUM_TFC | AX_MEDIUM_PS | \
 131         AX_MEDIUM_AC | AX_MEDIUM_RE)
 132
 133/* AX88772 & AX88178 RX_CTL values */
 134#define AX_RX_CTL_SO            0x0080
 135#define AX_RX_CTL_AP            0x0020
 136#define AX_RX_CTL_AM            0x0010
 137#define AX_RX_CTL_AB            0x0008
 138#define AX_RX_CTL_SEP           0x0004
 139#define AX_RX_CTL_AMALL         0x0002
 140#define AX_RX_CTL_PRO           0x0001
 141#define AX_RX_CTL_MFB_2048      0x0000
 142#define AX_RX_CTL_MFB_4096      0x0100
 143#define AX_RX_CTL_MFB_8192      0x0200
 144#define AX_RX_CTL_MFB_16384     0x0300
 145
 146#define AX_DEFAULT_RX_CTL       (AX_RX_CTL_SO | AX_RX_CTL_AB)
 147
 148/* GPIO 0 .. 2 toggles */
 149#define AX_GPIO_GPO0EN          0x01    /* GPIO0 Output enable */
 150#define AX_GPIO_GPO_0           0x02    /* GPIO0 Output value */
 151#define AX_GPIO_GPO1EN          0x04    /* GPIO1 Output enable */
 152#define AX_GPIO_GPO_1           0x08    /* GPIO1 Output value */
 153#define AX_GPIO_GPO2EN          0x10    /* GPIO2 Output enable */
 154#define AX_GPIO_GPO_2           0x20    /* GPIO2 Output value */
 155#define AX_GPIO_RESERVED        0x40    /* Reserved */
 156#define AX_GPIO_RSE             0x80    /* Reload serial EEPROM */
 157
 158#define AX_EEPROM_MAGIC         0xdeadbeef
 159#define AX_EEPROM_LEN           0x200
 160
 161/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
 162struct asix_data {
 163        u8 multi_filter[AX_MCAST_FILTER_SIZE];
 164        u8 mac_addr[ETH_ALEN];
 165        u8 phymode;
 166        u8 ledmode;
 167        u8 res;
 168};
 169
 170struct asix_rx_fixup_info {
 171        struct sk_buff *ax_skb;
 172        u32 header;
 173        u16 remaining;
 174        bool split_head;
 175};
 176
 177struct asix_common_private {
 178        void (*resume)(struct usbnet *dev);
 179        void (*suspend)(struct usbnet *dev);
 180        u16 presvd_phy_advertise;
 181        u16 presvd_phy_bmcr;
 182        struct asix_rx_fixup_info rx_fixup_info;
 183        struct mii_bus *mdio;
 184        struct phy_device *phydev;
 185        u16 phy_addr;
 186        char phy_name[20];
 187        bool embd_phy;
 188};
 189
 190extern const struct driver_info ax88172a_info;
 191
 192/* ASIX specific flags */
 193#define FLAG_EEPROM_MAC         (1UL << 0)  /* init device MAC from eeprom */
 194
 195int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
 196                  u16 size, void *data, int in_pm);
 197
 198int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
 199                   u16 size, void *data, int in_pm);
 200
 201void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
 202                          u16 index, u16 size, void *data);
 203
 204int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
 205                           struct asix_rx_fixup_info *rx);
 206int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
 207void asix_rx_fixup_common_free(struct asix_common_private *dp);
 208
 209struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
 210                              gfp_t flags);
 211
 212int asix_set_sw_mii(struct usbnet *dev, int in_pm);
 213int asix_set_hw_mii(struct usbnet *dev, int in_pm);
 214
 215int asix_read_phy_addr(struct usbnet *dev, bool internal);
 216
 217int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
 218
 219u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
 220int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
 221
 222u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
 223int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
 224void asix_adjust_link(struct net_device *netdev);
 225
 226int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
 227
 228void asix_set_multicast(struct net_device *net);
 229
 230int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
 231void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
 232
 233int asix_mdio_bus_read(struct mii_bus *bus, int phy_id, int regnum);
 234int asix_mdio_bus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
 235
 236int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
 237void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
 238                          int val);
 239
 240void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
 241int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
 242
 243int asix_get_eeprom_len(struct net_device *net);
 244int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
 245                    u8 *data);
 246int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
 247                    u8 *data);
 248
 249void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);
 250
 251int asix_set_mac_address(struct net_device *net, void *p);
 252
 253#endif /* _ASIX_H */
 254