LXR linux/drivers/net/wan/z85230.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 *      Description of Z8530 Z85C30 and Z85230 communications chips
   4 *
   5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6 * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
   7 */
   8
   9#ifndef _Z8530_H
  10#define _Z8530_H
  11
  12#include <linux/tty.h>
  13#include <linux/interrupt.h>
  14
  15/* Conversion routines to/from brg time constants from/to bits
  16 * per second.
  17 */
  18#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
  19#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
  20
  21/* The Zilog register set */
  22
  23#define FLAG    0x7e
  24
  25/* Write Register 0 */
  26#define R0      0               /* Register selects */
  27#define R1      1
  28#define R2      2
  29#define R3      3
  30#define R4      4
  31#define R5      5
  32#define R6      6
  33#define R7      7
  34#define R8      8
  35#define R9      9
  36#define R10     10
  37#define R11     11
  38#define R12     12
  39#define R13     13
  40#define R14     14
  41#define R15     15
  42
  43#define RPRIME  16              /* Indicate a prime register access on 230 */
  44
  45#define NULLCODE        0       /* Null Code */
  46#define POINT_HIGH      0x8     /* Select upper half of registers */
  47#define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
  48#define SEND_ABORT      0x18    /* HDLC Abort */
  49#define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
  50#define RES_Tx_P        0x28    /* Reset TxINT Pending */
  51#define ERR_RES         0x30    /* Error Reset */
  52#define RES_H_IUS       0x38    /* Reset highest IUS */
  53
  54#define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
  55#define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
  56#define RES_EOM_L       0xC0    /* Reset EOM latch */
  57
  58/* Write Register 1 */
  59
  60#define EXT_INT_ENAB    0x1     /* Ext Int Enable */
  61#define TxINT_ENAB      0x2     /* Tx Int Enable */
  62#define PAR_SPEC        0x4     /* Parity is special condition */
  63
  64#define RxINT_DISAB     0       /* Rx Int Disable */
  65#define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
  66#define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
  67#define INT_ERR_Rx      0x18    /* Int on error only */
  68
  69#define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
  70#define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
  71#define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
  72
  73/* Write Register #2 (Interrupt Vector) */
  74
  75/* Write Register 3 */
  76
  77#define RxENABLE        0x1     /* Rx Enable */
  78#define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
  79#define ADD_SM          0x4     /* Address Search Mode (SDLC) */
  80#define RxCRC_ENAB      0x8     /* Rx CRC Enable */
  81#define ENT_HM          0x10    /* Enter Hunt Mode */
  82#define AUTO_ENAB       0x20    /* Auto Enables */
  83#define Rx5             0x0     /* Rx 5 Bits/Character */
  84#define Rx7             0x40    /* Rx 7 Bits/Character */
  85#define Rx6             0x80    /* Rx 6 Bits/Character */
  86#define Rx8             0xc0    /* Rx 8 Bits/Character */
  87
  88/* Write Register 4 */
  89
  90#define PAR_ENA         0x1     /* Parity Enable */
  91#define PAR_EVEN        0x2     /* Parity Even/Odd* */
  92
  93#define SYNC_ENAB       0       /* Sync Modes Enable */
  94#define SB1             0x4     /* 1 stop bit/char */
  95#define SB15            0x8     /* 1.5 stop bits/char */
  96#define SB2             0xc     /* 2 stop bits/char */
  97
  98#define MONSYNC         0       /* 8 Bit Sync character */
  99#define BISYNC          0x10    /* 16 bit sync character */
 100#define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 101#define EXTSYNC         0x30    /* External Sync Mode */
 102
 103#define X1CLK           0x0     /* x1 clock mode */
 104#define X16CLK          0x40    /* x16 clock mode */
 105#define X32CLK          0x80    /* x32 clock mode */
 106#define X64CLK          0xC0    /* x64 clock mode */
 107
 108/* Write Register 5 */
 109
 110#define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 111#define RTS             0x2     /* RTS */
 112#define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 113#define TxENAB          0x8     /* Tx Enable */
 114#define SND_BRK         0x10    /* Send Break */
 115#define Tx5             0x0     /* Tx 5 bits (or less)/character */
 116#define Tx7             0x20    /* Tx 7 bits/character */
 117#define Tx6             0x40    /* Tx 6 bits/character */
 118#define Tx8             0x60    /* Tx 8 bits/character */
 119#define DTR             0x80    /* DTR */
 120
 121/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 122
 123/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 124
 125/* Write Register 8 (transmit buffer) */
 126
 127/* Write Register 9 (Master interrupt control) */
 128#define VIS     1       /* Vector Includes Status */
 129#define NV      2       /* No Vector */
 130#define DLC     4       /* Disable Lower Chain */
 131#define MIE     8       /* Master Interrupt Enable */
 132#define STATHI  0x10    /* Status high */
 133#define NORESET 0       /* No reset on write to R9 */
 134#define CHRB    0x40    /* Reset channel B */
 135#define CHRA    0x80    /* Reset channel A */
 136#define FHWRES  0xc0    /* Force hardware reset */
 137
 138/* Write Register 10 (misc control bits) */
 139#define BIT6    1       /* 6 bit/8bit sync */
 140#define LOOPMODE 2      /* SDLC Loop mode */
 141#define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 142#define MARKIDLE 8      /* Mark/flag on idle */
 143#define GAOP    0x10    /* Go active on poll */
 144#define NRZ     0       /* NRZ mode */
 145#define NRZI    0x20    /* NRZI mode */
 146#define FM1     0x40    /* FM1 (transition = 1) */
 147#define FM0     0x60    /* FM0 (transition = 0) */
 148#define CRCPS   0x80    /* CRC Preset I/O */
 149
 150/* Write Register 11 (Clock Mode control) */
 151#define TRxCXT  0       /* TRxC = Xtal output */
 152#define TRxCTC  1       /* TRxC = Transmit clock */
 153#define TRxCBR  2       /* TRxC = BR Generator Output */
 154#define TRxCDP  3       /* TRxC = DPLL output */
 155#define TRxCOI  4       /* TRxC O/I */
 156#define TCRTxCP 0       /* Transmit clock = RTxC pin */
 157#define TCTRxCP 8       /* Transmit clock = TRxC pin */
 158#define TCBR    0x10    /* Transmit clock = BR Generator output */
 159#define TCDPLL  0x18    /* Transmit clock = DPLL output */
 160#define RCRTxCP 0       /* Receive clock = RTxC pin */
 161#define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 162#define RCBR    0x40    /* Receive clock = BR Generator output */
 163#define RCDPLL  0x60    /* Receive clock = DPLL output */
 164#define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 165
 166/* Write Register 12 (lower byte of baud rate generator time constant) */
 167
 168/* Write Register 13 (upper byte of baud rate generator time constant) */
 169
 170/* Write Register 14 (Misc control bits) */
 171#define BRENABL 1       /* Baud rate generator enable */
 172#define BRSRC   2       /* Baud rate generator source */
 173#define DTRREQ  4       /* DTR/Request function */
 174#define AUTOECHO 8      /* Auto Echo */
 175#define LOOPBAK 0x10    /* Local loopback */
 176#define SEARCH  0x20    /* Enter search mode */
 177#define RMC     0x40    /* Reset missing clock */
 178#define DISDPLL 0x60    /* Disable DPLL */
 179#define SSBR    0x80    /* Set DPLL source = BR generator */
 180#define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 181#define SFMM    0xc0    /* Set FM mode */
 182#define SNRZI   0xe0    /* Set NRZI mode */
 183
 184/* Write Register 15 (external/status interrupt control) */
 185#define PRIME   1       /* R5' etc register access (Z85C30/230 only) */
 186#define ZCIE    2       /* Zero count IE */
 187#define FIFOE   4       /* Z85230 only */
 188#define DCDIE   8       /* DCD IE */
 189#define SYNCIE  0x10    /* Sync/hunt IE */
 190#define CTSIE   0x20    /* CTS IE */
 191#define TxUIE   0x40    /* Tx Underrun/EOM IE */
 192#define BRKIE   0x80    /* Break/Abort IE */
 193
 194
 195/* Read Register 0 */
 196#define Rx_CH_AV        0x1     /* Rx Character Available */
 197#define ZCOUNT          0x2     /* Zero count */
 198#define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 199#define DCD             0x8     /* DCD */
 200#define SYNC_HUNT       0x10    /* Sync/hunt */
 201#define CTS             0x20    /* CTS */
 202#define TxEOM           0x40    /* Tx underrun */
 203#define BRK_ABRT        0x80    /* Break/Abort */
 204
 205/* Read Register 1 */
 206#define ALL_SNT         0x1     /* All sent */
 207/* Residue Data for 8 Rx bits/char programmed */
 208#define RES3            0x8     /* 0/3 */
 209#define RES4            0x4     /* 0/4 */
 210#define RES5            0xc     /* 0/5 */
 211#define RES6            0x2     /* 0/6 */
 212#define RES7            0xa     /* 0/7 */
 213#define RES8            0x6     /* 0/8 */
 214#define RES18           0xe     /* 1/8 */
 215#define RES28           0x0     /* 2/8 */
 216/* Special Rx Condition Interrupts */
 217#define PAR_ERR         0x10    /* Parity error */
 218#define Rx_OVR          0x20    /* Rx Overrun Error */
 219#define CRC_ERR         0x40    /* CRC/Framing Error */
 220#define END_FR          0x80    /* End of Frame (SDLC) */
 221
 222/* Read Register 2 (channel b only) - Interrupt vector */
 223
 224/* Read Register 3 (interrupt pending register) ch a only */
 225#define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 226#define CHBTxIP 0x2             /* Channel B Tx IP */
 227#define CHBRxIP 0x4             /* Channel B Rx IP */
 228#define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 229#define CHATxIP 0x10            /* Channel A Tx IP */
 230#define CHARxIP 0x20            /* Channel A Rx IP */
 231
 232/* Read Register 8 (receive data register) */
 233
 234/* Read Register 10  (misc status bits) */
 235#define ONLOOP  2               /* On loop */
 236#define LOOPSEND 0x10           /* Loop sending */
 237#define CLK2MIS 0x40            /* Two clocks missing */
 238#define CLK1MIS 0x80            /* One clock missing */
 239
 240/* Read Register 12 (lower byte of baud rate generator constant) */
 241
 242/* Read Register 13 (upper byte of baud rate generator constant) */
 243
 244/* Read Register 15 (value of WR 15) */
 245
 246
 247/*
 248 *      Interrupt handling functions for this SCC
 249 */
 250
 251struct z8530_channel;
 252 
 253struct z8530_irqhandler
 254{
 255        void (*rx)(struct z8530_channel *);
 256        void (*tx)(struct z8530_channel *);
 257        void (*status)(struct z8530_channel *);
 258};
 259
 260/*
 261 *      A channel of the Z8530
 262 */
 263
 264struct z8530_channel
 265{
 266        struct          z8530_irqhandler *irqs;         /* IRQ handlers */
 267        /*
 268         *      Synchronous
 269         */
 270        u16             count;          /* Buyes received */
 271        u16             max;            /* Most we can receive this frame */
 272        u16             mtu;            /* MTU of the device */
 273        u8              *dptr;          /* Pointer into rx buffer */
 274        struct sk_buff  *skb;           /* Buffer dptr points into */
 275        struct sk_buff  *skb2;          /* Pending buffer */
 276        u8              status;         /* Current DCD */
 277        u8              dcdcheck;       /* which bit to check for line */
 278        u8              sync;           /* Set if in sync mode */
 279
 280        u8              regs[32];       /* Register map for the chip */
 281        u8              pendregs[32];   /* Pending register values */
 282        
 283        struct sk_buff  *tx_skb;        /* Buffer being transmitted */
 284        struct sk_buff  *tx_next_skb;   /* Next transmit buffer */
 285        u8              *tx_ptr;        /* Byte pointer into the buffer */
 286        u8              *tx_next_ptr;   /* Next pointer to use */
 287        u8              *tx_dma_buf[2]; /* TX flip buffers for DMA */
 288        u8              tx_dma_used;    /* Flip buffer usage toggler */
 289        u16             txcount;        /* Count of bytes to transmit */
 290        
 291        void            (*rx_function)(struct z8530_channel *, struct sk_buff *);
 292        
 293        /*
 294         *      Sync DMA
 295         */
 296        
 297        u8              rxdma;          /* DMA channels */
 298        u8              txdma;          
 299        u8              rxdma_on;       /* DMA active if flag set */
 300        u8              txdma_on;
 301        u8              dma_num;        /* Buffer we are DMAing into */
 302        u8              dma_ready;      /* Is the other buffer free */
 303        u8              dma_tx;         /* TX is to use DMA */
 304        u8              *rx_buf[2];     /* The flip buffers */
 305        
 306        /*
 307         *      System
 308         */
 309         
 310        struct z8530_dev *dev;          /* Z85230 chip instance we are from */
 311        unsigned long   ctrlio;         /* I/O ports */
 312        unsigned long   dataio;
 313
 314        /*
 315         *      For PC we encode this way.
 316         */     
 317#define Z8530_PORT_SLEEP        0x80000000
 318#define Z8530_PORT_OF(x)        ((x)&0xFFFF)
 319
 320        u32             rx_overrun;             /* Overruns - not done yet */
 321        u32             rx_crc_err;
 322
 323        /*
 324         *      Bound device pointers
 325         */
 326
 327        void            *private;       /* For our owner */
 328        struct net_device       *netdevice;     /* Network layer device */
 329
 330        spinlock_t              *lock;    /* Device lock */
 331};
 332
 333/*
 334 *      Each Z853x0 device.
 335 */
 336
 337struct z8530_dev
 338{
 339        char *name;     /* Device instance name */
 340        struct z8530_channel chanA;     /* SCC channel A */
 341        struct z8530_channel chanB;     /* SCC channel B */
 342        int type;
 343#define Z8530   0       /* NMOS dinosaur */     
 344#define Z85C30  1       /* CMOS - better */
 345#define Z85230  2       /* CMOS with real FIFO */
 346        int irq;        /* Interrupt for the device */
 347        int active;     /* Soft interrupt enable - the Mac doesn't 
 348                           always have a hard disable on its 8530s... */
 349        spinlock_t lock;
 350};
 351
 352
 353/*
 354 *      Functions
 355 */
 356 
 357extern u8 z8530_dead_port[];
 358extern u8 z8530_hdlc_kilostream_85230[];
 359extern u8 z8530_hdlc_kilostream[];
 360irqreturn_t z8530_interrupt(int, void *);
 361void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io);
 362int z8530_init(struct z8530_dev *);
 363int z8530_shutdown(struct z8530_dev *);
 364int z8530_sync_open(struct net_device *, struct z8530_channel *);
 365int z8530_sync_close(struct net_device *, struct z8530_channel *);
 366int z8530_sync_dma_open(struct net_device *, struct z8530_channel *);
 367int z8530_sync_dma_close(struct net_device *, struct z8530_channel *);
 368int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *);
 369int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *);
 370int z8530_channel_load(struct z8530_channel *, u8 *);
 371netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb);
 372void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb);
 373
 374
 375/*
 376 *      Standard interrupt vector sets
 377 */
 378 
 379extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop;
 380
 381/*
 382 *      Asynchronous Interfacing
 383 */
 384
 385/*
 386 * The size of the serial xmit buffer is 1 page, or 4096 bytes
 387 */
 388
 389#define SERIAL_XMIT_SIZE 4096
 390#define WAKEUP_CHARS    256
 391
 392/*
 393 * Events are used to schedule things to happen at timer-interrupt
 394 * time, instead of at rs interrupt time.
 395 */
 396#define RS_EVENT_WRITE_WAKEUP   0
 397
 398/* Internal flags used only by kernel/chr_drv/serial.c */
 399#define ZILOG_INITIALIZED       0x80000000 /* Serial port was initialized */
 400#define ZILOG_CALLOUT_ACTIVE    0x40000000 /* Call out device is active */
 401#define ZILOG_NORMAL_ACTIVE     0x20000000 /* Normal device is active */
 402#define ZILOG_BOOT_AUTOCONF     0x10000000 /* Autoconfigure port on bootup */
 403#define ZILOG_CLOSING           0x08000000 /* Serial port is closing */
 404#define ZILOG_CTS_FLOW          0x04000000 /* Do CTS flow control */
 405#define ZILOG_CHECK_CD          0x02000000 /* i.e., CLOCAL */
 406
 407#endif /* !(_Z8530_H) */
 408