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43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/module.h>
46#include <linux/delay.h>
47#include <linux/dma-mapping.h>
48#include <linux/hardirq.h>
49#include <linux/if.h>
50#include <linux/io.h>
51#include <linux/netdevice.h>
52#include <linux/cache.h>
53#include <linux/ethtool.h>
54#include <linux/uaccess.h>
55#include <linux/slab.h>
56#include <linux/etherdevice.h>
57#include <linux/nl80211.h>
58
59#include <net/cfg80211.h>
60#include <net/ieee80211_radiotap.h>
61
62#include <asm/unaligned.h>
63
64#include <net/mac80211.h>
65#include "base.h"
66#include "reg.h"
67#include "debug.h"
68#include "ani.h"
69#include "ath5k.h"
70#include "../regd.h"
71
72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
75bool ath5k_modparam_nohwcrypt;
76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, 0444);
77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78
79static bool modparam_fastchanswitch;
80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, 0444);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
83static bool ath5k_modparam_no_hw_rfkill_switch;
84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, 0444);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
88
89
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_LICENSE("Dual BSD/GPL");
94
95static int ath5k_init(struct ieee80211_hw *hw);
96static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
97 bool skip_pcu);
98
99
100static const struct ath5k_srev_name srev_names[] = {
101#ifdef CONFIG_ATH5K_AHB
102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
104 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
109#else
110 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
111 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
112 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
113 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
114 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
115 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
116 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
117 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
118 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
119 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
120 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
121 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
122 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
123 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
124 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
125 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
126 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
127 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
128#endif
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
143 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
144#ifdef CONFIG_ATH5K_AHB
145 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
146 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
147#endif
148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149};
150
151static const struct ieee80211_rate ath5k_rates[] = {
152 { .bitrate = 10,
153 .hw_value = ATH5K_RATE_CODE_1M, },
154 { .bitrate = 20,
155 .hw_value = ATH5K_RATE_CODE_2M,
156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 55,
159 .hw_value = ATH5K_RATE_CODE_5_5M,
160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
161 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 { .bitrate = 110,
163 .hw_value = ATH5K_RATE_CODE_11M,
164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 { .bitrate = 60,
167 .hw_value = ATH5K_RATE_CODE_6M,
168 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
169 IEEE80211_RATE_SUPPORTS_10MHZ },
170 { .bitrate = 90,
171 .hw_value = ATH5K_RATE_CODE_9M,
172 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
173 IEEE80211_RATE_SUPPORTS_10MHZ },
174 { .bitrate = 120,
175 .hw_value = ATH5K_RATE_CODE_12M,
176 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
177 IEEE80211_RATE_SUPPORTS_10MHZ },
178 { .bitrate = 180,
179 .hw_value = ATH5K_RATE_CODE_18M,
180 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
181 IEEE80211_RATE_SUPPORTS_10MHZ },
182 { .bitrate = 240,
183 .hw_value = ATH5K_RATE_CODE_24M,
184 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
185 IEEE80211_RATE_SUPPORTS_10MHZ },
186 { .bitrate = 360,
187 .hw_value = ATH5K_RATE_CODE_36M,
188 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
189 IEEE80211_RATE_SUPPORTS_10MHZ },
190 { .bitrate = 480,
191 .hw_value = ATH5K_RATE_CODE_48M,
192 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
193 IEEE80211_RATE_SUPPORTS_10MHZ },
194 { .bitrate = 540,
195 .hw_value = ATH5K_RATE_CODE_54M,
196 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
197 IEEE80211_RATE_SUPPORTS_10MHZ },
198};
199
200static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
201{
202 u64 tsf = ath5k_hw_get_tsf64(ah);
203
204 if ((tsf & 0x7fff) < rstamp)
205 tsf -= 0x8000;
206
207 return (tsf & ~0x7fff) | rstamp;
208}
209
210const char *
211ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
212{
213 const char *name = "xxxxx";
214 unsigned int i;
215
216 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
217 if (srev_names[i].sr_type != type)
218 continue;
219
220 if ((val & 0xf0) == srev_names[i].sr_val)
221 name = srev_names[i].sr_name;
222
223 if ((val & 0xff) == srev_names[i].sr_val) {
224 name = srev_names[i].sr_name;
225 break;
226 }
227 }
228
229 return name;
230}
231static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
232{
233 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
234 return ath5k_hw_reg_read(ah, reg_offset);
235}
236
237static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
238{
239 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
240 ath5k_hw_reg_write(ah, val, reg_offset);
241}
242
243static const struct ath_ops ath5k_common_ops = {
244 .read = ath5k_ioread32,
245 .write = ath5k_iowrite32,
246};
247
248
249
250
251
252static void ath5k_reg_notifier(struct wiphy *wiphy,
253 struct regulatory_request *request)
254{
255 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
256 struct ath5k_hw *ah = hw->priv;
257 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
258
259 ath_reg_notifier_apply(wiphy, request, regulatory);
260}
261
262
263
264
265
266
267
268
269#ifdef CONFIG_ATH5K_TEST_CHANNELS
270static bool ath5k_is_standard_channel(short chan, enum nl80211_band band)
271{
272 return true;
273}
274
275#else
276static bool ath5k_is_standard_channel(short chan, enum nl80211_band band)
277{
278 if (band == NL80211_BAND_2GHZ && chan <= 14)
279 return true;
280
281 return
282 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
283
284 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
285
286 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
287
288 (chan == 8 || chan == 12 || chan == 16) ||
289
290 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
291}
292#endif
293
294static unsigned int
295ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
296 unsigned int mode, unsigned int max)
297{
298 unsigned int count, size, freq, ch;
299 enum nl80211_band band;
300
301 switch (mode) {
302 case AR5K_MODE_11A:
303
304 size = 220;
305 band = NL80211_BAND_5GHZ;
306 break;
307 case AR5K_MODE_11B:
308 case AR5K_MODE_11G:
309 size = 26;
310 band = NL80211_BAND_2GHZ;
311 break;
312 default:
313 ATH5K_WARN(ah, "bad mode, not copying channels\n");
314 return 0;
315 }
316
317 count = 0;
318 for (ch = 1; ch <= size && count < max; ch++) {
319 freq = ieee80211_channel_to_frequency(ch, band);
320
321 if (freq == 0)
322 continue;
323
324
325 channels[count].center_freq = freq;
326 channels[count].band = band;
327 channels[count].hw_value = mode;
328
329
330 if (!ath5k_channel_ok(ah, &channels[count]))
331 continue;
332
333 if (!ath5k_is_standard_channel(ch, band))
334 continue;
335
336 count++;
337 }
338
339 return count;
340}
341
342static void
343ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
344{
345 u8 i;
346
347 for (i = 0; i < AR5K_MAX_RATES; i++)
348 ah->rate_idx[b->band][i] = -1;
349
350 for (i = 0; i < b->n_bitrates; i++) {
351 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
352 if (b->bitrates[i].hw_value_short)
353 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
354 }
355}
356
357static int
358ath5k_setup_bands(struct ieee80211_hw *hw)
359{
360 struct ath5k_hw *ah = hw->priv;
361 struct ieee80211_supported_band *sband;
362 int max_c, count_c = 0;
363 int i;
364
365 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS);
366 max_c = ARRAY_SIZE(ah->channels);
367
368
369 sband = &ah->sbands[NL80211_BAND_2GHZ];
370 sband->band = NL80211_BAND_2GHZ;
371 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0];
372
373 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
374
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 12);
377 sband->n_bitrates = 12;
378
379 sband->channels = ah->channels;
380 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
381 AR5K_MODE_11G, max_c);
382
383 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
384 count_c = sband->n_channels;
385 max_c -= count_c;
386 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
387
388 memcpy(sband->bitrates, &ath5k_rates[0],
389 sizeof(struct ieee80211_rate) * 4);
390 sband->n_bitrates = 4;
391
392
393
394
395
396 if (ah->ah_version == AR5K_AR5211) {
397 for (i = 0; i < 4; i++) {
398 sband->bitrates[i].hw_value =
399 sband->bitrates[i].hw_value & 0xF;
400 sband->bitrates[i].hw_value_short =
401 sband->bitrates[i].hw_value_short & 0xF;
402 }
403 }
404
405 sband->channels = ah->channels;
406 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
407 AR5K_MODE_11B, max_c);
408
409 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
410 count_c = sband->n_channels;
411 max_c -= count_c;
412 }
413 ath5k_setup_rate_idx(ah, sband);
414
415
416 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
417 sband = &ah->sbands[NL80211_BAND_5GHZ];
418 sband->band = NL80211_BAND_5GHZ;
419 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0];
420
421 memcpy(sband->bitrates, &ath5k_rates[4],
422 sizeof(struct ieee80211_rate) * 8);
423 sband->n_bitrates = 8;
424
425 sband->channels = &ah->channels[count_c];
426 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
427 AR5K_MODE_11A, max_c);
428
429 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
430 }
431 ath5k_setup_rate_idx(ah, sband);
432
433 ath5k_debug_dump_bands(ah);
434
435 return 0;
436}
437
438
439
440
441
442
443
444
445int
446ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
447{
448 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
449 "channel set, resetting (%u -> %u MHz)\n",
450 ah->curchan->center_freq, chandef->chan->center_freq);
451
452 switch (chandef->width) {
453 case NL80211_CHAN_WIDTH_20:
454 case NL80211_CHAN_WIDTH_20_NOHT:
455 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
456 break;
457 case NL80211_CHAN_WIDTH_5:
458 ah->ah_bwmode = AR5K_BWMODE_5MHZ;
459 break;
460 case NL80211_CHAN_WIDTH_10:
461 ah->ah_bwmode = AR5K_BWMODE_10MHZ;
462 break;
463 default:
464 WARN_ON(1);
465 return -EINVAL;
466 }
467
468
469
470
471
472
473
474 return ath5k_reset(ah, chandef->chan, true);
475}
476
477void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
478{
479 struct ath5k_vif_iter_data *iter_data = data;
480 int i;
481 struct ath5k_vif *avf = (void *)vif->drv_priv;
482
483 if (iter_data->hw_macaddr)
484 for (i = 0; i < ETH_ALEN; i++)
485 iter_data->mask[i] &=
486 ~(iter_data->hw_macaddr[i] ^ mac[i]);
487
488 if (!iter_data->found_active) {
489 iter_data->found_active = true;
490 memcpy(iter_data->active_mac, mac, ETH_ALEN);
491 }
492
493 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
494 if (ether_addr_equal(iter_data->hw_macaddr, mac))
495 iter_data->need_set_hw_addr = false;
496
497 if (!iter_data->any_assoc) {
498 if (avf->assoc)
499 iter_data->any_assoc = true;
500 }
501
502
503
504
505
506
507 if (avf->opmode == NL80211_IFTYPE_AP)
508 iter_data->opmode = NL80211_IFTYPE_AP;
509 else {
510 if (avf->opmode == NL80211_IFTYPE_STATION)
511 iter_data->n_stas++;
512 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
513 iter_data->opmode = avf->opmode;
514 }
515}
516
517void
518ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
519 struct ieee80211_vif *vif)
520{
521 struct ath_common *common = ath5k_hw_common(ah);
522 struct ath5k_vif_iter_data iter_data;
523 u32 rfilt;
524
525
526
527
528
529 iter_data.hw_macaddr = common->macaddr;
530 eth_broadcast_addr(iter_data.mask);
531 iter_data.found_active = false;
532 iter_data.need_set_hw_addr = true;
533 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
534 iter_data.n_stas = 0;
535
536 if (vif)
537 ath5k_vif_iter(&iter_data, vif->addr, vif);
538
539
540 ieee80211_iterate_active_interfaces_atomic(
541 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
542 ath5k_vif_iter, &iter_data);
543 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
544
545 ah->opmode = iter_data.opmode;
546 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
547
548 ah->opmode = NL80211_IFTYPE_STATION;
549
550 ath5k_hw_set_opmode(ah, ah->opmode);
551 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
552 ah->opmode, ath_opmode_to_string(ah->opmode));
553
554 if (iter_data.need_set_hw_addr && iter_data.found_active)
555 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
556
557 if (ath5k_hw_hasbssidmask(ah))
558 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
559
560
561 if (iter_data.n_stas > 1) {
562
563
564
565
566 ah->filter_flags |= AR5K_RX_FILTER_PROM;
567 }
568
569 rfilt = ah->filter_flags;
570 ath5k_hw_set_rx_filter(ah, rfilt);
571 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
572}
573
574static inline int
575ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
576{
577 int rix;
578
579
580 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
581 "hw_rix out of bounds: %x\n", hw_rix))
582 return 0;
583
584 rix = ah->rate_idx[ah->curchan->band][hw_rix];
585 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
586 rix = 0;
587
588 return rix;
589}
590
591
592
593
594
595static
596struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
597{
598 struct ath_common *common = ath5k_hw_common(ah);
599 struct sk_buff *skb;
600
601
602
603
604
605 skb = ath_rxbuf_alloc(common,
606 common->rx_bufsize,
607 GFP_ATOMIC);
608
609 if (!skb) {
610 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
611 common->rx_bufsize);
612 return NULL;
613 }
614
615 *skb_addr = dma_map_single(ah->dev,
616 skb->data, common->rx_bufsize,
617 DMA_FROM_DEVICE);
618
619 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
620 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
621 dev_kfree_skb(skb);
622 return NULL;
623 }
624 return skb;
625}
626
627static int
628ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
629{
630 struct sk_buff *skb = bf->skb;
631 struct ath5k_desc *ds;
632 int ret;
633
634 if (!skb) {
635 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
636 if (!skb)
637 return -ENOMEM;
638 bf->skb = skb;
639 }
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656 ds = bf->desc;
657 ds->ds_link = bf->daddr;
658 ds->ds_data = bf->skbaddr;
659 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
660 if (ret) {
661 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
662 return ret;
663 }
664
665 if (ah->rxlink != NULL)
666 *ah->rxlink = bf->daddr;
667 ah->rxlink = &ds->ds_link;
668 return 0;
669}
670
671static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
672{
673 struct ieee80211_hdr *hdr;
674 enum ath5k_pkt_type htype;
675 __le16 fc;
676
677 hdr = (struct ieee80211_hdr *)skb->data;
678 fc = hdr->frame_control;
679
680 if (ieee80211_is_beacon(fc))
681 htype = AR5K_PKT_TYPE_BEACON;
682 else if (ieee80211_is_probe_resp(fc))
683 htype = AR5K_PKT_TYPE_PROBE_RESP;
684 else if (ieee80211_is_atim(fc))
685 htype = AR5K_PKT_TYPE_ATIM;
686 else if (ieee80211_is_pspoll(fc))
687 htype = AR5K_PKT_TYPE_PSPOLL;
688 else
689 htype = AR5K_PKT_TYPE_NORMAL;
690
691 return htype;
692}
693
694static struct ieee80211_rate *
695ath5k_get_rate(const struct ieee80211_hw *hw,
696 const struct ieee80211_tx_info *info,
697 struct ath5k_buf *bf, int idx)
698{
699
700
701
702
703 if (bf->rates[idx].idx < 0) {
704 return NULL;
705 }
706
707 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
708}
709
710static u16
711ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
712 const struct ieee80211_tx_info *info,
713 struct ath5k_buf *bf, int idx)
714{
715 struct ieee80211_rate *rate;
716 u16 hw_rate;
717 u8 rc_flags;
718
719 rate = ath5k_get_rate(hw, info, bf, idx);
720 if (!rate)
721 return 0;
722
723 rc_flags = bf->rates[idx].flags;
724 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
725 rate->hw_value_short : rate->hw_value;
726
727 return hw_rate;
728}
729
730static int
731ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
732 struct ath5k_txq *txq, int padsize,
733 struct ieee80211_tx_control *control)
734{
735 struct ath5k_desc *ds = bf->desc;
736 struct sk_buff *skb = bf->skb;
737 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
738 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
739 struct ieee80211_rate *rate;
740 unsigned int mrr_rate[3], mrr_tries[3];
741 int i, ret;
742 u16 hw_rate;
743 u16 cts_rate = 0;
744 u16 duration = 0;
745 u8 rc_flags;
746
747 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
748
749
750 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
751 DMA_TO_DEVICE);
752
753 if (dma_mapping_error(ah->dev, bf->skbaddr))
754 return -ENOSPC;
755
756 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
757 ARRAY_SIZE(bf->rates));
758
759 rate = ath5k_get_rate(ah->hw, info, bf, 0);
760
761 if (!rate) {
762 ret = -EINVAL;
763 goto err_unmap;
764 }
765
766 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
767 flags |= AR5K_TXDESC_NOACK;
768
769 rc_flags = bf->rates[0].flags;
770
771 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
772
773 pktlen = skb->len;
774
775
776
777
778 if (info->control.hw_key) {
779 keyidx = info->control.hw_key->hw_key_idx;
780 pktlen += info->control.hw_key->icv_len;
781 }
782 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
783 flags |= AR5K_TXDESC_RTSENA;
784 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
785 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
786 info->control.vif, pktlen, info));
787 }
788 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
789 flags |= AR5K_TXDESC_CTSENA;
790 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
791 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
792 info->control.vif, pktlen, info));
793 }
794
795 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
796 ieee80211_get_hdrlen_from_skb(skb), padsize,
797 get_hw_packet_type(skb),
798 (ah->ah_txpower.txp_requested * 2),
799 hw_rate,
800 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
801 cts_rate, duration);
802 if (ret)
803 goto err_unmap;
804
805
806 if (ah->ah_capabilities.cap_has_mrr_support) {
807 memset(mrr_rate, 0, sizeof(mrr_rate));
808 memset(mrr_tries, 0, sizeof(mrr_tries));
809
810 for (i = 0; i < 3; i++) {
811
812 rate = ath5k_get_rate(ah->hw, info, bf, i);
813 if (!rate)
814 break;
815
816 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
817 mrr_tries[i] = bf->rates[i].count;
818 }
819
820 ath5k_hw_setup_mrr_tx_desc(ah, ds,
821 mrr_rate[0], mrr_tries[0],
822 mrr_rate[1], mrr_tries[1],
823 mrr_rate[2], mrr_tries[2]);
824 }
825
826 ds->ds_link = 0;
827 ds->ds_data = bf->skbaddr;
828
829 spin_lock_bh(&txq->lock);
830 list_add_tail(&bf->list, &txq->q);
831 txq->txq_len++;
832 if (txq->link == NULL)
833 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
834 else
835 *txq->link = bf->daddr;
836
837 txq->link = &ds->ds_link;
838 ath5k_hw_start_tx_dma(ah, txq->qnum);
839 spin_unlock_bh(&txq->lock);
840
841 return 0;
842err_unmap:
843 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
844 return ret;
845}
846
847
848
849
850
851static int
852ath5k_desc_alloc(struct ath5k_hw *ah)
853{
854 struct ath5k_desc *ds;
855 struct ath5k_buf *bf;
856 dma_addr_t da;
857 unsigned int i;
858 int ret;
859
860
861 ah->desc_len = sizeof(struct ath5k_desc) *
862 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
863
864 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
865 &ah->desc_daddr, GFP_KERNEL);
866 if (ah->desc == NULL) {
867 ATH5K_ERR(ah, "can't allocate descriptors\n");
868 ret = -ENOMEM;
869 goto err;
870 }
871 ds = ah->desc;
872 da = ah->desc_daddr;
873 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
874 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
875
876 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
877 sizeof(struct ath5k_buf), GFP_KERNEL);
878 if (bf == NULL) {
879 ATH5K_ERR(ah, "can't allocate bufptr\n");
880 ret = -ENOMEM;
881 goto err_free;
882 }
883 ah->bufptr = bf;
884
885 INIT_LIST_HEAD(&ah->rxbuf);
886 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
887 bf->desc = ds;
888 bf->daddr = da;
889 list_add_tail(&bf->list, &ah->rxbuf);
890 }
891
892 INIT_LIST_HEAD(&ah->txbuf);
893 ah->txbuf_len = ATH_TXBUF;
894 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
895 bf->desc = ds;
896 bf->daddr = da;
897 list_add_tail(&bf->list, &ah->txbuf);
898 }
899
900
901 INIT_LIST_HEAD(&ah->bcbuf);
902 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
903 bf->desc = ds;
904 bf->daddr = da;
905 list_add_tail(&bf->list, &ah->bcbuf);
906 }
907
908 return 0;
909err_free:
910 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
911err:
912 ah->desc = NULL;
913 return ret;
914}
915
916void
917ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
918{
919 BUG_ON(!bf);
920 if (!bf->skb)
921 return;
922 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
923 DMA_TO_DEVICE);
924 ieee80211_free_txskb(ah->hw, bf->skb);
925 bf->skb = NULL;
926 bf->skbaddr = 0;
927 bf->desc->ds_data = 0;
928}
929
930void
931ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
932{
933 struct ath_common *common = ath5k_hw_common(ah);
934
935 BUG_ON(!bf);
936 if (!bf->skb)
937 return;
938 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
939 DMA_FROM_DEVICE);
940 dev_kfree_skb_any(bf->skb);
941 bf->skb = NULL;
942 bf->skbaddr = 0;
943 bf->desc->ds_data = 0;
944}
945
946static void
947ath5k_desc_free(struct ath5k_hw *ah)
948{
949 struct ath5k_buf *bf;
950
951 list_for_each_entry(bf, &ah->txbuf, list)
952 ath5k_txbuf_free_skb(ah, bf);
953 list_for_each_entry(bf, &ah->rxbuf, list)
954 ath5k_rxbuf_free_skb(ah, bf);
955 list_for_each_entry(bf, &ah->bcbuf, list)
956 ath5k_txbuf_free_skb(ah, bf);
957
958
959 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
960 ah->desc = NULL;
961 ah->desc_daddr = 0;
962
963 kfree(ah->bufptr);
964 ah->bufptr = NULL;
965}
966
967
968
969
970
971
972static struct ath5k_txq *
973ath5k_txq_setup(struct ath5k_hw *ah,
974 int qtype, int subtype)
975{
976 struct ath5k_txq *txq;
977 struct ath5k_txq_info qi = {
978 .tqi_subtype = subtype,
979
980
981 .tqi_aifs = AR5K_TUNE_AIFS,
982 .tqi_cw_min = AR5K_TUNE_CWMIN,
983 .tqi_cw_max = AR5K_TUNE_CWMAX
984 };
985 int qnum;
986
987
988
989
990
991
992
993
994
995
996
997
998
999 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1000 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1001 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1002 if (qnum < 0) {
1003
1004
1005
1006
1007 return ERR_PTR(qnum);
1008 }
1009 txq = &ah->txqs[qnum];
1010 if (!txq->setup) {
1011 txq->qnum = qnum;
1012 txq->link = NULL;
1013 INIT_LIST_HEAD(&txq->q);
1014 spin_lock_init(&txq->lock);
1015 txq->setup = true;
1016 txq->txq_len = 0;
1017 txq->txq_max = ATH5K_TXQ_LEN_MAX;
1018 txq->txq_poll_mark = false;
1019 txq->txq_stuck = 0;
1020 }
1021 return &ah->txqs[qnum];
1022}
1023
1024static int
1025ath5k_beaconq_setup(struct ath5k_hw *ah)
1026{
1027 struct ath5k_txq_info qi = {
1028
1029
1030 .tqi_aifs = AR5K_TUNE_AIFS,
1031 .tqi_cw_min = AR5K_TUNE_CWMIN,
1032 .tqi_cw_max = AR5K_TUNE_CWMAX,
1033
1034 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1035 };
1036
1037 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1038}
1039
1040static int
1041ath5k_beaconq_config(struct ath5k_hw *ah)
1042{
1043 struct ath5k_txq_info qi;
1044 int ret;
1045
1046 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
1047 if (ret)
1048 goto err;
1049
1050 if (ah->opmode == NL80211_IFTYPE_AP ||
1051 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1052
1053
1054
1055
1056 qi.tqi_aifs = 0;
1057 qi.tqi_cw_min = 0;
1058 qi.tqi_cw_max = 0;
1059 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
1060
1061
1062
1063 qi.tqi_aifs = 0;
1064 qi.tqi_cw_min = 0;
1065 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1066 }
1067
1068 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1069 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1070 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1071
1072 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1073 if (ret) {
1074 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1075 "hardware queue!\n", __func__);
1076 goto err;
1077 }
1078 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq);
1079 if (ret)
1080 goto err;
1081
1082
1083 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1084 if (ret)
1085 goto err;
1086
1087 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1088 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1089 if (ret)
1090 goto err;
1091
1092 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1093err:
1094 return ret;
1095}
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static void
1109ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1110{
1111 struct ath5k_txq *txq;
1112 struct ath5k_buf *bf, *bf0;
1113 int i;
1114
1115 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1116 if (ah->txqs[i].setup) {
1117 txq = &ah->txqs[i];
1118 spin_lock_bh(&txq->lock);
1119 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1120 ath5k_debug_printtxbuf(ah, bf);
1121
1122 ath5k_txbuf_free_skb(ah, bf);
1123
1124 spin_lock(&ah->txbuflock);
1125 list_move_tail(&bf->list, &ah->txbuf);
1126 ah->txbuf_len++;
1127 txq->txq_len--;
1128 spin_unlock(&ah->txbuflock);
1129 }
1130 txq->link = NULL;
1131 txq->txq_poll_mark = false;
1132 spin_unlock_bh(&txq->lock);
1133 }
1134 }
1135}
1136
1137static void
1138ath5k_txq_release(struct ath5k_hw *ah)
1139{
1140 struct ath5k_txq *txq = ah->txqs;
1141 unsigned int i;
1142
1143 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1144 if (txq->setup) {
1145 ath5k_hw_release_tx_queue(ah, txq->qnum);
1146 txq->setup = false;
1147 }
1148}
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158static int
1159ath5k_rx_start(struct ath5k_hw *ah)
1160{
1161 struct ath_common *common = ath5k_hw_common(ah);
1162 struct ath5k_buf *bf;
1163 int ret;
1164
1165 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1166
1167 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1168 common->cachelsz, common->rx_bufsize);
1169
1170 spin_lock_bh(&ah->rxbuflock);
1171 ah->rxlink = NULL;
1172 list_for_each_entry(bf, &ah->rxbuf, list) {
1173 ret = ath5k_rxbuf_setup(ah, bf);
1174 if (ret != 0) {
1175 spin_unlock_bh(&ah->rxbuflock);
1176 goto err;
1177 }
1178 }
1179 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1180 ath5k_hw_set_rxdp(ah, bf->daddr);
1181 spin_unlock_bh(&ah->rxbuflock);
1182
1183 ath5k_hw_start_rx_dma(ah);
1184 ath5k_update_bssid_mask_and_opmode(ah, NULL);
1185 ath5k_hw_start_rx_pcu(ah);
1186
1187 return 0;
1188err:
1189 return ret;
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199static void
1200ath5k_rx_stop(struct ath5k_hw *ah)
1201{
1202
1203 ath5k_hw_set_rx_filter(ah, 0);
1204 ath5k_hw_stop_rx_pcu(ah);
1205
1206 ath5k_debug_printrxbuffs(ah);
1207}
1208
1209static unsigned int
1210ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1211 struct ath5k_rx_status *rs)
1212{
1213 struct ath_common *common = ath5k_hw_common(ah);
1214 struct ieee80211_hdr *hdr = (void *)skb->data;
1215 unsigned int keyix, hlen;
1216
1217 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1218 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1219 return RX_FLAG_DECRYPTED;
1220
1221
1222
1223
1224 hlen = ieee80211_hdrlen(hdr->frame_control);
1225 if (ieee80211_has_protected(hdr->frame_control) &&
1226 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1227 skb->len >= hlen + 4) {
1228 keyix = skb->data[hlen + 3] >> 6;
1229
1230 if (test_bit(keyix, common->keymap))
1231 return RX_FLAG_DECRYPTED;
1232 }
1233
1234 return 0;
1235}
1236
1237
1238static void
1239ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1240 struct ieee80211_rx_status *rxs)
1241{
1242 u64 tsf, bc_tstamp;
1243 u32 hw_tu;
1244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1245
1246 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) {
1247
1248
1249
1250
1251
1252 tsf = ath5k_hw_get_tsf64(ah);
1253 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1254 hw_tu = TSF_TO_TU(tsf);
1255
1256 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1257 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1258 (unsigned long long)bc_tstamp,
1259 (unsigned long long)rxs->mactime,
1260 (unsigned long long)(rxs->mactime - bc_tstamp),
1261 (unsigned long long)tsf);
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274 if (bc_tstamp > rxs->mactime) {
1275 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1276 "fixing mactime from %llx to %llx\n",
1277 (unsigned long long)rxs->mactime,
1278 (unsigned long long)tsf);
1279 rxs->mactime = tsf;
1280 }
1281
1282
1283
1284
1285
1286
1287
1288 if (hw_tu >= ah->nexttbtt)
1289 ath5k_beacon_update_timers(ah, bc_tstamp);
1290
1291
1292
1293
1294 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1295 ath5k_beacon_update_timers(ah, bc_tstamp);
1296 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1297 "fixed beacon timers after beacon receive\n");
1298 }
1299 }
1300}
1301
1302
1303
1304
1305static int ath5k_common_padpos(struct sk_buff *skb)
1306{
1307 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1308 __le16 frame_control = hdr->frame_control;
1309 int padpos = 24;
1310
1311 if (ieee80211_has_a4(frame_control))
1312 padpos += ETH_ALEN;
1313
1314 if (ieee80211_is_data_qos(frame_control))
1315 padpos += IEEE80211_QOS_CTL_LEN;
1316
1317 return padpos;
1318}
1319
1320
1321
1322
1323
1324static int ath5k_add_padding(struct sk_buff *skb)
1325{
1326 int padpos = ath5k_common_padpos(skb);
1327 int padsize = padpos & 3;
1328
1329 if (padsize && skb->len > padpos) {
1330
1331 if (skb_headroom(skb) < padsize)
1332 return -1;
1333
1334 skb_push(skb, padsize);
1335 memmove(skb->data, skb->data + padsize, padpos);
1336 return padsize;
1337 }
1338
1339 return 0;
1340}
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355static int ath5k_remove_padding(struct sk_buff *skb)
1356{
1357 int padpos = ath5k_common_padpos(skb);
1358 int padsize = padpos & 3;
1359
1360 if (padsize && skb->len >= padpos + padsize) {
1361 memmove(skb->data + padsize, skb->data, padpos);
1362 skb_pull(skb, padsize);
1363 return padsize;
1364 }
1365
1366 return 0;
1367}
1368
1369static void
1370ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1371 struct ath5k_rx_status *rs)
1372{
1373 struct ieee80211_rx_status *rxs;
1374 struct ath_common *common = ath5k_hw_common(ah);
1375
1376 ath5k_remove_padding(skb);
1377
1378 rxs = IEEE80211_SKB_RXCB(skb);
1379
1380 rxs->flag = 0;
1381 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1382 rxs->flag |= RX_FLAG_MMIC_ERROR;
1383 if (unlikely(rs->rs_status & AR5K_RXERR_CRC))
1384 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1397 rxs->flag |= RX_FLAG_MACTIME_END;
1398
1399 rxs->freq = ah->curchan->center_freq;
1400 rxs->band = ah->curchan->band;
1401
1402 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1403
1404 rxs->antenna = rs->rs_antenna;
1405
1406 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1407 ah->stats.antenna_rx[rs->rs_antenna]++;
1408 else
1409 ah->stats.antenna_rx[0]++;
1410
1411 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1412 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1413 switch (ah->ah_bwmode) {
1414 case AR5K_BWMODE_5MHZ:
1415 rxs->bw = RATE_INFO_BW_5;
1416 break;
1417 case AR5K_BWMODE_10MHZ:
1418 rxs->bw = RATE_INFO_BW_10;
1419 break;
1420 default:
1421 break;
1422 }
1423
1424 if (rs->rs_rate ==
1425 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1426 rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
1427
1428 trace_ath5k_rx(ah, skb);
1429
1430 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) {
1431 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi);
1432
1433
1434 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1435 ath5k_check_ibss_tsf(ah, skb, rxs);
1436 }
1437
1438 ieee80211_rx(ah->hw, skb);
1439}
1440
1441
1442
1443
1444
1445
1446static bool
1447ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1448{
1449 ah->stats.rx_all_count++;
1450 ah->stats.rx_bytes_count += rs->rs_datalen;
1451
1452 if (unlikely(rs->rs_status)) {
1453 unsigned int filters;
1454
1455 if (rs->rs_status & AR5K_RXERR_CRC)
1456 ah->stats.rxerr_crc++;
1457 if (rs->rs_status & AR5K_RXERR_FIFO)
1458 ah->stats.rxerr_fifo++;
1459 if (rs->rs_status & AR5K_RXERR_PHY) {
1460 ah->stats.rxerr_phy++;
1461 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1462 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1463
1464
1465
1466
1467
1468
1469
1470 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART ||
1471 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) {
1472 rs->rs_status |= AR5K_RXERR_CRC;
1473 rs->rs_status &= ~AR5K_RXERR_PHY;
1474 } else {
1475 return false;
1476 }
1477 }
1478 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489 ah->stats.rxerr_decrypt++;
1490 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1491 !(rs->rs_status & AR5K_RXERR_CRC))
1492 return true;
1493 }
1494 if (rs->rs_status & AR5K_RXERR_MIC) {
1495 ah->stats.rxerr_mic++;
1496 return true;
1497 }
1498
1499
1500
1501
1502
1503 filters = AR5K_RXERR_DECRYPT;
1504 if (ah->fif_filter_flags & FIF_FCSFAIL)
1505 filters |= AR5K_RXERR_CRC;
1506
1507 if (rs->rs_status & ~filters)
1508 return false;
1509 }
1510
1511 if (unlikely(rs->rs_more)) {
1512 ah->stats.rxerr_jumbo++;
1513 return false;
1514 }
1515 return true;
1516}
1517
1518static void
1519ath5k_set_current_imask(struct ath5k_hw *ah)
1520{
1521 enum ath5k_int imask;
1522 unsigned long flags;
1523
1524 if (test_bit(ATH_STAT_RESET, ah->status))
1525 return;
1526
1527 spin_lock_irqsave(&ah->irqlock, flags);
1528 imask = ah->imask;
1529 if (ah->rx_pending)
1530 imask &= ~AR5K_INT_RX_ALL;
1531 if (ah->tx_pending)
1532 imask &= ~AR5K_INT_TX_ALL;
1533 ath5k_hw_set_imr(ah, imask);
1534 spin_unlock_irqrestore(&ah->irqlock, flags);
1535}
1536
1537static void
1538ath5k_tasklet_rx(struct tasklet_struct *t)
1539{
1540 struct ath5k_rx_status rs = {};
1541 struct sk_buff *skb, *next_skb;
1542 dma_addr_t next_skb_addr;
1543 struct ath5k_hw *ah = from_tasklet(ah, t, rxtq);
1544 struct ath_common *common = ath5k_hw_common(ah);
1545 struct ath5k_buf *bf;
1546 struct ath5k_desc *ds;
1547 int ret;
1548
1549 spin_lock(&ah->rxbuflock);
1550 if (list_empty(&ah->rxbuf)) {
1551 ATH5K_WARN(ah, "empty rx buf pool\n");
1552 goto unlock;
1553 }
1554 do {
1555 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1556 BUG_ON(bf->skb == NULL);
1557 skb = bf->skb;
1558 ds = bf->desc;
1559
1560
1561 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1562 break;
1563
1564 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1565 if (unlikely(ret == -EINPROGRESS))
1566 break;
1567 else if (unlikely(ret)) {
1568 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1569 ah->stats.rxerr_proc++;
1570 break;
1571 }
1572
1573 if (ath5k_receive_frame_ok(ah, &rs)) {
1574 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1575
1576
1577
1578
1579
1580 if (!next_skb)
1581 goto next;
1582
1583 dma_unmap_single(ah->dev, bf->skbaddr,
1584 common->rx_bufsize,
1585 DMA_FROM_DEVICE);
1586
1587 skb_put(skb, rs.rs_datalen);
1588
1589 ath5k_receive_frame(ah, skb, &rs);
1590
1591 bf->skb = next_skb;
1592 bf->skbaddr = next_skb_addr;
1593 }
1594next:
1595 list_move_tail(&bf->list, &ah->rxbuf);
1596 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1597unlock:
1598 spin_unlock(&ah->rxbuflock);
1599 ah->rx_pending = false;
1600 ath5k_set_current_imask(ah);
1601}
1602
1603
1604
1605
1606
1607
1608void
1609ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1610 struct ath5k_txq *txq, struct ieee80211_tx_control *control)
1611{
1612 struct ath5k_hw *ah = hw->priv;
1613 struct ath5k_buf *bf;
1614 unsigned long flags;
1615 int padsize;
1616
1617 trace_ath5k_tx(ah, skb, txq);
1618
1619
1620
1621
1622
1623 padsize = ath5k_add_padding(skb);
1624 if (padsize < 0) {
1625 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1626 " headroom to pad");
1627 goto drop_packet;
1628 }
1629
1630 if (txq->txq_len >= txq->txq_max &&
1631 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1632 ieee80211_stop_queue(hw, txq->qnum);
1633
1634 spin_lock_irqsave(&ah->txbuflock, flags);
1635 if (list_empty(&ah->txbuf)) {
1636 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1637 spin_unlock_irqrestore(&ah->txbuflock, flags);
1638 ieee80211_stop_queues(hw);
1639 goto drop_packet;
1640 }
1641 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1642 list_del(&bf->list);
1643 ah->txbuf_len--;
1644 if (list_empty(&ah->txbuf))
1645 ieee80211_stop_queues(hw);
1646 spin_unlock_irqrestore(&ah->txbuflock, flags);
1647
1648 bf->skb = skb;
1649
1650 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
1651 bf->skb = NULL;
1652 spin_lock_irqsave(&ah->txbuflock, flags);
1653 list_add_tail(&bf->list, &ah->txbuf);
1654 ah->txbuf_len++;
1655 spin_unlock_irqrestore(&ah->txbuflock, flags);
1656 goto drop_packet;
1657 }
1658 return;
1659
1660drop_packet:
1661 ieee80211_free_txskb(hw, skb);
1662}
1663
1664static void
1665ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1666 struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1667 struct ath5k_buf *bf)
1668{
1669 struct ieee80211_tx_info *info;
1670 u8 tries[3];
1671 int i;
1672 int size = 0;
1673
1674 ah->stats.tx_all_count++;
1675 ah->stats.tx_bytes_count += skb->len;
1676 info = IEEE80211_SKB_CB(skb);
1677
1678 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1679 memcpy(info->status.rates, bf->rates, size);
1680
1681 tries[0] = info->status.rates[0].count;
1682 tries[1] = info->status.rates[1].count;
1683 tries[2] = info->status.rates[2].count;
1684
1685 ieee80211_tx_info_clear_status(info);
1686
1687 for (i = 0; i < ts->ts_final_idx; i++) {
1688 struct ieee80211_tx_rate *r =
1689 &info->status.rates[i];
1690
1691 r->count = tries[i];
1692 }
1693
1694 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1695 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1696
1697 if (unlikely(ts->ts_status)) {
1698 ah->stats.ack_fail++;
1699 if (ts->ts_status & AR5K_TXERR_FILT) {
1700 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1701 ah->stats.txerr_filt++;
1702 }
1703 if (ts->ts_status & AR5K_TXERR_XRETRY)
1704 ah->stats.txerr_retry++;
1705 if (ts->ts_status & AR5K_TXERR_FIFO)
1706 ah->stats.txerr_fifo++;
1707 } else {
1708 info->flags |= IEEE80211_TX_STAT_ACK;
1709 info->status.ack_signal = ts->ts_rssi;
1710
1711
1712 info->status.rates[ts->ts_final_idx].count++;
1713 }
1714
1715
1716
1717
1718
1719 ath5k_remove_padding(skb);
1720
1721 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1722 ah->stats.antenna_tx[ts->ts_antenna]++;
1723 else
1724 ah->stats.antenna_tx[0]++;
1725
1726 trace_ath5k_tx_complete(ah, skb, txq, ts);
1727 ieee80211_tx_status(ah->hw, skb);
1728}
1729
1730static void
1731ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1732{
1733 struct ath5k_tx_status ts = {};
1734 struct ath5k_buf *bf, *bf0;
1735 struct ath5k_desc *ds;
1736 struct sk_buff *skb;
1737 int ret;
1738
1739 spin_lock(&txq->lock);
1740 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1741
1742 txq->txq_poll_mark = false;
1743
1744
1745 if (bf->skb != NULL) {
1746 ds = bf->desc;
1747
1748 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1749 if (unlikely(ret == -EINPROGRESS))
1750 break;
1751 else if (unlikely(ret)) {
1752 ATH5K_ERR(ah,
1753 "error %d while processing "
1754 "queue %u\n", ret, txq->qnum);
1755 break;
1756 }
1757
1758 skb = bf->skb;
1759 bf->skb = NULL;
1760
1761 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1762 DMA_TO_DEVICE);
1763 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
1764 }
1765
1766
1767
1768
1769
1770
1771
1772 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1773 spin_lock(&ah->txbuflock);
1774 list_move_tail(&bf->list, &ah->txbuf);
1775 ah->txbuf_len++;
1776 txq->txq_len--;
1777 spin_unlock(&ah->txbuflock);
1778 }
1779 }
1780 spin_unlock(&txq->lock);
1781 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1782 ieee80211_wake_queue(ah->hw, txq->qnum);
1783}
1784
1785static void
1786ath5k_tasklet_tx(struct tasklet_struct *t)
1787{
1788 int i;
1789 struct ath5k_hw *ah = from_tasklet(ah, t, txtq);
1790
1791 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1792 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1793 ath5k_tx_processq(ah, &ah->txqs[i]);
1794
1795 ah->tx_pending = false;
1796 ath5k_set_current_imask(ah);
1797}
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807static int
1808ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1809{
1810 struct sk_buff *skb = bf->skb;
1811 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1812 struct ath5k_desc *ds;
1813 int ret = 0;
1814 u8 antenna;
1815 u32 flags;
1816 const int padsize = 0;
1817
1818 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1819 DMA_TO_DEVICE);
1820 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1821 "skbaddr %llx\n", skb, skb->data, skb->len,
1822 (unsigned long long)bf->skbaddr);
1823
1824 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1825 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1826 dev_kfree_skb_any(skb);
1827 bf->skb = NULL;
1828 return -EIO;
1829 }
1830
1831 ds = bf->desc;
1832 antenna = ah->ah_tx_ant;
1833
1834 flags = AR5K_TXDESC_NOACK;
1835 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1836 ds->ds_link = bf->daddr;
1837 flags |= AR5K_TXDESC_VEOL;
1838 } else
1839 ds->ds_link = 0;
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1860 antenna = ah->bsent & 4 ? 2 : 1;
1861
1862
1863
1864
1865
1866 ds->ds_data = bf->skbaddr;
1867 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1868 ieee80211_get_hdrlen_from_skb(skb), padsize,
1869 AR5K_PKT_TYPE_BEACON,
1870 (ah->ah_txpower.txp_requested * 2),
1871 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1872 1, AR5K_TXKEYIX_INVALID,
1873 antenna, flags, 0, 0);
1874 if (ret)
1875 goto err_unmap;
1876
1877 return 0;
1878err_unmap:
1879 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1880 return ret;
1881}
1882
1883
1884
1885
1886
1887
1888
1889
1890int
1891ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1892{
1893 int ret;
1894 struct ath5k_hw *ah = hw->priv;
1895 struct ath5k_vif *avf;
1896 struct sk_buff *skb;
1897
1898 if (WARN_ON(!vif)) {
1899 ret = -EINVAL;
1900 goto out;
1901 }
1902
1903 skb = ieee80211_beacon_get(hw, vif);
1904
1905 if (!skb) {
1906 ret = -ENOMEM;
1907 goto out;
1908 }
1909
1910 avf = (void *)vif->drv_priv;
1911 ath5k_txbuf_free_skb(ah, avf->bbuf);
1912 avf->bbuf->skb = skb;
1913 ret = ath5k_beacon_setup(ah, avf->bbuf);
1914out:
1915 return ret;
1916}
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926static void
1927ath5k_beacon_send(struct ath5k_hw *ah)
1928{
1929 struct ieee80211_vif *vif;
1930 struct ath5k_vif *avf;
1931 struct ath5k_buf *bf;
1932 struct sk_buff *skb;
1933 int err;
1934
1935 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1936
1937
1938
1939
1940
1941
1942
1943
1944 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1945 ah->bmisscount++;
1946 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1947 "missed %u consecutive beacons\n", ah->bmisscount);
1948 if (ah->bmisscount > 10) {
1949 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1950 "stuck beacon time (%u missed)\n",
1951 ah->bmisscount);
1952 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1953 "stuck beacon, resetting\n");
1954 ieee80211_queue_work(ah->hw, &ah->reset_work);
1955 }
1956 return;
1957 }
1958 if (unlikely(ah->bmisscount != 0)) {
1959 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1960 "resume beacon xmit after %u misses\n",
1961 ah->bmisscount);
1962 ah->bmisscount = 0;
1963 }
1964
1965 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1966 ah->num_mesh_vifs > 1) ||
1967 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1968 u64 tsf = ath5k_hw_get_tsf64(ah);
1969 u32 tsftu = TSF_TO_TU(tsf);
1970 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1971 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1972 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1973 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1974 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1975 } else
1976 vif = ah->bslot[0];
1977
1978 if (!vif)
1979 return;
1980
1981 avf = (void *)vif->drv_priv;
1982 bf = avf->bbuf;
1983
1984
1985
1986
1987
1988
1989 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1990 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1991
1992 }
1993
1994
1995 if (ah->opmode == NL80211_IFTYPE_AP ||
1996 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1997 err = ath5k_beacon_update(ah->hw, vif);
1998 if (err)
1999 return;
2000 }
2001
2002 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
2003 ah->opmode == NL80211_IFTYPE_MONITOR)) {
2004 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
2005 return;
2006 }
2007
2008 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
2009
2010 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
2011 ath5k_hw_start_tx_dma(ah, ah->bhalq);
2012 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2013 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
2014
2015 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2016 while (skb) {
2017 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
2018
2019 if (ah->cabq->txq_len >= ah->cabq->txq_max)
2020 break;
2021
2022 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2023 }
2024
2025 ah->bsent++;
2026}
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044void
2045ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2046{
2047 u32 nexttbtt, intval, hw_tu, bc_tu;
2048 u64 hw_tsf;
2049
2050 intval = ah->bintval & AR5K_BEACON_PERIOD;
2051 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2052 + ah->num_mesh_vifs > 1) {
2053 intval /= ATH_BCBUF;
2054 if (intval < 15)
2055 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
2056 intval);
2057 }
2058 if (WARN_ON(!intval))
2059 return;
2060
2061
2062 bc_tu = TSF_TO_TU(bc_tsf);
2063
2064
2065 hw_tsf = ath5k_hw_get_tsf64(ah);
2066 hw_tu = TSF_TO_TU(hw_tsf);
2067
2068#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2069
2070
2071
2072
2073 if (bc_tsf == -1) {
2074
2075
2076
2077
2078 nexttbtt = roundup(hw_tu + FUDGE, intval);
2079 } else if (bc_tsf == 0) {
2080
2081
2082
2083
2084 nexttbtt = intval;
2085 intval |= AR5K_BEACON_RESET_TSF;
2086 } else if (bc_tsf > hw_tsf) {
2087
2088
2089
2090
2091
2092
2093
2094 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2095 "need to wait for HW TSF sync\n");
2096 return;
2097 } else {
2098
2099
2100
2101
2102
2103
2104
2105 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2106 }
2107#undef FUDGE
2108
2109 ah->nexttbtt = nexttbtt;
2110
2111 intval |= AR5K_BEACON_ENA;
2112 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2113
2114
2115
2116
2117
2118 if (bc_tsf == -1)
2119 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2120 "reconfigured timers based on HW TSF\n");
2121 else if (bc_tsf == 0)
2122 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2123 "reset HW TSF and timers\n");
2124 else
2125 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2126 "updated timers based on beacon TSF\n");
2127
2128 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2129 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2130 (unsigned long long) bc_tsf,
2131 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2132 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2133 intval & AR5K_BEACON_PERIOD,
2134 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2135 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2136}
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146void
2147ath5k_beacon_config(struct ath5k_hw *ah)
2148{
2149 spin_lock_bh(&ah->block);
2150 ah->bmisscount = 0;
2151 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2152
2153 if (ah->enable_beacon) {
2154
2155
2156
2157
2158
2159
2160
2161 ath5k_beaconq_config(ah);
2162
2163 ah->imask |= AR5K_INT_SWBA;
2164
2165 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2166 if (ath5k_hw_hasveol(ah))
2167 ath5k_beacon_send(ah);
2168 } else
2169 ath5k_beacon_update_timers(ah, -1);
2170 } else {
2171 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2172 }
2173
2174 ath5k_hw_set_imr(ah, ah->imask);
2175 spin_unlock_bh(&ah->block);
2176}
2177
2178static void ath5k_tasklet_beacon(struct tasklet_struct *t)
2179{
2180 struct ath5k_hw *ah = from_tasklet(ah, t, beacontq);
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2191
2192 u64 tsf = ath5k_hw_get_tsf64(ah);
2193 ah->nexttbtt += ah->bintval;
2194 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2195 "SWBA nexttbtt: %x hw_tu: %x "
2196 "TSF: %llx\n",
2197 ah->nexttbtt,
2198 TSF_TO_TU(tsf),
2199 (unsigned long long) tsf);
2200 } else {
2201 spin_lock(&ah->block);
2202 ath5k_beacon_send(ah);
2203 spin_unlock(&ah->block);
2204 }
2205}
2206
2207
2208
2209
2210
2211
2212static void
2213ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2214{
2215 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2216 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2217 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2218
2219
2220
2221 ah->ah_cal_next_ani = jiffies +
2222 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2223 tasklet_schedule(&ah->ani_tasklet);
2224
2225 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2226 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2227 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2228
2229
2230
2231
2232
2233
2234
2235
2236 ah->ah_cal_next_short = jiffies +
2237 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2238 ieee80211_queue_work(ah->hw, &ah->calib_work);
2239 }
2240
2241
2242
2243}
2244
2245static void
2246ath5k_schedule_rx(struct ath5k_hw *ah)
2247{
2248 ah->rx_pending = true;
2249 tasklet_schedule(&ah->rxtq);
2250}
2251
2252static void
2253ath5k_schedule_tx(struct ath5k_hw *ah)
2254{
2255 ah->tx_pending = true;
2256 tasklet_schedule(&ah->txtq);
2257}
2258
2259static irqreturn_t
2260ath5k_intr(int irq, void *dev_id)
2261{
2262 struct ath5k_hw *ah = dev_id;
2263 enum ath5k_int status;
2264 unsigned int counter = 1000;
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2278 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2279 !ath5k_hw_is_intr_pending(ah))))
2280 return IRQ_NONE;
2281
2282
2283 do {
2284 ath5k_hw_get_isr(ah, &status);
2285
2286 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2287 status, ah->imask);
2288
2289
2290
2291
2292
2293
2294
2295
2296 if (unlikely(status & AR5K_INT_FATAL)) {
2297
2298 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2299 "fatal int, resetting\n");
2300 ieee80211_queue_work(ah->hw, &ah->reset_work);
2301
2302
2303
2304
2305
2306
2307
2308
2309 } else if (unlikely(status & AR5K_INT_RXORN)) {
2310
2311
2312
2313
2314
2315
2316
2317 ah->stats.rxorn_intr++;
2318
2319 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2320 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2321 "rx overrun, resetting\n");
2322 ieee80211_queue_work(ah->hw, &ah->reset_work);
2323 } else
2324 ath5k_schedule_rx(ah);
2325
2326 } else {
2327
2328
2329 if (status & AR5K_INT_SWBA)
2330 tasklet_hi_schedule(&ah->beacontq);
2331
2332
2333
2334
2335
2336
2337
2338
2339 if (status & AR5K_INT_RXEOL)
2340 ah->stats.rxeol_intr++;
2341
2342
2343
2344 if (status & AR5K_INT_TXURN)
2345 ath5k_hw_update_tx_triglevel(ah, true);
2346
2347
2348 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2349 ath5k_schedule_rx(ah);
2350
2351
2352 if (status & (AR5K_INT_TXOK
2353 | AR5K_INT_TXDESC
2354 | AR5K_INT_TXERR
2355 | AR5K_INT_TXEOL))
2356 ath5k_schedule_tx(ah);
2357
2358
2359
2360
2361
2362
2363 if (status & AR5K_INT_MIB) {
2364 ah->stats.mib_intr++;
2365 ath5k_hw_update_mib_counters(ah);
2366 ath5k_ani_mib_intr(ah);
2367 }
2368
2369
2370 if (status & AR5K_INT_GPIO)
2371 tasklet_schedule(&ah->rf_kill.toggleq);
2372
2373 }
2374
2375 if (ath5k_get_bus_type(ah) == ATH_AHB)
2376 break;
2377
2378 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2379
2380
2381
2382
2383
2384
2385
2386 if (ah->rx_pending || ah->tx_pending)
2387 ath5k_set_current_imask(ah);
2388
2389 if (unlikely(!counter))
2390 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2391
2392
2393 ath5k_intr_calibration_poll(ah);
2394
2395 return IRQ_HANDLED;
2396}
2397
2398
2399
2400
2401
2402static void
2403ath5k_calibrate_work(struct work_struct *work)
2404{
2405 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2406 calib_work);
2407
2408
2409 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2410
2411 ah->ah_cal_next_full = jiffies +
2412 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2413 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2414
2415 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2416 "running full calibration\n");
2417
2418 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2419
2420
2421
2422
2423 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2424 "got new rfgain, resetting\n");
2425 ieee80211_queue_work(ah->hw, &ah->reset_work);
2426 }
2427 } else
2428 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2429
2430
2431 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2432 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2433 ah->curchan->hw_value);
2434
2435 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2436 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2437 ieee80211_frequency_to_channel(
2438 ah->curchan->center_freq));
2439
2440
2441 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2442 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2443 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2444 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2445}
2446
2447
2448static void
2449ath5k_tasklet_ani(struct tasklet_struct *t)
2450{
2451 struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet);
2452
2453 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2454 ath5k_ani_calibration(ah);
2455 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2456}
2457
2458
2459static void
2460ath5k_tx_complete_poll_work(struct work_struct *work)
2461{
2462 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2463 tx_complete_work.work);
2464 struct ath5k_txq *txq;
2465 int i;
2466 bool needreset = false;
2467
2468 if (!test_bit(ATH_STAT_STARTED, ah->status))
2469 return;
2470
2471 mutex_lock(&ah->lock);
2472
2473 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2474 if (ah->txqs[i].setup) {
2475 txq = &ah->txqs[i];
2476 spin_lock_bh(&txq->lock);
2477 if (txq->txq_len > 1) {
2478 if (txq->txq_poll_mark) {
2479 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2480 "TX queue stuck %d\n",
2481 txq->qnum);
2482 needreset = true;
2483 txq->txq_stuck++;
2484 spin_unlock_bh(&txq->lock);
2485 break;
2486 } else {
2487 txq->txq_poll_mark = true;
2488 }
2489 }
2490 spin_unlock_bh(&txq->lock);
2491 }
2492 }
2493
2494 if (needreset) {
2495 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2496 "TX queues stuck, resetting\n");
2497 ath5k_reset(ah, NULL, true);
2498 }
2499
2500 mutex_unlock(&ah->lock);
2501
2502 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2503 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2504}
2505
2506
2507
2508
2509
2510
2511static const struct ieee80211_iface_limit if_limits[] = {
2512 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2513 { .max = 4, .types =
2514#ifdef CONFIG_MAC80211_MESH
2515 BIT(NL80211_IFTYPE_MESH_POINT) |
2516#endif
2517 BIT(NL80211_IFTYPE_AP) },
2518};
2519
2520static const struct ieee80211_iface_combination if_comb = {
2521 .limits = if_limits,
2522 .n_limits = ARRAY_SIZE(if_limits),
2523 .max_interfaces = 2048,
2524 .num_different_channels = 1,
2525};
2526
2527int
2528ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2529{
2530 struct ieee80211_hw *hw = ah->hw;
2531 struct ath_common *common;
2532 int ret;
2533 int csz;
2534
2535
2536 SET_IEEE80211_DEV(hw, ah->dev);
2537 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
2538 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2539 ieee80211_hw_set(hw, MFP_CAPABLE);
2540 ieee80211_hw_set(hw, SIGNAL_DBM);
2541 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2542 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
2543
2544 hw->wiphy->interface_modes =
2545 BIT(NL80211_IFTYPE_AP) |
2546 BIT(NL80211_IFTYPE_STATION) |
2547 BIT(NL80211_IFTYPE_ADHOC) |
2548 BIT(NL80211_IFTYPE_MESH_POINT);
2549
2550 hw->wiphy->iface_combinations = &if_comb;
2551 hw->wiphy->n_iface_combinations = 1;
2552
2553
2554 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2555
2556 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2557
2558
2559 hw->wiphy->available_antennas_tx = 0x3;
2560 hw->wiphy->available_antennas_rx = 0x3;
2561
2562 hw->extra_tx_headroom = 2;
2563
2564 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
2565
2566
2567
2568
2569
2570 __set_bit(ATH_STAT_INVALID, ah->status);
2571
2572 ah->opmode = NL80211_IFTYPE_STATION;
2573 ah->bintval = 1000;
2574 mutex_init(&ah->lock);
2575 spin_lock_init(&ah->rxbuflock);
2576 spin_lock_init(&ah->txbuflock);
2577 spin_lock_init(&ah->block);
2578 spin_lock_init(&ah->irqlock);
2579
2580
2581 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2582 if (ret) {
2583 ATH5K_ERR(ah, "request_irq failed\n");
2584 goto err;
2585 }
2586
2587 common = ath5k_hw_common(ah);
2588 common->ops = &ath5k_common_ops;
2589 common->bus_ops = bus_ops;
2590 common->ah = ah;
2591 common->hw = hw;
2592 common->priv = ah;
2593 common->clockrate = 40;
2594
2595
2596
2597
2598
2599 ath5k_read_cachesize(common, &csz);
2600 common->cachelsz = csz << 2;
2601
2602 spin_lock_init(&common->cc_lock);
2603
2604
2605 ret = ath5k_hw_init(ah);
2606 if (ret)
2607 goto err_irq;
2608
2609
2610 if (ah->ah_capabilities.cap_has_mrr_support) {
2611 hw->max_rates = 4;
2612 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2613 AR5K_INIT_RETRY_LONG);
2614 }
2615
2616 hw->vif_data_size = sizeof(struct ath5k_vif);
2617
2618
2619 ret = ath5k_init(hw);
2620 if (ret)
2621 goto err_ah;
2622
2623 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2624 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2625 ah->ah_mac_srev,
2626 ah->ah_phy_revision);
2627
2628 if (!ah->ah_single_chip) {
2629
2630 if (ah->ah_radio_5ghz_revision &&
2631 !ah->ah_radio_2ghz_revision) {
2632
2633 if (!test_bit(AR5K_MODE_11A,
2634 ah->ah_capabilities.cap_mode)) {
2635 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2636 ath5k_chip_name(AR5K_VERSION_RAD,
2637 ah->ah_radio_5ghz_revision),
2638 ah->ah_radio_5ghz_revision);
2639
2640
2641 } else if (!test_bit(AR5K_MODE_11B,
2642 ah->ah_capabilities.cap_mode)) {
2643 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2644 ath5k_chip_name(AR5K_VERSION_RAD,
2645 ah->ah_radio_5ghz_revision),
2646 ah->ah_radio_5ghz_revision);
2647
2648 } else {
2649 ATH5K_INFO(ah, "RF%s multiband radio found"
2650 " (0x%x)\n",
2651 ath5k_chip_name(AR5K_VERSION_RAD,
2652 ah->ah_radio_5ghz_revision),
2653 ah->ah_radio_5ghz_revision);
2654 }
2655 }
2656
2657
2658 else if (ah->ah_radio_5ghz_revision &&
2659 ah->ah_radio_2ghz_revision) {
2660 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2661 ath5k_chip_name(AR5K_VERSION_RAD,
2662 ah->ah_radio_5ghz_revision),
2663 ah->ah_radio_5ghz_revision);
2664 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2665 ath5k_chip_name(AR5K_VERSION_RAD,
2666 ah->ah_radio_2ghz_revision),
2667 ah->ah_radio_2ghz_revision);
2668 }
2669 }
2670
2671 ath5k_debug_init_device(ah);
2672
2673
2674 __clear_bit(ATH_STAT_INVALID, ah->status);
2675
2676 return 0;
2677err_ah:
2678 ath5k_hw_deinit(ah);
2679err_irq:
2680 free_irq(ah->irq, ah);
2681err:
2682 return ret;
2683}
2684
2685static int
2686ath5k_stop_locked(struct ath5k_hw *ah)
2687{
2688
2689 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2690 test_bit(ATH_STAT_INVALID, ah->status));
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707 ieee80211_stop_queues(ah->hw);
2708
2709 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2710 ath5k_led_off(ah);
2711 ath5k_hw_set_imr(ah, 0);
2712 synchronize_irq(ah->irq);
2713 ath5k_rx_stop(ah);
2714 ath5k_hw_dma_stop(ah);
2715 ath5k_drain_tx_buffs(ah);
2716 ath5k_hw_phy_disable(ah);
2717 }
2718
2719 return 0;
2720}
2721
2722int ath5k_start(struct ieee80211_hw *hw)
2723{
2724 struct ath5k_hw *ah = hw->priv;
2725 struct ath_common *common = ath5k_hw_common(ah);
2726 int ret, i;
2727
2728 mutex_lock(&ah->lock);
2729
2730 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2731
2732
2733
2734
2735
2736 ath5k_stop_locked(ah);
2737
2738
2739
2740
2741
2742
2743
2744
2745 ah->curchan = ah->hw->conf.chandef.chan;
2746 ah->imask = AR5K_INT_RXOK
2747 | AR5K_INT_RXERR
2748 | AR5K_INT_RXEOL
2749 | AR5K_INT_RXORN
2750 | AR5K_INT_TXDESC
2751 | AR5K_INT_TXEOL
2752 | AR5K_INT_FATAL
2753 | AR5K_INT_GLOBAL
2754 | AR5K_INT_MIB;
2755
2756 ret = ath5k_reset(ah, NULL, false);
2757 if (ret)
2758 goto done;
2759
2760 if (!ath5k_modparam_no_hw_rfkill_switch)
2761 ath5k_rfkill_hw_start(ah);
2762
2763
2764
2765
2766
2767 for (i = 0; i < common->keymax; i++)
2768 ath_hw_keyreset(common, (u16) i);
2769
2770
2771
2772 ah->ah_ack_bitrate_high = true;
2773
2774 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2775 ah->bslot[i] = NULL;
2776
2777 ret = 0;
2778done:
2779 mutex_unlock(&ah->lock);
2780
2781 set_bit(ATH_STAT_STARTED, ah->status);
2782 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2783 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2784
2785 return ret;
2786}
2787
2788static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2789{
2790 ah->rx_pending = false;
2791 ah->tx_pending = false;
2792 tasklet_kill(&ah->rxtq);
2793 tasklet_kill(&ah->txtq);
2794 tasklet_kill(&ah->beacontq);
2795 tasklet_kill(&ah->ani_tasklet);
2796}
2797
2798
2799
2800
2801
2802
2803
2804void ath5k_stop(struct ieee80211_hw *hw)
2805{
2806 struct ath5k_hw *ah = hw->priv;
2807 int ret;
2808
2809 mutex_lock(&ah->lock);
2810 ret = ath5k_stop_locked(ah);
2811 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832 ret = ath5k_hw_on_hold(ah);
2833
2834 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2835 "putting device to sleep\n");
2836 }
2837
2838 mutex_unlock(&ah->lock);
2839
2840 ath5k_stop_tasklets(ah);
2841
2842 clear_bit(ATH_STAT_STARTED, ah->status);
2843 cancel_delayed_work_sync(&ah->tx_complete_work);
2844
2845 if (!ath5k_modparam_no_hw_rfkill_switch)
2846 ath5k_rfkill_hw_stop(ah);
2847}
2848
2849
2850
2851
2852
2853
2854
2855static int
2856ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2857 bool skip_pcu)
2858{
2859 struct ath_common *common = ath5k_hw_common(ah);
2860 int ret, ani_mode;
2861 bool fast = chan && modparam_fastchanswitch ? 1 : 0;
2862
2863 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2864
2865 __set_bit(ATH_STAT_RESET, ah->status);
2866
2867 ath5k_hw_set_imr(ah, 0);
2868 synchronize_irq(ah->irq);
2869 ath5k_stop_tasklets(ah);
2870
2871
2872
2873
2874 ani_mode = ah->ani_state.ani_mode;
2875 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2876
2877
2878
2879
2880 ath5k_drain_tx_buffs(ah);
2881
2882
2883 ath5k_hw_stop_rx_pcu(ah);
2884
2885
2886
2887
2888
2889
2890 ret = ath5k_hw_dma_stop(ah);
2891
2892
2893
2894
2895 if (ret && fast) {
2896 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2897 "DMA didn't stop, falling back to normal reset\n");
2898 fast = false;
2899 }
2900
2901 if (chan)
2902 ah->curchan = chan;
2903
2904 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2905 if (ret) {
2906 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2907 goto err;
2908 }
2909
2910 ret = ath5k_rx_start(ah);
2911 if (ret) {
2912 ATH5K_ERR(ah, "can't start recv logic\n");
2913 goto err;
2914 }
2915
2916 ath5k_ani_init(ah, ani_mode);
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929 ah->ah_cal_next_full = jiffies +
2930 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2931 ah->ah_cal_next_ani = jiffies +
2932 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2933 ah->ah_cal_next_short = jiffies +
2934 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2935
2936 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg);
2937
2938
2939 memset(&ah->survey, 0, sizeof(ah->survey));
2940 spin_lock_bh(&common->cc_lock);
2941 ath_hw_cycle_counters_update(common);
2942 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2943 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2944 spin_unlock_bh(&common->cc_lock);
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957 __clear_bit(ATH_STAT_RESET, ah->status);
2958
2959 ath5k_beacon_config(ah);
2960
2961
2962 ieee80211_wake_queues(ah->hw);
2963
2964 return 0;
2965err:
2966 return ret;
2967}
2968
2969static void ath5k_reset_work(struct work_struct *work)
2970{
2971 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2972 reset_work);
2973
2974 mutex_lock(&ah->lock);
2975 ath5k_reset(ah, NULL, true);
2976 mutex_unlock(&ah->lock);
2977}
2978
2979static int
2980ath5k_init(struct ieee80211_hw *hw)
2981{
2982
2983 struct ath5k_hw *ah = hw->priv;
2984 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2985 struct ath5k_txq *txq;
2986 u8 mac[ETH_ALEN] = {};
2987 int ret;
2988
2989
2990
2991
2992
2993
2994
2995
2996 ret = ath5k_setup_bands(hw);
2997 if (ret) {
2998 ATH5K_ERR(ah, "can't get channels\n");
2999 goto err;
3000 }
3001
3002
3003
3004
3005 ret = ath5k_desc_alloc(ah);
3006 if (ret) {
3007 ATH5K_ERR(ah, "can't allocate descriptors\n");
3008 goto err;
3009 }
3010
3011
3012
3013
3014
3015
3016
3017 ret = ath5k_beaconq_setup(ah);
3018 if (ret < 0) {
3019 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
3020 goto err_desc;
3021 }
3022 ah->bhalq = ret;
3023 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
3024 if (IS_ERR(ah->cabq)) {
3025 ATH5K_ERR(ah, "can't setup cab queue\n");
3026 ret = PTR_ERR(ah->cabq);
3027 goto err_bhal;
3028 }
3029
3030
3031
3032 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
3033
3034
3035 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
3036 if (IS_ERR(txq)) {
3037 ATH5K_ERR(ah, "can't setup xmit queue\n");
3038 ret = PTR_ERR(txq);
3039 goto err_queues;
3040 }
3041 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
3042 if (IS_ERR(txq)) {
3043 ATH5K_ERR(ah, "can't setup xmit queue\n");
3044 ret = PTR_ERR(txq);
3045 goto err_queues;
3046 }
3047 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3048 if (IS_ERR(txq)) {
3049 ATH5K_ERR(ah, "can't setup xmit queue\n");
3050 ret = PTR_ERR(txq);
3051 goto err_queues;
3052 }
3053 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
3054 if (IS_ERR(txq)) {
3055 ATH5K_ERR(ah, "can't setup xmit queue\n");
3056 ret = PTR_ERR(txq);
3057 goto err_queues;
3058 }
3059 hw->queues = 4;
3060 } else {
3061
3062 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3063 if (IS_ERR(txq)) {
3064 ATH5K_ERR(ah, "can't setup xmit queue\n");
3065 ret = PTR_ERR(txq);
3066 goto err_queues;
3067 }
3068 hw->queues = 1;
3069 }
3070
3071 tasklet_setup(&ah->rxtq, ath5k_tasklet_rx);
3072 tasklet_setup(&ah->txtq, ath5k_tasklet_tx);
3073 tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon);
3074 tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani);
3075
3076 INIT_WORK(&ah->reset_work, ath5k_reset_work);
3077 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
3078 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
3079
3080 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
3081 if (ret) {
3082 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
3083 goto err_queues;
3084 }
3085
3086 SET_IEEE80211_PERM_ADDR(hw, mac);
3087
3088 ath5k_update_bssid_mask_and_opmode(ah, NULL);
3089
3090 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3091 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3092 if (ret) {
3093 ATH5K_ERR(ah, "can't initialize regulatory system\n");
3094 goto err_queues;
3095 }
3096
3097 ret = ieee80211_register_hw(hw);
3098 if (ret) {
3099 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
3100 goto err_queues;
3101 }
3102
3103 if (!ath_is_world_regd(regulatory))
3104 regulatory_hint(hw->wiphy, regulatory->alpha2);
3105
3106 ath5k_init_leds(ah);
3107
3108 ath5k_sysfs_register(ah);
3109
3110 return 0;
3111err_queues:
3112 ath5k_txq_release(ah);
3113err_bhal:
3114 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3115err_desc:
3116 ath5k_desc_free(ah);
3117err:
3118 return ret;
3119}
3120
3121void
3122ath5k_deinit_ah(struct ath5k_hw *ah)
3123{
3124 struct ieee80211_hw *hw = ah->hw;
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139 ieee80211_unregister_hw(hw);
3140 ath5k_desc_free(ah);
3141 ath5k_txq_release(ah);
3142 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3143 ath5k_unregister_leds(ah);
3144
3145 ath5k_sysfs_unregister(ah);
3146
3147
3148
3149
3150
3151 ath5k_hw_deinit(ah);
3152 free_irq(ah->irq, ah);
3153}
3154
3155bool
3156ath5k_any_vif_assoc(struct ath5k_hw *ah)
3157{
3158 struct ath5k_vif_iter_data iter_data;
3159 iter_data.hw_macaddr = NULL;
3160 iter_data.any_assoc = false;
3161 iter_data.need_set_hw_addr = false;
3162 iter_data.found_active = true;
3163
3164 ieee80211_iterate_active_interfaces_atomic(
3165 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3166 ath5k_vif_iter, &iter_data);
3167 return iter_data.any_assoc;
3168}
3169
3170void
3171ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3172{
3173 struct ath5k_hw *ah = hw->priv;
3174 u32 rfilt;
3175 rfilt = ath5k_hw_get_rx_filter(ah);
3176 if (enable)
3177 rfilt |= AR5K_RX_FILTER_BEACON;
3178 else
3179 rfilt &= ~AR5K_RX_FILTER_BEACON;
3180 ath5k_hw_set_rx_filter(ah, rfilt);
3181 ah->filter_flags = rfilt;
3182}
3183
3184void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3185 const char *fmt, ...)
3186{
3187 struct va_format vaf;
3188 va_list args;
3189
3190 va_start(args, fmt);
3191
3192 vaf.fmt = fmt;
3193 vaf.va = &args;
3194
3195 if (ah && ah->hw)
3196 printk("%s" pr_fmt("%s: %pV"),
3197 level, wiphy_name(ah->hw->wiphy), &vaf);
3198 else
3199 printk("%s" pr_fmt("%pV"), level, &vaf);
3200
3201 va_end(args);
3202}
3203