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27#include <asm/unaligned.h>
28
29#include "ath5k.h"
30#include "reg.h"
31#include "debug.h"
32
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81
82static const unsigned int ack_rates_high[] =
83
84 { 0,
85 1,
86 1,
87 1,
88 4,
89 4,
90 6,
91 6,
92 8,
93 8,
94 8,
95 8 };
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111
112
113int
114ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,
115 int len, struct ieee80211_rate *rate, bool shortpre)
116{
117 int sifs, preamble, plcp_bits, sym_time;
118 int bitrate, bits, symbols, symbol_bits;
119 int dur;
120
121
122 if (!ah->ah_bwmode) {
123 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,
124 NULL, band, len, rate);
125
126
127 dur = le16_to_cpu(raw_dur);
128 if (shortpre)
129 dur -= 96;
130
131 return dur;
132 }
133
134 bitrate = rate->bitrate;
135 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME;
136 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS;
137 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME;
138
139 switch (ah->ah_bwmode) {
140 case AR5K_BWMODE_40MHZ:
141 sifs = AR5K_INIT_SIFS_TURBO;
142 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN;
143 break;
144 case AR5K_BWMODE_10MHZ:
145 sifs = AR5K_INIT_SIFS_HALF_RATE;
146 preamble *= 2;
147 sym_time *= 2;
148 bitrate = DIV_ROUND_UP(bitrate, 2);
149 break;
150 case AR5K_BWMODE_5MHZ:
151 sifs = AR5K_INIT_SIFS_QUARTER_RATE;
152 preamble *= 4;
153 sym_time *= 4;
154 bitrate = DIV_ROUND_UP(bitrate, 4);
155 break;
156 default:
157 sifs = AR5K_INIT_SIFS_DEFAULT_BG;
158 break;
159 }
160
161 bits = plcp_bits + (len << 3);
162
163 symbol_bits = bitrate * sym_time;
164 symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
165
166 dur = sifs + preamble + (sym_time * symbols);
167
168 return dur;
169}
170
171
172
173
174
175unsigned int
176ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
177{
178 struct ieee80211_channel *channel = ah->ah_current_channel;
179 unsigned int slot_time;
180
181 switch (ah->ah_bwmode) {
182 case AR5K_BWMODE_40MHZ:
183 slot_time = AR5K_INIT_SLOT_TIME_TURBO;
184 break;
185 case AR5K_BWMODE_10MHZ:
186 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
187 break;
188 case AR5K_BWMODE_5MHZ:
189 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
190 break;
191 case AR5K_BWMODE_DEFAULT:
192 default:
193 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
194 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot)
195 slot_time = AR5K_INIT_SLOT_TIME_B;
196 break;
197 }
198
199 return slot_time;
200}
201
202
203
204
205
206unsigned int
207ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
208{
209 struct ieee80211_channel *channel = ah->ah_current_channel;
210 unsigned int sifs;
211
212 switch (ah->ah_bwmode) {
213 case AR5K_BWMODE_40MHZ:
214 sifs = AR5K_INIT_SIFS_TURBO;
215 break;
216 case AR5K_BWMODE_10MHZ:
217 sifs = AR5K_INIT_SIFS_HALF_RATE;
218 break;
219 case AR5K_BWMODE_5MHZ:
220 sifs = AR5K_INIT_SIFS_QUARTER_RATE;
221 break;
222 case AR5K_BWMODE_DEFAULT:
223 default:
224 sifs = AR5K_INIT_SIFS_DEFAULT_BG;
225 if (channel->band == NL80211_BAND_5GHZ)
226 sifs = AR5K_INIT_SIFS_DEFAULT_A;
227 break;
228 }
229
230 return sifs;
231}
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241
242
243void
244ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
245{
246 struct ath5k_statistics *stats = &ah->stats;
247
248
249 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
250 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
251 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
252 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
253 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
254}
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277static inline void
278ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
279{
280 struct ieee80211_rate *rate;
281 unsigned int i;
282
283 u8 band = NL80211_BAND_2GHZ;
284
285
286 for (i = 0; i < ah->sbands[band].n_bitrates; i++) {
287 u32 reg;
288 u16 tx_time;
289
290 if (ah->ah_ack_bitrate_high)
291 rate = &ah->sbands[band].bitrates[ack_rates_high[i]];
292
293 else if (i < 4)
294 rate = &ah->sbands[band].bitrates[0];
295
296 else
297 rate = &ah->sbands[band].bitrates[4];
298
299
300 reg = AR5K_RATE_DUR(rate->hw_value);
301
302
303
304
305
306
307
308 tx_time = ath5k_hw_get_frame_duration(ah, band, 10,
309 rate, false);
310
311 ath5k_hw_reg_write(ah, tx_time, reg);
312
313 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
314 continue;
315
316 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true);
317 ath5k_hw_reg_write(ah, tx_time,
318 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
319 }
320}
321
322
323
324
325
326
327static int
328ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
329{
330 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
331 <= timeout)
332 return -EINVAL;
333
334 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
335 ath5k_hw_htoclock(ah, timeout));
336
337 return 0;
338}
339
340
341
342
343
344
345static int
346ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
347{
348 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
349 <= timeout)
350 return -EINVAL;
351
352 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
353 ath5k_hw_htoclock(ah, timeout));
354
355 return 0;
356}
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368
369
370int
371ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
372{
373 struct ath_common *common = ath5k_hw_common(ah);
374 u32 low_id, high_id;
375 u32 pcu_reg;
376
377
378 memcpy(common->macaddr, mac, ETH_ALEN);
379
380 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
381
382 low_id = get_unaligned_le32(mac);
383 high_id = get_unaligned_le16(mac + 4);
384
385 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
386 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
387
388 return 0;
389}
390
391
392
393
394
395
396
397
398void
399ath5k_hw_set_bssid(struct ath5k_hw *ah)
400{
401 struct ath_common *common = ath5k_hw_common(ah);
402 u16 tim_offset = 0;
403
404
405
406
407 if (ah->ah_version == AR5K_AR5212)
408 ath_hw_setbssidmask(common);
409
410
411
412
413 ath5k_hw_reg_write(ah,
414 get_unaligned_le32(common->curbssid),
415 AR5K_BSS_ID0);
416 ath5k_hw_reg_write(ah,
417 get_unaligned_le16(common->curbssid + 4) |
418 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
419 AR5K_BSS_ID1);
420
421 if (common->curaid == 0) {
422 ath5k_hw_disable_pspoll(ah);
423 return;
424 }
425
426 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
427 tim_offset ? tim_offset + 4 : 0);
428
429 ath5k_hw_enable_pspoll(ah, NULL, 0);
430}
431
432
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446
447void
448ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
449{
450 struct ath_common *common = ath5k_hw_common(ah);
451
452
453
454 memcpy(common->bssidmask, mask, ETH_ALEN);
455 if (ah->ah_version == AR5K_AR5212)
456 ath_hw_setbssidmask(common);
457}
458
459
460
461
462
463
464
465void
466ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
467{
468 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
469 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
470}
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472
473
474
475
476
477
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480
481
482u32
483ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
484{
485 u32 data, filter = 0;
486
487 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
488
489
490 if (ah->ah_version == AR5K_AR5212) {
491 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
492
493 if (data & AR5K_PHY_ERR_FIL_RADAR)
494 filter |= AR5K_RX_FILTER_RADARERR;
495 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
496 filter |= AR5K_RX_FILTER_PHYERR;
497 }
498
499 return filter;
500}
501
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510
511void
512ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
513{
514 u32 data = 0;
515
516
517 if (ah->ah_version == AR5K_AR5212) {
518 if (filter & AR5K_RX_FILTER_RADARERR)
519 data |= AR5K_PHY_ERR_FIL_RADAR;
520 if (filter & AR5K_RX_FILTER_PHYERR)
521 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
522 }
523
524
525
526
527 if (ah->ah_version == AR5K_AR5210 &&
528 (filter & AR5K_RX_FILTER_RADARERR)) {
529 filter &= ~AR5K_RX_FILTER_RADARERR;
530 filter |= AR5K_RX_FILTER_PROM;
531 }
532
533
534 if (data)
535 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
536 else
537 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
538
539
540 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
541
542
543 if (ah->ah_version == AR5K_AR5212)
544 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
545
546}
547
548
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551
552
553#define ATH5K_MAX_TSF_READ 10
554
555
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560
561u64
562ath5k_hw_get_tsf64(struct ath5k_hw *ah)
563{
564 u32 tsf_lower, tsf_upper1, tsf_upper2;
565 int i;
566 unsigned long flags;
567
568
569 local_irq_save(flags);
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582
583 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
584 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
585 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
586 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
587 if (tsf_upper2 == tsf_upper1)
588 break;
589 tsf_upper1 = tsf_upper2;
590 }
591
592 local_irq_restore(flags);
593
594 WARN_ON(i == ATH5K_MAX_TSF_READ);
595
596 return ((u64)tsf_upper1 << 32) | tsf_lower;
597}
598
599#undef ATH5K_MAX_TSF_READ
600
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607
608void
609ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
610{
611 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
612 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
613}
614
615
616
617
618
619
620
621void
622ath5k_hw_reset_tsf(struct ath5k_hw *ah)
623{
624 u32 val;
625
626 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
627
628
629
630
631
632
633
634 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
635 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
636}
637
638
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640
641
642
643
644
645
646
647void
648ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
649{
650 u32 timer1, timer2, timer3;
651
652
653
654
655 switch (ah->opmode) {
656 case NL80211_IFTYPE_MONITOR:
657 case NL80211_IFTYPE_STATION:
658
659
660
661
662 if (ah->ah_version == AR5K_AR5210) {
663 timer1 = 0xffffffff;
664 timer2 = 0xffffffff;
665 } else {
666 timer1 = 0x0000ffff;
667 timer2 = 0x0007ffff;
668 }
669
670 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
671 break;
672 case NL80211_IFTYPE_ADHOC:
673 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
674 fallthrough;
675 default:
676
677
678
679 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
680 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
681 break;
682 }
683
684
685
686
687 timer3 = next_beacon + 1;
688
689
690
691
692
693 if (ah->opmode == NL80211_IFTYPE_AP ||
694 ah->opmode == NL80211_IFTYPE_MESH_POINT)
695 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
696
697 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
698 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
699 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
700 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
701
702
703 if (interval & AR5K_BEACON_RESET_TSF)
704 ath5k_hw_reset_tsf(ah);
705
706 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
707 AR5K_BEACON_ENABLE),
708 AR5K_BEACON);
709
710
711
712
713
714
715 if (ah->ah_version == AR5K_AR5210)
716 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
717 else
718 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
719
720
721
722
723 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
724
725}
726
727
728
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730
731
732
733
734
735
736
737
738
739
740static inline bool
741ath5k_check_timer_win(int a, int b, int window, int intval)
742{
743
744
745
746
747
748
749 if ((b - a == window) ||
750 (a - b == intval - window) ||
751 ((a | 0x10000) - b == intval - window) ||
752 ((b | 0x10000) - a == window))
753 return true;
754 return false;
755}
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795
796bool
797ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
798{
799 unsigned int nbtt, atim, dma;
800
801 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
802 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
803 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
804
805
806
807
808
809 if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
810 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
811 intval))
812 return true;
813 return false;
814}
815
816
817
818
819
820
821
822
823void
824ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
825{
826
827 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
828 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
829 int cts_timeout = ack_timeout;
830
831 ath5k_hw_set_ifs_intervals(ah, slot_time);
832 ath5k_hw_set_ack_timeout(ah, ack_timeout);
833 ath5k_hw_set_cts_timeout(ah, cts_timeout);
834
835 ah->ah_coverage_class = coverage_class;
836}
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851void
852ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
853{
854 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
855}
856
857
858
859
860
861
862
863void
864ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
865{
866 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
867}
868
869
870
871
872
873
874
875
876int
877ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
878{
879 struct ath_common *common = ath5k_hw_common(ah);
880 u32 pcu_reg, beacon_reg, low_id, high_id;
881
882 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
883
884
885 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
886 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
887 | AR5K_STA_ID1_KEYSRCH_MODE
888 | (ah->ah_version == AR5K_AR5210 ?
889 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
890
891 beacon_reg = 0;
892
893 switch (op_mode) {
894 case NL80211_IFTYPE_ADHOC:
895 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
896 beacon_reg |= AR5K_BCR_ADHOC;
897 if (ah->ah_version == AR5K_AR5210)
898 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
899 else
900 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
901 break;
902
903 case NL80211_IFTYPE_AP:
904 case NL80211_IFTYPE_MESH_POINT:
905 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
906 beacon_reg |= AR5K_BCR_AP;
907 if (ah->ah_version == AR5K_AR5210)
908 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
909 else
910 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
911 break;
912
913 case NL80211_IFTYPE_STATION:
914 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
915 | (ah->ah_version == AR5K_AR5210 ?
916 AR5K_STA_ID1_PWR_SV : 0);
917 fallthrough;
918 case NL80211_IFTYPE_MONITOR:
919 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
920 | (ah->ah_version == AR5K_AR5210 ?
921 AR5K_STA_ID1_NO_PSPOLL : 0);
922 break;
923
924 default:
925 return -EINVAL;
926 }
927
928
929
930
931 low_id = get_unaligned_le32(common->macaddr);
932 high_id = get_unaligned_le16(common->macaddr + 4);
933 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
934 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
935
936
937
938
939 if (ah->ah_version == AR5K_AR5210)
940 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
941
942 return 0;
943}
944
945
946
947
948
949
950
951
952
953void
954ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
955{
956
957 ath5k_hw_set_bssid(ah);
958
959
960 ath5k_hw_set_opmode(ah, op_mode);
961
962
963
964
965
966 if (ah->ah_version == AR5K_AR5212 &&
967 ah->nvifs)
968 ath5k_hw_write_rate_duration(ah);
969
970
971
972
973
974
975
976
977
978 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
979 AR5K_TUNE_BMISS_THRES <<
980 AR5K_RSSI_THR_BMISS_S),
981 AR5K_RSSI_THR);
982
983
984 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
985 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
986 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
987 }
988
989
990 if (ah->ah_version == AR5K_AR5212) {
991 ath5k_hw_reg_write(ah,
992 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
993 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
994 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
995 AR5K_QOS_NOACK);
996 }
997
998
999 if (ah->ah_coverage_class > 0)
1000 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1001
1002
1003 if (ah->ah_version == AR5K_AR5212) {
1004 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
1005 if (ah->ah_ack_bitrate_high)
1006 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
1007 else
1008 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
1009 }
1010 return;
1011}
1012