LXR linux/drivers/net/wireless/ath/ath9k/ar9003

   1/*
   2 * Copyright (c) 2010-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef AR9003_MCI_H
  18#define AR9003_MCI_H
  19
  20#define MCI_FLAG_DISABLE_TIMESTAMP      0x00000001      /* Disable time stamp */
  21#define MCI_RECOVERY_DUR_TSF            (100 * 1000)    /* 100 ms */
  22
  23/* Default remote BT device MCI COEX version */
  24#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT  3
  25#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT  0
  26
  27/* Local WLAN MCI COEX version */
  28#define MCI_GPM_COEX_MAJOR_VERSION_WLAN     3
  29#define MCI_GPM_COEX_MINOR_VERSION_WLAN     0
  30
  31enum mci_gpm_coex_query_type {
  32        MCI_GPM_COEX_QUERY_BT_ALL_INFO      = BIT(0),
  33        MCI_GPM_COEX_QUERY_BT_TOPOLOGY      = BIT(1),
  34        MCI_GPM_COEX_QUERY_BT_DEBUG         = BIT(2),
  35};
  36
  37enum mci_gpm_coex_halt_bt_gpm {
  38        MCI_GPM_COEX_BT_GPM_UNHALT,
  39        MCI_GPM_COEX_BT_GPM_HALT
  40};
  41
  42enum mci_gpm_coex_bt_update_flags_op {
  43        MCI_GPM_COEX_BT_FLAGS_READ,
  44        MCI_GPM_COEX_BT_FLAGS_SET,
  45        MCI_GPM_COEX_BT_FLAGS_CLEAR
  46};
  47
  48#define MCI_NUM_BT_CHANNELS     79
  49
  50#define MCI_BT_MCI_FLAGS_UPDATE_CORR          0x00000002
  51#define MCI_BT_MCI_FLAGS_UPDATE_HDR           0x00000004
  52#define MCI_BT_MCI_FLAGS_UPDATE_PLD           0x00000008
  53#define MCI_BT_MCI_FLAGS_LNA_CTRL             0x00000010
  54#define MCI_BT_MCI_FLAGS_DEBUG                0x00000020
  55#define MCI_BT_MCI_FLAGS_SCHED_MSG            0x00000040
  56#define MCI_BT_MCI_FLAGS_CONT_MSG             0x00000080
  57#define MCI_BT_MCI_FLAGS_COEX_GPM             0x00000100
  58#define MCI_BT_MCI_FLAGS_CPU_INT_MSG          0x00000200
  59#define MCI_BT_MCI_FLAGS_MCI_MODE             0x00000400
  60#define MCI_BT_MCI_FLAGS_AR9462_MODE          0x00001000
  61#define MCI_BT_MCI_FLAGS_OTHER                0x00010000
  62
  63#define MCI_DEFAULT_BT_MCI_FLAGS              0x00011dde
  64
  65#define MCI_TOGGLE_BT_MCI_FLAGS  (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
  66                                  MCI_BT_MCI_FLAGS_UPDATE_HDR  | \
  67                                  MCI_BT_MCI_FLAGS_UPDATE_PLD  | \
  68                                  MCI_BT_MCI_FLAGS_MCI_MODE)
  69
  70#define MCI_2G_FLAGS_CLEAR_MASK   0x00000000
  71#define MCI_2G_FLAGS_SET_MASK     MCI_TOGGLE_BT_MCI_FLAGS
  72#define MCI_2G_FLAGS              MCI_DEFAULT_BT_MCI_FLAGS
  73
  74#define MCI_5G_FLAGS_CLEAR_MASK   MCI_TOGGLE_BT_MCI_FLAGS
  75#define MCI_5G_FLAGS_SET_MASK     0x00000000
  76#define MCI_5G_FLAGS              (MCI_DEFAULT_BT_MCI_FLAGS & \
  77                                   ~MCI_TOGGLE_BT_MCI_FLAGS)
  78
  79/*
  80 * Default value for AR9462 is 0x00002201
  81 */
  82#define ATH_MCI_CONFIG_CONCUR_TX            0x00000003
  83#define ATH_MCI_CONFIG_MCI_OBS_MCI          0x00000004
  84#define ATH_MCI_CONFIG_MCI_OBS_TXRX         0x00000008
  85#define ATH_MCI_CONFIG_MCI_OBS_BT           0x00000010
  86#define ATH_MCI_CONFIG_DISABLE_MCI_CAL      0x00000020
  87#define ATH_MCI_CONFIG_DISABLE_OSLA         0x00000040
  88#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP    0x00000080
  89#define ATH_MCI_CONFIG_AGGR_THRESH          0x00000700
  90#define ATH_MCI_CONFIG_AGGR_THRESH_S        8
  91#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH  0x00000800
  92#define ATH_MCI_CONFIG_CLK_DIV              0x00003000
  93#define ATH_MCI_CONFIG_CLK_DIV_S            12
  94#define ATH_MCI_CONFIG_DISABLE_TUNING       0x00004000
  95#define ATH_MCI_CONFIG_DISABLE_AIC          0x00008000
  96#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN     0x007f0000
  97#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S   16
  98#define ATH_MCI_CONFIG_NO_QUIET_ACK         0x00800000
  99#define ATH_MCI_CONFIG_NO_QUIET_ACK_S       23
 100#define ATH_MCI_CONFIG_ANT_ARCH             0x07000000
 101#define ATH_MCI_CONFIG_ANT_ARCH_S           24
 102#define ATH_MCI_CONFIG_FORCE_QUIET_ACK      0x08000000
 103#define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S    27
 104#define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK     0x10000000
 105#define ATH_MCI_CONFIG_MCI_STAT_DBG         0x20000000
 106#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG       0x40000000
 107#define ATH_MCI_CONFIG_DISABLE_MCI          0x80000000
 108
 109#define ATH_MCI_CONFIG_MCI_OBS_MASK     (ATH_MCI_CONFIG_MCI_OBS_MCI  | \
 110                                         ATH_MCI_CONFIG_MCI_OBS_TXRX | \
 111                                         ATH_MCI_CONFIG_MCI_OBS_BT)
 112
 113#define ATH_MCI_CONFIG_MCI_OBS_GPIO     0x0000002F
 114
 115#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
 116#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED     0x01
 117#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
 118#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED     0x03
 119#define ATH_MCI_ANT_ARCH_3_ANT                   0x04
 120
 121#define MCI_ANT_ARCH_PA_LNA_SHARED(mci)                                 \
 122        ((MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
 123         (MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
 124
 125enum mci_message_header {               /* length of payload */
 126        MCI_LNA_CTRL     = 0x10,        /* len = 0 */
 127        MCI_CONT_NACK    = 0x20,        /* len = 0 */
 128        MCI_CONT_INFO    = 0x30,        /* len = 4 */
 129        MCI_CONT_RST     = 0x40,        /* len = 0 */
 130        MCI_SCHD_INFO    = 0x50,        /* len = 16 */
 131        MCI_CPU_INT      = 0x60,        /* len = 4 */
 132        MCI_SYS_WAKING   = 0x70,        /* len = 0 */
 133        MCI_GPM          = 0x80,        /* len = 16 */
 134        MCI_LNA_INFO     = 0x90,        /* len = 1 */
 135        MCI_LNA_STATE    = 0x94,
 136        MCI_LNA_TAKE     = 0x98,
 137        MCI_LNA_TRANS    = 0x9c,
 138        MCI_SYS_SLEEPING = 0xa0,        /* len = 0 */
 139        MCI_REQ_WAKE     = 0xc0,        /* len = 0 */
 140        MCI_DEBUG_16     = 0xfe,        /* len = 2 */
 141        MCI_REMOTE_RESET = 0xff         /* len = 16 */
 142};
 143
 144enum ath_mci_gpm_coex_profile_type {
 145        MCI_GPM_COEX_PROFILE_UNKNOWN,
 146        MCI_GPM_COEX_PROFILE_RFCOMM,
 147        MCI_GPM_COEX_PROFILE_A2DP,
 148        MCI_GPM_COEX_PROFILE_HID,
 149        MCI_GPM_COEX_PROFILE_BNEP,
 150        MCI_GPM_COEX_PROFILE_VOICE,
 151        MCI_GPM_COEX_PROFILE_A2DPVO,
 152        MCI_GPM_COEX_PROFILE_MAX
 153};
 154
 155/* MCI GPM/Coex opcode/type definitions */
 156enum {
 157        MCI_GPM_COEX_W_GPM_PAYLOAD      = 1,
 158        MCI_GPM_COEX_B_GPM_TYPE         = 4,
 159        MCI_GPM_COEX_B_GPM_OPCODE       = 5,
 160        /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
 161        MCI_GPM_WLAN_CAL_W_SEQUENCE     = 2,
 162
 163        /* MCI_GPM_COEX_VERSION_QUERY */
 164        /* MCI_GPM_COEX_VERSION_RESPONSE */
 165        MCI_GPM_COEX_B_MAJOR_VERSION    = 6,
 166        MCI_GPM_COEX_B_MINOR_VERSION    = 7,
 167        /* MCI_GPM_COEX_STATUS_QUERY */
 168        MCI_GPM_COEX_B_BT_BITMAP        = 6,
 169        MCI_GPM_COEX_B_WLAN_BITMAP      = 7,
 170        /* MCI_GPM_COEX_HALT_BT_GPM */
 171        MCI_GPM_COEX_B_HALT_STATE       = 6,
 172        /* MCI_GPM_COEX_WLAN_CHANNELS */
 173        MCI_GPM_COEX_B_CHANNEL_MAP      = 6,
 174        /* MCI_GPM_COEX_BT_PROFILE_INFO */
 175        MCI_GPM_COEX_B_PROFILE_TYPE     = 6,
 176        MCI_GPM_COEX_B_PROFILE_LINKID   = 7,
 177        MCI_GPM_COEX_B_PROFILE_STATE    = 8,
 178        MCI_GPM_COEX_B_PROFILE_ROLE     = 9,
 179        MCI_GPM_COEX_B_PROFILE_RATE     = 10,
 180        MCI_GPM_COEX_B_PROFILE_VOTYPE   = 11,
 181        MCI_GPM_COEX_H_PROFILE_T        = 12,
 182        MCI_GPM_COEX_B_PROFILE_W        = 14,
 183        MCI_GPM_COEX_B_PROFILE_A        = 15,
 184        /* MCI_GPM_COEX_BT_STATUS_UPDATE */
 185        MCI_GPM_COEX_B_STATUS_TYPE      = 6,
 186        MCI_GPM_COEX_B_STATUS_LINKID    = 7,
 187        MCI_GPM_COEX_B_STATUS_STATE     = 8,
 188        /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
 189        MCI_GPM_COEX_W_BT_FLAGS         = 6,
 190        MCI_GPM_COEX_B_BT_FLAGS_OP      = 10
 191};
 192
 193enum mci_gpm_subtype {
 194        MCI_GPM_BT_CAL_REQ      = 0,
 195        MCI_GPM_BT_CAL_GRANT    = 1,
 196        MCI_GPM_BT_CAL_DONE     = 2,
 197        MCI_GPM_WLAN_CAL_REQ    = 3,
 198        MCI_GPM_WLAN_CAL_GRANT  = 4,
 199        MCI_GPM_WLAN_CAL_DONE   = 5,
 200        MCI_GPM_COEX_AGENT      = 0x0c,
 201        MCI_GPM_RSVD_PATTERN    = 0xfe,
 202        MCI_GPM_RSVD_PATTERN32  = 0xfefefefe,
 203        MCI_GPM_BT_DEBUG        = 0xff
 204};
 205
 206enum mci_bt_state {
 207        MCI_BT_SLEEP,
 208        MCI_BT_AWAKE,
 209        MCI_BT_CAL_START,
 210        MCI_BT_CAL
 211};
 212
 213enum mci_ps_state {
 214        MCI_PS_DISABLE,
 215        MCI_PS_ENABLE,
 216        MCI_PS_ENABLE_OFF,
 217        MCI_PS_ENABLE_ON
 218};
 219
 220/* Type of state query */
 221enum mci_state_type {
 222        MCI_STATE_ENABLE,
 223        MCI_STATE_INIT_GPM_OFFSET,
 224        MCI_STATE_CHECK_GPM_OFFSET,
 225        MCI_STATE_NEXT_GPM_OFFSET,
 226        MCI_STATE_LAST_GPM_OFFSET,
 227        MCI_STATE_BT,
 228        MCI_STATE_SET_BT_SLEEP,
 229        MCI_STATE_SET_BT_AWAKE,
 230        MCI_STATE_SET_BT_CAL_START,
 231        MCI_STATE_SET_BT_CAL,
 232        MCI_STATE_LAST_SCHD_MSG_OFFSET,
 233        MCI_STATE_REMOTE_SLEEP,
 234        MCI_STATE_CONT_STATUS,
 235        MCI_STATE_RESET_REQ_WAKE,
 236        MCI_STATE_SEND_WLAN_COEX_VERSION,
 237        MCI_STATE_SET_BT_COEX_VERSION,
 238        MCI_STATE_SEND_WLAN_CHANNELS,
 239        MCI_STATE_SEND_VERSION_QUERY,
 240        MCI_STATE_SEND_STATUS_QUERY,
 241        MCI_STATE_NEED_FLUSH_BT_INFO,
 242        MCI_STATE_SET_CONCUR_TX_PRI,
 243        MCI_STATE_RECOVER_RX,
 244        MCI_STATE_NEED_FTP_STOMP,
 245        MCI_STATE_NEED_TUNING,
 246        MCI_STATE_NEED_STAT_DEBUG,
 247        MCI_STATE_SHARED_CHAIN_CONCUR_TX,
 248        MCI_STATE_AIC_CAL,
 249        MCI_STATE_AIC_START,
 250        MCI_STATE_AIC_CAL_RESET,
 251        MCI_STATE_AIC_CAL_SINGLE,
 252        MCI_STATE_IS_AR9462,
 253        MCI_STATE_IS_AR9565_1ANT,
 254        MCI_STATE_IS_AR9565_2ANT,
 255        MCI_STATE_WLAN_WEAK_SIGNAL,
 256        MCI_STATE_SET_WLAN_PS_STATE,
 257        MCI_STATE_GET_WLAN_PS_STATE,
 258        MCI_STATE_DEBUG,
 259        MCI_STATE_STAT_DEBUG,
 260        MCI_STATE_ALLOW_FCS,
 261        MCI_STATE_SET_2G_CONTENTION,
 262        MCI_STATE_MAX
 263};
 264
 265enum mci_gpm_coex_opcode {
 266        MCI_GPM_COEX_VERSION_QUERY,
 267        MCI_GPM_COEX_VERSION_RESPONSE,
 268        MCI_GPM_COEX_STATUS_QUERY,
 269        MCI_GPM_COEX_HALT_BT_GPM,
 270        MCI_GPM_COEX_WLAN_CHANNELS,
 271        MCI_GPM_COEX_BT_PROFILE_INFO,
 272        MCI_GPM_COEX_BT_STATUS_UPDATE,
 273        MCI_GPM_COEX_BT_UPDATE_FLAGS,
 274        MCI_GPM_COEX_NOOP,
 275};
 276
 277#define MCI_GPM_NOMORE  0
 278#define MCI_GPM_MORE    1
 279#define MCI_GPM_INVALID 0xffffffff
 280
 281#define MCI_GPM_RECYCLE(_p_gpm) do {                      \
 282        *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
 283                                MCI_GPM_RSVD_PATTERN32;   \
 284} while (0)
 285
 286#define MCI_GPM_TYPE(_p_gpm)    \
 287        (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
 288
 289#define MCI_GPM_OPCODE(_p_gpm)  \
 290        (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
 291
 292#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do {                       \
 293        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
 294} while (0)
 295
 296#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do {               \
 297        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff;    \
 298        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
 299} while (0)
 300
 301#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
 302
 303/*
 304 * Functions that are available to the MCI driver core.
 305 */
 306bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
 307                             u32 *payload, u8 len, bool wait_done,
 308                             bool check_bt);
 309u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
 310int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
 311                     u16 len, u32 sched_addr);
 312void ar9003_mci_cleanup(struct ath_hw *ah);
 313void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
 314                              u32 *rx_msg_intr);
 315u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, u32 *more);
 316void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor);
 317void ar9003_mci_send_wlan_channels(struct ath_hw *ah);
 318/*
 319 * These functions are used by ath9k_hw.
 320 */
 321
 322#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 323
 324void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
 325void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
 326void ar9003_mci_init_cal_done(struct ath_hw *ah);
 327void ar9003_mci_set_full_sleep(struct ath_hw *ah);
 328void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
 329void ar9003_mci_check_bt(struct ath_hw *ah);
 330bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
 331int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 332                         struct ath9k_hw_cal_data *caldata);
 333int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 334                     bool is_full_sleep);
 335void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
 336void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
 337void ar9003_mci_set_power_awake(struct ath_hw *ah);
 338void ar9003_mci_check_gpm_offset(struct ath_hw *ah);
 339u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode);
 340
 341#else
 342
 343static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
 344{
 345}
 346static inline void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
 347{
 348}
 349static inline void ar9003_mci_init_cal_done(struct ath_hw *ah)
 350{
 351}
 352static inline void ar9003_mci_set_full_sleep(struct ath_hw *ah)
 353{
 354}
 355static inline void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
 356{
 357}
 358static inline void ar9003_mci_check_bt(struct ath_hw *ah)
 359{
 360}
 361static inline bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
 362{
 363        return false;
 364}
 365static inline int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 366                                       struct ath9k_hw_cal_data *caldata)
 367{
 368        return 0;
 369}
 370static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 371                                    bool is_full_sleep)
 372{
 373}
 374static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 375{
 376}
 377static inline void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
 378{
 379}
 380static inline void ar9003_mci_set_power_awake(struct ath_hw *ah)
 381{
 382}
 383static inline void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
 384{
 385}
 386static inline u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
 387{
 388        return -1;
 389}
 390#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 391
 392#endif
 393