1
2#ifndef B43_XMIT_H_
3#define B43_XMIT_H_
4
5#include "main.h"
6#include <net/mac80211.h>
7
8
9#define _b43_declare_plcp_hdr(size) \
10 struct b43_plcp_hdr##size { \
11 union { \
12 __le32 data; \
13 __u8 raw[size]; \
14 } __packed; \
15 } __packed
16
17
18_b43_declare_plcp_hdr(4);
19
20_b43_declare_plcp_hdr(6);
21
22#undef _b43_declare_plcp_hdr
23
24
25struct b43_txhdr {
26 __le32 mac_ctl;
27 __le16 mac_frame_ctl;
28 __le16 tx_fes_time_norm;
29 __le16 phy_ctl;
30 __le16 phy_ctl1;
31 __le16 phy_ctl1_fb;
32 __le16 phy_ctl1_rts;
33 __le16 phy_ctl1_rts_fb;
34 __u8 phy_rate;
35 __u8 phy_rate_rts;
36 __u8 extra_ft;
37 __u8 chan_radio_code;
38 __u8 iv[16];
39 __u8 tx_receiver[6];
40 __le16 tx_fes_time_fb;
41 struct b43_plcp_hdr6 rts_plcp_fb;
42 __le16 rts_dur_fb;
43 struct b43_plcp_hdr6 plcp_fb;
44 __le16 dur_fb;
45 __le16 mimo_modelen;
46 __le16 mimo_ratelen_fb;
47 __le32 timeout;
48
49 union {
50
51 struct {
52 __le16 mimo_antenna;
53 __le16 preload_size;
54 PAD_BYTES(2);
55 __le16 cookie;
56 __le16 tx_status;
57 __le16 max_n_mpdus;
58 __le16 max_a_bytes_mrt;
59 __le16 max_a_bytes_fbr;
60 __le16 min_m_bytes;
61 struct b43_plcp_hdr6 rts_plcp;
62 __u8 rts_frame[16];
63 PAD_BYTES(2);
64 struct b43_plcp_hdr6 plcp;
65 } format_598 __packed;
66
67
68 struct {
69 __le16 mimo_antenna;
70 __le16 preload_size;
71 PAD_BYTES(2);
72 __le16 cookie;
73 __le16 tx_status;
74 struct b43_plcp_hdr6 rts_plcp;
75 __u8 rts_frame[16];
76 PAD_BYTES(2);
77 struct b43_plcp_hdr6 plcp;
78 } format_410 __packed;
79
80
81 struct {
82 PAD_BYTES(2);
83 __le16 cookie;
84 __le16 tx_status;
85 struct b43_plcp_hdr6 rts_plcp;
86 __u8 rts_frame[16];
87 PAD_BYTES(2);
88 struct b43_plcp_hdr6 plcp;
89 } format_351 __packed;
90
91 } __packed;
92} __packed;
93
94struct b43_tx_legacy_rate_phy_ctl_entry {
95 u8 bitrate;
96 u16 coding_rate;
97 u16 modulation;
98};
99
100
101#define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000
102#define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000
103#define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000
104#define B43_TXH_MAC_USEFBR 0x10000000
105#define B43_TXH_MAC_KEYIDX 0x0FF00000
106#define B43_TXH_MAC_KEYIDX_SHIFT 20
107#define B43_TXH_MAC_ALT_TXPWR 0x00080000
108#define B43_TXH_MAC_KEYALG 0x00070000
109#define B43_TXH_MAC_KEYALG_SHIFT 16
110#define B43_TXH_MAC_AMIC 0x00008000
111#define B43_TXH_MAC_RIFS 0x00004000
112#define B43_TXH_MAC_LIFETIME 0x00002000
113#define B43_TXH_MAC_FRAMEBURST 0x00001000
114#define B43_TXH_MAC_SENDCTS 0x00000800
115#define B43_TXH_MAC_AMPDU 0x00000600
116#define B43_TXH_MAC_AMPDU_MPDU 0x00000000
117#define B43_TXH_MAC_AMPDU_FIRST 0x00000200
118#define B43_TXH_MAC_AMPDU_INTER 0x00000400
119#define B43_TXH_MAC_AMPDU_LAST 0x00000600
120#define B43_TXH_MAC_40MHZ 0x00000100
121#define B43_TXH_MAC_5GHZ 0x00000080
122#define B43_TXH_MAC_DFCS 0x00000040
123#define B43_TXH_MAC_IGNPMQ 0x00000020
124#define B43_TXH_MAC_HWSEQ 0x00000010
125#define B43_TXH_MAC_STMSDU 0x00000008
126#define B43_TXH_MAC_SENDRTS 0x00000004
127#define B43_TXH_MAC_LONGFRAME 0x00000002
128#define B43_TXH_MAC_ACK 0x00000001
129
130
131#define B43_TXH_EFT_FB 0x03
132#define B43_TXH_EFT_FB_CCK 0x00
133#define B43_TXH_EFT_FB_OFDM 0x01
134#define B43_TXH_EFT_FB_HT 0x02
135#define B43_TXH_EFT_FB_VHT 0x03
136#define B43_TXH_EFT_RTS 0x0C
137#define B43_TXH_EFT_RTS_CCK 0x00
138#define B43_TXH_EFT_RTS_OFDM 0x04
139#define B43_TXH_EFT_RTS_HT 0x08
140#define B43_TXH_EFT_RTS_VHT 0x0C
141#define B43_TXH_EFT_RTSFB 0x30
142#define B43_TXH_EFT_RTSFB_CCK 0x00
143#define B43_TXH_EFT_RTSFB_OFDM 0x10
144#define B43_TXH_EFT_RTSFB_HT 0x20
145#define B43_TXH_EFT_RTSFB_VHT 0x30
146
147
148#define B43_TXH_PHY_ENC 0x0003
149#define B43_TXH_PHY_ENC_CCK 0x0000
150#define B43_TXH_PHY_ENC_OFDM 0x0001
151#define B43_TXH_PHY_ENC_HT 0x0002
152#define B43_TXH_PHY_ENC_VHT 0x0003
153#define B43_TXH_PHY_SHORTPRMBL 0x0010
154#define B43_TXH_PHY_ANT 0x03C0
155#define B43_TXH_PHY_ANT0 0x0000
156#define B43_TXH_PHY_ANT1 0x0040
157#define B43_TXH_PHY_ANT01AUTO 0x00C0
158#define B43_TXH_PHY_ANT2 0x0100
159#define B43_TXH_PHY_ANT3 0x0200
160#define B43_TXH_PHY_TXPWR 0xFC00
161#define B43_TXH_PHY_TXPWR_SHIFT 10
162
163
164#define B43_TXH_PHY1_BW 0x0007
165#define B43_TXH_PHY1_BW_10 0x0000
166#define B43_TXH_PHY1_BW_10U 0x0001
167#define B43_TXH_PHY1_BW_20 0x0002
168#define B43_TXH_PHY1_BW_20U 0x0003
169#define B43_TXH_PHY1_BW_40 0x0004
170#define B43_TXH_PHY1_BW_40DUP 0x0005
171#define B43_TXH_PHY1_MODE 0x0038
172#define B43_TXH_PHY1_MODE_SISO 0x0000
173#define B43_TXH_PHY1_MODE_CDD 0x0008
174#define B43_TXH_PHY1_MODE_STBC 0x0010
175#define B43_TXH_PHY1_MODE_SDM 0x0018
176#define B43_TXH_PHY1_CRATE 0x0700
177#define B43_TXH_PHY1_CRATE_1_2 0x0000
178#define B43_TXH_PHY1_CRATE_2_3 0x0100
179#define B43_TXH_PHY1_CRATE_3_4 0x0200
180#define B43_TXH_PHY1_CRATE_4_5 0x0300
181#define B43_TXH_PHY1_CRATE_5_6 0x0400
182#define B43_TXH_PHY1_CRATE_7_8 0x0600
183#define B43_TXH_PHY1_MODUL 0x3800
184#define B43_TXH_PHY1_MODUL_BPSK 0x0000
185#define B43_TXH_PHY1_MODUL_QPSK 0x0800
186#define B43_TXH_PHY1_MODUL_QAM16 0x1000
187#define B43_TXH_PHY1_MODUL_QAM64 0x1800
188#define B43_TXH_PHY1_MODUL_QAM256 0x2000
189
190
191static inline
192size_t b43_txhdr_size(struct b43_wldev *dev)
193{
194 switch (dev->fw.hdr_format) {
195 case B43_FW_HDR_598:
196 return 112 + sizeof(struct b43_plcp_hdr6);
197 case B43_FW_HDR_410:
198 return 104 + sizeof(struct b43_plcp_hdr6);
199 case B43_FW_HDR_351:
200 return 100 + sizeof(struct b43_plcp_hdr6);
201 }
202 return 0;
203}
204
205
206int b43_generate_txhdr(struct b43_wldev *dev,
207 u8 * txhdr,
208 struct sk_buff *skb_frag,
209 struct ieee80211_tx_info *txctl, u16 cookie);
210
211
212struct b43_txstatus {
213 u16 cookie;
214 u16 seq;
215 u8 phy_stat;
216 u8 frame_count;
217 u8 rts_count;
218 u8 supp_reason;
219
220 u8 pm_indicated;
221 u8 intermediate;
222 u8 for_ampdu;
223 u8 acked;
224};
225
226
227enum {
228 B43_TXST_SUPP_NONE,
229 B43_TXST_SUPP_PMQ,
230 B43_TXST_SUPP_FLUSH,
231 B43_TXST_SUPP_PREV,
232 B43_TXST_SUPP_CHAN,
233 B43_TXST_SUPP_LIFE,
234 B43_TXST_SUPP_UNDER,
235 B43_TXST_SUPP_ABNACK,
236};
237
238
239struct b43_rxhdr_fw4 {
240 __le16 frame_len;
241 PAD_BYTES(2);
242 __le16 phy_status0;
243 union {
244
245 struct {
246 __u8 jssi;
247 __u8 sig_qual;
248 } __packed;
249
250
251 struct {
252 __s8 power0;
253 __s8 power1;
254 } __packed;
255 } __packed;
256 union {
257
258 struct {
259 PAD_BYTES(1);
260 __s8 phy_ht_power0;
261 } __packed;
262
263
264 struct {
265 __s8 power2;
266 PAD_BYTES(1);
267 } __packed;
268
269 __le16 phy_status2;
270 } __packed;
271 union {
272
273 struct {
274 __s8 phy_ht_power1;
275 __s8 phy_ht_power2;
276 } __packed;
277
278 __le16 phy_status3;
279 } __packed;
280 union {
281
282 struct {
283 __le16 phy_status4;
284 __le16 phy_status5;
285 __le32 mac_status;
286 __le16 mac_time;
287 __le16 channel;
288 } format_598 __packed;
289
290
291 struct {
292 __le32 mac_status;
293 __le16 mac_time;
294 __le16 channel;
295 } format_351 __packed;
296 } __packed;
297} __packed;
298
299
300#define B43_RX_PHYST0_GAINCTL 0x4000
301#define B43_RX_PHYST0_PLCPHCF 0x0200
302#define B43_RX_PHYST0_PLCPFV 0x0100
303#define B43_RX_PHYST0_SHORTPRMBL 0x0080
304#define B43_RX_PHYST0_LCRS 0x0040
305#define B43_RX_PHYST0_ANT 0x0020
306#define B43_RX_PHYST0_UNSRATE 0x0010
307#define B43_RX_PHYST0_CLIP 0x000C
308#define B43_RX_PHYST0_CLIP_SHIFT 2
309#define B43_RX_PHYST0_FTYPE 0x0003
310#define B43_RX_PHYST0_CCK 0x0000
311#define B43_RX_PHYST0_OFDM 0x0001
312#define B43_RX_PHYST0_PRE_N 0x0002
313#define B43_RX_PHYST0_STD_N 0x0003
314
315
316#define B43_RX_PHYST2_LNAG 0xC000
317#define B43_RX_PHYST2_LNAG_SHIFT 14
318#define B43_RX_PHYST2_PNAG 0x3C00
319#define B43_RX_PHYST2_PNAG_SHIFT 10
320#define B43_RX_PHYST2_FOFF 0x03FF
321
322
323#define B43_RX_PHYST3_DIGG 0x1800
324#define B43_RX_PHYST3_DIGG_SHIFT 11
325#define B43_RX_PHYST3_TRSTATE 0x0400
326
327
328#define B43_RX_MAC_RXST_VALID 0x01000000
329#define B43_RX_MAC_TKIP_MICERR 0x00100000
330#define B43_RX_MAC_TKIP_MICATT 0x00080000
331#define B43_RX_MAC_AGGTYPE 0x00060000
332#define B43_RX_MAC_AGGTYPE_SHIFT 17
333#define B43_RX_MAC_AMSDU 0x00010000
334#define B43_RX_MAC_BEACONSENT 0x00008000
335#define B43_RX_MAC_KEYIDX 0x000007E0
336#define B43_RX_MAC_KEYIDX_SHIFT 5
337#define B43_RX_MAC_DECERR 0x00000010
338#define B43_RX_MAC_DEC 0x00000008
339#define B43_RX_MAC_PADDING 0x00000004
340#define B43_RX_MAC_RESP 0x00000002
341#define B43_RX_MAC_FCSERR 0x00000001
342
343
344#define B43_RX_CHAN_40MHZ 0x1000
345#define B43_RX_CHAN_5GHZ 0x0800
346#define B43_RX_CHAN_ID 0x07F8
347#define B43_RX_CHAN_ID_SHIFT 3
348#define B43_RX_CHAN_PHYTYPE 0x0007
349
350
351u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
352u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
353
354void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
355 const u16 octets, const u8 bitrate);
356
357void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
358
359void b43_handle_txstatus(struct b43_wldev *dev,
360 const struct b43_txstatus *status);
361bool b43_fill_txstatus_report(struct b43_wldev *dev,
362 struct ieee80211_tx_info *report,
363 const struct b43_txstatus *status);
364
365void b43_tx_suspend(struct b43_wldev *dev);
366void b43_tx_resume(struct b43_wldev *dev);
367
368
369
370
371
372static inline int b43_new_kidx_api(struct b43_wldev *dev)
373{
374
375 return (dev->fw.rev >= 351);
376}
377static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
378{
379 u8 firmware_kidx;
380 if (b43_new_kidx_api(dev)) {
381 firmware_kidx = raw_kidx;
382 } else {
383 if (raw_kidx >= 4)
384 firmware_kidx = raw_kidx - 4;
385 else
386 firmware_kidx = raw_kidx;
387 }
388 return firmware_kidx;
389}
390static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
391{
392 u8 raw_kidx;
393 if (b43_new_kidx_api(dev))
394 raw_kidx = firmware_kidx;
395 else
396 raw_kidx = firmware_kidx + 4;
397 return raw_kidx;
398}
399
400
401
402
403
404
405struct b43_private_tx_info {
406 void *bouncebuffer;
407};
408
409static inline struct b43_private_tx_info *
410b43_get_priv_tx_info(struct ieee80211_tx_info *info)
411{
412 BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >
413 sizeof(info->rate_driver_data));
414 return (struct b43_private_tx_info *)info->rate_driver_data;
415}
416
417#endif
418