1
2
3
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/list.h>
8#include <linux/ssb/ssb_regs.h>
9#include <linux/bcma/bcma.h>
10#include <linux/bcma/bcma_regs.h>
11
12#include <defs.h>
13#include <soc.h>
14#include <brcm_hw_ids.h>
15#include <brcmu_utils.h>
16#include <chipcommon.h>
17#include "debug.h"
18#include "chip.h"
19
20
21#define SOCI_SB 0
22#define SOCI_AI 1
23
24
25#define DMP_DESC_TYPE_MSK 0x0000000F
26#define DMP_DESC_EMPTY 0x00000000
27#define DMP_DESC_VALID 0x00000001
28#define DMP_DESC_COMPONENT 0x00000001
29#define DMP_DESC_MASTER_PORT 0x00000003
30#define DMP_DESC_ADDRESS 0x00000005
31#define DMP_DESC_ADDRSIZE_GT32 0x00000008
32#define DMP_DESC_EOT 0x0000000F
33
34#define DMP_COMP_DESIGNER 0xFFF00000
35#define DMP_COMP_DESIGNER_S 20
36#define DMP_COMP_PARTNUM 0x000FFF00
37#define DMP_COMP_PARTNUM_S 8
38#define DMP_COMP_CLASS 0x000000F0
39#define DMP_COMP_CLASS_S 4
40#define DMP_COMP_REVISION 0xFF000000
41#define DMP_COMP_REVISION_S 24
42#define DMP_COMP_NUM_SWRAP 0x00F80000
43#define DMP_COMP_NUM_SWRAP_S 19
44#define DMP_COMP_NUM_MWRAP 0x0007C000
45#define DMP_COMP_NUM_MWRAP_S 14
46#define DMP_COMP_NUM_SPORT 0x00003E00
47#define DMP_COMP_NUM_SPORT_S 9
48#define DMP_COMP_NUM_MPORT 0x000001F0
49#define DMP_COMP_NUM_MPORT_S 4
50
51#define DMP_MASTER_PORT_UID 0x0000FF00
52#define DMP_MASTER_PORT_UID_S 8
53#define DMP_MASTER_PORT_NUM 0x000000F0
54#define DMP_MASTER_PORT_NUM_S 4
55
56#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
57#define DMP_SLAVE_ADDR_BASE_S 12
58#define DMP_SLAVE_PORT_NUM 0x00000F00
59#define DMP_SLAVE_PORT_NUM_S 8
60#define DMP_SLAVE_TYPE 0x000000C0
61#define DMP_SLAVE_TYPE_S 6
62#define DMP_SLAVE_TYPE_SLAVE 0
63#define DMP_SLAVE_TYPE_BRIDGE 1
64#define DMP_SLAVE_TYPE_SWRAP 2
65#define DMP_SLAVE_TYPE_MWRAP 3
66#define DMP_SLAVE_SIZE_TYPE 0x00000030
67#define DMP_SLAVE_SIZE_TYPE_S 4
68#define DMP_SLAVE_SIZE_4K 0
69#define DMP_SLAVE_SIZE_8K 1
70#define DMP_SLAVE_SIZE_16K 2
71#define DMP_SLAVE_SIZE_DESC 3
72
73
74#define CIB_REV_MASK 0xff000000
75#define CIB_REV_SHIFT 24
76
77
78#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
79
80
81#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
82#define D11_BCMA_IOCTL_PHYRESET 0x0008
83
84
85
86
87#define BCM4329_CORE_BUS_BASE 0x18011000
88
89#define BCM4329_CORE_SOCRAM_BASE 0x18003000
90
91#define BCM4329_CORE_ARM_BASE 0x18002000
92
93
94#define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
95
96#define CORE_SB(base, field) \
97 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
98#define SBCOREREV(sbidh) \
99 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
100 ((sbidh) & SSB_IDHIGH_RCLO))
101
102struct sbconfig {
103 u32 PAD[2];
104 u32 sbipsflag;
105 u32 PAD[3];
106 u32 sbtpsflag;
107 u32 PAD[11];
108 u32 sbtmerrloga;
109 u32 PAD;
110 u32 sbtmerrlog;
111 u32 PAD[3];
112 u32 sbadmatch3;
113 u32 PAD;
114 u32 sbadmatch2;
115 u32 PAD;
116 u32 sbadmatch1;
117 u32 PAD[7];
118 u32 sbimstate;
119 u32 sbintvec;
120 u32 sbtmstatelow;
121 u32 sbtmstatehigh;
122 u32 sbbwa0;
123 u32 PAD;
124 u32 sbimconfiglow;
125 u32 sbimconfighigh;
126 u32 sbadmatch0;
127 u32 PAD;
128 u32 sbtmconfiglow;
129 u32 sbtmconfighigh;
130 u32 sbbconfig;
131 u32 PAD;
132 u32 sbbstate;
133 u32 PAD[3];
134 u32 sbactcnfg;
135 u32 PAD[3];
136 u32 sbflagst;
137 u32 PAD[3];
138 u32 sbidlow;
139 u32 sbidhigh;
140};
141
142#define INVALID_RAMBASE ((u32)(~0))
143
144
145#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
146#define SOCRAM_BANKINFO_SZMASK 0x0000007f
147#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
148
149#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
150
151#define SOCRAM_MEMTYPE_RAM 0
152#define SOCRAM_MEMTYPE_R0M 1
153#define SOCRAM_MEMTYPE_DEVRAM 2
154
155#define SOCRAM_BANKINFO_SZBASE 8192
156#define SRCI_LSS_MASK 0x00f00000
157#define SRCI_LSS_SHIFT 20
158#define SRCI_SRNB_MASK 0xf0
159#define SRCI_SRNB_MASK_EXT 0x100
160#define SRCI_SRNB_SHIFT 4
161#define SRCI_SRBSZ_MASK 0xf
162#define SRCI_SRBSZ_SHIFT 0
163#define SR_BSZ_BASE 14
164
165struct sbsocramregs {
166 u32 coreinfo;
167 u32 bwalloc;
168 u32 extracoreinfo;
169 u32 biststat;
170 u32 bankidx;
171 u32 standbyctrl;
172
173 u32 errlogstatus;
174 u32 errlogaddr;
175
176 u32 cambankidx;
177 u32 cambankstandbyctrl;
178 u32 cambankpatchctrl;
179 u32 cambankpatchtblbaseaddr;
180 u32 cambankcmdreg;
181 u32 cambankdatareg;
182 u32 cambankmaskreg;
183 u32 PAD[1];
184 u32 bankinfo;
185 u32 bankpda;
186 u32 PAD[14];
187 u32 extmemconfig;
188 u32 extmemparitycsr;
189 u32 extmemparityerrdata;
190 u32 extmemparityerrcnt;
191 u32 extmemwrctrlandsize;
192 u32 PAD[84];
193 u32 workaround;
194 u32 pwrctl;
195 u32 PAD[133];
196 u32 sr_control;
197 u32 sr_status;
198 u32 sr_address;
199 u32 sr_data;
200};
201
202#define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
203#define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
204
205#define ARMCR4_CAP (0x04)
206#define ARMCR4_BANKIDX (0x40)
207#define ARMCR4_BANKINFO (0x44)
208#define ARMCR4_BANKPDA (0x4C)
209
210#define ARMCR4_TCBBNB_MASK 0xf0
211#define ARMCR4_TCBBNB_SHIFT 4
212#define ARMCR4_TCBANB_MASK 0xf
213#define ARMCR4_TCBANB_SHIFT 0
214
215#define ARMCR4_BSZ_MASK 0x3f
216#define ARMCR4_BSZ_MULT 8192
217
218struct brcmf_core_priv {
219 struct brcmf_core pub;
220 u32 wrapbase;
221 struct list_head list;
222 struct brcmf_chip_priv *chip;
223};
224
225struct brcmf_chip_priv {
226 struct brcmf_chip pub;
227 const struct brcmf_buscore_ops *ops;
228 void *ctx;
229
230 struct list_head cores;
231 u16 num_cores;
232
233 bool (*iscoreup)(struct brcmf_core_priv *core);
234 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
235 u32 reset);
236 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
237 u32 postreset);
238};
239
240static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
241 struct brcmf_core *core)
242{
243 u32 regdata;
244
245 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
246 core->rev = SBCOREREV(regdata);
247}
248
249static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
250{
251 struct brcmf_chip_priv *ci;
252 u32 regdata;
253 u32 address;
254
255 ci = core->chip;
256 address = CORE_SB(core->pub.base, sbtmstatelow);
257 regdata = ci->ops->read32(ci->ctx, address);
258 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
259 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
260 return SSB_TMSLOW_CLOCK == regdata;
261}
262
263static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
264{
265 struct brcmf_chip_priv *ci;
266 u32 regdata;
267 bool ret;
268
269 ci = core->chip;
270 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
271 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
272
273 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
274 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
275
276 return ret;
277}
278
279static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
280 u32 prereset, u32 reset)
281{
282 struct brcmf_chip_priv *ci;
283 u32 val, base;
284
285 ci = core->chip;
286 base = core->pub.base;
287 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
288 if (val & SSB_TMSLOW_RESET)
289 return;
290
291 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
292 if ((val & SSB_TMSLOW_CLOCK) != 0) {
293
294
295
296
297 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
298 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
299 val | SSB_TMSLOW_REJECT);
300
301 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
302 udelay(1);
303 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
304 & SSB_TMSHIGH_BUSY), 100000);
305
306 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
307 if (val & SSB_TMSHIGH_BUSY)
308 brcmf_err("core state still busy\n");
309
310 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
311 if (val & SSB_IDLOW_INITIATOR) {
312 val = ci->ops->read32(ci->ctx,
313 CORE_SB(base, sbimstate));
314 val |= SSB_IMSTATE_REJECT;
315 ci->ops->write32(ci->ctx,
316 CORE_SB(base, sbimstate), val);
317 val = ci->ops->read32(ci->ctx,
318 CORE_SB(base, sbimstate));
319 udelay(1);
320 SPINWAIT((ci->ops->read32(ci->ctx,
321 CORE_SB(base, sbimstate)) &
322 SSB_IMSTATE_BUSY), 100000);
323 }
324
325
326 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
327 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
328 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
329 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
330 udelay(10);
331
332
333 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
334 if (val & SSB_IDLOW_INITIATOR) {
335 val = ci->ops->read32(ci->ctx,
336 CORE_SB(base, sbimstate));
337 val &= ~SSB_IMSTATE_REJECT;
338 ci->ops->write32(ci->ctx,
339 CORE_SB(base, sbimstate), val);
340 }
341 }
342
343
344 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
345 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
346 udelay(1);
347}
348
349static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
350 u32 prereset, u32 reset)
351{
352 struct brcmf_chip_priv *ci;
353 u32 regdata;
354
355 ci = core->chip;
356
357
358 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
359 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
360 goto in_reset_configure;
361
362
363 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
364 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
365 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
366
367
368 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
369 BCMA_RESET_CTL_RESET);
370 usleep_range(10, 20);
371
372
373 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
374 BCMA_RESET_CTL_RESET, 300);
375
376in_reset_configure:
377
378 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
379 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
380 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
381}
382
383static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
384 u32 reset, u32 postreset)
385{
386 struct brcmf_chip_priv *ci;
387 u32 regdata;
388 u32 base;
389
390 ci = core->chip;
391 base = core->pub.base;
392
393
394
395
396 brcmf_chip_sb_coredisable(core, 0, 0);
397
398
399
400
401
402
403 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
404 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
405 SSB_TMSLOW_RESET);
406 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
407 udelay(1);
408
409
410 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
411 if (regdata & SSB_TMSHIGH_SERR)
412 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
413
414 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
415 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
416 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
417 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
418 }
419
420
421 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
422 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
423 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
424 udelay(1);
425
426
427 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
428 SSB_TMSLOW_CLOCK);
429 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
430 udelay(1);
431}
432
433static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
434 u32 reset, u32 postreset)
435{
436 struct brcmf_chip_priv *ci;
437 int count;
438 struct brcmf_core *d11core2 = NULL;
439 struct brcmf_core_priv *d11priv2 = NULL;
440
441 ci = core->chip;
442
443
444 if (core->pub.id == BCMA_CORE_80211) {
445 d11core2 = brcmf_chip_get_d11core(&ci->pub, 1);
446 if (d11core2) {
447 brcmf_dbg(INFO, "found two d11 cores, reset both\n");
448 d11priv2 = container_of(d11core2,
449 struct brcmf_core_priv, pub);
450 }
451 }
452
453
454 brcmf_chip_ai_coredisable(core, prereset, reset);
455 if (d11priv2)
456 brcmf_chip_ai_coredisable(d11priv2, prereset, reset);
457
458 count = 0;
459 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
460 BCMA_RESET_CTL_RESET) {
461 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
462 count++;
463 if (count > 50)
464 break;
465 usleep_range(40, 60);
466 }
467
468 if (d11priv2) {
469 count = 0;
470 while (ci->ops->read32(ci->ctx,
471 d11priv2->wrapbase + BCMA_RESET_CTL) &
472 BCMA_RESET_CTL_RESET) {
473 ci->ops->write32(ci->ctx,
474 d11priv2->wrapbase + BCMA_RESET_CTL,
475 0);
476 count++;
477 if (count > 50)
478 break;
479 usleep_range(40, 60);
480 }
481 }
482
483 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
484 postreset | BCMA_IOCTL_CLK);
485 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
486
487 if (d11priv2) {
488 ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL,
489 postreset | BCMA_IOCTL_CLK);
490 ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
491 }
492}
493
494char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
495{
496 const char *fmt;
497
498 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
499 snprintf(buf, len, fmt, id, rev);
500 return buf;
501}
502
503static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
504 u16 coreid, u32 base,
505 u32 wrapbase)
506{
507 struct brcmf_core_priv *core;
508
509 core = kzalloc(sizeof(*core), GFP_KERNEL);
510 if (!core)
511 return ERR_PTR(-ENOMEM);
512
513 core->pub.id = coreid;
514 core->pub.base = base;
515 core->chip = ci;
516 core->wrapbase = wrapbase;
517
518 list_add_tail(&core->list, &ci->cores);
519 return &core->pub;
520}
521
522
523static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
524{
525 struct brcmf_core_priv *core;
526 bool need_socram = false;
527 bool has_socram = false;
528 bool cpu_found = false;
529 int idx = 1;
530
531 list_for_each_entry(core, &ci->cores, list) {
532 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n",
533 idx++, core->pub.id, core->pub.rev, core->pub.base,
534 core->wrapbase);
535
536 switch (core->pub.id) {
537 case BCMA_CORE_ARM_CM3:
538 cpu_found = true;
539 need_socram = true;
540 break;
541 case BCMA_CORE_INTERNAL_MEM:
542 has_socram = true;
543 break;
544 case BCMA_CORE_ARM_CR4:
545 cpu_found = true;
546 break;
547 case BCMA_CORE_ARM_CA7:
548 cpu_found = true;
549 break;
550 default:
551 break;
552 }
553 }
554
555 if (!cpu_found) {
556 brcmf_err("CPU core not detected\n");
557 return -ENXIO;
558 }
559
560 if (need_socram && !has_socram) {
561 brcmf_err("RAM core not provided with ARM CM3 core\n");
562 return -ENODEV;
563 }
564 return 0;
565}
566
567static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
568{
569 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
570}
571
572static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
573 u16 reg, u32 val)
574{
575 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
576}
577
578static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
579 u32 *banksize)
580{
581 u32 bankinfo;
582 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
583
584 bankidx |= idx;
585 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
586 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
587 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
588 *banksize *= SOCRAM_BANKINFO_SZBASE;
589 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
590}
591
592static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
593 u32 *srsize)
594{
595 u32 coreinfo;
596 uint nb, banksize, lss;
597 bool retent;
598 int i;
599
600 *ramsize = 0;
601 *srsize = 0;
602
603 if (WARN_ON(sr->pub.rev < 4))
604 return;
605
606 if (!brcmf_chip_iscoreup(&sr->pub))
607 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
608
609
610 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
611 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
612
613 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
614 banksize = (coreinfo & SRCI_SRBSZ_MASK);
615 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
616 if (lss != 0)
617 nb--;
618 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
619 if (lss != 0)
620 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
621 } else {
622
623 if (sr->pub.rev >= 23) {
624 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
625 >> SRCI_SRNB_SHIFT;
626 } else {
627 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
628 }
629 for (i = 0; i < nb; i++) {
630 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
631 *ramsize += banksize;
632 if (retent)
633 *srsize += banksize;
634 }
635 }
636
637
638 switch (sr->chip->pub.chip) {
639 case BRCM_CC_4334_CHIP_ID:
640 if (sr->chip->pub.chiprev < 2)
641 *srsize = (32 * 1024);
642 break;
643 case BRCM_CC_43430_CHIP_ID:
644
645
646
647 *srsize = (64 * 1024);
648 break;
649 default:
650 break;
651 }
652}
653
654
655static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
656{
657 u32 memsize = 0;
658 u32 coreinfo;
659 u32 idx;
660 u32 nb;
661 u32 banksize;
662
663 if (!brcmf_chip_iscoreup(&sysmem->pub))
664 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
665
666 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
667 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
668
669 for (idx = 0; idx < nb; idx++) {
670 brcmf_chip_socram_banksize(sysmem, idx, &banksize);
671 memsize += banksize;
672 }
673
674 return memsize;
675}
676
677
678static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
679{
680 u32 corecap;
681 u32 memsize = 0;
682 u32 nab;
683 u32 nbb;
684 u32 totb;
685 u32 bxinfo;
686 u32 idx;
687
688 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
689
690 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
691 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
692 totb = nab + nbb;
693
694 for (idx = 0; idx < totb; idx++) {
695 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
696 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
697 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
698 }
699
700 return memsize;
701}
702
703static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
704{
705 switch (ci->pub.chip) {
706 case BRCM_CC_4345_CHIP_ID:
707 return 0x198000;
708 case BRCM_CC_4335_CHIP_ID:
709 case BRCM_CC_4339_CHIP_ID:
710 case BRCM_CC_4350_CHIP_ID:
711 case BRCM_CC_4354_CHIP_ID:
712 case BRCM_CC_4356_CHIP_ID:
713 case BRCM_CC_43567_CHIP_ID:
714 case BRCM_CC_43569_CHIP_ID:
715 case BRCM_CC_43570_CHIP_ID:
716 case BRCM_CC_4358_CHIP_ID:
717 case BRCM_CC_43602_CHIP_ID:
718 case BRCM_CC_4371_CHIP_ID:
719 return 0x180000;
720 case BRCM_CC_43465_CHIP_ID:
721 case BRCM_CC_43525_CHIP_ID:
722 case BRCM_CC_4365_CHIP_ID:
723 case BRCM_CC_4366_CHIP_ID:
724 case BRCM_CC_43664_CHIP_ID:
725 case BRCM_CC_43666_CHIP_ID:
726 return 0x200000;
727 case BRCM_CC_4359_CHIP_ID:
728 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000;
729 case BRCM_CC_4364_CHIP_ID:
730 case CY_CC_4373_CHIP_ID:
731 return 0x160000;
732 case CY_CC_43752_CHIP_ID:
733 return 0x170000;
734 default:
735 brcmf_err("unknown chip: %s\n", ci->pub.name);
736 break;
737 }
738 return INVALID_RAMBASE;
739}
740
741int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
742{
743 struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
744 pub);
745 struct brcmf_core_priv *mem_core;
746 struct brcmf_core *mem;
747
748 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
749 if (mem) {
750 mem_core = container_of(mem, struct brcmf_core_priv, pub);
751 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
752 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
753 if (ci->pub.rambase == INVALID_RAMBASE) {
754 brcmf_err("RAM base not provided with ARM CR4 core\n");
755 return -EINVAL;
756 }
757 } else {
758 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
759 if (mem) {
760 mem_core = container_of(mem, struct brcmf_core_priv,
761 pub);
762 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
763 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
764 if (ci->pub.rambase == INVALID_RAMBASE) {
765 brcmf_err("RAM base not provided with ARM CA7 core\n");
766 return -EINVAL;
767 }
768 } else {
769 mem = brcmf_chip_get_core(&ci->pub,
770 BCMA_CORE_INTERNAL_MEM);
771 if (!mem) {
772 brcmf_err("No memory cores found\n");
773 return -ENOMEM;
774 }
775 mem_core = container_of(mem, struct brcmf_core_priv,
776 pub);
777 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
778 &ci->pub.srsize);
779 }
780 }
781 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
782 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
783 ci->pub.srsize, ci->pub.srsize);
784
785 if (!ci->pub.ramsize) {
786 brcmf_err("RAM size is undetermined\n");
787 return -ENOMEM;
788 }
789
790 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
791 brcmf_err("RAM size is incorrect\n");
792 return -ENOMEM;
793 }
794
795 return 0;
796}
797
798static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
799 u8 *type)
800{
801 u32 val;
802
803
804 val = ci->ops->read32(ci->ctx, *eromaddr);
805 *eromaddr += 4;
806
807 if (!type)
808 return val;
809
810
811 *type = (val & DMP_DESC_TYPE_MSK);
812 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
813 *type = DMP_DESC_ADDRESS;
814
815 return val;
816}
817
818static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
819 u32 *regbase, u32 *wrapbase)
820{
821 u8 desc;
822 u32 val, szdesc;
823 u8 stype, sztype, wraptype;
824
825 *regbase = 0;
826 *wrapbase = 0;
827
828 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
829 if (desc == DMP_DESC_MASTER_PORT) {
830 wraptype = DMP_SLAVE_TYPE_MWRAP;
831 } else if (desc == DMP_DESC_ADDRESS) {
832
833 *eromaddr -= 4;
834 wraptype = DMP_SLAVE_TYPE_SWRAP;
835 } else {
836 *eromaddr -= 4;
837 return -EILSEQ;
838 }
839
840 do {
841
842 do {
843 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
844
845 if (desc == DMP_DESC_EOT) {
846 *eromaddr -= 4;
847 return -EFAULT;
848 }
849 } while (desc != DMP_DESC_ADDRESS &&
850 desc != DMP_DESC_COMPONENT);
851
852
853 if (desc == DMP_DESC_COMPONENT) {
854 *eromaddr -= 4;
855 return 0;
856 }
857
858
859 if (val & DMP_DESC_ADDRSIZE_GT32)
860 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
861
862 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
863
864
865 if (sztype == DMP_SLAVE_SIZE_DESC) {
866 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
867
868 if (szdesc & DMP_DESC_ADDRSIZE_GT32)
869 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
870 }
871
872
873 if (sztype != DMP_SLAVE_SIZE_4K &&
874 sztype != DMP_SLAVE_SIZE_8K)
875 continue;
876
877 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
878
879
880 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
881 *regbase = val & DMP_SLAVE_ADDR_BASE;
882 if (*wrapbase == 0 && stype == wraptype)
883 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
884 } while (*regbase == 0 || *wrapbase == 0);
885
886 return 0;
887}
888
889static
890int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
891{
892 struct brcmf_core *core;
893 u32 eromaddr;
894 u8 desc_type = 0;
895 u32 val;
896 u16 id;
897 u8 nmw, nsw, rev;
898 u32 base, wrap;
899 int err;
900
901 eromaddr = ci->ops->read32(ci->ctx,
902 CORE_CC_REG(ci->pub.enum_base, eromptr));
903
904 while (desc_type != DMP_DESC_EOT) {
905 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
906 if (!(val & DMP_DESC_VALID))
907 continue;
908
909 if (desc_type == DMP_DESC_EMPTY)
910 continue;
911
912
913 if (desc_type != DMP_DESC_COMPONENT)
914 continue;
915
916 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
917
918
919 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
920 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
921 return -EFAULT;
922
923
924 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
925 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
926 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
927
928
929 if (nmw + nsw == 0 &&
930 id != BCMA_CORE_PMU &&
931 id != BCMA_CORE_GCI)
932 continue;
933
934
935 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
936 if (err)
937 continue;
938
939
940 core = brcmf_chip_add_core(ci, id, base, wrap);
941 if (IS_ERR(core))
942 return PTR_ERR(core);
943
944 core->rev = rev;
945 }
946
947 return 0;
948}
949
950u32 brcmf_chip_enum_base(u16 devid)
951{
952 return SI_ENUM_BASE_DEFAULT;
953}
954
955static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
956{
957 struct brcmf_core *core;
958 u32 regdata;
959 u32 socitype;
960 int ret;
961
962
963
964
965
966
967 regdata = ci->ops->read32(ci->ctx,
968 CORE_CC_REG(ci->pub.enum_base, chipid));
969 ci->pub.chip = regdata & CID_ID_MASK;
970 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
971 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
972
973 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
974 ci->pub.name, sizeof(ci->pub.name));
975 brcmf_dbg(INFO, "found %s chip: %s\n",
976 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
977
978 if (socitype == SOCI_SB) {
979 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
980 brcmf_err("SB chip is not supported\n");
981 return -ENODEV;
982 }
983 ci->iscoreup = brcmf_chip_sb_iscoreup;
984 ci->coredisable = brcmf_chip_sb_coredisable;
985 ci->resetcore = brcmf_chip_sb_resetcore;
986
987 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
988 SI_ENUM_BASE_DEFAULT, 0);
989 brcmf_chip_sb_corerev(ci, core);
990 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
991 BCM4329_CORE_BUS_BASE, 0);
992 brcmf_chip_sb_corerev(ci, core);
993 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
994 BCM4329_CORE_SOCRAM_BASE, 0);
995 brcmf_chip_sb_corerev(ci, core);
996 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
997 BCM4329_CORE_ARM_BASE, 0);
998 brcmf_chip_sb_corerev(ci, core);
999
1000 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
1001 brcmf_chip_sb_corerev(ci, core);
1002 } else if (socitype == SOCI_AI) {
1003 ci->iscoreup = brcmf_chip_ai_iscoreup;
1004 ci->coredisable = brcmf_chip_ai_coredisable;
1005 ci->resetcore = brcmf_chip_ai_resetcore;
1006
1007 brcmf_chip_dmp_erom_scan(ci);
1008 } else {
1009 brcmf_err("chip backplane type %u is not supported\n",
1010 socitype);
1011 return -ENODEV;
1012 }
1013
1014 ret = brcmf_chip_cores_check(ci);
1015 if (ret)
1016 return ret;
1017
1018
1019 brcmf_chip_set_passive(&ci->pub);
1020
1021
1022
1023
1024 if (ci->ops->reset) {
1025 ci->ops->reset(ci->ctx, &ci->pub);
1026 brcmf_chip_set_passive(&ci->pub);
1027 }
1028
1029 return brcmf_chip_get_raminfo(&ci->pub);
1030}
1031
1032static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
1033{
1034 struct brcmf_core *core;
1035 struct brcmf_core_priv *cpu;
1036 u32 val;
1037
1038
1039 core = brcmf_chip_get_core(&chip->pub, id);
1040 if (!core)
1041 return;
1042
1043 switch (id) {
1044 case BCMA_CORE_ARM_CM3:
1045 brcmf_chip_coredisable(core, 0, 0);
1046 break;
1047 case BCMA_CORE_ARM_CR4:
1048 case BCMA_CORE_ARM_CA7:
1049 cpu = container_of(core, struct brcmf_core_priv, pub);
1050
1051
1052 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1053 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1054 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1055 ARMCR4_BCMA_IOCTL_CPUHALT);
1056 break;
1057 default:
1058 brcmf_err("unknown id: %u\n", id);
1059 break;
1060 }
1061}
1062
1063static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1064{
1065 struct brcmf_chip *pub;
1066 struct brcmf_core_priv *cc;
1067 struct brcmf_core *pmu;
1068 u32 base;
1069 u32 val;
1070 int ret = 0;
1071
1072 pub = &chip->pub;
1073 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1074 base = cc->pub.base;
1075
1076
1077 pub->cc_caps = chip->ops->read32(chip->ctx,
1078 CORE_CC_REG(base, capabilities));
1079 pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1080 CORE_CC_REG(base,
1081 capabilities_ext));
1082
1083
1084 pmu = brcmf_chip_get_pmu(pub);
1085 if (pub->cc_caps & CC_CAP_PMU) {
1086 val = chip->ops->read32(chip->ctx,
1087 CORE_CC_REG(pmu->base, pmucapabilities));
1088 pub->pmurev = val & PCAP_REV_MASK;
1089 pub->pmucaps = val;
1090 }
1091
1092 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1093 cc->pub.rev, pub->pmurev, pub->pmucaps);
1094
1095
1096 if (chip->ops->setup)
1097 ret = chip->ops->setup(chip->ctx, pub);
1098
1099 return ret;
1100}
1101
1102struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
1103 const struct brcmf_buscore_ops *ops)
1104{
1105 struct brcmf_chip_priv *chip;
1106 int err = 0;
1107
1108 if (WARN_ON(!ops->read32))
1109 err = -EINVAL;
1110 if (WARN_ON(!ops->write32))
1111 err = -EINVAL;
1112 if (WARN_ON(!ops->prepare))
1113 err = -EINVAL;
1114 if (WARN_ON(!ops->activate))
1115 err = -EINVAL;
1116 if (err < 0)
1117 return ERR_PTR(-EINVAL);
1118
1119 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1120 if (!chip)
1121 return ERR_PTR(-ENOMEM);
1122
1123 INIT_LIST_HEAD(&chip->cores);
1124 chip->num_cores = 0;
1125 chip->ops = ops;
1126 chip->ctx = ctx;
1127 chip->pub.enum_base = brcmf_chip_enum_base(devid);
1128
1129 err = ops->prepare(ctx);
1130 if (err < 0)
1131 goto fail;
1132
1133 err = brcmf_chip_recognition(chip);
1134 if (err < 0)
1135 goto fail;
1136
1137 err = brcmf_chip_setup(chip);
1138 if (err < 0)
1139 goto fail;
1140
1141 return &chip->pub;
1142
1143fail:
1144 brcmf_chip_detach(&chip->pub);
1145 return ERR_PTR(err);
1146}
1147
1148void brcmf_chip_detach(struct brcmf_chip *pub)
1149{
1150 struct brcmf_chip_priv *chip;
1151 struct brcmf_core_priv *core;
1152 struct brcmf_core_priv *tmp;
1153
1154 chip = container_of(pub, struct brcmf_chip_priv, pub);
1155 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1156 list_del(&core->list);
1157 kfree(core);
1158 }
1159 kfree(chip);
1160}
1161
1162struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit)
1163{
1164 struct brcmf_chip_priv *chip;
1165 struct brcmf_core_priv *core;
1166
1167 chip = container_of(pub, struct brcmf_chip_priv, pub);
1168 list_for_each_entry(core, &chip->cores, list) {
1169 if (core->pub.id == BCMA_CORE_80211) {
1170 if (unit-- == 0)
1171 return &core->pub;
1172 }
1173 }
1174 return NULL;
1175}
1176
1177struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1178{
1179 struct brcmf_chip_priv *chip;
1180 struct brcmf_core_priv *core;
1181
1182 chip = container_of(pub, struct brcmf_chip_priv, pub);
1183 list_for_each_entry(core, &chip->cores, list)
1184 if (core->pub.id == coreid)
1185 return &core->pub;
1186
1187 return NULL;
1188}
1189
1190struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1191{
1192 struct brcmf_chip_priv *chip;
1193 struct brcmf_core_priv *cc;
1194
1195 chip = container_of(pub, struct brcmf_chip_priv, pub);
1196 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1197 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1198 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1199 return &cc->pub;
1200}
1201
1202struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1203{
1204 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1205 struct brcmf_core *pmu;
1206
1207
1208 if (cc->rev >= 35 &&
1209 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1210 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1211 if (pmu)
1212 return pmu;
1213 }
1214
1215
1216 return cc;
1217}
1218
1219bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1220{
1221 struct brcmf_core_priv *core;
1222
1223 core = container_of(pub, struct brcmf_core_priv, pub);
1224 return core->chip->iscoreup(core);
1225}
1226
1227void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1228{
1229 struct brcmf_core_priv *core;
1230
1231 core = container_of(pub, struct brcmf_core_priv, pub);
1232 core->chip->coredisable(core, prereset, reset);
1233}
1234
1235void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1236 u32 postreset)
1237{
1238 struct brcmf_core_priv *core;
1239
1240 core = container_of(pub, struct brcmf_core_priv, pub);
1241 core->chip->resetcore(core, prereset, reset, postreset);
1242}
1243
1244static void
1245brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1246{
1247 struct brcmf_core *core;
1248 struct brcmf_core_priv *sr;
1249
1250 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1251 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1252 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1253 D11_BCMA_IOCTL_PHYCLOCKEN,
1254 D11_BCMA_IOCTL_PHYCLOCKEN,
1255 D11_BCMA_IOCTL_PHYCLOCKEN);
1256 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1257 brcmf_chip_resetcore(core, 0, 0, 0);
1258
1259
1260 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1261 sr = container_of(core, struct brcmf_core_priv, pub);
1262 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1263 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1264 }
1265}
1266
1267static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1268{
1269 struct brcmf_core *core;
1270
1271 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1272 if (!brcmf_chip_iscoreup(core)) {
1273 brcmf_err("SOCRAM core is down after reset?\n");
1274 return false;
1275 }
1276
1277 chip->ops->activate(chip->ctx, &chip->pub, 0);
1278
1279 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1280 brcmf_chip_resetcore(core, 0, 0, 0);
1281
1282 return true;
1283}
1284
1285static inline void
1286brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1287{
1288 struct brcmf_core *core;
1289
1290 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1291
1292 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1293 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1294 D11_BCMA_IOCTL_PHYCLOCKEN,
1295 D11_BCMA_IOCTL_PHYCLOCKEN,
1296 D11_BCMA_IOCTL_PHYCLOCKEN);
1297}
1298
1299static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1300{
1301 struct brcmf_core *core;
1302
1303 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1304
1305
1306 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1307 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1308
1309 return true;
1310}
1311
1312static inline void
1313brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1314{
1315 struct brcmf_core *core;
1316
1317 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1318
1319 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1320 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1321 D11_BCMA_IOCTL_PHYCLOCKEN,
1322 D11_BCMA_IOCTL_PHYCLOCKEN,
1323 D11_BCMA_IOCTL_PHYCLOCKEN);
1324}
1325
1326static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1327{
1328 struct brcmf_core *core;
1329
1330 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1331
1332
1333 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1334 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1335
1336 return true;
1337}
1338
1339void brcmf_chip_set_passive(struct brcmf_chip *pub)
1340{
1341 struct brcmf_chip_priv *chip;
1342 struct brcmf_core *arm;
1343
1344 brcmf_dbg(TRACE, "Enter\n");
1345
1346 chip = container_of(pub, struct brcmf_chip_priv, pub);
1347 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1348 if (arm) {
1349 brcmf_chip_cr4_set_passive(chip);
1350 return;
1351 }
1352 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1353 if (arm) {
1354 brcmf_chip_ca7_set_passive(chip);
1355 return;
1356 }
1357 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1358 if (arm) {
1359 brcmf_chip_cm3_set_passive(chip);
1360 return;
1361 }
1362}
1363
1364bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1365{
1366 struct brcmf_chip_priv *chip;
1367 struct brcmf_core *arm;
1368
1369 brcmf_dbg(TRACE, "Enter\n");
1370
1371 chip = container_of(pub, struct brcmf_chip_priv, pub);
1372 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1373 if (arm)
1374 return brcmf_chip_cr4_set_active(chip, rstvec);
1375 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1376 if (arm)
1377 return brcmf_chip_ca7_set_active(chip, rstvec);
1378 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1379 if (arm)
1380 return brcmf_chip_cm3_set_active(chip);
1381
1382 return false;
1383}
1384
1385bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1386{
1387 u32 base, addr, reg, pmu_cc3_mask = ~0;
1388 struct brcmf_chip_priv *chip;
1389 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1390
1391 brcmf_dbg(TRACE, "Enter\n");
1392
1393
1394 if (pub->pmurev < 17)
1395 return false;
1396
1397 base = brcmf_chip_get_chipcommon(pub)->base;
1398 chip = container_of(pub, struct brcmf_chip_priv, pub);
1399
1400 switch (pub->chip) {
1401 case BRCM_CC_4354_CHIP_ID:
1402 case BRCM_CC_4356_CHIP_ID:
1403 case BRCM_CC_4345_CHIP_ID:
1404
1405 pmu_cc3_mask = BIT(2);
1406 fallthrough;
1407 case BRCM_CC_43241_CHIP_ID:
1408 case BRCM_CC_4335_CHIP_ID:
1409 case BRCM_CC_4339_CHIP_ID:
1410
1411 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1412 chip->ops->write32(chip->ctx, addr, 3);
1413 addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1414 reg = chip->ops->read32(chip->ctx, addr);
1415 return (reg & pmu_cc3_mask) != 0;
1416 case BRCM_CC_43430_CHIP_ID:
1417 addr = CORE_CC_REG(base, sr_control1);
1418 reg = chip->ops->read32(chip->ctx, addr);
1419 return reg != 0;
1420 case CY_CC_4373_CHIP_ID:
1421
1422 addr = CORE_CC_REG(base, sr_control0);
1423 reg = chip->ops->read32(chip->ctx, addr);
1424 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1425 case BRCM_CC_4359_CHIP_ID:
1426 case CY_CC_43752_CHIP_ID:
1427 case CY_CC_43012_CHIP_ID:
1428 addr = CORE_CC_REG(pmu->base, retention_ctl);
1429 reg = chip->ops->read32(chip->ctx, addr);
1430 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1431 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1432 default:
1433 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1434 reg = chip->ops->read32(chip->ctx, addr);
1435 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1436 return false;
1437
1438 addr = CORE_CC_REG(pmu->base, retention_ctl);
1439 reg = chip->ops->read32(chip->ctx, addr);
1440 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1441 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1442 }
1443}
1444
