LXR linux/drivers/net/wireless/intel/iwlwifi/fw/dump.c

   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2012-2014, 2018-2021 Intel Corporation
   4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
   5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
   6 */
   7#include <linux/devcoredump.h>
   8#include "iwl-drv.h"
   9#include "runtime.h"
  10#include "dbg.h"
  11#include "debugfs.h"
  12#include "iwl-io.h"
  13#include "iwl-prph.h"
  14#include "iwl-csr.h"
  15
  16/*
  17 * Note: This structure is read from the device with IO accesses,
  18 * and the reading already does the endian conversion. As it is
  19 * read with u32-sized accesses, any members with a different size
  20 * need to be ordered correctly though!
  21 */
  22struct iwl_error_event_table_v1 {
  23        u32 valid;              /* (nonzero) valid, (0) log is empty */
  24        u32 error_id;           /* type of error */
  25        u32 pc;                 /* program counter */
  26        u32 blink1;             /* branch link */
  27        u32 blink2;             /* branch link */
  28        u32 ilink1;             /* interrupt link */
  29        u32 ilink2;             /* interrupt link */
  30        u32 data1;              /* error-specific data */
  31        u32 data2;              /* error-specific data */
  32        u32 data3;              /* error-specific data */
  33        u32 bcon_time;          /* beacon timer */
  34        u32 tsf_low;            /* network timestamp function timer */
  35        u32 tsf_hi;             /* network timestamp function timer */
  36        u32 gp1;                /* GP1 timer register */
  37        u32 gp2;                /* GP2 timer register */
  38        u32 gp3;                /* GP3 timer register */
  39        u32 ucode_ver;          /* uCode version */
  40        u32 hw_ver;             /* HW Silicon version */
  41        u32 brd_ver;            /* HW board version */
  42        u32 log_pc;             /* log program counter */
  43        u32 frame_ptr;          /* frame pointer */
  44        u32 stack_ptr;          /* stack pointer */
  45        u32 hcmd;               /* last host command header */
  46        u32 isr0;               /* isr status register LMPM_NIC_ISR0:
  47                                 * rxtx_flag */
  48        u32 isr1;               /* isr status register LMPM_NIC_ISR1:
  49                                 * host_flag */
  50        u32 isr2;               /* isr status register LMPM_NIC_ISR2:
  51                                 * enc_flag */
  52        u32 isr3;               /* isr status register LMPM_NIC_ISR3:
  53                                 * time_flag */
  54        u32 isr4;               /* isr status register LMPM_NIC_ISR4:
  55                                 * wico interrupt */
  56        u32 isr_pref;           /* isr status register LMPM_NIC_PREF_STAT */
  57        u32 wait_event;         /* wait event() caller address */
  58        u32 l2p_control;        /* L2pControlField */
  59        u32 l2p_duration;       /* L2pDurationField */
  60        u32 l2p_mhvalid;        /* L2pMhValidBits */
  61        u32 l2p_addr_match;     /* L2pAddrMatchStat */
  62        u32 lmpm_pmg_sel;       /* indicate which clocks are turned on
  63                                 * (LMPM_PMG_SEL) */
  64        u32 u_timestamp;        /* indicate when the date and time of the
  65                                 * compilation */
  66        u32 flow_handler;       /* FH read/write pointers, RX credit */
  67} __packed /* LOG_ERROR_TABLE_API_S_VER_1 */;
  68
  69struct iwl_error_event_table {
  70        u32 valid;              /* (nonzero) valid, (0) log is empty */
  71        u32 error_id;           /* type of error */
  72        u32 trm_hw_status0;     /* TRM HW status */
  73        u32 trm_hw_status1;     /* TRM HW status */
  74        u32 blink2;             /* branch link */
  75        u32 ilink1;             /* interrupt link */
  76        u32 ilink2;             /* interrupt link */
  77        u32 data1;              /* error-specific data */
  78        u32 data2;              /* error-specific data */
  79        u32 data3;              /* error-specific data */
  80        u32 bcon_time;          /* beacon timer */
  81        u32 tsf_low;            /* network timestamp function timer */
  82        u32 tsf_hi;             /* network timestamp function timer */
  83        u32 gp1;                /* GP1 timer register */
  84        u32 gp2;                /* GP2 timer register */
  85        u32 fw_rev_type;        /* firmware revision type */
  86        u32 major;              /* uCode version major */
  87        u32 minor;              /* uCode version minor */
  88        u32 hw_ver;             /* HW Silicon version */
  89        u32 brd_ver;            /* HW board version */
  90        u32 log_pc;             /* log program counter */
  91        u32 frame_ptr;          /* frame pointer */
  92        u32 stack_ptr;          /* stack pointer */
  93        u32 hcmd;               /* last host command header */
  94        u32 isr0;               /* isr status register LMPM_NIC_ISR0:
  95                                 * rxtx_flag */
  96        u32 isr1;               /* isr status register LMPM_NIC_ISR1:
  97                                 * host_flag */
  98        u32 isr2;               /* isr status register LMPM_NIC_ISR2:
  99                                 * enc_flag */
 100        u32 isr3;               /* isr status register LMPM_NIC_ISR3:
 101                                 * time_flag */
 102        u32 isr4;               /* isr status register LMPM_NIC_ISR4:
 103                                 * wico interrupt */
 104        u32 last_cmd_id;        /* last HCMD id handled by the firmware */
 105        u32 wait_event;         /* wait event() caller address */
 106        u32 l2p_control;        /* L2pControlField */
 107        u32 l2p_duration;       /* L2pDurationField */
 108        u32 l2p_mhvalid;        /* L2pMhValidBits */
 109        u32 l2p_addr_match;     /* L2pAddrMatchStat */
 110        u32 lmpm_pmg_sel;       /* indicate which clocks are turned on
 111                                 * (LMPM_PMG_SEL) */
 112        u32 u_timestamp;        /* indicate when the date and time of the
 113                                 * compilation */
 114        u32 flow_handler;       /* FH read/write pointers, RX credit */
 115} __packed /* LOG_ERROR_TABLE_API_S_VER_3 */;
 116
 117/*
 118 * UMAC error struct - relevant starting from family 8000 chip.
 119 * Note: This structure is read from the device with IO accesses,
 120 * and the reading already does the endian conversion. As it is
 121 * read with u32-sized accesses, any members with a different size
 122 * need to be ordered correctly though!
 123 */
 124struct iwl_umac_error_event_table {
 125        u32 valid;              /* (nonzero) valid, (0) log is empty */
 126        u32 error_id;           /* type of error */
 127        u32 blink1;             /* branch link */
 128        u32 blink2;             /* branch link */
 129        u32 ilink1;             /* interrupt link */
 130        u32 ilink2;             /* interrupt link */
 131        u32 data1;              /* error-specific data */
 132        u32 data2;              /* error-specific data */
 133        u32 data3;              /* error-specific data */
 134        u32 umac_major;
 135        u32 umac_minor;
 136        u32 frame_pointer;      /* core register 27*/
 137        u32 stack_pointer;      /* core register 28 */
 138        u32 cmd_header;         /* latest host cmd sent to UMAC */
 139        u32 nic_isr_pref;       /* ISR status register */
 140} __packed;
 141
 142#define ERROR_START_OFFSET  (1 * sizeof(u32))
 143#define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 144
 145static void iwl_fwrt_dump_umac_error_log(struct iwl_fw_runtime *fwrt)
 146{
 147        struct iwl_trans *trans = fwrt->trans;
 148        struct iwl_umac_error_event_table table = {};
 149        u32 base = fwrt->trans->dbg.umac_error_event_table;
 150
 151        if (!base &&
 152            !(fwrt->trans->dbg.error_event_table_tlv_status &
 153              IWL_ERROR_EVENT_TABLE_UMAC))
 154                return;
 155
 156        iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
 157
 158        if (table.valid)
 159                fwrt->dump.umac_err_id = table.error_id;
 160
 161        if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 162                IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 163                IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n",
 164                        fwrt->trans->status, table.valid);
 165        }
 166
 167        IWL_ERR(fwrt, "0x%08X | %s\n", table.error_id,
 168                iwl_fw_lookup_assert_desc(table.error_id));
 169        IWL_ERR(fwrt, "0x%08X | umac branchlink1\n", table.blink1);
 170        IWL_ERR(fwrt, "0x%08X | umac branchlink2\n", table.blink2);
 171        IWL_ERR(fwrt, "0x%08X | umac interruptlink1\n", table.ilink1);
 172        IWL_ERR(fwrt, "0x%08X | umac interruptlink2\n", table.ilink2);
 173        IWL_ERR(fwrt, "0x%08X | umac data1\n", table.data1);
 174        IWL_ERR(fwrt, "0x%08X | umac data2\n", table.data2);
 175        IWL_ERR(fwrt, "0x%08X | umac data3\n", table.data3);
 176        IWL_ERR(fwrt, "0x%08X | umac major\n", table.umac_major);
 177        IWL_ERR(fwrt, "0x%08X | umac minor\n", table.umac_minor);
 178        IWL_ERR(fwrt, "0x%08X | frame pointer\n", table.frame_pointer);
 179        IWL_ERR(fwrt, "0x%08X | stack pointer\n", table.stack_pointer);
 180        IWL_ERR(fwrt, "0x%08X | last host cmd\n", table.cmd_header);
 181        IWL_ERR(fwrt, "0x%08X | isr status reg\n", table.nic_isr_pref);
 182}
 183
 184static void iwl_fwrt_dump_lmac_error_log(struct iwl_fw_runtime *fwrt, u8 lmac_num)
 185{
 186        struct iwl_trans *trans = fwrt->trans;
 187        struct iwl_error_event_table table = {};
 188        u32 val, base = fwrt->trans->dbg.lmac_error_event_table[lmac_num];
 189
 190        if (fwrt->cur_fw_img == IWL_UCODE_INIT) {
 191                if (!base)
 192                        base = fwrt->fw->init_errlog_ptr;
 193        } else {
 194                if (!base)
 195                        base = fwrt->fw->inst_errlog_ptr;
 196        }
 197
 198        if (base < 0x400000) {
 199                IWL_ERR(fwrt,
 200                        "Not valid error log pointer 0x%08X for %s uCode\n",
 201                        base,
 202                        (fwrt->cur_fw_img == IWL_UCODE_INIT)
 203                        ? "Init" : "RT");
 204                return;
 205        }
 206
 207        /* check if there is a HW error */
 208        val = iwl_trans_read_mem32(trans, base);
 209        if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) {
 210                int err;
 211
 212                IWL_ERR(trans, "HW error, resetting before reading\n");
 213
 214                /* reset the device */
 215                iwl_trans_sw_reset(trans);
 216
 217                err = iwl_finish_nic_init(trans, trans->trans_cfg);
 218                if (err)
 219                        return;
 220        }
 221
 222        iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
 223
 224        if (table.valid)
 225                fwrt->dump.lmac_err_id[lmac_num] = table.error_id;
 226
 227        if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 228                IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 229                IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n",
 230                        fwrt->trans->status, table.valid);
 231        }
 232
 233        /* Do not change this output - scripts rely on it */
 234
 235        IWL_ERR(fwrt, "Loaded firmware version: %s\n", fwrt->fw->fw_version);
 236
 237        IWL_ERR(fwrt, "0x%08X | %-28s\n", table.error_id,
 238                iwl_fw_lookup_assert_desc(table.error_id));
 239        IWL_ERR(fwrt, "0x%08X | trm_hw_status0\n", table.trm_hw_status0);
 240        IWL_ERR(fwrt, "0x%08X | trm_hw_status1\n", table.trm_hw_status1);
 241        IWL_ERR(fwrt, "0x%08X | branchlink2\n", table.blink2);
 242        IWL_ERR(fwrt, "0x%08X | interruptlink1\n", table.ilink1);
 243        IWL_ERR(fwrt, "0x%08X | interruptlink2\n", table.ilink2);
 244        IWL_ERR(fwrt, "0x%08X | data1\n", table.data1);
 245        IWL_ERR(fwrt, "0x%08X | data2\n", table.data2);
 246        IWL_ERR(fwrt, "0x%08X | data3\n", table.data3);
 247        IWL_ERR(fwrt, "0x%08X | beacon time\n", table.bcon_time);
 248        IWL_ERR(fwrt, "0x%08X | tsf low\n", table.tsf_low);
 249        IWL_ERR(fwrt, "0x%08X | tsf hi\n", table.tsf_hi);
 250        IWL_ERR(fwrt, "0x%08X | time gp1\n", table.gp1);
 251        IWL_ERR(fwrt, "0x%08X | time gp2\n", table.gp2);
 252        IWL_ERR(fwrt, "0x%08X | uCode revision type\n", table.fw_rev_type);
 253        IWL_ERR(fwrt, "0x%08X | uCode version major\n", table.major);
 254        IWL_ERR(fwrt, "0x%08X | uCode version minor\n", table.minor);
 255        IWL_ERR(fwrt, "0x%08X | hw version\n", table.hw_ver);
 256        IWL_ERR(fwrt, "0x%08X | board version\n", table.brd_ver);
 257        IWL_ERR(fwrt, "0x%08X | hcmd\n", table.hcmd);
 258        IWL_ERR(fwrt, "0x%08X | isr0\n", table.isr0);
 259        IWL_ERR(fwrt, "0x%08X | isr1\n", table.isr1);
 260        IWL_ERR(fwrt, "0x%08X | isr2\n", table.isr2);
 261        IWL_ERR(fwrt, "0x%08X | isr3\n", table.isr3);
 262        IWL_ERR(fwrt, "0x%08X | isr4\n", table.isr4);
 263        IWL_ERR(fwrt, "0x%08X | last cmd Id\n", table.last_cmd_id);
 264        IWL_ERR(fwrt, "0x%08X | wait_event\n", table.wait_event);
 265        IWL_ERR(fwrt, "0x%08X | l2p_control\n", table.l2p_control);
 266        IWL_ERR(fwrt, "0x%08X | l2p_duration\n", table.l2p_duration);
 267        IWL_ERR(fwrt, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
 268        IWL_ERR(fwrt, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
 269        IWL_ERR(fwrt, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
 270        IWL_ERR(fwrt, "0x%08X | timestamp\n", table.u_timestamp);
 271        IWL_ERR(fwrt, "0x%08X | flow_handler\n", table.flow_handler);
 272}
 273
 274/*
 275 * TCM error struct.
 276 * Note: This structure is read from the device with IO accesses,
 277 * and the reading already does the endian conversion. As it is
 278 * read with u32-sized accesses, any members with a different size
 279 * need to be ordered correctly though!
 280 */
 281struct iwl_tcm_error_event_table {
 282        u32 valid;
 283        u32 error_id;
 284        u32 blink2;
 285        u32 ilink1;
 286        u32 ilink2;
 287        u32 data1, data2, data3;
 288        u32 logpc;
 289        u32 frame_pointer;
 290        u32 stack_pointer;
 291        u32 msgid;
 292        u32 isr;
 293        u32 hw_status[5];
 294        u32 sw_status[1];
 295        u32 reserved[4];
 296} __packed; /* TCM_LOG_ERROR_TABLE_API_S_VER_1 */
 297
 298static void iwl_fwrt_dump_tcm_error_log(struct iwl_fw_runtime *fwrt)
 299{
 300        struct iwl_trans *trans = fwrt->trans;
 301        struct iwl_tcm_error_event_table table = {};
 302        u32 base = fwrt->trans->dbg.tcm_error_event_table;
 303        int i;
 304
 305        if (!base ||
 306            !(fwrt->trans->dbg.error_event_table_tlv_status &
 307              IWL_ERROR_EVENT_TABLE_TCM))
 308                return;
 309
 310        iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
 311
 312        IWL_ERR(fwrt, "TCM status:\n");
 313        IWL_ERR(fwrt, "0x%08X | error ID\n", table.error_id);
 314        IWL_ERR(fwrt, "0x%08X | tcm branchlink2\n", table.blink2);
 315        IWL_ERR(fwrt, "0x%08X | tcm interruptlink1\n", table.ilink1);
 316        IWL_ERR(fwrt, "0x%08X | tcm interruptlink2\n", table.ilink2);
 317        IWL_ERR(fwrt, "0x%08X | tcm data1\n", table.data1);
 318        IWL_ERR(fwrt, "0x%08X | tcm data2\n", table.data2);
 319        IWL_ERR(fwrt, "0x%08X | tcm data3\n", table.data3);
 320        IWL_ERR(fwrt, "0x%08X | tcm log PC\n", table.logpc);
 321        IWL_ERR(fwrt, "0x%08X | tcm frame pointer\n", table.frame_pointer);
 322        IWL_ERR(fwrt, "0x%08X | tcm stack pointer\n", table.stack_pointer);
 323        IWL_ERR(fwrt, "0x%08X | tcm msg ID\n", table.msgid);
 324        IWL_ERR(fwrt, "0x%08X | tcm ISR status\n", table.isr);
 325        for (i = 0; i < ARRAY_SIZE(table.hw_status); i++)
 326                IWL_ERR(fwrt, "0x%08X | tcm HW status[%d]\n",
 327                        table.hw_status[i], i);
 328        for (i = 0; i < ARRAY_SIZE(table.sw_status); i++)
 329                IWL_ERR(fwrt, "0x%08X | tcm SW status[%d]\n",
 330                        table.sw_status[i], i);
 331}
 332
 333static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)
 334{
 335        struct iwl_trans *trans = fwrt->trans;
 336        u32 error, data1;
 337
 338        if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
 339                error = UMAG_SB_CPU_2_STATUS;
 340                data1 = UMAG_SB_CPU_1_STATUS;
 341        } else if (fwrt->trans->trans_cfg->device_family >=
 342                   IWL_DEVICE_FAMILY_8000) {
 343                error = SB_CPU_2_STATUS;
 344                data1 = SB_CPU_1_STATUS;
 345        } else {
 346                return;
 347        }
 348
 349        error = iwl_read_umac_prph(trans, UMAG_SB_CPU_2_STATUS);
 350
 351        IWL_ERR(trans, "IML/ROM dump:\n");
 352
 353        if (error & 0xFFFF0000)
 354                IWL_ERR(trans, "0x%04X | IML/ROM SYSASSERT\n", error >> 16);
 355
 356        IWL_ERR(fwrt, "0x%08X | IML/ROM error/state\n", error);
 357        IWL_ERR(fwrt, "0x%08X | IML/ROM data1\n",
 358                iwl_read_umac_prph(trans, data1));
 359
 360        if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000)
 361                IWL_ERR(fwrt, "0x%08X | IML/ROM WFPM_AUTH_KEY_0\n",
 362                        iwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));
 363}
 364
 365#define FSEQ_REG(x) { .addr = (x), .str = #x, }
 366
 367static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt)
 368{
 369        struct iwl_trans *trans = fwrt->trans;
 370        int i;
 371        struct {
 372                u32 addr;
 373                const char *str;
 374        } fseq_regs[] = {
 375                FSEQ_REG(FSEQ_ERROR_CODE),
 376                FSEQ_REG(FSEQ_TOP_INIT_VERSION),
 377                FSEQ_REG(FSEQ_CNVIO_INIT_VERSION),
 378                FSEQ_REG(FSEQ_OTP_VERSION),
 379                FSEQ_REG(FSEQ_TOP_CONTENT_VERSION),
 380                FSEQ_REG(FSEQ_ALIVE_TOKEN),
 381                FSEQ_REG(FSEQ_CNVI_ID),
 382                FSEQ_REG(FSEQ_CNVR_ID),
 383                FSEQ_REG(CNVI_AUX_MISC_CHIP),
 384                FSEQ_REG(CNVR_AUX_MISC_CHIP),
 385                FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM),
 386                FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
 387        };
 388
 389        if (!iwl_trans_grab_nic_access(trans))
 390                return;
 391
 392        IWL_ERR(fwrt, "Fseq Registers:\n");
 393
 394        for (i = 0; i < ARRAY_SIZE(fseq_regs); i++)
 395                IWL_ERR(fwrt, "0x%08X | %s\n",
 396                        iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
 397                        fseq_regs[i].str);
 398
 399        iwl_trans_release_nic_access(trans);
 400}
 401
 402void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt)
 403{
 404        if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
 405                IWL_ERR(fwrt,
 406                        "DEVICE_ENABLED bit is not set. Aborting dump.\n");
 407                return;
 408        }
 409
 410        iwl_fwrt_dump_lmac_error_log(fwrt, 0);
 411        if (fwrt->trans->dbg.lmac_error_event_table[1])
 412                iwl_fwrt_dump_lmac_error_log(fwrt, 1);
 413        iwl_fwrt_dump_umac_error_log(fwrt);
 414        iwl_fwrt_dump_tcm_error_log(fwrt);
 415        iwl_fwrt_dump_iml_error_log(fwrt);
 416        iwl_fwrt_dump_fseq_regs(fwrt);
 417}
 418IWL_EXPORT_SYMBOL(iwl_fwrt_dump_error_logs);
 419