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20#include <linux/firmware.h>
21
22#include "decl.h"
23#include "ioctl.h"
24#include "util.h"
25#include "fw.h"
26#include "main.h"
27#include "wmm.h"
28#include "11n.h"
29#include "pcie.h"
30#include "pcie_quirks.h"
31
32#define PCIE_VERSION "1.0"
33#define DRV_NAME "Marvell mwifiex PCIe"
34
35static struct mwifiex_if_ops pcie_ops;
36
37static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
38 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
39 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
40 .cmd_size = PCIE_SCRATCH_2_REG,
41 .fw_status = PCIE_SCRATCH_3_REG,
42 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
43 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
44 .tx_rdptr = PCIE_SCRATCH_6_REG,
45 .tx_wrptr = PCIE_SCRATCH_7_REG,
46 .rx_rdptr = PCIE_SCRATCH_8_REG,
47 .rx_wrptr = PCIE_SCRATCH_9_REG,
48 .evt_rdptr = PCIE_SCRATCH_10_REG,
49 .evt_wrptr = PCIE_SCRATCH_11_REG,
50 .drv_rdy = PCIE_SCRATCH_12_REG,
51 .tx_start_ptr = 0,
52 .tx_mask = MWIFIEX_TXBD_MASK,
53 .tx_wrap_mask = 0,
54 .rx_mask = MWIFIEX_RXBD_MASK,
55 .rx_wrap_mask = 0,
56 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
57 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
58 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
59 .ring_flag_sop = 0,
60 .ring_flag_eop = 0,
61 .ring_flag_xs_sop = 0,
62 .ring_flag_xs_eop = 0,
63 .ring_tx_start_ptr = 0,
64 .pfu_enabled = 0,
65 .sleep_cookie = 1,
66 .msix_support = 0,
67};
68
69static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
70 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
71 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
72 .cmd_size = PCIE_SCRATCH_2_REG,
73 .fw_status = PCIE_SCRATCH_3_REG,
74 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
75 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
76 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
77 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
78 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
79 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
80 .evt_rdptr = PCIE_SCRATCH_10_REG,
81 .evt_wrptr = PCIE_SCRATCH_11_REG,
82 .drv_rdy = PCIE_SCRATCH_12_REG,
83 .tx_start_ptr = 16,
84 .tx_mask = 0x03FF0000,
85 .tx_wrap_mask = 0x07FF0000,
86 .rx_mask = 0x000003FF,
87 .rx_wrap_mask = 0x000007FF,
88 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
89 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
90 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
91 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
92 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
93 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
94 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
95 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
96 .pfu_enabled = 1,
97 .sleep_cookie = 0,
98 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
99 .fw_dump_start = PCIE_SCRATCH_14_REG,
100 .fw_dump_end = 0xcff,
101 .fw_dump_host_ready = 0xee,
102 .fw_dump_read_done = 0xfe,
103 .msix_support = 0,
104};
105
106static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
107 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
108 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
109 .cmd_size = PCIE_SCRATCH_2_REG,
110 .fw_status = PCIE_SCRATCH_3_REG,
111 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
112 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
113 .tx_rdptr = 0xC1A4,
114 .tx_wrptr = 0xC174,
115 .rx_rdptr = 0xC174,
116 .rx_wrptr = 0xC1A4,
117 .evt_rdptr = PCIE_SCRATCH_10_REG,
118 .evt_wrptr = PCIE_SCRATCH_11_REG,
119 .drv_rdy = PCIE_SCRATCH_12_REG,
120 .tx_start_ptr = 16,
121 .tx_mask = 0x0FFF0000,
122 .tx_wrap_mask = 0x1FFF0000,
123 .rx_mask = 0x00000FFF,
124 .rx_wrap_mask = 0x00001FFF,
125 .tx_rollover_ind = BIT(28),
126 .rx_rollover_ind = BIT(12),
127 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
128 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
129 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
130 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
131 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
132 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
133 .pfu_enabled = 1,
134 .sleep_cookie = 0,
135 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
136 .fw_dump_start = PCIE_SCRATCH_14_REG,
137 .fw_dump_end = 0xcff,
138 .fw_dump_host_ready = 0xcc,
139 .fw_dump_read_done = 0xdd,
140 .msix_support = 0,
141};
142
143static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
144 {"ITCM", NULL, 0, 0xF0},
145 {"DTCM", NULL, 0, 0xF1},
146 {"SQRAM", NULL, 0, 0xF2},
147 {"IRAM", NULL, 0, 0xF3},
148 {"APU", NULL, 0, 0xF4},
149 {"CIU", NULL, 0, 0xF5},
150 {"ICU", NULL, 0, 0xF6},
151 {"MAC", NULL, 0, 0xF7},
152};
153
154static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
155 {"DUMP", NULL, 0, 0xDD},
156};
157
158static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
159 .reg = &mwifiex_reg_8766,
160 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
161 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
162 .can_dump_fw = false,
163 .can_ext_scan = true,
164};
165
166static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
167 .reg = &mwifiex_reg_8897,
168 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
169 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
170 .can_dump_fw = true,
171 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
172 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
173 .can_ext_scan = true,
174};
175
176static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
177 .reg = &mwifiex_reg_8997,
178 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
179 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
180 .can_dump_fw = true,
181 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
182 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
183 .can_ext_scan = true,
184};
185
186static const struct of_device_id mwifiex_pcie_of_match_table[] = {
187 { .compatible = "pci11ab,2b42" },
188 { .compatible = "pci1b4b,2b42" },
189 { }
190};
191
192static int mwifiex_pcie_probe_of(struct device *dev)
193{
194 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
195 dev_err(dev, "required compatible string missing\n");
196 return -EINVAL;
197 }
198
199 return 0;
200}
201
202static void mwifiex_pcie_work(struct work_struct *work);
203
204static int
205mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
206 size_t size, int flags)
207{
208 struct pcie_service_card *card = adapter->card;
209 struct mwifiex_dma_mapping mapping;
210
211 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags);
212 if (dma_mapping_error(&card->dev->dev, mapping.addr)) {
213 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
214 return -1;
215 }
216 mapping.len = size;
217 mwifiex_store_mapping(skb, &mapping);
218 return 0;
219}
220
221static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
222 struct sk_buff *skb, int flags)
223{
224 struct pcie_service_card *card = adapter->card;
225 struct mwifiex_dma_mapping mapping;
226
227 mwifiex_get_mapping(skb, &mapping);
228 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags);
229}
230
231
232
233
234static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
235{
236 struct pcie_service_card *card = adapter->card;
237
238 iowrite32(data, card->pci_mmap1 + reg);
239
240 return 0;
241}
242
243
244
245static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
246{
247 struct pcie_service_card *card = adapter->card;
248
249 *data = ioread32(card->pci_mmap1 + reg);
250 if (*data == 0xffffffff)
251 return 0xffffffff;
252
253 return 0;
254}
255
256
257static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
258 int reg, u8 *data)
259{
260 struct pcie_service_card *card = adapter->card;
261
262 *data = ioread8(card->pci_mmap1 + reg);
263
264 return 0;
265}
266
267
268
269
270static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
271{
272 u32 cookie_value;
273 struct pcie_service_card *card = adapter->card;
274 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
275
276 if (!reg->sleep_cookie)
277 return true;
278
279 if (card->sleep_cookie_vbase) {
280 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase);
281 mwifiex_dbg(adapter, INFO,
282 "info: ACCESS_HW: sleep cookie=0x%x\n",
283 cookie_value);
284 if (cookie_value == FW_AWAKE_COOKIE)
285 return true;
286 }
287
288 return false;
289}
290
291#ifdef CONFIG_PM_SLEEP
292
293
294
295
296
297
298
299
300static int mwifiex_pcie_suspend(struct device *dev)
301{
302 struct mwifiex_adapter *adapter;
303 struct pcie_service_card *card = dev_get_drvdata(dev);
304
305
306
307 wait_for_completion(&card->fw_done);
308
309 adapter = card->adapter;
310 if (!adapter) {
311 dev_err(dev, "adapter is not valid\n");
312 return 0;
313 }
314
315 mwifiex_enable_wake(adapter);
316
317
318 if (!mwifiex_enable_hs(adapter)) {
319 mwifiex_dbg(adapter, ERROR,
320 "cmd: failed to suspend\n");
321 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
322 mwifiex_disable_wake(adapter);
323 return -EFAULT;
324 }
325
326 flush_workqueue(adapter->workqueue);
327
328
329 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
330 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
331
332 return 0;
333}
334
335
336
337
338
339
340
341
342
343static int mwifiex_pcie_resume(struct device *dev)
344{
345 struct mwifiex_adapter *adapter;
346 struct pcie_service_card *card = dev_get_drvdata(dev);
347
348
349 if (!card->adapter) {
350 dev_err(dev, "adapter structure is not valid\n");
351 return 0;
352 }
353
354 adapter = card->adapter;
355
356 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
357 mwifiex_dbg(adapter, WARN,
358 "Device already resumed\n");
359 return 0;
360 }
361
362 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
363
364 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
365 MWIFIEX_ASYNC_CMD);
366 mwifiex_disable_wake(adapter);
367
368 return 0;
369}
370#endif
371
372
373
374
375
376
377
378static int mwifiex_pcie_probe(struct pci_dev *pdev,
379 const struct pci_device_id *ent)
380{
381 struct pcie_service_card *card;
382 int ret;
383
384 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
385 pdev->vendor, pdev->device, pdev->revision);
386
387 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
388 if (!card)
389 return -ENOMEM;
390
391 init_completion(&card->fw_done);
392
393 card->dev = pdev;
394
395 if (ent->driver_data) {
396 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
397 card->pcie.reg = data->reg;
398 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
399 card->pcie.tx_buf_size = data->tx_buf_size;
400 card->pcie.can_dump_fw = data->can_dump_fw;
401 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
402 card->pcie.num_mem_types = data->num_mem_types;
403 card->pcie.can_ext_scan = data->can_ext_scan;
404 INIT_WORK(&card->work, mwifiex_pcie_work);
405 }
406
407
408 if (pdev->dev.of_node) {
409 ret = mwifiex_pcie_probe_of(&pdev->dev);
410 if (ret)
411 return ret;
412 }
413
414
415 mwifiex_initialize_quirks(card);
416
417 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops,
418 MWIFIEX_PCIE, &pdev->dev)) {
419 pr_err("%s failed\n", __func__);
420 return -1;
421 }
422
423 return 0;
424}
425
426
427
428
429static void mwifiex_pcie_remove(struct pci_dev *pdev)
430{
431 struct pcie_service_card *card;
432 struct mwifiex_adapter *adapter;
433 struct mwifiex_private *priv;
434 const struct mwifiex_pcie_card_reg *reg;
435 u32 fw_status;
436
437 card = pci_get_drvdata(pdev);
438
439 wait_for_completion(&card->fw_done);
440
441 adapter = card->adapter;
442 if (!adapter || !adapter->priv_num)
443 return;
444
445 reg = card->pcie.reg;
446 if (reg)
447 mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
448 else
449 fw_status = -1;
450
451 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) {
452 mwifiex_deauthenticate_all(adapter);
453
454 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
455
456 mwifiex_disable_auto_ds(priv);
457
458 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
459 }
460
461 mwifiex_remove_card(adapter);
462}
463
464static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
465{
466 mwifiex_pcie_remove(pdev);
467
468 return;
469}
470
471static void mwifiex_pcie_coredump(struct device *dev)
472{
473 struct pci_dev *pdev;
474 struct pcie_service_card *card;
475
476 pdev = container_of(dev, struct pci_dev, dev);
477 card = pci_get_drvdata(pdev);
478
479 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
480 &card->work_flags))
481 schedule_work(&card->work);
482}
483
484static const struct pci_device_id mwifiex_ids[] = {
485 {
486 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
488 .driver_data = (unsigned long)&mwifiex_pcie8766,
489 },
490 {
491 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
493 .driver_data = (unsigned long)&mwifiex_pcie8897,
494 },
495 {
496 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
498 .driver_data = (unsigned long)&mwifiex_pcie8997,
499 },
500 {
501 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
503 .driver_data = (unsigned long)&mwifiex_pcie8997,
504 },
505 {},
506};
507
508MODULE_DEVICE_TABLE(pci, mwifiex_ids);
509
510
511
512
513static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev)
514{
515 struct pcie_service_card *card = pci_get_drvdata(pdev);
516 struct mwifiex_adapter *adapter = card->adapter;
517
518 if (!adapter) {
519 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
520 __func__);
521 return;
522 }
523
524 mwifiex_dbg(adapter, INFO,
525 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n",
526 __func__, pdev->vendor, pdev->device, pdev->revision);
527
528 mwifiex_shutdown_sw(adapter);
529 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
530 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
531
532
533
534
535 if (card->quirks & QUIRK_FW_RST_D3COLD)
536 mwifiex_pcie_reset_d3cold_quirk(pdev);
537
538 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
539
540 card->pci_reset_ongoing = true;
541}
542
543
544
545
546
547
548static void mwifiex_pcie_reset_done(struct pci_dev *pdev)
549{
550 struct pcie_service_card *card = pci_get_drvdata(pdev);
551 struct mwifiex_adapter *adapter = card->adapter;
552 int ret;
553
554 if (!adapter) {
555 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
556 __func__);
557 return;
558 }
559
560 mwifiex_dbg(adapter, INFO,
561 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n",
562 __func__, pdev->vendor, pdev->device, pdev->revision);
563
564 ret = mwifiex_reinit_sw(adapter);
565 if (ret)
566 dev_err(&pdev->dev, "reinit failed: %d\n", ret);
567 else
568 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
569
570 card->pci_reset_ongoing = false;
571}
572
573static const struct pci_error_handlers mwifiex_pcie_err_handler = {
574 .reset_prepare = mwifiex_pcie_reset_prepare,
575 .reset_done = mwifiex_pcie_reset_done,
576};
577
578#ifdef CONFIG_PM_SLEEP
579
580static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
581 mwifiex_pcie_resume);
582#endif
583
584
585static struct pci_driver mwifiex_pcie = {
586 .name = "mwifiex_pcie",
587 .id_table = mwifiex_ids,
588 .probe = mwifiex_pcie_probe,
589 .remove = mwifiex_pcie_remove,
590 .driver = {
591 .coredump = mwifiex_pcie_coredump,
592#ifdef CONFIG_PM_SLEEP
593 .pm = &mwifiex_pcie_pm_ops,
594#endif
595 },
596 .shutdown = mwifiex_pcie_shutdown,
597 .err_handler = &mwifiex_pcie_err_handler,
598};
599
600
601
602
603static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
604{
605 int i = 0;
606
607 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
608 i++;
609 usleep_range(10, 20);
610
611 if (i == 5000)
612 break;
613 }
614
615 return;
616}
617
618static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
619 u32 max_delay_loop_cnt)
620{
621 struct pcie_service_card *card = adapter->card;
622 u8 *buffer;
623 u32 sleep_cookie, count;
624 struct sk_buff *cmdrsp = card->cmdrsp_buf;
625
626 for (count = 0; count < max_delay_loop_cnt; count++) {
627 dma_sync_single_for_cpu(&card->dev->dev,
628 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
629 sizeof(sleep_cookie), DMA_FROM_DEVICE);
630 buffer = cmdrsp->data;
631 sleep_cookie = get_unaligned_le32(buffer);
632
633 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
634 mwifiex_dbg(adapter, INFO,
635 "sleep cookie found at count %d\n", count);
636 break;
637 }
638 dma_sync_single_for_device(&card->dev->dev,
639 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
640 sizeof(sleep_cookie),
641 DMA_FROM_DEVICE);
642 usleep_range(20, 30);
643 }
644
645 if (count >= max_delay_loop_cnt)
646 mwifiex_dbg(adapter, INFO,
647 "max count reached while accessing sleep cookie\n");
648}
649
650
651static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
652{
653 struct pcie_service_card *card = adapter->card;
654 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
655
656 mwifiex_dbg(adapter, EVENT,
657 "event: Wakeup device...\n");
658
659 if (reg->sleep_cookie)
660 mwifiex_pcie_dev_wakeup_delay(adapter);
661
662
663 if (mwifiex_write_reg(adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
664 mwifiex_dbg(adapter, ERROR,
665 "Writing fw_status register failed\n");
666 return -1;
667 }
668
669 if (reg->sleep_cookie) {
670 mwifiex_pcie_dev_wakeup_delay(adapter);
671 mwifiex_dbg(adapter, INFO,
672 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
673 adapter->ps_state = PS_STATE_AWAKE;
674 }
675
676 return 0;
677}
678
679
680
681
682
683
684static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
685{
686 mwifiex_dbg(adapter, CMD,
687 "cmd: Wakeup device completed\n");
688
689 return 0;
690}
691
692
693
694
695
696
697
698static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
699{
700 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
701 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
702 0x00000000)) {
703 mwifiex_dbg(adapter, ERROR,
704 "Disable host interrupt failed\n");
705 return -1;
706 }
707 }
708
709 atomic_set(&adapter->tx_hw_pending, 0);
710 return 0;
711}
712
713static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
714{
715 WARN_ON(mwifiex_pcie_disable_host_int(adapter));
716}
717
718
719
720
721
722
723
724static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
725{
726 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
727
728 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
729 HOST_INTR_MASK)) {
730 mwifiex_dbg(adapter, ERROR,
731 "Enable host interrupt failed\n");
732 return -1;
733 }
734 }
735
736 return 0;
737}
738
739
740
741
742static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
743{
744 struct pcie_service_card *card = adapter->card;
745 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
746 struct mwifiex_pcie_buf_desc *desc;
747 struct mwifiex_pfu_buf_desc *desc2;
748 int i;
749
750 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
751 card->tx_buf_list[i] = NULL;
752 if (reg->pfu_enabled) {
753 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
754 (sizeof(*desc2) * i);
755 desc2 = card->txbd_ring[i];
756 memset(desc2, 0, sizeof(*desc2));
757 } else {
758 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
759 (sizeof(*desc) * i);
760 desc = card->txbd_ring[i];
761 memset(desc, 0, sizeof(*desc));
762 }
763 }
764
765 return 0;
766}
767
768
769
770
771
772static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
773{
774 struct pcie_service_card *card = adapter->card;
775 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
776 struct sk_buff *skb;
777 struct mwifiex_pcie_buf_desc *desc;
778 struct mwifiex_pfu_buf_desc *desc2;
779 dma_addr_t buf_pa;
780 int i;
781
782 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
783
784 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
785 GFP_KERNEL);
786 if (!skb) {
787 mwifiex_dbg(adapter, ERROR,
788 "Unable to allocate skb for RX ring.\n");
789 kfree(card->rxbd_ring_vbase);
790 return -ENOMEM;
791 }
792
793 if (mwifiex_map_pci_memory(adapter, skb,
794 MWIFIEX_RX_DATA_BUF_SIZE,
795 DMA_FROM_DEVICE))
796 return -1;
797
798 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
799
800 mwifiex_dbg(adapter, INFO,
801 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
802 skb, skb->len, skb->data, (u32)buf_pa,
803 (u32)((u64)buf_pa >> 32));
804
805 card->rx_buf_list[i] = skb;
806 if (reg->pfu_enabled) {
807 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
808 (sizeof(*desc2) * i);
809 desc2 = card->rxbd_ring[i];
810 desc2->paddr = buf_pa;
811 desc2->len = (u16)skb->len;
812 desc2->frag_len = (u16)skb->len;
813 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
814 desc2->offset = 0;
815 } else {
816 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
817 (sizeof(*desc) * i));
818 desc = card->rxbd_ring[i];
819 desc->paddr = buf_pa;
820 desc->len = (u16)skb->len;
821 desc->flags = 0;
822 }
823 }
824
825 return 0;
826}
827
828
829
830
831
832static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
833{
834 struct pcie_service_card *card = adapter->card;
835 struct mwifiex_evt_buf_desc *desc;
836 struct sk_buff *skb;
837 dma_addr_t buf_pa;
838 int i;
839
840 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
841
842 skb = dev_alloc_skb(MAX_EVENT_SIZE);
843 if (!skb) {
844 mwifiex_dbg(adapter, ERROR,
845 "Unable to allocate skb for EVENT buf.\n");
846 kfree(card->evtbd_ring_vbase);
847 return -ENOMEM;
848 }
849 skb_put(skb, MAX_EVENT_SIZE);
850
851 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
852 DMA_FROM_DEVICE)) {
853 kfree_skb(skb);
854 kfree(card->evtbd_ring_vbase);
855 return -1;
856 }
857
858 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
859
860 mwifiex_dbg(adapter, EVENT,
861 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
862 skb, skb->len, skb->data, (u32)buf_pa,
863 (u32)((u64)buf_pa >> 32));
864
865 card->evt_buf_list[i] = skb;
866 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
867 (sizeof(*desc) * i));
868 desc = card->evtbd_ring[i];
869 desc->paddr = buf_pa;
870 desc->len = (u16)skb->len;
871 desc->flags = 0;
872 }
873
874 return 0;
875}
876
877
878
879
880static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
881{
882 struct pcie_service_card *card = adapter->card;
883 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
884 struct sk_buff *skb;
885 struct mwifiex_pcie_buf_desc *desc;
886 struct mwifiex_pfu_buf_desc *desc2;
887 int i;
888
889 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
890 if (reg->pfu_enabled) {
891 desc2 = card->txbd_ring[i];
892 if (card->tx_buf_list[i]) {
893 skb = card->tx_buf_list[i];
894 mwifiex_unmap_pci_memory(adapter, skb,
895 DMA_TO_DEVICE);
896 dev_kfree_skb_any(skb);
897 }
898 memset(desc2, 0, sizeof(*desc2));
899 } else {
900 desc = card->txbd_ring[i];
901 if (card->tx_buf_list[i]) {
902 skb = card->tx_buf_list[i];
903 mwifiex_unmap_pci_memory(adapter, skb,
904 DMA_TO_DEVICE);
905 dev_kfree_skb_any(skb);
906 }
907 memset(desc, 0, sizeof(*desc));
908 }
909 card->tx_buf_list[i] = NULL;
910 }
911
912 atomic_set(&adapter->tx_hw_pending, 0);
913 return;
914}
915
916
917
918
919static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
920{
921 struct pcie_service_card *card = adapter->card;
922 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
923 struct mwifiex_pcie_buf_desc *desc;
924 struct mwifiex_pfu_buf_desc *desc2;
925 struct sk_buff *skb;
926 int i;
927
928 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
929 if (reg->pfu_enabled) {
930 desc2 = card->rxbd_ring[i];
931 if (card->rx_buf_list[i]) {
932 skb = card->rx_buf_list[i];
933 mwifiex_unmap_pci_memory(adapter, skb,
934 DMA_FROM_DEVICE);
935 dev_kfree_skb_any(skb);
936 }
937 memset(desc2, 0, sizeof(*desc2));
938 } else {
939 desc = card->rxbd_ring[i];
940 if (card->rx_buf_list[i]) {
941 skb = card->rx_buf_list[i];
942 mwifiex_unmap_pci_memory(adapter, skb,
943 DMA_FROM_DEVICE);
944 dev_kfree_skb_any(skb);
945 }
946 memset(desc, 0, sizeof(*desc));
947 }
948 card->rx_buf_list[i] = NULL;
949 }
950
951 return;
952}
953
954
955
956
957static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
958{
959 struct pcie_service_card *card = adapter->card;
960 struct mwifiex_evt_buf_desc *desc;
961 struct sk_buff *skb;
962 int i;
963
964 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
965 desc = card->evtbd_ring[i];
966 if (card->evt_buf_list[i]) {
967 skb = card->evt_buf_list[i];
968 mwifiex_unmap_pci_memory(adapter, skb,
969 DMA_FROM_DEVICE);
970 dev_kfree_skb_any(skb);
971 }
972 card->evt_buf_list[i] = NULL;
973 memset(desc, 0, sizeof(*desc));
974 }
975
976 return;
977}
978
979
980
981static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
982{
983 struct pcie_service_card *card = adapter->card;
984 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
985
986
987
988
989
990
991 card->txbd_wrptr = 0;
992
993 if (reg->pfu_enabled)
994 card->txbd_rdptr = 0;
995 else
996 card->txbd_rdptr |= reg->tx_rollover_ind;
997
998
999
1000 if (reg->pfu_enabled)
1001 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1002 MWIFIEX_MAX_TXRX_BD;
1003 else
1004 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1005 MWIFIEX_MAX_TXRX_BD;
1006
1007 mwifiex_dbg(adapter, INFO,
1008 "info: txbd_ring: Allocating %d bytes\n",
1009 card->txbd_ring_size);
1010 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1011 card->txbd_ring_size,
1012 &card->txbd_ring_pbase,
1013 GFP_KERNEL);
1014 if (!card->txbd_ring_vbase) {
1015 mwifiex_dbg(adapter, ERROR,
1016 "allocate coherent memory (%d bytes) failed!\n",
1017 card->txbd_ring_size);
1018 return -ENOMEM;
1019 }
1020
1021 mwifiex_dbg(adapter, DATA,
1022 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1023 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase,
1024 (u32)((u64)card->txbd_ring_pbase >> 32),
1025 card->txbd_ring_size);
1026
1027 return mwifiex_init_txq_ring(adapter);
1028}
1029
1030static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
1031{
1032 struct pcie_service_card *card = adapter->card;
1033 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1034
1035 mwifiex_cleanup_txq_ring(adapter);
1036
1037 if (card->txbd_ring_vbase)
1038 dma_free_coherent(&card->dev->dev, card->txbd_ring_size,
1039 card->txbd_ring_vbase,
1040 card->txbd_ring_pbase);
1041 card->txbd_ring_size = 0;
1042 card->txbd_wrptr = 0;
1043 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
1044 card->txbd_ring_vbase = NULL;
1045 card->txbd_ring_pbase = 0;
1046
1047 return 0;
1048}
1049
1050
1051
1052
1053static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
1054{
1055 struct pcie_service_card *card = adapter->card;
1056 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1057
1058
1059
1060
1061
1062
1063 card->rxbd_wrptr = 0;
1064 card->rxbd_rdptr = reg->rx_rollover_ind;
1065
1066 if (reg->pfu_enabled)
1067 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1068 MWIFIEX_MAX_TXRX_BD;
1069 else
1070 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1071 MWIFIEX_MAX_TXRX_BD;
1072
1073 mwifiex_dbg(adapter, INFO,
1074 "info: rxbd_ring: Allocating %d bytes\n",
1075 card->rxbd_ring_size);
1076 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1077 card->rxbd_ring_size,
1078 &card->rxbd_ring_pbase,
1079 GFP_KERNEL);
1080 if (!card->rxbd_ring_vbase) {
1081 mwifiex_dbg(adapter, ERROR,
1082 "allocate coherent memory (%d bytes) failed!\n",
1083 card->rxbd_ring_size);
1084 return -ENOMEM;
1085 }
1086
1087 mwifiex_dbg(adapter, DATA,
1088 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1089 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
1090 (u32)((u64)card->rxbd_ring_pbase >> 32),
1091 card->rxbd_ring_size);
1092
1093 return mwifiex_init_rxq_ring(adapter);
1094}
1095
1096
1097
1098
1099static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
1100{
1101 struct pcie_service_card *card = adapter->card;
1102 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1103
1104 mwifiex_cleanup_rxq_ring(adapter);
1105
1106 if (card->rxbd_ring_vbase)
1107 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size,
1108 card->rxbd_ring_vbase,
1109 card->rxbd_ring_pbase);
1110 card->rxbd_ring_size = 0;
1111 card->rxbd_wrptr = 0;
1112 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
1113 card->rxbd_ring_vbase = NULL;
1114 card->rxbd_ring_pbase = 0;
1115
1116 return 0;
1117}
1118
1119
1120
1121
1122static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
1123{
1124 struct pcie_service_card *card = adapter->card;
1125 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1126
1127
1128
1129
1130
1131
1132 card->evtbd_wrptr = 0;
1133 card->evtbd_rdptr = reg->evt_rollover_ind;
1134
1135 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
1136 MWIFIEX_MAX_EVT_BD;
1137
1138 mwifiex_dbg(adapter, INFO,
1139 "info: evtbd_ring: Allocating %d bytes\n",
1140 card->evtbd_ring_size);
1141 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1142 card->evtbd_ring_size,
1143 &card->evtbd_ring_pbase,
1144 GFP_KERNEL);
1145 if (!card->evtbd_ring_vbase) {
1146 mwifiex_dbg(adapter, ERROR,
1147 "allocate coherent memory (%d bytes) failed!\n",
1148 card->evtbd_ring_size);
1149 return -ENOMEM;
1150 }
1151
1152 mwifiex_dbg(adapter, EVENT,
1153 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
1154 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
1155 (u32)((u64)card->evtbd_ring_pbase >> 32),
1156 card->evtbd_ring_size);
1157
1158 return mwifiex_pcie_init_evt_ring(adapter);
1159}
1160
1161
1162
1163
1164static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
1165{
1166 struct pcie_service_card *card = adapter->card;
1167 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1168
1169 mwifiex_cleanup_evt_ring(adapter);
1170
1171 if (card->evtbd_ring_vbase)
1172 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size,
1173 card->evtbd_ring_vbase,
1174 card->evtbd_ring_pbase);
1175 card->evtbd_wrptr = 0;
1176 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
1177 card->evtbd_ring_size = 0;
1178 card->evtbd_ring_vbase = NULL;
1179 card->evtbd_ring_pbase = 0;
1180
1181 return 0;
1182}
1183
1184
1185
1186
1187static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
1188{
1189 struct pcie_service_card *card = adapter->card;
1190 struct sk_buff *skb;
1191
1192
1193 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1194 if (!skb) {
1195 mwifiex_dbg(adapter, ERROR,
1196 "Unable to allocate skb for command response data.\n");
1197 return -ENOMEM;
1198 }
1199 skb_put(skb, MWIFIEX_UPLD_SIZE);
1200 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1201 DMA_FROM_DEVICE)) {
1202 kfree_skb(skb);
1203 return -1;
1204 }
1205
1206 card->cmdrsp_buf = skb;
1207
1208 return 0;
1209}
1210
1211
1212
1213
1214static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
1215{
1216 struct pcie_service_card *card;
1217
1218 if (!adapter)
1219 return 0;
1220
1221 card = adapter->card;
1222
1223 if (card && card->cmdrsp_buf) {
1224 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
1225 DMA_FROM_DEVICE);
1226 dev_kfree_skb_any(card->cmdrsp_buf);
1227 card->cmdrsp_buf = NULL;
1228 }
1229
1230 if (card && card->cmd_buf) {
1231 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1232 DMA_TO_DEVICE);
1233 dev_kfree_skb_any(card->cmd_buf);
1234 card->cmd_buf = NULL;
1235 }
1236 return 0;
1237}
1238
1239
1240
1241
1242static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1243{
1244 struct pcie_service_card *card = adapter->card;
1245 u32 *cookie;
1246
1247 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev,
1248 sizeof(u32),
1249 &card->sleep_cookie_pbase,
1250 GFP_KERNEL);
1251 if (!card->sleep_cookie_vbase) {
1252 mwifiex_dbg(adapter, ERROR,
1253 "dma_alloc_coherent failed!\n");
1254 return -ENOMEM;
1255 }
1256 cookie = (u32 *)card->sleep_cookie_vbase;
1257
1258 *cookie = FW_AWAKE_COOKIE;
1259
1260 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie);
1261
1262 return 0;
1263}
1264
1265
1266
1267
1268static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1269{
1270 struct pcie_service_card *card;
1271
1272 if (!adapter)
1273 return 0;
1274
1275 card = adapter->card;
1276
1277 if (card && card->sleep_cookie_vbase) {
1278 dma_free_coherent(&card->dev->dev, sizeof(u32),
1279 card->sleep_cookie_vbase,
1280 card->sleep_cookie_pbase);
1281 card->sleep_cookie_vbase = NULL;
1282 }
1283
1284 return 0;
1285}
1286
1287
1288
1289
1290
1291static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1292{
1293 struct pcie_service_card *card = adapter->card;
1294
1295 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
1296 card->txbd_flush = 1;
1297
1298
1299
1300 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1301 CPU_INTR_DNLD_RDY)) {
1302 mwifiex_dbg(adapter, ERROR,
1303 "failed to assert dnld-rdy interrupt.\n");
1304 return -1;
1305 }
1306 }
1307 return 0;
1308}
1309
1310
1311
1312
1313static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
1314{
1315 struct sk_buff *skb;
1316 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
1317 struct mwifiex_pcie_buf_desc *desc;
1318 struct mwifiex_pfu_buf_desc *desc2;
1319 struct pcie_service_card *card = adapter->card;
1320 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1321
1322 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1323 mwifiex_pm_wakeup_card(adapter);
1324
1325
1326 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
1327 mwifiex_dbg(adapter, ERROR,
1328 "SEND COMP: failed to read reg->tx_rdptr\n");
1329 return -1;
1330 }
1331
1332 mwifiex_dbg(adapter, DATA,
1333 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1334 card->txbd_rdptr, rdptr);
1335
1336 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1337
1338 while (((card->txbd_rdptr & reg->tx_mask) !=
1339 (rdptr & reg->tx_mask)) ||
1340 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1341 (rdptr & reg->tx_rollover_ind))) {
1342 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1343 reg->tx_start_ptr;
1344
1345 skb = card->tx_buf_list[wrdoneidx];
1346
1347 if (skb) {
1348 mwifiex_dbg(adapter, DATA,
1349 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1350 skb, wrdoneidx);
1351 mwifiex_unmap_pci_memory(adapter, skb,
1352 DMA_TO_DEVICE);
1353
1354 unmap_count++;
1355
1356 if (card->txbd_flush)
1357 mwifiex_write_data_complete(adapter, skb, 0,
1358 -1);
1359 else
1360 mwifiex_write_data_complete(adapter, skb, 0, 0);
1361 atomic_dec(&adapter->tx_hw_pending);
1362 }
1363
1364 card->tx_buf_list[wrdoneidx] = NULL;
1365
1366 if (reg->pfu_enabled) {
1367 desc2 = card->txbd_ring[wrdoneidx];
1368 memset(desc2, 0, sizeof(*desc2));
1369 } else {
1370 desc = card->txbd_ring[wrdoneidx];
1371 memset(desc, 0, sizeof(*desc));
1372 }
1373 switch (card->dev->device) {
1374 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1375 card->txbd_rdptr++;
1376 break;
1377 case PCIE_DEVICE_ID_MARVELL_88W8897:
1378 case PCIE_DEVICE_ID_MARVELL_88W8997:
1379 card->txbd_rdptr += reg->ring_tx_start_ptr;
1380 break;
1381 }
1382
1383
1384 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
1385 card->txbd_rdptr = ((card->txbd_rdptr &
1386 reg->tx_rollover_ind) ^
1387 reg->tx_rollover_ind);
1388 }
1389
1390 if (unmap_count)
1391 adapter->data_sent = false;
1392
1393 if (card->txbd_flush) {
1394 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
1395 card->txbd_flush = 0;
1396 else
1397 mwifiex_clean_pcie_ring_buf(adapter);
1398 }
1399
1400 return 0;
1401}
1402
1403
1404
1405
1406
1407
1408
1409
1410static int
1411mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1412 struct mwifiex_tx_param *tx_param)
1413{
1414 struct pcie_service_card *card = adapter->card;
1415 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1416 u32 wrindx, num_tx_buffs, rx_val;
1417 int ret;
1418 dma_addr_t buf_pa;
1419 struct mwifiex_pcie_buf_desc *desc = NULL;
1420 struct mwifiex_pfu_buf_desc *desc2 = NULL;
1421
1422 if (!(skb->data && skb->len)) {
1423 mwifiex_dbg(adapter, ERROR,
1424 "%s(): invalid parameter <%p, %#x>\n",
1425 __func__, skb->data, skb->len);
1426 return -1;
1427 }
1428
1429 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1430 mwifiex_pm_wakeup_card(adapter);
1431
1432 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1433 mwifiex_dbg(adapter, DATA,
1434 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
1435 card->txbd_rdptr, card->txbd_wrptr);
1436 if (mwifiex_pcie_txbd_not_full(card)) {
1437 u8 *payload;
1438
1439 adapter->data_sent = true;
1440 payload = skb->data;
1441 put_unaligned_le16((u16)skb->len, payload + 0);
1442 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2);
1443
1444 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
1445 DMA_TO_DEVICE))
1446 return -1;
1447
1448 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
1449 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1450 card->tx_buf_list[wrindx] = skb;
1451 atomic_inc(&adapter->tx_hw_pending);
1452
1453 if (reg->pfu_enabled) {
1454 desc2 = card->txbd_ring[wrindx];
1455 desc2->paddr = buf_pa;
1456 desc2->len = (u16)skb->len;
1457 desc2->frag_len = (u16)skb->len;
1458 desc2->offset = 0;
1459 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1460 MWIFIEX_BD_FLAG_LAST_DESC;
1461 } else {
1462 desc = card->txbd_ring[wrindx];
1463 desc->paddr = buf_pa;
1464 desc->len = (u16)skb->len;
1465 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1466 MWIFIEX_BD_FLAG_LAST_DESC;
1467 }
1468
1469 switch (card->dev->device) {
1470 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1471 card->txbd_wrptr++;
1472 break;
1473 case PCIE_DEVICE_ID_MARVELL_88W8897:
1474 case PCIE_DEVICE_ID_MARVELL_88W8997:
1475 card->txbd_wrptr += reg->ring_tx_start_ptr;
1476 break;
1477 }
1478
1479 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
1480 card->txbd_wrptr = ((card->txbd_wrptr &
1481 reg->tx_rollover_ind) ^
1482 reg->tx_rollover_ind);
1483
1484 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
1485
1486 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
1487 card->txbd_wrptr | rx_val)) {
1488 mwifiex_dbg(adapter, ERROR,
1489 "SEND DATA: failed to write reg->tx_wrptr\n");
1490 ret = -1;
1491 goto done_unmap;
1492 }
1493 if ((mwifiex_pcie_txbd_not_full(card)) &&
1494 tx_param->next_pkt_len) {
1495
1496 mwifiex_dbg(adapter, DATA,
1497 "SEND DATA: delay dnld-rdy interrupt.\n");
1498 adapter->data_sent = false;
1499 } else {
1500
1501 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1502 CPU_INTR_DNLD_RDY)) {
1503 mwifiex_dbg(adapter, ERROR,
1504 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
1505 ret = -1;
1506 goto done_unmap;
1507 }
1508 }
1509 mwifiex_dbg(adapter, DATA,
1510 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1511 "%#x> and sent packet to firmware successfully\n",
1512 card->txbd_rdptr, card->txbd_wrptr);
1513 } else {
1514 mwifiex_dbg(adapter, DATA,
1515 "info: TX Ring full, can't send packets to fw\n");
1516 adapter->data_sent = true;
1517
1518 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1519 CPU_INTR_DNLD_RDY))
1520 mwifiex_dbg(adapter, ERROR,
1521 "SEND DATA: failed to assert door-bell intr\n");
1522 return -EBUSY;
1523 }
1524
1525 return -EINPROGRESS;
1526done_unmap:
1527 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1528 card->tx_buf_list[wrindx] = NULL;
1529 atomic_dec(&adapter->tx_hw_pending);
1530 if (reg->pfu_enabled)
1531 memset(desc2, 0, sizeof(*desc2));
1532 else
1533 memset(desc, 0, sizeof(*desc));
1534
1535 return ret;
1536}
1537
1538
1539
1540
1541
1542static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1543{
1544 struct pcie_service_card *card = adapter->card;
1545 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1546 u32 wrptr, rd_index, tx_val;
1547 dma_addr_t buf_pa;
1548 int ret = 0;
1549 struct sk_buff *skb_tmp = NULL;
1550 struct mwifiex_pcie_buf_desc *desc;
1551 struct mwifiex_pfu_buf_desc *desc2;
1552
1553 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1554 mwifiex_pm_wakeup_card(adapter);
1555
1556
1557 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1558 mwifiex_dbg(adapter, ERROR,
1559 "RECV DATA: failed to read reg->rx_wrptr\n");
1560 ret = -1;
1561 goto done;
1562 }
1563 card->rxbd_wrptr = wrptr;
1564
1565 while (((wrptr & reg->rx_mask) !=
1566 (card->rxbd_rdptr & reg->rx_mask)) ||
1567 ((wrptr & reg->rx_rollover_ind) ==
1568 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
1569 struct sk_buff *skb_data;
1570 u16 rx_len;
1571
1572 rd_index = card->rxbd_rdptr & reg->rx_mask;
1573 skb_data = card->rx_buf_list[rd_index];
1574
1575
1576
1577
1578 if (!skb_data)
1579 return -ENOMEM;
1580
1581 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE);
1582 card->rx_buf_list[rd_index] = NULL;
1583
1584
1585
1586
1587 rx_len = get_unaligned_le16(skb_data->data);
1588 if (WARN_ON(rx_len <= adapter->intf_hdr_len ||
1589 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
1590 mwifiex_dbg(adapter, ERROR,
1591 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1592 rx_len, card->rxbd_rdptr, wrptr);
1593 dev_kfree_skb_any(skb_data);
1594 } else {
1595 skb_put(skb_data, rx_len);
1596 mwifiex_dbg(adapter, DATA,
1597 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1598 card->rxbd_rdptr, wrptr, rx_len);
1599 skb_pull(skb_data, adapter->intf_hdr_len);
1600 if (adapter->rx_work_enabled) {
1601 skb_queue_tail(&adapter->rx_data_q, skb_data);
1602 adapter->data_received = true;
1603 atomic_inc(&adapter->rx_pending);
1604 } else {
1605 mwifiex_handle_rx_packet(adapter, skb_data);
1606 }
1607 }
1608
1609 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
1610 GFP_KERNEL);
1611 if (!skb_tmp) {
1612 mwifiex_dbg(adapter, ERROR,
1613 "Unable to allocate skb.\n");
1614 return -ENOMEM;
1615 }
1616
1617 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1618 MWIFIEX_RX_DATA_BUF_SIZE,
1619 DMA_FROM_DEVICE))
1620 return -1;
1621
1622 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
1623
1624 mwifiex_dbg(adapter, INFO,
1625 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1626 skb_tmp, rd_index);
1627 card->rx_buf_list[rd_index] = skb_tmp;
1628
1629 if (reg->pfu_enabled) {
1630 desc2 = card->rxbd_ring[rd_index];
1631 desc2->paddr = buf_pa;
1632 desc2->len = skb_tmp->len;
1633 desc2->frag_len = skb_tmp->len;
1634 desc2->offset = 0;
1635 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1636 } else {
1637 desc = card->rxbd_ring[rd_index];
1638 desc->paddr = buf_pa;
1639 desc->len = skb_tmp->len;
1640 desc->flags = 0;
1641 }
1642
1643 if ((++card->rxbd_rdptr & reg->rx_mask) ==
1644 MWIFIEX_MAX_TXRX_BD) {
1645 card->rxbd_rdptr = ((card->rxbd_rdptr &
1646 reg->rx_rollover_ind) ^
1647 reg->rx_rollover_ind);
1648 }
1649 mwifiex_dbg(adapter, DATA,
1650 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1651 card->rxbd_rdptr, wrptr);
1652
1653 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
1654
1655 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
1656 card->rxbd_rdptr | tx_val)) {
1657 mwifiex_dbg(adapter, DATA,
1658 "RECV DATA: failed to write reg->rx_rdptr\n");
1659 ret = -1;
1660 goto done;
1661 }
1662
1663
1664 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1665 mwifiex_dbg(adapter, ERROR,
1666 "RECV DATA: failed to read reg->rx_wrptr\n");
1667 ret = -1;
1668 goto done;
1669 }
1670 mwifiex_dbg(adapter, DATA,
1671 "info: RECV DATA: Rcvd packet from fw successfully\n");
1672 card->rxbd_wrptr = wrptr;
1673 }
1674
1675done:
1676 return ret;
1677}
1678
1679
1680
1681
1682static int
1683mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1684{
1685 dma_addr_t buf_pa;
1686 struct pcie_service_card *card = adapter->card;
1687 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1688
1689 if (!(skb->data && skb->len)) {
1690 mwifiex_dbg(adapter, ERROR,
1691 "Invalid parameter in %s <%p. len %d>\n",
1692 __func__, skb->data, skb->len);
1693 return -1;
1694 }
1695
1696 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1697 return -1;
1698
1699 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1700
1701
1702
1703
1704 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
1705 mwifiex_dbg(adapter, ERROR,
1706 "%s: failed to write download command to boot code.\n",
1707 __func__);
1708 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1709 return -1;
1710 }
1711
1712
1713
1714
1715 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1716 (u32)((u64)buf_pa >> 32))) {
1717 mwifiex_dbg(adapter, ERROR,
1718 "%s: failed to write download command to boot code.\n",
1719 __func__);
1720 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1721 return -1;
1722 }
1723
1724
1725 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
1726 mwifiex_dbg(adapter, ERROR,
1727 "%s: failed to write command len to cmd_size scratch reg\n",
1728 __func__);
1729 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1730 return -1;
1731 }
1732
1733
1734 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1735 CPU_INTR_DOOR_BELL)) {
1736 mwifiex_dbg(adapter, ERROR,
1737 "%s: failed to assert door-bell intr\n", __func__);
1738 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1739 return -1;
1740 }
1741
1742 return 0;
1743}
1744
1745
1746
1747
1748static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1749{
1750 struct pcie_service_card *card = adapter->card;
1751 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1752 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
1753
1754
1755 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1756 tx_wrap)) {
1757 mwifiex_dbg(adapter, ERROR,
1758 "RECV DATA: failed to write reg->rx_rdptr\n");
1759 return -1;
1760 }
1761 return 0;
1762}
1763
1764
1765
1766static int
1767mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1768{
1769 struct pcie_service_card *card = adapter->card;
1770 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1771 int ret = 0;
1772 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1773 u8 *payload = (u8 *)skb->data;
1774
1775 if (!(skb->data && skb->len)) {
1776 mwifiex_dbg(adapter, ERROR,
1777 "Invalid parameter in %s <%p, %#x>\n",
1778 __func__, skb->data, skb->len);
1779 return -1;
1780 }
1781
1782
1783 if (!card->cmdrsp_buf) {
1784 mwifiex_dbg(adapter, ERROR,
1785 "No response buffer available, send command failed\n");
1786 return -EBUSY;
1787 }
1788
1789 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1790 mwifiex_pm_wakeup_card(adapter);
1791
1792 adapter->cmd_sent = true;
1793
1794 put_unaligned_le16((u16)skb->len, &payload[0]);
1795 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]);
1796
1797 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1798 return -1;
1799
1800 card->cmd_buf = skb;
1801
1802
1803
1804
1805 skb_get(skb);
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817 if (card->cmdrsp_buf) {
1818 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
1819
1820
1821 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
1822 (u32)cmdrsp_buf_pa)) {
1823 mwifiex_dbg(adapter, ERROR,
1824 "Failed to write download cmd to boot code.\n");
1825 ret = -1;
1826 goto done;
1827 }
1828
1829
1830 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
1831 (u32)((u64)cmdrsp_buf_pa >> 32))) {
1832 mwifiex_dbg(adapter, ERROR,
1833 "Failed to write download cmd to boot code.\n");
1834 ret = -1;
1835 goto done;
1836 }
1837 }
1838
1839 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
1840
1841 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1842 (u32)cmd_buf_pa)) {
1843 mwifiex_dbg(adapter, ERROR,
1844 "Failed to write download cmd to boot code.\n");
1845 ret = -1;
1846 goto done;
1847 }
1848
1849 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1850 (u32)((u64)cmd_buf_pa >> 32))) {
1851 mwifiex_dbg(adapter, ERROR,
1852 "Failed to write download cmd to boot code.\n");
1853 ret = -1;
1854 goto done;
1855 }
1856
1857
1858 if (mwifiex_write_reg(adapter, reg->cmd_size,
1859 card->cmd_buf->len)) {
1860 mwifiex_dbg(adapter, ERROR,
1861 "Failed to write cmd len to reg->cmd_size\n");
1862 ret = -1;
1863 goto done;
1864 }
1865
1866
1867 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1868 CPU_INTR_DOOR_BELL)) {
1869 mwifiex_dbg(adapter, ERROR,
1870 "Failed to assert door-bell intr\n");
1871 ret = -1;
1872 goto done;
1873 }
1874
1875done:
1876 if (ret)
1877 adapter->cmd_sent = false;
1878
1879 return 0;
1880}
1881
1882
1883
1884
1885static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1886{
1887 struct pcie_service_card *card = adapter->card;
1888 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1889 struct sk_buff *skb = card->cmdrsp_buf;
1890 int count = 0;
1891 u16 rx_len;
1892
1893 mwifiex_dbg(adapter, CMD,
1894 "info: Rx CMD Response\n");
1895
1896 if (adapter->curr_cmd)
1897 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE);
1898 else
1899 dma_sync_single_for_cpu(&card->dev->dev,
1900 MWIFIEX_SKB_DMA_ADDR(skb),
1901 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE);
1902
1903
1904 if (card->cmd_buf) {
1905 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1906 DMA_TO_DEVICE);
1907 dev_kfree_skb_any(card->cmd_buf);
1908 card->cmd_buf = NULL;
1909 }
1910
1911 rx_len = get_unaligned_le16(skb->data);
1912 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
1913 skb_trim(skb, rx_len);
1914
1915 if (!adapter->curr_cmd) {
1916 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
1917 dma_sync_single_for_device(&card->dev->dev,
1918 MWIFIEX_SKB_DMA_ADDR(skb),
1919 MWIFIEX_SLEEP_COOKIE_SIZE,
1920 DMA_FROM_DEVICE);
1921 if (mwifiex_write_reg(adapter,
1922 PCIE_CPU_INT_EVENT,
1923 CPU_INTR_SLEEP_CFM_DONE)) {
1924 mwifiex_dbg(adapter, ERROR,
1925 "Write register failed\n");
1926 return -1;
1927 }
1928 mwifiex_delay_for_sleep_cookie(adapter,
1929 MWIFIEX_MAX_DELAY_COUNT);
1930 mwifiex_unmap_pci_memory(adapter, skb,
1931 DMA_FROM_DEVICE);
1932 skb_pull(skb, adapter->intf_hdr_len);
1933 while (reg->sleep_cookie && (count++ < 10) &&
1934 mwifiex_pcie_ok_to_access_hw(adapter))
1935 usleep_range(50, 60);
1936 mwifiex_pcie_enable_host_int(adapter);
1937 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1938 skb->len);
1939 } else {
1940 mwifiex_dbg(adapter, ERROR,
1941 "There is no command but got cmdrsp\n");
1942 }
1943 memcpy(adapter->upld_buf, skb->data,
1944 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
1945 skb_push(skb, adapter->intf_hdr_len);
1946 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1947 DMA_FROM_DEVICE))
1948 return -1;
1949 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
1950 skb_pull(skb, adapter->intf_hdr_len);
1951 adapter->curr_cmd->resp_skb = skb;
1952 adapter->cmd_resp_received = true;
1953
1954
1955 card->cmdrsp_buf = NULL;
1956
1957
1958
1959
1960 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
1961 mwifiex_dbg(adapter, ERROR,
1962 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
1963 return -1;
1964 }
1965
1966
1967 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
1968 mwifiex_dbg(adapter, ERROR,
1969 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
1970 return -1;
1971 }
1972 }
1973
1974 return 0;
1975}
1976
1977
1978
1979
1980static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1981 struct sk_buff *skb)
1982{
1983 struct pcie_service_card *card = adapter->card;
1984
1985 if (skb) {
1986 card->cmdrsp_buf = skb;
1987 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len);
1988 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1989 DMA_FROM_DEVICE))
1990 return -1;
1991 }
1992
1993 return 0;
1994}
1995
1996
1997
1998
1999static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
2000{
2001 struct pcie_service_card *card = adapter->card;
2002 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2003 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2004 u32 wrptr, event;
2005 struct mwifiex_evt_buf_desc *desc;
2006
2007 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2008 mwifiex_pm_wakeup_card(adapter);
2009
2010 if (adapter->event_received) {
2011 mwifiex_dbg(adapter, EVENT,
2012 "info: Event being processed,\t"
2013 "do not process this interrupt just yet\n");
2014 return 0;
2015 }
2016
2017 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2018 mwifiex_dbg(adapter, ERROR,
2019 "info: Invalid read pointer...\n");
2020 return -1;
2021 }
2022
2023
2024 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2025 mwifiex_dbg(adapter, ERROR,
2026 "EventReady: failed to read reg->evt_wrptr\n");
2027 return -1;
2028 }
2029
2030 mwifiex_dbg(adapter, EVENT,
2031 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
2032 card->evtbd_rdptr, wrptr);
2033 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
2034 & MWIFIEX_EVTBD_MASK)) ||
2035 ((wrptr & reg->evt_rollover_ind) ==
2036 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
2037 struct sk_buff *skb_cmd;
2038 __le16 data_len = 0;
2039 u16 evt_len;
2040
2041 mwifiex_dbg(adapter, INFO,
2042 "info: Read Index: %d\n", rdptr);
2043 skb_cmd = card->evt_buf_list[rdptr];
2044 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE);
2045
2046
2047
2048 card->evt_buf_list[rdptr] = NULL;
2049 desc = card->evtbd_ring[rdptr];
2050 memset(desc, 0, sizeof(*desc));
2051
2052 event = get_unaligned_le32(
2053 &skb_cmd->data[adapter->intf_hdr_len]);
2054 adapter->event_cause = event;
2055
2056
2057 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
2058 evt_len = le16_to_cpu(data_len);
2059 skb_trim(skb_cmd, evt_len);
2060 skb_pull(skb_cmd, adapter->intf_hdr_len);
2061 mwifiex_dbg(adapter, EVENT,
2062 "info: Event length: %d\n", evt_len);
2063
2064 if (evt_len > MWIFIEX_EVENT_HEADER_LEN &&
2065 evt_len < MAX_EVENT_SIZE)
2066 memcpy(adapter->event_body, skb_cmd->data +
2067 MWIFIEX_EVENT_HEADER_LEN, evt_len -
2068 MWIFIEX_EVENT_HEADER_LEN);
2069
2070 adapter->event_received = true;
2071 adapter->event_skb = skb_cmd;
2072
2073
2074
2075
2076
2077 } else {
2078 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
2079 CPU_INTR_EVENT_DONE)) {
2080 mwifiex_dbg(adapter, ERROR,
2081 "Write register failed\n");
2082 return -1;
2083 }
2084 }
2085
2086 return 0;
2087}
2088
2089
2090
2091
2092static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
2093 struct sk_buff *skb)
2094{
2095 struct pcie_service_card *card = adapter->card;
2096 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2097 int ret = 0;
2098 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2099 u32 wrptr;
2100 struct mwifiex_evt_buf_desc *desc;
2101
2102 if (!skb)
2103 return 0;
2104
2105 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2106 mwifiex_dbg(adapter, ERROR,
2107 "event_complete: Invalid rdptr 0x%x\n",
2108 rdptr);
2109 return -EINVAL;
2110 }
2111
2112
2113 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2114 mwifiex_dbg(adapter, ERROR,
2115 "event_complete: failed to read reg->evt_wrptr\n");
2116 return -1;
2117 }
2118
2119 if (!card->evt_buf_list[rdptr]) {
2120 skb_push(skb, adapter->intf_hdr_len);
2121 skb_put(skb, MAX_EVENT_SIZE - skb->len);
2122 if (mwifiex_map_pci_memory(adapter, skb,
2123 MAX_EVENT_SIZE,
2124 DMA_FROM_DEVICE))
2125 return -1;
2126 card->evt_buf_list[rdptr] = skb;
2127 desc = card->evtbd_ring[rdptr];
2128 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
2129 desc->len = (u16)skb->len;
2130 desc->flags = 0;
2131 skb = NULL;
2132 } else {
2133 mwifiex_dbg(adapter, ERROR,
2134 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
2135 rdptr, card->evt_buf_list[rdptr], skb);
2136 }
2137
2138 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
2139 card->evtbd_rdptr = ((card->evtbd_rdptr &
2140 reg->evt_rollover_ind) ^
2141 reg->evt_rollover_ind);
2142 }
2143
2144 mwifiex_dbg(adapter, EVENT,
2145 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
2146 card->evtbd_rdptr, wrptr);
2147
2148
2149 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
2150 card->evtbd_rdptr)) {
2151 mwifiex_dbg(adapter, ERROR,
2152 "event_complete: failed to read reg->evt_rdptr\n");
2153 return -1;
2154 }
2155
2156 mwifiex_dbg(adapter, EVENT,
2157 "info: Check Events Again\n");
2158 ret = mwifiex_pcie_process_event_ready(adapter);
2159
2160 return ret;
2161}
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter,
2174 const void *firmware, u32 firmware_len) {
2175 const struct mwifiex_fw_data *fwdata;
2176 u32 offset = 0, data_len, dnld_cmd;
2177 int ret = 0;
2178 bool cmd7_before = false, first_cmd = false;
2179
2180 while (1) {
2181
2182 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) ||
2183 offset + sizeof(fwdata->header) >= firmware_len) {
2184 mwifiex_dbg(adapter, ERROR,
2185 "extract wifi-only fw failure!\n");
2186 ret = -1;
2187 goto done;
2188 }
2189
2190 fwdata = firmware + offset;
2191 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd);
2192 data_len = le32_to_cpu(fwdata->header.data_length);
2193
2194
2195 offset += sizeof(fwdata->header);
2196
2197 switch (dnld_cmd) {
2198 case MWIFIEX_FW_DNLD_CMD_1:
2199 if (offset + data_len < data_len) {
2200 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2201 ret = -1;
2202 goto done;
2203 }
2204
2205
2206 if (!first_cmd) {
2207 mwifiex_dbg(adapter, MSG,
2208 "input wifi-only firmware\n");
2209 return 0;
2210 }
2211
2212 if (!cmd7_before) {
2213 mwifiex_dbg(adapter, ERROR,
2214 "no cmd7 before cmd1!\n");
2215 ret = -1;
2216 goto done;
2217 }
2218 offset += data_len;
2219 break;
2220 case MWIFIEX_FW_DNLD_CMD_5:
2221 first_cmd = true;
2222
2223 if (offset + data_len < data_len) {
2224 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2225 ret = -1;
2226 goto done;
2227 }
2228 offset += data_len;
2229 break;
2230 case MWIFIEX_FW_DNLD_CMD_6:
2231 first_cmd = true;
2232
2233 if (offset + data_len < data_len) {
2234 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2235 ret = -1;
2236 goto done;
2237 }
2238 offset += data_len;
2239 if (offset >= firmware_len) {
2240 mwifiex_dbg(adapter, ERROR,
2241 "extract wifi-only fw failure!\n");
2242 ret = -1;
2243 } else {
2244 ret = offset;
2245 }
2246 goto done;
2247 case MWIFIEX_FW_DNLD_CMD_7:
2248 first_cmd = true;
2249 cmd7_before = true;
2250 break;
2251 default:
2252 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n",
2253 dnld_cmd);
2254 ret = -1;
2255 goto done;
2256 }
2257 }
2258
2259done:
2260 return ret;
2261}
2262
2263
2264
2265
2266
2267
2268
2269
2270static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
2271 struct mwifiex_fw_image *fw)
2272{
2273 int ret;
2274 u8 *firmware = fw->fw_buf;
2275 u32 firmware_len = fw->fw_len;
2276 u32 offset = 0;
2277 struct sk_buff *skb;
2278 u32 txlen, tx_blocks = 0, tries, len, val;
2279 u32 block_retry_cnt = 0;
2280 struct pcie_service_card *card = adapter->card;
2281 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2282
2283 if (!firmware || !firmware_len) {
2284 mwifiex_dbg(adapter, ERROR,
2285 "No firmware image found! Terminating download\n");
2286 return -1;
2287 }
2288
2289 mwifiex_dbg(adapter, INFO,
2290 "info: Downloading FW image (%d bytes)\n",
2291 firmware_len);
2292
2293 if (mwifiex_pcie_disable_host_int(adapter)) {
2294 mwifiex_dbg(adapter, ERROR,
2295 "%s: Disabling interrupts failed.\n", __func__);
2296 return -1;
2297 }
2298
2299 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
2300 if (!skb) {
2301 ret = -ENOMEM;
2302 goto done;
2303 }
2304
2305 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val);
2306 if (ret) {
2307 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n");
2308 goto done;
2309 }
2310
2311
2312 if (val == MWIFIEX_PCIE_FLR_HAPPENS) {
2313 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len);
2314 if (ret < 0) {
2315 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n");
2316 goto done;
2317 }
2318 offset = ret;
2319 mwifiex_dbg(adapter, MSG,
2320 "info: dnld wifi firmware from %d bytes\n", offset);
2321 }
2322
2323
2324 do {
2325 u32 ireg_intr = 0;
2326
2327
2328 if (offset >= firmware_len)
2329 break;
2330
2331 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2332 ret = mwifiex_read_reg(adapter, reg->cmd_size,
2333 &len);
2334 if (ret) {
2335 mwifiex_dbg(adapter, FATAL,
2336 "Failed reading len from boot code\n");
2337 goto done;
2338 }
2339 if (len)
2340 break;
2341 usleep_range(10, 20);
2342 }
2343
2344 if (!len) {
2345 break;
2346 } else if (len > MWIFIEX_UPLD_SIZE) {
2347 mwifiex_dbg(adapter, ERROR,
2348 "FW download failure @ %d, invalid length %d\n",
2349 offset, len);
2350 ret = -1;
2351 goto done;
2352 }
2353
2354 txlen = len;
2355
2356 if (len & BIT(0)) {
2357 block_retry_cnt++;
2358 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
2359 mwifiex_dbg(adapter, ERROR,
2360 "FW download failure @ %d, over max\t"
2361 "retry count\n", offset);
2362 ret = -1;
2363 goto done;
2364 }
2365 mwifiex_dbg(adapter, ERROR,
2366 "FW CRC error indicated by the\t"
2367 "helper: len = 0x%04X, txlen = %d\n",
2368 len, txlen);
2369 len &= ~BIT(0);
2370
2371 txlen = 0;
2372 } else {
2373 block_retry_cnt = 0;
2374
2375
2376 if (firmware_len - offset < txlen)
2377 txlen = firmware_len - offset;
2378
2379 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
2380 card->pcie.blksz_fw_dl;
2381
2382
2383 memmove(skb->data, &firmware[offset], txlen);
2384 }
2385
2386 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
2387 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
2388
2389
2390 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
2391 mwifiex_dbg(adapter, ERROR,
2392 "Failed to send firmware download command\n");
2393 ret = -1;
2394 goto done;
2395 }
2396
2397
2398 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2399 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
2400 &ireg_intr)) {
2401 mwifiex_dbg(adapter, ERROR,
2402 "%s: Failed to read\t"
2403 "interrupt status during fw dnld.\n",
2404 __func__);
2405 mwifiex_unmap_pci_memory(adapter, skb,
2406 DMA_TO_DEVICE);
2407 ret = -1;
2408 goto done;
2409 }
2410 if (!(ireg_intr & CPU_INTR_DOOR_BELL))
2411 break;
2412 usleep_range(10, 20);
2413 }
2414 if (ireg_intr & CPU_INTR_DOOR_BELL) {
2415 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n",
2416 __func__);
2417 mwifiex_unmap_pci_memory(adapter, skb,
2418 DMA_TO_DEVICE);
2419 ret = -1;
2420 goto done;
2421 }
2422
2423 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
2424
2425 offset += txlen;
2426 } while (true);
2427
2428 mwifiex_dbg(adapter, MSG,
2429 "info: FW download over, size %d bytes\n", offset);
2430
2431 ret = 0;
2432
2433done:
2434 dev_kfree_skb_any(skb);
2435 return ret;
2436}
2437
2438
2439
2440
2441static int
2442mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2443{
2444 int ret = 0;
2445 u32 firmware_stat;
2446 struct pcie_service_card *card = adapter->card;
2447 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2448 u32 tries;
2449
2450
2451 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
2452 HOST_INTR_MASK)) {
2453 mwifiex_dbg(adapter, ERROR,
2454 "Write register failed\n");
2455 return -1;
2456 }
2457
2458 mwifiex_dbg(adapter, INFO,
2459 "Setting driver ready signature\n");
2460 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2461 FIRMWARE_READY_PCIE)) {
2462 mwifiex_dbg(adapter, ERROR,
2463 "Failed to write driver ready signature\n");
2464 return -1;
2465 }
2466
2467
2468 for (tries = 0; tries < poll_num; tries++) {
2469 if (mwifiex_read_reg(adapter, reg->fw_status,
2470 &firmware_stat))
2471 ret = -1;
2472 else
2473 ret = 0;
2474
2475 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>",
2476 tries, ret, firmware_stat);
2477
2478 if (ret)
2479 continue;
2480 if (firmware_stat == FIRMWARE_READY_PCIE) {
2481 ret = 0;
2482 break;
2483 } else {
2484 msleep(100);
2485 ret = -1;
2486 }
2487 }
2488
2489 return ret;
2490}
2491
2492
2493
2494static int
2495mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2496{
2497 u32 winner = 0;
2498 int ret = 0;
2499 struct pcie_service_card *card = adapter->card;
2500 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2501
2502 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2503 ret = -1;
2504 } else if (!winner) {
2505 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2506 adapter->winner = 1;
2507 } else {
2508 mwifiex_dbg(adapter, ERROR,
2509 "PCI-E is not the winner <%#x>", winner);
2510 }
2511
2512 return ret;
2513}
2514
2515
2516
2517
2518static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2519 int msg_id)
2520{
2521 u32 pcie_ireg;
2522 unsigned long flags;
2523 struct pcie_service_card *card = adapter->card;
2524
2525 if (card->msi_enable) {
2526 spin_lock_irqsave(&adapter->int_lock, flags);
2527 adapter->int_status = 1;
2528 spin_unlock_irqrestore(&adapter->int_lock, flags);
2529 return;
2530 }
2531
2532 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2533 return;
2534
2535 if (card->msix_enable && msg_id >= 0) {
2536 pcie_ireg = BIT(msg_id);
2537 } else {
2538 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2539 &pcie_ireg)) {
2540 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2541 return;
2542 }
2543
2544 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2545 return;
2546
2547
2548 mwifiex_pcie_disable_host_int(adapter);
2549
2550
2551 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2552 ~pcie_ireg)) {
2553 mwifiex_dbg(adapter, ERROR,
2554 "Write register failed\n");
2555 return;
2556 }
2557 }
2558
2559 if (!adapter->pps_uapsd_mode &&
2560 adapter->ps_state == PS_STATE_SLEEP &&
2561 mwifiex_pcie_ok_to_access_hw(adapter)) {
2562
2563
2564
2565
2566 adapter->ps_state = PS_STATE_AWAKE;
2567 adapter->pm_wakeup_fw_try = false;
2568 del_timer(&adapter->wakeup_timer);
2569 }
2570
2571 spin_lock_irqsave(&adapter->int_lock, flags);
2572 adapter->int_status |= pcie_ireg;
2573 spin_unlock_irqrestore(&adapter->int_lock, flags);
2574 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
2575}
2576
2577
2578
2579
2580
2581
2582
2583static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2584{
2585 struct mwifiex_msix_context *ctx = context;
2586 struct pci_dev *pdev = ctx->dev;
2587 struct pcie_service_card *card;
2588 struct mwifiex_adapter *adapter;
2589
2590 card = pci_get_drvdata(pdev);
2591
2592 if (!card->adapter) {
2593 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2594 card ? card->adapter : NULL);
2595 goto exit;
2596 }
2597 adapter = card->adapter;
2598
2599 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags))
2600 goto exit;
2601
2602 if (card->msix_enable)
2603 mwifiex_interrupt_status(adapter, ctx->msg_id);
2604 else
2605 mwifiex_interrupt_status(adapter, -1);
2606
2607 mwifiex_queue_main_work(adapter);
2608
2609exit:
2610 return IRQ_HANDLED;
2611}
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2627{
2628 int ret;
2629 u32 pcie_ireg = 0;
2630 unsigned long flags;
2631 struct pcie_service_card *card = adapter->card;
2632
2633 spin_lock_irqsave(&adapter->int_lock, flags);
2634 if (!card->msi_enable) {
2635
2636 pcie_ireg = adapter->int_status;
2637 }
2638 adapter->int_status = 0;
2639 spin_unlock_irqrestore(&adapter->int_lock, flags);
2640
2641 if (card->msi_enable) {
2642 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2643 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2644 &pcie_ireg)) {
2645 mwifiex_dbg(adapter, ERROR,
2646 "Read register failed\n");
2647 return -1;
2648 }
2649
2650 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2651 if (mwifiex_write_reg(adapter,
2652 PCIE_HOST_INT_STATUS,
2653 ~pcie_ireg)) {
2654 mwifiex_dbg(adapter, ERROR,
2655 "Write register failed\n");
2656 return -1;
2657 }
2658 if (!adapter->pps_uapsd_mode &&
2659 adapter->ps_state == PS_STATE_SLEEP) {
2660 adapter->ps_state = PS_STATE_AWAKE;
2661 adapter->pm_wakeup_fw_try = false;
2662 del_timer(&adapter->wakeup_timer);
2663 }
2664 }
2665 }
2666 }
2667
2668 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2669 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n");
2670 ret = mwifiex_pcie_send_data_complete(adapter);
2671 if (ret)
2672 return ret;
2673 }
2674 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2675 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n");
2676 ret = mwifiex_pcie_process_recv_data(adapter);
2677 if (ret)
2678 return ret;
2679 }
2680 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2681 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n");
2682 ret = mwifiex_pcie_process_event_ready(adapter);
2683 if (ret)
2684 return ret;
2685 }
2686 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2687 if (adapter->cmd_sent) {
2688 mwifiex_dbg(adapter, INTR,
2689 "info: CMD sent Interrupt\n");
2690 adapter->cmd_sent = false;
2691 }
2692
2693 ret = mwifiex_pcie_process_cmd_complete(adapter);
2694 if (ret)
2695 return ret;
2696 }
2697
2698 mwifiex_dbg(adapter, INTR,
2699 "info: cmd_sent=%d data_sent=%d\n",
2700 adapter->cmd_sent, adapter->data_sent);
2701 if (!card->msi_enable && !card->msix_enable &&
2702 adapter->ps_state != PS_STATE_SLEEP)
2703 mwifiex_pcie_enable_host_int(adapter);
2704
2705 return 0;
2706}
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2719 struct sk_buff *skb,
2720 struct mwifiex_tx_param *tx_param)
2721{
2722 if (!skb) {
2723 mwifiex_dbg(adapter, ERROR,
2724 "Passed NULL skb to %s\n", __func__);
2725 return -1;
2726 }
2727
2728 if (type == MWIFIEX_TYPE_DATA)
2729 return mwifiex_pcie_send_data(adapter, skb, tx_param);
2730 else if (type == MWIFIEX_TYPE_CMD)
2731 return mwifiex_pcie_send_cmd(adapter, skb);
2732
2733 return 0;
2734}
2735
2736
2737
2738static int
2739mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2740{
2741 char *p = drv_buf;
2742 char buf[256], *ptr;
2743 int i;
2744 u32 value;
2745 struct pcie_service_card *card = adapter->card;
2746 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2747 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2748 PCIE_SCRATCH_14_REG,
2749 PCIE_SCRATCH_15_REG};
2750
2751 if (!p)
2752 return 0;
2753
2754 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2755
2756 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2757 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2758 return 0;
2759 }
2760
2761 ptr = buf;
2762 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2763 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2764 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2765 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2766 pcie_scratch_reg[i], value);
2767 }
2768
2769 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2770 p += sprintf(p, "%s\n", buf);
2771
2772 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2773
2774 return p - drv_buf;
2775}
2776
2777
2778static enum rdwr_status
2779mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2780{
2781 int ret, tries;
2782 u8 ctrl_data;
2783 u32 fw_status;
2784 struct pcie_service_card *card = adapter->card;
2785 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2786
2787 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2788 return RDWR_STATUS_FAILURE;
2789
2790 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2791 reg->fw_dump_host_ready);
2792 if (ret) {
2793 mwifiex_dbg(adapter, ERROR,
2794 "PCIE write err\n");
2795 return RDWR_STATUS_FAILURE;
2796 }
2797
2798 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2799 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2800 if (ctrl_data == FW_DUMP_DONE)
2801 return RDWR_STATUS_SUCCESS;
2802 if (doneflag && ctrl_data == doneflag)
2803 return RDWR_STATUS_DONE;
2804 if (ctrl_data != reg->fw_dump_host_ready) {
2805 mwifiex_dbg(adapter, WARN,
2806 "The ctrl reg was changed, re-try again!\n");
2807 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2808 reg->fw_dump_host_ready);
2809 if (ret) {
2810 mwifiex_dbg(adapter, ERROR,
2811 "PCIE write err\n");
2812 return RDWR_STATUS_FAILURE;
2813 }
2814 }
2815 usleep_range(100, 200);
2816 }
2817
2818 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
2819 return RDWR_STATUS_FAILURE;
2820}
2821
2822
2823static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
2824{
2825 struct pcie_service_card *card = adapter->card;
2826 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2827 unsigned int reg, reg_start, reg_end;
2828 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
2829 u8 idx, i, read_reg, doneflag = 0;
2830 enum rdwr_status stat;
2831 u32 memory_size;
2832 int ret;
2833
2834 if (!card->pcie.can_dump_fw)
2835 return;
2836
2837 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2838 struct memory_type_mapping *entry =
2839 &adapter->mem_type_mapping_tbl[idx];
2840
2841 if (entry->mem_ptr) {
2842 vfree(entry->mem_ptr);
2843 entry->mem_ptr = NULL;
2844 }
2845 entry->mem_size = 0;
2846 }
2847
2848 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
2849
2850
2851 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2852 if (stat == RDWR_STATUS_FAILURE)
2853 return;
2854
2855 reg = creg->fw_dump_start;
2856 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2857
2858
2859 if (fw_dump_num == 0)
2860 dump_num = 1;
2861 else
2862 dump_num = fw_dump_num;
2863
2864
2865 for (idx = 0; idx < dump_num; idx++) {
2866 struct memory_type_mapping *entry =
2867 &adapter->mem_type_mapping_tbl[idx];
2868 memory_size = 0;
2869 if (fw_dump_num != 0) {
2870 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2871 if (stat == RDWR_STATUS_FAILURE)
2872 return;
2873
2874 reg = creg->fw_dump_start;
2875 for (i = 0; i < 4; i++) {
2876 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2877 memory_size |= (read_reg << (i * 8));
2878 reg++;
2879 }
2880 } else {
2881 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
2882 }
2883
2884 if (memory_size == 0) {
2885 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
2886 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
2887 creg->fw_dump_read_done);
2888 if (ret) {
2889 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
2890 return;
2891 }
2892 break;
2893 }
2894
2895 mwifiex_dbg(adapter, DUMP,
2896 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
2897 entry->mem_ptr = vmalloc(memory_size + 1);
2898 entry->mem_size = memory_size;
2899 if (!entry->mem_ptr) {
2900 mwifiex_dbg(adapter, ERROR,
2901 "Vmalloc %s failed\n", entry->mem_name);
2902 return;
2903 }
2904 dbg_ptr = entry->mem_ptr;
2905 end_ptr = dbg_ptr + memory_size;
2906
2907 doneflag = entry->done_flag;
2908 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2909 entry->mem_name);
2910
2911 do {
2912 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2913 if (RDWR_STATUS_FAILURE == stat)
2914 return;
2915
2916 reg_start = creg->fw_dump_start;
2917 reg_end = creg->fw_dump_end;
2918 for (reg = reg_start; reg <= reg_end; reg++) {
2919 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
2920 if (dbg_ptr < end_ptr) {
2921 dbg_ptr++;
2922 continue;
2923 }
2924 mwifiex_dbg(adapter, ERROR,
2925 "pre-allocated buf not enough\n");
2926 tmp_ptr =
2927 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2928 if (!tmp_ptr)
2929 return;
2930 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2931 vfree(entry->mem_ptr);
2932 entry->mem_ptr = tmp_ptr;
2933 tmp_ptr = NULL;
2934 dbg_ptr = entry->mem_ptr + memory_size;
2935 memory_size += MWIFIEX_SIZE_4K;
2936 end_ptr = entry->mem_ptr + memory_size;
2937 }
2938
2939 if (stat != RDWR_STATUS_DONE)
2940 continue;
2941
2942 mwifiex_dbg(adapter, DUMP,
2943 "%s done: size=0x%tx\n",
2944 entry->mem_name, dbg_ptr - entry->mem_ptr);
2945 break;
2946 } while (true);
2947 }
2948 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
2949}
2950
2951static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2952{
2953 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE);
2954 if (!adapter->devdump_data) {
2955 mwifiex_dbg(adapter, ERROR,
2956 "vzalloc devdump data failure!\n");
2957 return;
2958 }
2959
2960 mwifiex_drv_info_dump(adapter);
2961 mwifiex_pcie_fw_dump(adapter);
2962 mwifiex_prepare_fw_dump_info(adapter);
2963 mwifiex_upload_device_dump(adapter);
2964}
2965
2966static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter)
2967{
2968 struct pcie_service_card *card = adapter->card;
2969
2970
2971
2972
2973 pci_try_reset_function(card->dev);
2974}
2975
2976static void mwifiex_pcie_work(struct work_struct *work)
2977{
2978 struct pcie_service_card *card =
2979 container_of(work, struct pcie_service_card, work);
2980
2981 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2982 &card->work_flags))
2983 mwifiex_pcie_device_dump_work(card->adapter);
2984 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET,
2985 &card->work_flags))
2986 mwifiex_pcie_card_reset_work(card->adapter);
2987}
2988
2989
2990static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
2991{
2992 struct pcie_service_card *card = adapter->card;
2993
2994 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2995 &card->work_flags))
2996 schedule_work(&card->work);
2997}
2998
2999static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter)
3000{
3001 struct pcie_service_card *card = adapter->card;
3002
3003 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags))
3004 schedule_work(&card->work);
3005}
3006
3007static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter)
3008{
3009 struct pcie_service_card *card = adapter->card;
3010 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3011 int ret;
3012
3013 card->cmdrsp_buf = NULL;
3014 ret = mwifiex_pcie_create_txbd_ring(adapter);
3015 if (ret) {
3016 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n");
3017 goto err_cre_txbd;
3018 }
3019
3020 ret = mwifiex_pcie_create_rxbd_ring(adapter);
3021 if (ret) {
3022 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n");
3023 goto err_cre_rxbd;
3024 }
3025
3026 ret = mwifiex_pcie_create_evtbd_ring(adapter);
3027 if (ret) {
3028 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n");
3029 goto err_cre_evtbd;
3030 }
3031
3032 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
3033 if (ret) {
3034 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n");
3035 goto err_alloc_cmdbuf;
3036 }
3037
3038 if (reg->sleep_cookie) {
3039 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
3040 if (ret) {
3041 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n");
3042 goto err_alloc_cookie;
3043 }
3044 } else {
3045 card->sleep_cookie_vbase = NULL;
3046 }
3047
3048 return 0;
3049
3050err_alloc_cookie:
3051 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3052err_alloc_cmdbuf:
3053 mwifiex_pcie_delete_evtbd_ring(adapter);
3054err_cre_evtbd:
3055 mwifiex_pcie_delete_rxbd_ring(adapter);
3056err_cre_rxbd:
3057 mwifiex_pcie_delete_txbd_ring(adapter);
3058err_cre_txbd:
3059 return ret;
3060}
3061
3062static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter)
3063{
3064 struct pcie_service_card *card = adapter->card;
3065 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3066
3067 if (reg->sleep_cookie)
3068 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
3069
3070 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3071 mwifiex_pcie_delete_evtbd_ring(adapter);
3072 mwifiex_pcie_delete_rxbd_ring(adapter);
3073 mwifiex_pcie_delete_txbd_ring(adapter);
3074}
3075
3076
3077
3078
3079static int mwifiex_init_pcie(struct mwifiex_adapter *adapter)
3080{
3081 struct pcie_service_card *card = adapter->card;
3082 int ret;
3083 struct pci_dev *pdev = card->dev;
3084
3085 pci_set_drvdata(pdev, card);
3086
3087 ret = pci_enable_device(pdev);
3088 if (ret)
3089 goto err_enable_dev;
3090
3091 pci_set_master(pdev);
3092
3093 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3094 if (ret) {
3095 pr_err("dma_set_mask(32) failed: %d\n", ret);
3096 goto err_set_dma_mask;
3097 }
3098
3099 ret = pci_request_region(pdev, 0, DRV_NAME);
3100 if (ret) {
3101 pr_err("req_reg(0) error\n");
3102 goto err_req_region0;
3103 }
3104 card->pci_mmap = pci_iomap(pdev, 0, 0);
3105 if (!card->pci_mmap) {
3106 pr_err("iomap(0) error\n");
3107 ret = -EIO;
3108 goto err_iomap0;
3109 }
3110 ret = pci_request_region(pdev, 2, DRV_NAME);
3111 if (ret) {
3112 pr_err("req_reg(2) error\n");
3113 goto err_req_region2;
3114 }
3115 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
3116 if (!card->pci_mmap1) {
3117 pr_err("iomap(2) error\n");
3118 ret = -EIO;
3119 goto err_iomap2;
3120 }
3121
3122 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n",
3123 card->pci_mmap, card->pci_mmap1);
3124
3125 ret = mwifiex_pcie_alloc_buffers(adapter);
3126 if (ret)
3127 goto err_alloc_buffers;
3128
3129 return 0;
3130
3131err_alloc_buffers:
3132 pci_iounmap(pdev, card->pci_mmap1);
3133err_iomap2:
3134 pci_release_region(pdev, 2);
3135err_req_region2:
3136 pci_iounmap(pdev, card->pci_mmap);
3137err_iomap0:
3138 pci_release_region(pdev, 0);
3139err_req_region0:
3140err_set_dma_mask:
3141 pci_disable_device(pdev);
3142err_enable_dev:
3143 return ret;
3144}
3145
3146
3147
3148
3149static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter)
3150{
3151 struct pcie_service_card *card = adapter->card;
3152 struct pci_dev *pdev = card->dev;
3153 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3154 u32 fw_status;
3155
3156
3157
3158
3159
3160
3161 if (!card->pci_reset_ongoing) {
3162 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n");
3163 cancel_work_sync(&card->work);
3164 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n");
3165 } else {
3166 mwifiex_dbg(adapter, MSG,
3167 "skipped cancel_work_sync() because we're in card reset failure path\n");
3168 }
3169
3170 mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
3171 if (fw_status == FIRMWARE_READY_PCIE) {
3172 mwifiex_dbg(adapter, INFO,
3173 "Clearing driver ready signature\n");
3174 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3175 mwifiex_dbg(adapter, ERROR,
3176 "Failed to write driver not-ready signature\n");
3177 }
3178
3179 pci_disable_device(pdev);
3180
3181 pci_iounmap(pdev, card->pci_mmap);
3182 pci_iounmap(pdev, card->pci_mmap1);
3183 pci_release_region(pdev, 2);
3184 pci_release_region(pdev, 0);
3185
3186 mwifiex_pcie_free_buffers(adapter);
3187}
3188
3189static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
3190{
3191 int ret, i, j;
3192 struct pcie_service_card *card = adapter->card;
3193 struct pci_dev *pdev = card->dev;
3194
3195 if (card->pcie.reg->msix_support) {
3196 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3197 card->msix_entries[i].entry = i;
3198 ret = pci_enable_msix_exact(pdev, card->msix_entries,
3199 MWIFIEX_NUM_MSIX_VECTORS);
3200 if (!ret) {
3201 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
3202 card->msix_ctx[i].dev = pdev;
3203 card->msix_ctx[i].msg_id = i;
3204
3205 ret = request_irq(card->msix_entries[i].vector,
3206 mwifiex_pcie_interrupt, 0,
3207 "MWIFIEX_PCIE_MSIX",
3208 &card->msix_ctx[i]);
3209 if (ret)
3210 break;
3211 }
3212
3213 if (ret) {
3214 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
3215 ret);
3216 for (j = 0; j < i; j++)
3217 free_irq(card->msix_entries[j].vector,
3218 &card->msix_ctx[i]);
3219 pci_disable_msix(pdev);
3220 } else {
3221 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
3222 card->msix_enable = 1;
3223 return 0;
3224 }
3225 }
3226 }
3227
3228 if (pci_enable_msi(pdev) != 0)
3229 pci_disable_msi(pdev);
3230 else
3231 card->msi_enable = 1;
3232
3233 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
3234
3235 card->share_irq_ctx.dev = pdev;
3236 card->share_irq_ctx.msg_id = -1;
3237 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
3238 "MRVL_PCIE", &card->share_irq_ctx);
3239 if (ret) {
3240 pr_err("request_irq failed: ret=%d\n", ret);
3241 return -1;
3242 }
3243
3244 return 0;
3245}
3246
3247
3248
3249
3250
3251
3252static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
3253{
3254 int revision_id = 0;
3255 int version, magic;
3256 struct pcie_service_card *card = adapter->card;
3257
3258 switch (card->dev->device) {
3259 case PCIE_DEVICE_ID_MARVELL_88W8766P:
3260 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
3261 break;
3262 case PCIE_DEVICE_ID_MARVELL_88W8897:
3263 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
3264 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
3265 revision_id &= 0xff00;
3266 switch (revision_id) {
3267 case PCIE8897_A0:
3268 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
3269 break;
3270 case PCIE8897_B0:
3271 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
3272 break;
3273 default:
3274 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
3275
3276 break;
3277 }
3278 break;
3279 case PCIE_DEVICE_ID_MARVELL_88W8997:
3280 mwifiex_read_reg(adapter, 0x8, &revision_id);
3281 mwifiex_read_reg(adapter, 0x0cd0, &version);
3282 mwifiex_read_reg(adapter, 0x0cd4, &magic);
3283 revision_id &= 0xff;
3284 version &= 0x7;
3285 magic &= 0xff;
3286 if (revision_id == PCIE8997_A1 &&
3287 magic == CHIP_MAGIC_VALUE &&
3288 version == CHIP_VER_PCIEUART)
3289 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4);
3290 else
3291 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4);
3292 break;
3293 default:
3294 break;
3295 }
3296}
3297
3298
3299
3300
3301
3302
3303static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
3304{
3305 struct pcie_service_card *card = adapter->card;
3306
3307
3308 card->adapter = adapter;
3309
3310 if (mwifiex_pcie_request_irq(adapter))
3311 return -1;
3312
3313 adapter->tx_buf_size = card->pcie.tx_buf_size;
3314 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
3315 adapter->num_mem_types = card->pcie.num_mem_types;
3316 adapter->ext_scan = card->pcie.can_ext_scan;
3317 mwifiex_pcie_get_fw_name(adapter);
3318
3319 return 0;
3320}
3321
3322
3323
3324
3325
3326
3327
3328static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
3329{
3330 struct pcie_service_card *card = adapter->card;
3331 struct pci_dev *pdev = card->dev;
3332 int i;
3333
3334 if (card->msix_enable) {
3335 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3336 synchronize_irq(card->msix_entries[i].vector);
3337
3338 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3339 free_irq(card->msix_entries[i].vector,
3340 &card->msix_ctx[i]);
3341
3342 card->msix_enable = 0;
3343 pci_disable_msix(pdev);
3344 } else {
3345 mwifiex_dbg(adapter, INFO,
3346 "%s(): calling free_irq()\n", __func__);
3347 free_irq(card->dev->irq, &card->share_irq_ctx);
3348
3349 if (card->msi_enable)
3350 pci_disable_msi(pdev);
3351 }
3352 card->adapter = NULL;
3353}
3354
3355
3356
3357
3358
3359static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter)
3360{
3361 struct pcie_service_card *card = adapter->card;
3362 struct pci_dev *pdev = card->dev;
3363
3364
3365
3366
3367 adapter->tx_buf_size = card->pcie.tx_buf_size;
3368
3369 mwifiex_pcie_alloc_buffers(adapter);
3370
3371 pci_set_master(pdev);
3372}
3373
3374
3375static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter)
3376{
3377 struct pcie_service_card *card = adapter->card;
3378 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3379 struct pci_dev *pdev = card->dev;
3380
3381 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3382 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n");
3383
3384 pci_clear_master(pdev);
3385
3386 adapter->seq_num = 0;
3387
3388 mwifiex_pcie_free_buffers(adapter);
3389}
3390
3391static struct mwifiex_if_ops pcie_ops = {
3392 .init_if = mwifiex_init_pcie,
3393 .cleanup_if = mwifiex_cleanup_pcie,
3394 .check_fw_status = mwifiex_check_fw_status,
3395 .check_winner_status = mwifiex_check_winner_status,
3396 .prog_fw = mwifiex_prog_fw_w_helper,
3397 .register_dev = mwifiex_register_dev,
3398 .unregister_dev = mwifiex_unregister_dev,
3399 .enable_int = mwifiex_pcie_enable_host_int,
3400 .disable_int = mwifiex_pcie_disable_host_int_noerr,
3401 .process_int_status = mwifiex_process_int_status,
3402 .host_to_card = mwifiex_pcie_host_to_card,
3403 .wakeup = mwifiex_pm_wakeup_card,
3404 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
3405
3406
3407 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
3408 .event_complete = mwifiex_pcie_event_complete,
3409 .update_mp_end_port = NULL,
3410 .cleanup_mpa_buf = NULL,
3411 .init_fw_port = mwifiex_pcie_init_fw_port,
3412 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
3413 .card_reset = mwifiex_pcie_card_reset,
3414 .reg_dump = mwifiex_pcie_reg_dump,
3415 .device_dump = mwifiex_pcie_device_dump,
3416 .down_dev = mwifiex_pcie_down_dev,
3417 .up_dev = mwifiex_pcie_up_dev,
3418};
3419
3420module_pci_driver(mwifiex_pcie);
3421
3422MODULE_AUTHOR("Marvell International Ltd.");
3423MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3424MODULE_VERSION(PCIE_VERSION);
3425MODULE_LICENSE("GPL v2");
3426