1/* @file mwifiex_pcie.h 2 * 3 * @brief This file contains definitions for PCI-E interface. 4 * driver. 5 * 6 * Copyright 2011-2020 NXP 7 * 8 * This software file (the "File") is distributed by NXP 9 * under the terms of the GNU General Public License Version 2, June 1991 10 * (the "License"). You may use, redistribute and/or modify this File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 */ 21 22#ifndef _MWIFIEX_PCIE_H 23#define _MWIFIEX_PCIE_H 24 25#include <linux/completion.h> 26#include <linux/pci.h> 27#include <linux/interrupt.h> 28 29#include "decl.h" 30#include "main.h" 31 32#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" 33#define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" 34#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin" 35#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin" 36#define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin" 37#define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin" 38 39#define PCIE_VENDOR_ID_MARVELL (0x11ab) 40#define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b) 41#define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) 42#define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) 43#define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) 44 45#define PCIE8897_A0 0x1100 46#define PCIE8897_B0 0x1200 47#define PCIE8997_A0 0x10 48#define PCIE8997_A1 0x11 49#define CHIP_VER_PCIEUART 0x3 50#define CHIP_MAGIC_VALUE 0x24 51 52/* Constants for Buffer Descriptor (BD) rings */ 53#define MWIFIEX_MAX_TXRX_BD 0x20 54#define MWIFIEX_TXBD_MASK 0x3F 55#define MWIFIEX_RXBD_MASK 0x3F 56 57#define MWIFIEX_MAX_EVT_BD 0x08 58#define MWIFIEX_EVTBD_MASK 0x0f 59 60/* PCIE INTERNAL REGISTERS */ 61#define PCIE_SCRATCH_0_REG 0xC10 62#define PCIE_SCRATCH_1_REG 0xC14 63#define PCIE_CPU_INT_EVENT 0xC18 64#define PCIE_CPU_INT_STATUS 0xC1C 65#define PCIE_HOST_INT_STATUS 0xC30 66#define PCIE_HOST_INT_MASK 0xC34 67#define PCIE_HOST_INT_STATUS_MASK 0xC3C 68#define PCIE_SCRATCH_2_REG 0xC40 69#define PCIE_SCRATCH_3_REG 0xC44 70#define PCIE_SCRATCH_4_REG 0xCD0 71#define PCIE_SCRATCH_5_REG 0xCD4 72#define PCIE_SCRATCH_6_REG 0xCD8 73#define PCIE_SCRATCH_7_REG 0xCDC 74#define PCIE_SCRATCH_8_REG 0xCE0 75#define PCIE_SCRATCH_9_REG 0xCE4 76#define PCIE_SCRATCH_10_REG 0xCE8 77#define PCIE_SCRATCH_11_REG 0xCEC 78#define PCIE_SCRATCH_12_REG 0xCF0 79#define PCIE_SCRATCH_13_REG 0xCF4 80#define PCIE_SCRATCH_14_REG 0xCF8 81#define PCIE_SCRATCH_15_REG 0xCFC 82#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C 83#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C 84 85#define CPU_INTR_DNLD_RDY BIT(0) 86#define CPU_INTR_DOOR_BELL BIT(1) 87#define CPU_INTR_SLEEP_CFM_DONE BIT(2) 88#define CPU_INTR_RESET BIT(3) 89#define CPU_INTR_EVENT_DONE BIT(5) 90 91#define HOST_INTR_DNLD_DONE BIT(0) 92#define HOST_INTR_UPLD_RDY BIT(1) 93#define HOST_INTR_CMD_DONE BIT(2) 94#define HOST_INTR_EVENT_RDY BIT(3) 95#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ 96 HOST_INTR_UPLD_RDY | \ 97 HOST_INTR_CMD_DONE | \ 98 HOST_INTR_EVENT_RDY) 99 100#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) 101#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) 102#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) 103#define MWIFIEX_BD_FLAG_SOP BIT(0) 104#define MWIFIEX_BD_FLAG_EOP BIT(1) 105#define MWIFIEX_BD_FLAG_XS_SOP BIT(2) 106#define MWIFIEX_BD_FLAG_XS_EOP BIT(3) 107#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) 108#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) 109#define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) 110#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) 111 112/* Max retry number of command write */ 113#define MAX_WRITE_IOMEM_RETRY 2 114/* Define PCIE block size for firmware download */ 115#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 116/* FW awake cookie after FW ready */ 117#define FW_AWAKE_COOKIE (0xAA55AA55) 118#define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF 119#define MWIFIEX_SLEEP_COOKIE_SIZE 4 120#define MWIFIEX_MAX_DELAY_COUNT 100 121 122#define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA 123 124struct mwifiex_pcie_card_reg { 125 u16 cmd_addr_lo; 126 u16 cmd_addr_hi; 127 u16 fw_status; 128 u16 cmd_size; 129 u16 cmdrsp_addr_lo; 130 u16 cmdrsp_addr_hi; 131 u16 tx_rdptr; 132 u16 tx_wrptr; 133 u16 rx_rdptr; 134 u16 rx_wrptr; 135 u16 evt_rdptr; 136 u16 evt_wrptr; 137 u16 drv_rdy; 138 u16 tx_start_ptr; 139 u32 tx_mask; 140 u32 tx_wrap_mask; 141 u32 rx_mask; 142 u32 rx_wrap_mask; 143 u32 tx_rollover_ind; 144 u32 rx_rollover_ind; 145 u32 evt_rollover_ind; 146 u8 ring_flag_sop; 147 u8 ring_flag_eop; 148 u8 ring_flag_xs_sop; 149 u8 ring_flag_xs_eop; 150 u32 ring_tx_start_ptr; 151 u8 pfu_enabled; 152 u8 sleep_cookie; 153 u16 fw_dump_ctrl; 154 u16 fw_dump_start; 155 u16 fw_dump_end; 156 u8 fw_dump_host_ready; 157 u8 fw_dump_read_done; 158 u8 msix_support; 159}; 160 161struct mwifiex_pcie_device { 162 const struct mwifiex_pcie_card_reg *reg; 163 u16 blksz_fw_dl; 164 u16 tx_buf_size; 165 bool can_dump_fw; 166 struct memory_type_mapping *mem_type_mapping_tbl; 167 u8 num_mem_types; 168 bool can_ext_scan; 169}; 170 171struct mwifiex_evt_buf_desc { 172 u64 paddr; 173 u16 len; 174 u16 flags; 175} __packed; 176 177struct mwifiex_pcie_buf_desc { 178 u64 paddr; 179 u16 len; 180 u16 flags; 181} __packed; 182 183struct mwifiex_pfu_buf_desc { 184 u16 flags; 185 u16 offset; 186 u16 frag_len; 187 u16 len; 188 u64 paddr; 189 u32 reserved; 190} __packed; 191 192#define MWIFIEX_NUM_MSIX_VECTORS 4 193 194struct mwifiex_msix_context { 195 struct pci_dev *dev; 196 u16 msg_id; 197}; 198 199struct pcie_service_card { 200 struct pci_dev *dev; 201 struct mwifiex_adapter *adapter; 202 struct mwifiex_pcie_device pcie; 203 struct completion fw_done; 204 205 u8 txbd_flush; 206 u32 txbd_wrptr; 207 u32 txbd_rdptr; 208 u32 txbd_ring_size; 209 u8 *txbd_ring_vbase; 210 dma_addr_t txbd_ring_pbase; 211 void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; 212 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; 213 214 u32 rxbd_wrptr; 215 u32 rxbd_rdptr; 216 u32 rxbd_ring_size; 217 u8 *rxbd_ring_vbase; 218 dma_addr_t rxbd_ring_pbase; 219 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; 220 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; 221 222 u32 evtbd_wrptr; 223 u32 evtbd_rdptr; 224 u32 evtbd_ring_size; 225 u8 *evtbd_ring_vbase; 226 dma_addr_t evtbd_ring_pbase; 227 void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; 228 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; 229 230 struct sk_buff *cmd_buf; 231 struct sk_buff *cmdrsp_buf; 232 u8 *sleep_cookie_vbase; 233 dma_addr_t sleep_cookie_pbase; 234 void __iomem *pci_mmap; 235 void __iomem *pci_mmap1; 236 int msi_enable; 237 int msix_enable; 238#ifdef CONFIG_PCI 239 struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; 240#endif 241 struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; 242 struct mwifiex_msix_context share_irq_ctx; 243 struct work_struct work; 244 unsigned long work_flags; 245 246 bool pci_reset_ongoing; 247 unsigned long quirks; 248}; 249 250static inline int 251mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) 252{ 253 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 254 255 switch (card->dev->device) { 256 case PCIE_DEVICE_ID_MARVELL_88W8766P: 257 if (((card->txbd_wrptr & reg->tx_mask) == 258 (rdptr & reg->tx_mask)) && 259 ((card->txbd_wrptr & reg->tx_rollover_ind) != 260 (rdptr & reg->tx_rollover_ind))) 261 return 1; 262 break; 263 case PCIE_DEVICE_ID_MARVELL_88W8897: 264 case PCIE_DEVICE_ID_MARVELL_88W8997: 265 if (((card->txbd_wrptr & reg->tx_mask) == 266 (rdptr & reg->tx_mask)) && 267 ((card->txbd_wrptr & reg->tx_rollover_ind) == 268 (rdptr & reg->tx_rollover_ind))) 269 return 1; 270 break; 271 } 272 273 return 0; 274} 275 276static inline int 277mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) 278{ 279 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 280 281 switch (card->dev->device) { 282 case PCIE_DEVICE_ID_MARVELL_88W8766P: 283 if (((card->txbd_wrptr & reg->tx_mask) != 284 (card->txbd_rdptr & reg->tx_mask)) || 285 ((card->txbd_wrptr & reg->tx_rollover_ind) != 286 (card->txbd_rdptr & reg->tx_rollover_ind))) 287 return 1; 288 break; 289 case PCIE_DEVICE_ID_MARVELL_88W8897: 290 case PCIE_DEVICE_ID_MARVELL_88W8997: 291 if (((card->txbd_wrptr & reg->tx_mask) != 292 (card->txbd_rdptr & reg->tx_mask)) || 293 ((card->txbd_wrptr & reg->tx_rollover_ind) == 294 (card->txbd_rdptr & reg->tx_rollover_ind))) 295 return 1; 296 break; 297 } 298 299 return 0; 300} 301 302#endif /* _MWIFIEX_PCIE_H */ 303