1
2
3
4#ifndef __MT7615_MAC_H
5#define __MT7615_MAC_H
6
7#define MT_CT_PARSE_LEN 72
8#define MT_CT_DMA_BUF_NUM 2
9
10#define MT_RXD0_LENGTH GENMASK(15, 0)
11#define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12#define MT_RXD0_PKT_TYPE GENMASK(31, 29)
13
14#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15#define MT_RXD0_NORMAL_IP_SUM BIT(23)
16#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17#define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18#define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19#define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20#define MT_RXD0_NORMAL_GROUP_4 BIT(28)
21
22enum rx_pkt_type {
23 PKT_TYPE_TXS,
24 PKT_TYPE_TXRXV,
25 PKT_TYPE_NORMAL,
26 PKT_TYPE_RX_DUP_RFB,
27 PKT_TYPE_RX_TMR,
28 PKT_TYPE_RETRIEVE,
29 PKT_TYPE_TXRX_NOTIFY,
30 PKT_TYPE_RX_EVENT,
31 PKT_TYPE_NORMAL_MCU,
32};
33
34#define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
35#define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36#define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
37#define MT_RXD1_MID_AMSDU_FRAME BIT(1)
38#define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39#define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
40#define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
41#define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
42#define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
43#define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
44#define MT_RXD1_NORMAL_BEACON_UC BIT(5)
45#define MT_RXD1_NORMAL_BEACON_MC BIT(4)
46#define MT_RXD1_NORMAL_BF_REPORT BIT(3)
47#define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)
48#define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)
49#define MT_RXD1_NORMAL_MCAST BIT(2)
50#define MT_RXD1_NORMAL_U2M BIT(1)
51#define MT_RXD1_NORMAL_HTC_VLD BIT(0)
52
53#define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
54#define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)
55#define MT_RXD2_NORMAL_NDATA BIT(29)
56#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
57#define MT_RXD2_NORMAL_FRAG BIT(27)
58#define MT_RXD2_NORMAL_INT_FRAME BIT(26)
59#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
60#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
61#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62#define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)
63#define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
64#define MT_RXD2_NORMAL_ICV_ERR BIT(20)
65#define MT_RXD2_NORMAL_CLM BIT(19)
66#define MT_RXD2_NORMAL_CM BIT(18)
67#define MT_RXD2_NORMAL_FCS_ERR BIT(17)
68#define MT_RXD2_NORMAL_SW_BIT BIT(16)
69#define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
70#define MT_RXD2_NORMAL_TID GENMASK(11, 8)
71#define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
72
73#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
74#define MT_RXD3_NORMAL_PF_MODE BIT(29)
75#define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)
76#define MT_RXD3_NORMAL_WOL GENMASK(18, 14)
77#define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)
78#define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)
79#define MT_RXD3_NORMAL_CLS BIT(10)
80#define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
81#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
82#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
83
84#define MT_RXD4_FRAME_CONTROL GENMASK(15, 0)
85
86#define MT_RXD6_SEQ_CTRL GENMASK(15, 0)
87#define MT_RXD6_QOS_CTL GENMASK(31, 16)
88
89#define MT_RXV1_ACID_DET_H BIT(31)
90#define MT_RXV1_ACID_DET_L BIT(30)
91#define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
92#define MT_RXV1_NUM_RX GENMASK(23, 22)
93#define MT_RXV1_HT_NO_SOUND BIT(21)
94#define MT_RXV1_HT_SMOOTH BIT(20)
95#define MT_RXV1_HT_SHORT_GI BIT(19)
96#define MT_RXV1_HT_AGGR BIT(18)
97#define MT_RXV1_VHTA1_B22 BIT(17)
98#define MT_RXV1_FRAME_MODE GENMASK(16, 15)
99#define MT_RXV1_TX_MODE GENMASK(14, 12)
100#define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)
101#define MT_RXV1_HT_AD_CODE BIT(9)
102#define MT_RXV1_HT_STBC GENMASK(8, 7)
103#define MT_RXV1_TX_RATE GENMASK(6, 0)
104
105#define MT_RXV2_SEL_ANT BIT(31)
106#define MT_RXV2_VALID_BIT BIT(30)
107#define MT_RXV2_NSTS GENMASK(29, 27)
108#define MT_RXV2_GROUP_ID GENMASK(26, 21)
109#define MT_RXV2_LENGTH GENMASK(20, 0)
110
111#define MT_RXV3_WB_RSSI GENMASK(31, 24)
112#define MT_RXV3_IB_RSSI GENMASK(23, 16)
113
114#define MT_RXV4_RCPI3 GENMASK(31, 24)
115#define MT_RXV4_RCPI2 GENMASK(23, 16)
116#define MT_RXV4_RCPI1 GENMASK(15, 8)
117#define MT_RXV4_RCPI0 GENMASK(7, 0)
118
119#define MT_RXV5_FOE GENMASK(11, 0)
120
121#define MT_RXV6_NF3 GENMASK(31, 24)
122#define MT_RXV6_NF2 GENMASK(23, 16)
123#define MT_RXV6_NF1 GENMASK(15, 8)
124#define MT_RXV6_NF0 GENMASK(7, 0)
125
126enum tx_header_format {
127 MT_HDR_FORMAT_802_3,
128 MT_HDR_FORMAT_CMD,
129 MT_HDR_FORMAT_802_11,
130 MT_HDR_FORMAT_802_11_EXT,
131};
132
133enum tx_pkt_type {
134 MT_TX_TYPE_CT,
135 MT_TX_TYPE_SF,
136 MT_TX_TYPE_CMD,
137 MT_TX_TYPE_FW,
138};
139
140enum tx_port_idx {
141 MT_TX_PORT_IDX_LMAC,
142 MT_TX_PORT_IDX_MCU
143};
144
145enum tx_mcu_port_q_idx {
146 MT_TX_MCU_PORT_RX_Q0 = 0,
147 MT_TX_MCU_PORT_RX_Q1,
148 MT_TX_MCU_PORT_RX_Q2,
149 MT_TX_MCU_PORT_RX_Q3,
150 MT_TX_MCU_PORT_RX_FWDL = 0x1e
151};
152
153enum tx_phy_bandwidth {
154 MT_PHY_BW_20,
155 MT_PHY_BW_40,
156 MT_PHY_BW_80,
157 MT_PHY_BW_160,
158};
159
160#define MT_CT_INFO_APPLY_TXD BIT(0)
161#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
162#define MT_CT_INFO_MGMT_FRAME BIT(2)
163#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
164#define MT_CT_INFO_HSR2_TX BIT(4)
165
166#define MT_TXD_SIZE (8 * 4)
167
168#define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
169#define MT_USB_HDR_SIZE 4
170#define MT_USB_TAIL_SIZE 4
171
172#define MT_TXD0_P_IDX BIT(31)
173#define MT_TXD0_Q_IDX GENMASK(30, 26)
174#define MT_TXD0_UDP_TCP_SUM BIT(24)
175#define MT_TXD0_IP_SUM BIT(23)
176#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
177#define MT_TXD0_TX_BYTES GENMASK(15, 0)
178
179#define MT_TXD1_OWN_MAC GENMASK(31, 26)
180#define MT_TXD1_PKT_FMT GENMASK(25, 24)
181#define MT_TXD1_TID GENMASK(23, 21)
182#define MT_TXD1_AMSDU BIT(20)
183#define MT_TXD1_UNXV BIT(19)
184#define MT_TXD1_HDR_PAD GENMASK(18, 17)
185#define MT_TXD1_TXD_LEN BIT(16)
186#define MT_TXD1_LONG_FORMAT BIT(15)
187#define MT_TXD1_HDR_FORMAT GENMASK(14, 13)
188#define MT_TXD1_HDR_INFO GENMASK(12, 8)
189#define MT_TXD1_WLAN_IDX GENMASK(7, 0)
190
191#define MT_TXD2_FIX_RATE BIT(31)
192#define MT_TXD2_TIMING_MEASURE BIT(30)
193#define MT_TXD2_BA_DISABLE BIT(29)
194#define MT_TXD2_POWER_OFFSET GENMASK(28, 24)
195#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
196#define MT_TXD2_FRAG GENMASK(15, 14)
197#define MT_TXD2_HTC_VLD BIT(13)
198#define MT_TXD2_DURATION BIT(12)
199#define MT_TXD2_BIP BIT(11)
200#define MT_TXD2_MULTICAST BIT(10)
201#define MT_TXD2_RTS BIT(9)
202#define MT_TXD2_SOUNDING BIT(8)
203#define MT_TXD2_NDPA BIT(7)
204#define MT_TXD2_NDP BIT(6)
205#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
206#define MT_TXD2_SUB_TYPE GENMASK(3, 0)
207
208#define MT_TXD3_SN_VALID BIT(31)
209#define MT_TXD3_PN_VALID BIT(30)
210#define MT_TXD3_SEQ GENMASK(27, 16)
211#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
212#define MT_TXD3_TX_COUNT GENMASK(10, 6)
213#define MT_TXD3_PROTECT_FRAME BIT(1)
214#define MT_TXD3_NO_ACK BIT(0)
215
216#define MT_TXD4_PN_LOW GENMASK(31, 0)
217
218#define MT_TXD5_PN_HIGH GENMASK(31, 16)
219#define MT_TXD5_SW_POWER_MGMT BIT(13)
220#define MT_TXD5_DA_SELECT BIT(11)
221#define MT_TXD5_TX_STATUS_HOST BIT(10)
222#define MT_TXD5_TX_STATUS_MCU BIT(9)
223#define MT_TXD5_TX_STATUS_FMT BIT(8)
224#define MT_TXD5_PID GENMASK(7, 0)
225
226#define MT_TXD6_FIXED_RATE BIT(31)
227#define MT_TXD6_SGI BIT(30)
228#define MT_TXD6_LDPC BIT(29)
229#define MT_TXD6_TX_BF BIT(28)
230#define MT_TXD6_TX_RATE GENMASK(27, 16)
231#define MT_TXD6_ANT_ID GENMASK(15, 4)
232#define MT_TXD6_DYN_BW BIT(3)
233#define MT_TXD6_FIXED_BW BIT(2)
234#define MT_TXD6_BW GENMASK(1, 0)
235
236
237#define MT_TXD7_HW_AMSDU_CAP BIT(30)
238#define MT_TXD7_TYPE GENMASK(21, 20)
239#define MT_TXD7_SUB_TYPE GENMASK(19, 16)
240#define MT_TXD7_SPE_IDX GENMASK(15, 11)
241#define MT_TXD7_SPE_IDX_SLE BIT(10)
242
243#define MT_TXD8_L_TYPE GENMASK(5, 4)
244#define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
245
246#define MT_TX_RATE_STBC BIT(11)
247#define MT_TX_RATE_NSS GENMASK(10, 9)
248#define MT_TX_RATE_MODE GENMASK(8, 6)
249#define MT_TX_RATE_IDX GENMASK(5, 0)
250
251#define MT_TXP_MAX_BUF_NUM 6
252#define MT_HW_TXP_MAX_MSDU_NUM 4
253#define MT_HW_TXP_MAX_BUF_NUM 4
254
255#define MT_MSDU_ID_VALID BIT(15)
256
257#define MT_TXD_LEN_MASK GENMASK(11, 0)
258#define MT_TXD_LEN_MSDU_LAST BIT(14)
259#define MT_TXD_LEN_AMSDU_LAST BIT(15)
260
261#define MT_TXD_LEN_LAST BIT(15)
262
263struct mt7615_txp_ptr {
264 __le32 buf0;
265 __le16 len0;
266 __le16 len1;
267 __le32 buf1;
268} __packed __aligned(4);
269
270struct mt7615_hw_txp {
271 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
272 struct mt7615_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
273} __packed __aligned(4);
274
275struct mt7615_fw_txp {
276 __le16 flags;
277 __le16 token;
278 u8 bss_idx;
279 u8 rept_wds_wcid;
280 u8 rsv;
281 u8 nbuf;
282 __le32 buf[MT_TXP_MAX_BUF_NUM];
283 __le16 len[MT_TXP_MAX_BUF_NUM];
284} __packed __aligned(4);
285
286struct mt7615_txp_common {
287 union {
288 struct mt7615_fw_txp fw;
289 struct mt7615_hw_txp hw;
290 };
291};
292
293struct mt7615_tx_free {
294 __le16 rx_byte_cnt;
295 __le16 ctrl;
296 u8 txd_cnt;
297 u8 rsv[3];
298 __le16 token[];
299} __packed __aligned(4);
300
301#define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)
302
303#define MT_TXS0_PID GENMASK(31, 24)
304#define MT_TXS0_BA_ERROR BIT(22)
305#define MT_TXS0_PS_FLAG BIT(21)
306#define MT_TXS0_TXOP_TIMEOUT BIT(20)
307#define MT_TXS0_BIP_ERROR BIT(19)
308
309#define MT_TXS0_QUEUE_TIMEOUT BIT(18)
310#define MT_TXS0_RTS_TIMEOUT BIT(17)
311#define MT_TXS0_ACK_TIMEOUT BIT(16)
312#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
313
314#define MT_TXS0_TX_STATUS_HOST BIT(15)
315#define MT_TXS0_TX_STATUS_MCU BIT(14)
316#define MT_TXS0_TXS_FORMAT BIT(13)
317#define MT_TXS0_FIXED_RATE BIT(12)
318#define MT_TXS0_TX_RATE GENMASK(11, 0)
319
320#define MT_TXS1_ANT_ID GENMASK(31, 20)
321#define MT_TXS1_RESP_RATE GENMASK(19, 16)
322#define MT_TXS1_BW GENMASK(15, 14)
323#define MT_TXS1_I_TXBF BIT(13)
324#define MT_TXS1_E_TXBF BIT(12)
325#define MT_TXS1_TID GENMASK(11, 9)
326#define MT_TXS1_AMPDU BIT(8)
327#define MT_TXS1_ACKED_MPDU BIT(7)
328#define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)
329
330#define MT_TXS2_WCID GENMASK(31, 24)
331#define MT_TXS2_RXV_SEQNO GENMASK(23, 16)
332#define MT_TXS2_TX_DELAY GENMASK(15, 0)
333
334#define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
335#define MT_TXS3_TX_COUNT GENMASK(28, 24)
336#define MT_TXS3_F1_TSSI1 GENMASK(23, 12)
337#define MT_TXS3_F1_TSSI0 GENMASK(11, 0)
338#define MT_TXS3_F0_SEQNO GENMASK(11, 0)
339
340#define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
341#define MT_TXS4_F1_TSSI3 GENMASK(23, 12)
342#define MT_TXS4_F1_TSSI2 GENMASK(11, 0)
343
344#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
345#define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)
346#define MT_TXS5_F1_NOISE_1 GENMASK(15, 8)
347#define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)
348
349#define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)
350#define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)
351#define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)
352#define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)
353
354struct mt7615_dfs_pulse {
355 u32 max_width;
356 int max_pwr;
357 int min_pwr;
358 u32 min_stgr_pri;
359 u32 max_stgr_pri;
360 u32 min_cr_pri;
361 u32 max_cr_pri;
362};
363
364struct mt7615_dfs_pattern {
365 u8 enb;
366 u8 stgr;
367 u8 min_crpn;
368 u8 max_crpn;
369 u8 min_crpr;
370 u8 min_pw;
371 u8 max_pw;
372 u32 min_pri;
373 u32 max_pri;
374 u8 min_crbn;
375 u8 max_crbn;
376 u8 min_stgpn;
377 u8 max_stgpn;
378 u8 min_stgpr;
379};
380
381struct mt7615_dfs_radar_spec {
382 struct mt7615_dfs_pulse pulse_th;
383 struct mt7615_dfs_pattern radar_pattern[16];
384};
385
386static inline struct mt7615_txp_common *
387mt7615_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
388{
389 u8 *txwi;
390
391 if (!t)
392 return NULL;
393
394 txwi = mt76_get_txwi_ptr(dev, t);
395
396 return (struct mt7615_txp_common *)(txwi + MT_TXD_SIZE);
397}
398
399static inline u32 mt7615_mac_wtbl_addr(struct mt7615_dev *dev, int wcid)
400{
401 return MT_WTBL_BASE(dev) + wcid * MT_WTBL_ENTRY_SIZE;
402}
403
404#endif
405
