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6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/pci.h>
9
10#include "mt76x0.h"
11#include "mcu.h"
12
13static int mt76x0e_start(struct ieee80211_hw *hw)
14{
15 struct mt76x02_dev *dev = hw->priv;
16
17 mt76x02_mac_start(dev);
18 mt76x0_phy_calibrate(dev, true);
19 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mphy.mac_work,
20 MT_MAC_WORK_INTERVAL);
21 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
22 MT_CALIBRATE_INTERVAL);
23 set_bit(MT76_STATE_RUNNING, &dev->mphy.state);
24
25 return 0;
26}
27
28static void mt76x0e_stop_hw(struct mt76x02_dev *dev)
29{
30 cancel_delayed_work_sync(&dev->cal_work);
31 cancel_delayed_work_sync(&dev->mphy.mac_work);
32 clear_bit(MT76_RESTART, &dev->mphy.state);
33
34 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY,
35 0, 1000))
36 dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
37 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
38
39 mt76x0_mac_stop(dev);
40
41 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
42 0, 1000))
43 dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
44 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_EN);
45}
46
47static void mt76x0e_stop(struct ieee80211_hw *hw)
48{
49 struct mt76x02_dev *dev = hw->priv;
50
51 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
52 mt76x0e_stop_hw(dev);
53}
54
55static void
56mt76x0e_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
57 u32 queues, bool drop)
58{
59}
60
61static const struct ieee80211_ops mt76x0e_ops = {
62 .tx = mt76x02_tx,
63 .start = mt76x0e_start,
64 .stop = mt76x0e_stop,
65 .add_interface = mt76x02_add_interface,
66 .remove_interface = mt76x02_remove_interface,
67 .config = mt76x0_config,
68 .configure_filter = mt76x02_configure_filter,
69 .bss_info_changed = mt76x02_bss_info_changed,
70 .sta_state = mt76_sta_state,
71 .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
72 .set_key = mt76x02_set_key,
73 .conf_tx = mt76x02_conf_tx,
74 .sw_scan_start = mt76_sw_scan,
75 .sw_scan_complete = mt76x02_sw_scan_complete,
76 .ampdu_action = mt76x02_ampdu_action,
77 .sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
78 .wake_tx_queue = mt76_wake_tx_queue,
79 .get_survey = mt76_get_survey,
80 .get_txpower = mt76_get_txpower,
81 .flush = mt76x0e_flush,
82 .set_tim = mt76_set_tim,
83 .release_buffered_frames = mt76_release_buffered_frames,
84 .set_coverage_class = mt76x02_set_coverage_class,
85 .set_rts_threshold = mt76x02_set_rts_threshold,
86 .get_antenna = mt76_get_antenna,
87 .reconfig_complete = mt76x02_reconfig_complete,
88};
89
90static int mt76x0e_init_hardware(struct mt76x02_dev *dev, bool resume)
91{
92 int err;
93
94 mt76x0_chip_onoff(dev, true, false);
95 if (!mt76x02_wait_for_mac(&dev->mt76))
96 return -ETIMEDOUT;
97
98 mt76x02_dma_disable(dev);
99 err = mt76x0e_mcu_init(dev);
100 if (err < 0)
101 return err;
102
103 if (!resume) {
104 err = mt76x02_dma_init(dev);
105 if (err < 0)
106 return err;
107 }
108
109 err = mt76x0_init_hardware(dev);
110 if (err < 0)
111 return err;
112
113 mt76x02e_init_beacon_config(dev);
114
115 if (mt76_chip(&dev->mt76) == 0x7610) {
116 u16 val;
117
118 mt76_clear(dev, MT_COEXCFG0, BIT(0));
119
120 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
121 if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT))
122 mt76_set(dev, MT_XO_CTRL7, 0xc03);
123 }
124
125 mt76_clear(dev, 0x110, BIT(9));
126 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13));
127
128 return 0;
129}
130
131static int mt76x0e_register_device(struct mt76x02_dev *dev)
132{
133 int err;
134
135 err = mt76x0e_init_hardware(dev, false);
136 if (err < 0)
137 return err;
138
139 err = mt76x0_register_device(dev);
140 if (err < 0)
141 return err;
142
143 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
144
145 return 0;
146}
147
148static int
149mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
150{
151 static const struct mt76_driver_ops drv_ops = {
152 .txwi_size = sizeof(struct mt76x02_txwi),
153 .drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
154 MT_DRV_SW_RX_AIRTIME,
155 .survey_flags = SURVEY_INFO_TIME_TX,
156 .update_survey = mt76x02_update_channel,
157 .tx_prepare_skb = mt76x02_tx_prepare_skb,
158 .tx_complete_skb = mt76x02_tx_complete_skb,
159 .rx_skb = mt76x02_queue_rx_skb,
160 .rx_poll_complete = mt76x02_rx_poll_complete,
161 .sta_ps = mt76x02_sta_ps,
162 .sta_add = mt76x02_sta_add,
163 .sta_remove = mt76x02_sta_remove,
164 };
165 struct mt76x02_dev *dev;
166 struct mt76_dev *mdev;
167 int ret;
168
169 ret = pcim_enable_device(pdev);
170 if (ret)
171 return ret;
172
173 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
174 if (ret)
175 return ret;
176
177 pci_set_master(pdev);
178
179 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
180 if (ret)
181 return ret;
182
183 mt76_pci_disable_aspm(pdev);
184
185 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt76x0e_ops,
186 &drv_ops);
187 if (!mdev)
188 return -ENOMEM;
189
190 dev = container_of(mdev, struct mt76x02_dev, mt76);
191 mutex_init(&dev->phy_mutex);
192
193 mt76_mmio_init(mdev, pcim_iomap_table(pdev)[0]);
194
195 mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
196 dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
197
198 mt76_wr(dev, MT_INT_MASK_CSR, 0);
199
200 ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
201 IRQF_SHARED, KBUILD_MODNAME, dev);
202 if (ret)
203 goto error;
204
205 ret = mt76x0e_register_device(dev);
206 if (ret < 0)
207 goto error;
208
209 return 0;
210
211error:
212 mt76_free_device(&dev->mt76);
213
214 return ret;
215}
216
217static void mt76x0e_cleanup(struct mt76x02_dev *dev)
218{
219 clear_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
220 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
221 mt76x0_chip_onoff(dev, false, false);
222 mt76x0e_stop_hw(dev);
223 mt76_dma_cleanup(&dev->mt76);
224 mt76x02_mcu_cleanup(dev);
225}
226
227static void
228mt76x0e_remove(struct pci_dev *pdev)
229{
230 struct mt76_dev *mdev = pci_get_drvdata(pdev);
231 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
232
233 mt76_unregister_device(mdev);
234 mt76x0e_cleanup(dev);
235 mt76_free_device(mdev);
236}
237
238#ifdef CONFIG_PM
239static int mt76x0e_suspend(struct pci_dev *pdev, pm_message_t state)
240{
241 struct mt76_dev *mdev = pci_get_drvdata(pdev);
242 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
243 int i;
244
245 mt76_worker_disable(&mdev->tx_worker);
246 for (i = 0; i < ARRAY_SIZE(mdev->phy.q_tx); i++)
247 mt76_queue_tx_cleanup(dev, mdev->phy.q_tx[i], true);
248 for (i = 0; i < ARRAY_SIZE(mdev->q_mcu); i++)
249 mt76_queue_tx_cleanup(dev, mdev->q_mcu[i], true);
250 napi_disable(&mdev->tx_napi);
251
252 mt76_for_each_q_rx(mdev, i)
253 napi_disable(&mdev->napi[i]);
254
255 mt76x02_dma_disable(dev);
256 mt76x02_mcu_cleanup(dev);
257 mt76x0_chip_onoff(dev, false, false);
258
259 pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
260 pci_save_state(pdev);
261
262 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
263}
264
265static int mt76x0e_resume(struct pci_dev *pdev)
266{
267 struct mt76_dev *mdev = pci_get_drvdata(pdev);
268 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
269 int err, i;
270
271 err = pci_set_power_state(pdev, PCI_D0);
272 if (err)
273 return err;
274
275 pci_restore_state(pdev);
276
277 mt76_worker_enable(&mdev->tx_worker);
278
279 mt76_for_each_q_rx(mdev, i) {
280 mt76_queue_rx_reset(dev, i);
281 napi_enable(&mdev->napi[i]);
282 napi_schedule(&mdev->napi[i]);
283 }
284
285 napi_enable(&mdev->tx_napi);
286 napi_schedule(&mdev->tx_napi);
287
288 return mt76x0e_init_hardware(dev, true);
289}
290#endif
291
292static const struct pci_device_id mt76x0e_device_table[] = {
293 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7610) },
294 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7630) },
295 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7650) },
296 { },
297};
298
299MODULE_DEVICE_TABLE(pci, mt76x0e_device_table);
300MODULE_FIRMWARE(MT7610E_FIRMWARE);
301MODULE_FIRMWARE(MT7650E_FIRMWARE);
302MODULE_LICENSE("Dual BSD/GPL");
303
304static struct pci_driver mt76x0e_driver = {
305 .name = KBUILD_MODNAME,
306 .id_table = mt76x0e_device_table,
307 .probe = mt76x0e_probe,
308 .remove = mt76x0e_remove,
309#ifdef CONFIG_PM
310 .suspend = mt76x0e_suspend,
311 .resume = mt76x0e_resume,
312#endif
313};
314
315module_pci_driver(mt76x0e_driver);
316
