1
2
3
4#ifndef __MT7915_MCU_H
5#define __MT7915_MCU_H
6
7struct mt7915_mcu_txd {
8 __le32 txd[8];
9
10 __le16 len;
11 __le16 pq_id;
12
13 u8 cid;
14 u8 pkt_type;
15 u8 set_query;
16 u8 seq;
17
18 u8 uc_d2b0_rev;
19 u8 ext_cid;
20 u8 s2d_index;
21 u8 ext_cid_ack;
22
23 u32 reserved[5];
24} __packed __aligned(4);
25
26
27enum {
28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29 MCU_EVENT_FW_START = 0x01,
30 MCU_EVENT_GENERIC = 0x01,
31 MCU_EVENT_ACCESS_REG = 0x02,
32 MCU_EVENT_MT_PATCH_SEM = 0x04,
33 MCU_EVENT_CH_PRIVILEGE = 0x18,
34 MCU_EVENT_EXT = 0xed,
35 MCU_EVENT_RESTART_DL = 0xef,
36};
37
38
39enum {
40 MCU_EXT_EVENT_PS_SYNC = 0x5,
41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46 MCU_EXT_EVENT_RATE_REPORT = 0x87,
47};
48
49enum {
50 MCU_ATE_SET_TRX = 0x1,
51 MCU_ATE_SET_FREQ_OFFSET = 0xa,
52 MCU_ATE_SET_SLOT_TIME = 0x13,
53 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
54};
55
56struct mt7915_mcu_rxd {
57 __le32 rxd[6];
58
59 __le16 len;
60 __le16 pkt_type_id;
61
62 u8 eid;
63 u8 seq;
64 __le16 __rsv;
65
66 u8 ext_eid;
67 u8 __rsv1[2];
68 u8 s2d_index;
69};
70
71struct mt7915_mcu_thermal_ctrl {
72 u8 ctrl_id;
73 u8 band_idx;
74 union {
75 struct {
76 u8 protect_type;
77 u8 trigger_type;
78 } __packed type;
79 struct {
80 u8 duty_level;
81 u8 duty_cycle;
82 } __packed duty;
83 };
84} __packed;
85
86struct mt7915_mcu_thermal_notify {
87 struct mt7915_mcu_rxd rxd;
88
89 struct mt7915_mcu_thermal_ctrl ctrl;
90 __le32 temperature;
91 u8 rsv[8];
92} __packed;
93
94struct mt7915_mcu_csa_notify {
95 struct mt7915_mcu_rxd rxd;
96
97 u8 omac_idx;
98 u8 csa_count;
99 u8 band_idx;
100 u8 rsv;
101} __packed;
102
103struct mt7915_mcu_rdd_report {
104 struct mt7915_mcu_rxd rxd;
105
106 u8 band_idx;
107 u8 long_detected;
108 u8 constant_prf_detected;
109 u8 staggered_prf_detected;
110 u8 radar_type_idx;
111 u8 periodic_pulse_num;
112 u8 long_pulse_num;
113 u8 hw_pulse_num;
114
115 u8 out_lpn;
116 u8 out_spn;
117 u8 out_crpn;
118 u8 out_crpw;
119 u8 out_crbn;
120 u8 out_stgpn;
121 u8 out_stgpw;
122
123 u8 rsv;
124
125 __le32 out_pri_const;
126 __le32 out_pri_stg[3];
127
128 struct {
129 __le32 start;
130 __le16 pulse_width;
131 __le16 pulse_power;
132 u8 mdrdy_flag;
133 u8 rsv[3];
134 } long_pulse[32];
135
136 struct {
137 __le32 start;
138 __le16 pulse_width;
139 __le16 pulse_power;
140 u8 mdrdy_flag;
141 u8 rsv[3];
142 } periodic_pulse[32];
143
144 struct {
145 __le32 start;
146 __le16 pulse_width;
147 __le16 pulse_power;
148 u8 sc_pass;
149 u8 sw_reset;
150 u8 mdrdy_flag;
151 u8 tx_active;
152 } hw_pulse[32];
153} __packed;
154
155struct mt7915_mcu_eeprom {
156 u8 buffer_mode;
157 u8 format;
158 __le16 len;
159} __packed;
160
161struct mt7915_mcu_eeprom_info {
162 __le32 addr;
163 __le32 valid;
164 u8 data[16];
165} __packed;
166
167struct mt7915_mcu_ra_info {
168 struct mt7915_mcu_rxd rxd;
169
170 __le32 event_id;
171 __le16 wlan_idx;
172 __le16 ru_idx;
173 __le16 direction;
174 __le16 dump_group;
175
176 __le32 suggest_rate;
177 __le32 min_rate;
178 __le32 max_rate;
179 __le32 init_rate_down_rate;
180
181 __le16 curr_rate;
182 __le16 init_rate_down_total;
183 __le16 init_rate_down_succ;
184 __le16 success;
185 __le16 attempts;
186
187 __le16 prev_rate;
188 __le16 prob_up_rate;
189 u8 no_rate_up_cnt;
190 u8 ppdu_cnt;
191 u8 gi;
192
193 u8 try_up_fail;
194 u8 try_up_total;
195 u8 suggest_wf;
196 u8 try_up_check;
197 u8 prob_up_period;
198 u8 prob_down_pending;
199} __packed;
200
201
202struct mt7915_mcu_phy_rx_info {
203 u8 category;
204 u8 rate;
205 u8 mode;
206 u8 nsts;
207 u8 gi;
208 u8 coding;
209 u8 stbc;
210 u8 bw;
211};
212
213#define MT_RA_RATE_NSS GENMASK(8, 6)
214#define MT_RA_RATE_MCS GENMASK(3, 0)
215#define MT_RA_RATE_TX_MODE GENMASK(12, 9)
216#define MT_RA_RATE_DCM_EN BIT(4)
217#define MT_RA_RATE_BW GENMASK(14, 13)
218
219struct mt7915_mcu_mib {
220 __le32 band;
221 __le32 offs;
222 __le64 data;
223} __packed;
224
225enum mt7915_chan_mib_offs {
226 MIB_BUSY_TIME = 14,
227 MIB_TX_TIME = 81,
228 MIB_RX_TIME,
229 MIB_OBSS_AIRTIME = 86
230};
231
232struct edca {
233 u8 queue;
234 u8 set;
235 u8 aifs;
236 u8 cw_min;
237 __le16 cw_max;
238 __le16 txop;
239};
240
241struct mt7915_mcu_tx {
242 u8 total;
243 u8 action;
244 u8 valid;
245 u8 mode;
246
247 struct edca edca[IEEE80211_NUM_ACS];
248} __packed;
249
250#define WMM_AIFS_SET BIT(0)
251#define WMM_CW_MIN_SET BIT(1)
252#define WMM_CW_MAX_SET BIT(2)
253#define WMM_TXOP_SET BIT(3)
254#define WMM_PARAM_SET GENMASK(3, 0)
255
256#define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
257#define MCU_PKT_ID 0xa0
258
259enum {
260 MCU_Q_QUERY,
261 MCU_Q_SET,
262 MCU_Q_RESERVED,
263 MCU_Q_NA
264};
265
266enum {
267 MCU_S2D_H2N,
268 MCU_S2D_C2N,
269 MCU_S2D_H2C,
270 MCU_S2D_H2CN
271};
272
273
274#define __MCU_CMD_FIELD_ID GENMASK(7, 0)
275#define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
276#define __MCU_CMD_FIELD_QUERY BIT(16)
277#define __MCU_CMD_FIELD_WA BIT(17)
278
279enum {
280 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
281 MCU_CMD_FW_START_REQ = 0x02,
282 MCU_CMD_INIT_ACCESS_REG = 0x3,
283 MCU_CMD_NIC_POWER_CTRL = 0x4,
284 MCU_CMD_PATCH_START_REQ = 0x05,
285 MCU_CMD_PATCH_FINISH_REQ = 0x07,
286 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
287 MCU_CMD_WA_PARAM = 0xC4,
288 MCU_CMD_EXT_CID = 0xED,
289 MCU_CMD_FW_SCATTER = 0xEE,
290 MCU_CMD_RESTART_DL_REQ = 0xEF,
291};
292
293enum {
294 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
295 MCU_EXT_CMD_RF_TEST = 0x04,
296 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
297 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
298 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
299 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
300 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
301 MCU_EXT_CMD_THERMAL_PROT = 0x23,
302 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
303 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
304 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
305 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
306 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
307 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
308 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
309 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
310 MCU_EXT_CMD_ATE_CTRL = 0x3d,
311 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
312 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
313 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
314 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
315 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
316 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
317 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
318 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
319 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
320 MCU_EXT_CMD_SCS_CTRL = 0x82,
321 MCU_EXT_CMD_RATE_CTRL = 0x87,
322 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
323 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
324 MCU_EXT_CMD_SET_SPR = 0xa8,
325 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
326 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
327 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
328};
329
330enum {
331 MCU_WA_PARAM_CMD_QUERY,
332 MCU_WA_PARAM_CMD_SET,
333 MCU_WA_PARAM_CMD_CAPABILITY,
334 MCU_WA_PARAM_CMD_DEBUG,
335};
336
337enum {
338 MCU_WA_PARAM_RED = 0x0e,
339};
340
341#define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t)
342#define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
343 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
344 MCU_EXT_CMD_##_t))
345#define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
346
347#define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
348#define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
349#define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
350 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
351 MCU_WA_PARAM_CMD_##_t))
352
353enum {
354 PATCH_SEM_RELEASE,
355 PATCH_SEM_GET
356};
357
358enum {
359 PATCH_NOT_DL_SEM_FAIL,
360 PATCH_IS_DL,
361 PATCH_NOT_DL_SEM_SUCCESS,
362 PATCH_REL_SEM_SUCCESS
363};
364
365enum {
366 FW_STATE_INITIAL,
367 FW_STATE_FW_DOWNLOAD,
368 FW_STATE_NORMAL_OPERATION,
369 FW_STATE_NORMAL_TRX,
370 FW_STATE_WACPU_RDY = 7
371};
372
373enum {
374 EE_MODE_EFUSE,
375 EE_MODE_BUFFER,
376};
377
378enum {
379 EE_FORMAT_BIN,
380 EE_FORMAT_WHOLE,
381 EE_FORMAT_MULTIPLE,
382};
383
384enum {
385 MCU_PHY_STATE_TX_RATE,
386 MCU_PHY_STATE_RX_RATE,
387 MCU_PHY_STATE_RSSI,
388 MCU_PHY_STATE_CONTENTION_RX_RATE,
389 MCU_PHY_STATE_OFDMLQ_CNINFO,
390};
391
392#define STA_TYPE_STA BIT(0)
393#define STA_TYPE_AP BIT(1)
394#define STA_TYPE_ADHOC BIT(2)
395#define STA_TYPE_WDS BIT(4)
396#define STA_TYPE_BC BIT(5)
397
398#define NETWORK_INFRA BIT(16)
399#define NETWORK_P2P BIT(17)
400#define NETWORK_IBSS BIT(18)
401#define NETWORK_WDS BIT(21)
402
403#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
404#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
405#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
406#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
407#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
408#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
409#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
410
411#define CONN_STATE_DISCONNECT 0
412#define CONN_STATE_CONNECT 1
413#define CONN_STATE_PORT_SECURE 2
414
415enum {
416 DEV_INFO_ACTIVE,
417 DEV_INFO_MAX_NUM
418};
419
420enum {
421 SCS_SEND_DATA,
422 SCS_SET_MANUAL_PD_TH,
423 SCS_CONFIG,
424 SCS_ENABLE,
425 SCS_SHOW_INFO,
426 SCS_GET_GLO_ADDR,
427 SCS_GET_GLO_ADDR_EVENT,
428};
429
430enum {
431 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
432 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
433 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
434 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
435 CMD_CBW_10MHZ,
436 CMD_CBW_5MHZ,
437 CMD_CBW_8080MHZ,
438
439 CMD_HE_MCS_BW80 = 0,
440 CMD_HE_MCS_BW160,
441 CMD_HE_MCS_BW8080,
442 CMD_HE_MCS_BW_NUM
443};
444
445struct tlv {
446 __le16 tag;
447 __le16 len;
448} __packed;
449
450struct bss_info_omac {
451 __le16 tag;
452 __le16 len;
453 u8 hw_bss_idx;
454 u8 omac_idx;
455 u8 band_idx;
456 u8 rsv0;
457 __le32 conn_type;
458 u32 rsv1;
459} __packed;
460
461struct bss_info_basic {
462 __le16 tag;
463 __le16 len;
464 __le32 network_type;
465 u8 active;
466 u8 rsv0;
467 __le16 bcn_interval;
468 u8 bssid[ETH_ALEN];
469 u8 wmm_idx;
470 u8 dtim_period;
471 u8 bmc_wcid_lo;
472 u8 cipher;
473 u8 phy_mode;
474 u8 max_bssid;
475 u8 non_tx_bssid;
476 u8 bmc_wcid_hi;
477 u8 rsv[2];
478} __packed;
479
480struct bss_info_rf_ch {
481 __le16 tag;
482 __le16 len;
483 u8 pri_ch;
484 u8 center_ch0;
485 u8 center_ch1;
486 u8 bw;
487 u8 he_ru26_block;
488 u8 he_all_disable;
489 u8 rsv[2];
490} __packed;
491
492struct bss_info_ext_bss {
493 __le16 tag;
494 __le16 len;
495 __le32 mbss_tsf_offset;
496 u8 rsv[8];
497} __packed;
498
499struct bss_info_bmc_rate {
500 __le16 tag;
501 __le16 len;
502 __le16 bc_trans;
503 __le16 mc_trans;
504 u8 short_preamble;
505 u8 rsv[7];
506} __packed;
507
508struct bss_info_ra {
509 __le16 tag;
510 __le16 len;
511 u8 op_mode;
512 u8 adhoc_en;
513 u8 short_preamble;
514 u8 tx_streams;
515 u8 rx_streams;
516 u8 algo;
517 u8 force_sgi;
518 u8 force_gf;
519 u8 ht_mode;
520 u8 has_20_sta;
521 u8 bss_width_trigger_events;
522 u8 vht_nss_cap;
523 u8 vht_bw_signal;
524 u8 vht_force_sgi;
525 u8 se_off;
526 u8 antenna_idx;
527 u8 train_up_rule;
528 u8 rsv[3];
529 unsigned short train_up_high_thres;
530 short train_up_rule_rssi;
531 unsigned short low_traffic_thres;
532 __le16 max_phyrate;
533 __le32 phy_cap;
534 __le32 interval;
535 __le32 fast_interval;
536} __packed;
537
538struct bss_info_hw_amsdu {
539 __le16 tag;
540 __le16 len;
541 __le32 cmp_bitmap_0;
542 __le32 cmp_bitmap_1;
543 __le16 trig_thres;
544 u8 enable;
545 u8 rsv;
546} __packed;
547
548struct bss_info_he {
549 __le16 tag;
550 __le16 len;
551 u8 he_pe_duration;
552 u8 vht_op_info_present;
553 __le16 he_rts_thres;
554 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
555 u8 rsv[6];
556} __packed;
557
558struct bss_info_bcn {
559 __le16 tag;
560 __le16 len;
561 u8 ver;
562 u8 enable;
563 __le16 sub_ntlv;
564} __packed __aligned(4);
565
566struct bss_info_bcn_csa {
567 __le16 tag;
568 __le16 len;
569 u8 cnt;
570 u8 rsv[3];
571} __packed __aligned(4);
572
573struct bss_info_bcn_bcc {
574 __le16 tag;
575 __le16 len;
576 u8 cnt;
577 u8 rsv[3];
578} __packed __aligned(4);
579
580struct bss_info_bcn_mbss {
581#define MAX_BEACON_NUM 32
582 __le16 tag;
583 __le16 len;
584 __le32 bitmap;
585 __le16 offset[MAX_BEACON_NUM];
586 u8 rsv[8];
587} __packed __aligned(4);
588
589struct bss_info_bcn_cont {
590 __le16 tag;
591 __le16 len;
592 __le16 tim_ofs;
593 __le16 csa_ofs;
594 __le16 bcc_ofs;
595 __le16 pkt_len;
596} __packed __aligned(4);
597
598enum {
599 BSS_INFO_BCN_CSA,
600 BSS_INFO_BCN_BCC,
601 BSS_INFO_BCN_MBSSID,
602 BSS_INFO_BCN_CONTENT,
603 BSS_INFO_BCN_MAX
604};
605
606enum {
607 BSS_INFO_OMAC,
608 BSS_INFO_BASIC,
609 BSS_INFO_RF_CH,
610 BSS_INFO_PM,
611 BSS_INFO_UAPSD,
612 BSS_INFO_ROAM_DETECT,
613 BSS_INFO_LQ_RM,
614 BSS_INFO_EXT_BSS,
615 BSS_INFO_BMC_RATE,
616 BSS_INFO_SYNC_MODE,
617 BSS_INFO_RA,
618 BSS_INFO_HW_AMSDU,
619 BSS_INFO_BSS_COLOR,
620 BSS_INFO_HE_BASIC,
621 BSS_INFO_PROTECT_INFO,
622 BSS_INFO_OFFLOAD,
623 BSS_INFO_11V_MBSSID,
624 BSS_INFO_MAX_NUM
625};
626
627enum {
628 WTBL_RESET_AND_SET = 1,
629 WTBL_SET,
630 WTBL_QUERY,
631 WTBL_RESET_ALL
632};
633
634struct wtbl_req_hdr {
635 u8 wlan_idx_lo;
636 u8 operation;
637 __le16 tlv_num;
638 u8 wlan_idx_hi;
639 u8 rsv[3];
640} __packed;
641
642struct wtbl_generic {
643 __le16 tag;
644 __le16 len;
645 u8 peer_addr[ETH_ALEN];
646 u8 muar_idx;
647 u8 skip_tx;
648 u8 cf_ack;
649 u8 qos;
650 u8 mesh;
651 u8 adm;
652 __le16 partial_aid;
653 u8 baf_en;
654 u8 aad_om;
655} __packed;
656
657struct wtbl_rx {
658 __le16 tag;
659 __le16 len;
660 u8 rcid;
661 u8 rca1;
662 u8 rca2;
663 u8 rv;
664 u8 rsv[4];
665} __packed;
666
667struct wtbl_ht {
668 __le16 tag;
669 __le16 len;
670 u8 ht;
671 u8 ldpc;
672 u8 af;
673 u8 mm;
674 u8 rsv[4];
675} __packed;
676
677struct wtbl_vht {
678 __le16 tag;
679 __le16 len;
680 u8 ldpc;
681 u8 dyn_bw;
682 u8 vht;
683 u8 txop_ps;
684 u8 rsv[4];
685} __packed;
686
687struct wtbl_hdr_trans {
688 __le16 tag;
689 __le16 len;
690 u8 to_ds;
691 u8 from_ds;
692 u8 no_rx_trans;
693 u8 _rsv;
694};
695
696enum {
697 MT_BA_TYPE_INVALID,
698 MT_BA_TYPE_ORIGINATOR,
699 MT_BA_TYPE_RECIPIENT
700};
701
702enum {
703 RST_BA_MAC_TID_MATCH,
704 RST_BA_MAC_MATCH,
705 RST_BA_NO_MATCH
706};
707
708struct wtbl_ba {
709 __le16 tag;
710 __le16 len;
711
712 u8 tid;
713 u8 ba_type;
714 u8 rsv0[2];
715
716 __le16 sn;
717 u8 ba_en;
718 u8 ba_winsize_idx;
719 __le16 ba_winsize;
720
721 u8 peer_addr[ETH_ALEN];
722 u8 rst_ba_tid;
723 u8 rst_ba_sel;
724 u8 rst_ba_sb;
725 u8 band_idx;
726 u8 rsv1[4];
727} __packed;
728
729struct wtbl_smps {
730 __le16 tag;
731 __le16 len;
732 u8 smps;
733 u8 rsv[3];
734} __packed;
735
736enum {
737 WTBL_GENERIC,
738 WTBL_RX,
739 WTBL_HT,
740 WTBL_VHT,
741 WTBL_PEER_PS,
742 WTBL_TX_PS,
743 WTBL_HDR_TRANS,
744 WTBL_SEC_KEY,
745 WTBL_BA,
746 WTBL_RDG,
747 WTBL_PROTECT,
748 WTBL_CLEAR,
749 WTBL_BF,
750 WTBL_SMPS,
751 WTBL_RAW_DATA,
752 WTBL_PN,
753 WTBL_SPE,
754 WTBL_MAX_NUM
755};
756
757struct sta_ntlv_hdr {
758 u8 rsv[2];
759 __le16 tlv_num;
760} __packed;
761
762struct sta_req_hdr {
763 u8 bss_idx;
764 u8 wlan_idx_lo;
765 __le16 tlv_num;
766 u8 is_tlv_append;
767 u8 muar_idx;
768 u8 wlan_idx_hi;
769 u8 rsv;
770} __packed;
771
772struct sta_rec_basic {
773 __le16 tag;
774 __le16 len;
775 __le32 conn_type;
776 u8 conn_state;
777 u8 qos;
778 __le16 aid;
779 u8 peer_addr[ETH_ALEN];
780 __le16 extra_info;
781} __packed;
782
783struct sta_rec_ht {
784 __le16 tag;
785 __le16 len;
786 __le16 ht_cap;
787 u16 rsv;
788} __packed;
789
790struct sta_rec_vht {
791 __le16 tag;
792 __le16 len;
793 __le32 vht_cap;
794 __le16 vht_rx_mcs_map;
795 __le16 vht_tx_mcs_map;
796 u8 rts_bw_sig;
797 u8 rsv[3];
798} __packed;
799
800struct sta_rec_uapsd {
801 __le16 tag;
802 __le16 len;
803 u8 dac_map;
804 u8 tac_map;
805 u8 max_sp;
806 u8 rsv0;
807 __le16 listen_interval;
808 u8 rsv1[2];
809} __packed;
810
811struct sta_rec_muru {
812 __le16 tag;
813 __le16 len;
814
815 struct {
816 bool ofdma_dl_en;
817 bool ofdma_ul_en;
818 bool mimo_dl_en;
819 bool mimo_ul_en;
820 u8 rsv[4];
821 } cfg;
822
823 struct {
824 u8 punc_pream_rx;
825 bool he_20m_in_40m_2g;
826 bool he_20m_in_160m;
827 bool he_80m_in_160m;
828 bool lt16_sigb;
829 bool rx_su_comp_sigb;
830 bool rx_su_non_comp_sigb;
831 u8 rsv;
832 } ofdma_dl;
833
834 struct {
835 u8 t_frame_dur;
836 u8 mu_cascading;
837 u8 uo_ra;
838 u8 he_2x996_tone;
839 u8 rx_t_frame_11ac;
840 u8 rsv[3];
841 } ofdma_ul;
842
843 struct {
844 bool vht_mu_bfee;
845 bool partial_bw_dl_mimo;
846 u8 rsv[2];
847 } mimo_dl;
848
849 struct {
850 bool full_ul_mimo;
851 bool partial_ul_mimo;
852 u8 rsv[2];
853 } mimo_ul;
854} __packed;
855
856struct sta_rec_he {
857 __le16 tag;
858 __le16 len;
859
860 __le32 he_cap;
861
862 u8 t_frame_dur;
863 u8 max_ampdu_exp;
864 u8 bw_set;
865 u8 device_class;
866 u8 dcm_tx_mode;
867 u8 dcm_tx_max_nss;
868 u8 dcm_rx_mode;
869 u8 dcm_rx_max_nss;
870 u8 dcm_max_ru;
871 u8 punc_pream_rx;
872 u8 pkt_ext;
873 u8 rsv1;
874
875 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
876
877 u8 rsv2[2];
878} __packed;
879
880struct sta_rec_ba {
881 __le16 tag;
882 __le16 len;
883 u8 tid;
884 u8 ba_type;
885 u8 amsdu;
886 u8 ba_en;
887 __le16 ssn;
888 __le16 winsize;
889} __packed;
890
891struct sta_rec_amsdu {
892 __le16 tag;
893 __le16 len;
894 u8 max_amsdu_num;
895 u8 max_mpdu_size;
896 u8 amsdu_en;
897 u8 rsv;
898} __packed;
899
900struct sec_key {
901 u8 cipher_id;
902 u8 cipher_len;
903 u8 key_id;
904 u8 key_len;
905 u8 key[32];
906} __packed;
907
908struct sta_rec_sec {
909 __le16 tag;
910 __le16 len;
911 u8 add;
912 u8 n_cipher;
913 u8 rsv[2];
914
915 struct sec_key key[2];
916} __packed;
917
918struct ra_phy {
919 u8 type;
920 u8 flag;
921 u8 stbc;
922 u8 sgi;
923 u8 bw;
924 u8 ldpc;
925 u8 mcs;
926 u8 nss;
927 u8 he_ltf;
928};
929
930struct sta_rec_ra {
931 __le16 tag;
932 __le16 len;
933
934 u8 valid;
935 u8 auto_rate;
936 u8 phy_mode;
937 u8 channel;
938 u8 bw;
939 u8 disable_cck;
940 u8 ht_mcs32;
941 u8 ht_gf;
942 u8 ht_mcs[4];
943 u8 mmps_mode;
944 u8 gband_256;
945 u8 af;
946 u8 auth_wapi_mode;
947 u8 rate_len;
948
949 u8 supp_mode;
950 u8 supp_cck_rate;
951 u8 supp_ofdm_rate;
952 __le32 supp_ht_mcs;
953 __le16 supp_vht_mcs[4];
954
955 u8 op_mode;
956 u8 op_vht_chan_width;
957 u8 op_vht_rx_nss;
958 u8 op_vht_rx_nss_type;
959
960 __le32 sta_cap;
961
962 struct ra_phy phy;
963} __packed;
964
965struct sta_rec_ra_fixed {
966 __le16 tag;
967 __le16 len;
968
969 __le32 field;
970 u8 op_mode;
971 u8 op_vht_chan_width;
972 u8 op_vht_rx_nss;
973 u8 op_vht_rx_nss_type;
974
975 struct ra_phy phy;
976
977 u8 spe_en;
978 u8 short_preamble;
979 u8 is_5g;
980 u8 mmps_mode;
981} __packed;
982
983#define RATE_PARAM_FIXED 3
984#define RATE_PARAM_AUTO 20
985#define RATE_CFG_MCS GENMASK(3, 0)
986#define RATE_CFG_NSS GENMASK(7, 4)
987#define RATE_CFG_GI GENMASK(11, 8)
988#define RATE_CFG_BW GENMASK(15, 12)
989#define RATE_CFG_STBC GENMASK(19, 16)
990#define RATE_CFG_LDPC GENMASK(23, 20)
991#define RATE_CFG_PHY_TYPE GENMASK(27, 24)
992
993struct sta_rec_bf {
994 __le16 tag;
995 __le16 len;
996
997 __le16 pfmu;
998 bool su_mu;
999 u8 bf_cap;
1000 u8 sounding_phy;
1001 u8 ndpa_rate;
1002 u8 ndp_rate;
1003 u8 rept_poll_rate;
1004 u8 tx_mode;
1005 u8 nc;
1006 u8 nr;
1007 u8 bw;
1008
1009 u8 mem_total;
1010 u8 mem_20m;
1011 struct {
1012 u8 row;
1013 u8 col: 6, row_msb: 2;
1014 } mem[4];
1015
1016 __le16 smart_ant;
1017 u8 se_idx;
1018 u8 auto_sounding;
1019
1020
1021
1022 u8 ibf_timeout;
1023 u8 ibf_dbw;
1024 u8 ibf_ncol;
1025 u8 ibf_nrow;
1026 u8 nr_bw160;
1027 u8 nc_bw160;
1028 u8 ru_start_idx;
1029 u8 ru_end_idx;
1030
1031 bool trigger_su;
1032 bool trigger_mu;
1033 bool ng16_su;
1034 bool ng16_mu;
1035 bool codebook42_su;
1036 bool codebook75_mu;
1037
1038 u8 he_ltf;
1039 u8 rsv[2];
1040} __packed;
1041
1042struct sta_rec_bfee {
1043 __le16 tag;
1044 __le16 len;
1045 bool fb_identity_matrix;
1046 bool ignore_feedback;
1047 u8 rsv[2];
1048} __packed;
1049
1050enum {
1051 STA_REC_BASIC,
1052 STA_REC_RA,
1053 STA_REC_RA_CMM_INFO,
1054 STA_REC_RA_UPDATE,
1055 STA_REC_BF,
1056 STA_REC_AMSDU,
1057 STA_REC_BA,
1058 STA_REC_RED,
1059 STA_REC_TX_PROC,
1060 STA_REC_HT,
1061 STA_REC_VHT,
1062 STA_REC_APPS,
1063 STA_REC_KEY,
1064 STA_REC_WTBL,
1065 STA_REC_HE,
1066 STA_REC_HW_AMSDU,
1067 STA_REC_WTBL_AADOM,
1068 STA_REC_KEY_V2,
1069 STA_REC_MURU,
1070 STA_REC_MUEDCA,
1071 STA_REC_BFEE,
1072 STA_REC_MAX_NUM
1073};
1074
1075enum mcu_cipher_type {
1076 MCU_CIPHER_NONE = 0,
1077 MCU_CIPHER_WEP40,
1078 MCU_CIPHER_WEP104,
1079 MCU_CIPHER_WEP128,
1080 MCU_CIPHER_TKIP,
1081 MCU_CIPHER_AES_CCMP,
1082 MCU_CIPHER_CCMP_256,
1083 MCU_CIPHER_GCMP,
1084 MCU_CIPHER_GCMP_256,
1085 MCU_CIPHER_WAPI,
1086 MCU_CIPHER_BIP_CMAC_128,
1087};
1088
1089enum {
1090 CH_SWITCH_NORMAL = 0,
1091 CH_SWITCH_SCAN = 3,
1092 CH_SWITCH_MCC = 4,
1093 CH_SWITCH_DFS = 5,
1094 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1095 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1096 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1097 CH_SWITCH_SCAN_BYPASS_DPD = 9
1098};
1099
1100enum {
1101 THERMAL_SENSOR_TEMP_QUERY,
1102 THERMAL_SENSOR_MANUAL_CTRL,
1103 THERMAL_SENSOR_INFO_QUERY,
1104 THERMAL_SENSOR_TASK_CTRL,
1105};
1106
1107enum {
1108 THERMAL_PROTECT_PARAMETER_CTRL,
1109 THERMAL_PROTECT_BASIC_INFO,
1110 THERMAL_PROTECT_ENABLE,
1111 THERMAL_PROTECT_DISABLE,
1112 THERMAL_PROTECT_DUTY_CONFIG,
1113 THERMAL_PROTECT_MECH_INFO,
1114 THERMAL_PROTECT_DUTY_INFO,
1115 THERMAL_PROTECT_STATE_ACT,
1116};
1117
1118enum {
1119 MT_EBF = BIT(0),
1120 MT_IBF = BIT(1)
1121};
1122
1123enum {
1124 MT_BF_SOUNDING_ON = 1,
1125 MT_BF_TYPE_UPDATE = 20,
1126 MT_BF_MODULE_UPDATE = 25
1127};
1128
1129#define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
1130 sizeof(struct wtbl_generic) + \
1131 sizeof(struct wtbl_rx) + \
1132 sizeof(struct wtbl_ht) + \
1133 sizeof(struct wtbl_vht) + \
1134 sizeof(struct wtbl_hdr_trans) +\
1135 sizeof(struct wtbl_ba) + \
1136 sizeof(struct wtbl_smps))
1137
1138#define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1139 sizeof(struct sta_rec_basic) + \
1140 sizeof(struct sta_rec_ht) + \
1141 sizeof(struct sta_rec_he) + \
1142 sizeof(struct sta_rec_ba) + \
1143 sizeof(struct sta_rec_vht) + \
1144 sizeof(struct sta_rec_uapsd) + \
1145 sizeof(struct sta_rec_amsdu) + \
1146 sizeof(struct tlv) + \
1147 MT7915_WTBL_UPDATE_MAX_SIZE)
1148
1149#define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1150 sizeof(struct bss_info_omac) + \
1151 sizeof(struct bss_info_basic) +\
1152 sizeof(struct bss_info_rf_ch) +\
1153 sizeof(struct bss_info_ra) + \
1154 sizeof(struct bss_info_hw_amsdu) +\
1155 sizeof(struct bss_info_he) + \
1156 sizeof(struct bss_info_bmc_rate) +\
1157 sizeof(struct bss_info_ext_bss))
1158
1159#define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \
1160 sizeof(struct bss_info_bcn_csa) + \
1161 sizeof(struct bss_info_bcn_bcc) + \
1162 sizeof(struct bss_info_bcn_mbss) + \
1163 sizeof(struct bss_info_bcn_cont))
1164
1165#define PHY_MODE_A BIT(0)
1166#define PHY_MODE_B BIT(1)
1167#define PHY_MODE_G BIT(2)
1168#define PHY_MODE_GN BIT(3)
1169#define PHY_MODE_AN BIT(4)
1170#define PHY_MODE_AC BIT(5)
1171#define PHY_MODE_AX_24G BIT(6)
1172#define PHY_MODE_AX_5G BIT(7)
1173#define PHY_MODE_AX_6G BIT(8)
1174
1175#define MODE_CCK BIT(0)
1176#define MODE_OFDM BIT(1)
1177#define MODE_HT BIT(2)
1178#define MODE_VHT BIT(3)
1179#define MODE_HE BIT(4)
1180
1181#define STA_CAP_WMM BIT(0)
1182#define STA_CAP_SGI_20 BIT(4)
1183#define STA_CAP_SGI_40 BIT(5)
1184#define STA_CAP_TX_STBC BIT(6)
1185#define STA_CAP_RX_STBC BIT(7)
1186#define STA_CAP_VHT_SGI_80 BIT(16)
1187#define STA_CAP_VHT_SGI_160 BIT(17)
1188#define STA_CAP_VHT_TX_STBC BIT(18)
1189#define STA_CAP_VHT_RX_STBC BIT(19)
1190#define STA_CAP_VHT_LDPC BIT(23)
1191#define STA_CAP_LDPC BIT(24)
1192#define STA_CAP_HT BIT(26)
1193#define STA_CAP_VHT BIT(27)
1194#define STA_CAP_HE BIT(28)
1195
1196
1197#define STA_REC_HE_CAP_HTC BIT(0)
1198#define STA_REC_HE_CAP_BQR BIT(1)
1199#define STA_REC_HE_CAP_BSR BIT(2)
1200#define STA_REC_HE_CAP_OM BIT(3)
1201#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
1202
1203#define STA_REC_HE_CAP_DUAL_BAND BIT(5)
1204#define STA_REC_HE_CAP_LDPC BIT(6)
1205#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
1206#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
1207
1208#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
1209#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
1210#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
1211#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
1212
1213#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
1214#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
1215#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
1216#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
1217#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
1218
1219#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
1220#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
1221#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
1222
1223#endif
1224
