1
2
3
4#ifndef __RTL92E_TRX_H__
5#define __RTL92E_TRX_H__
6
7#define TX_DESC_SIZE 64
8
9#define RX_DRV_INFO_SIZE_UNIT 8
10
11#define TX_DESC_NEXT_DESC_OFFSET 40
12#define USB_HWDESC_HEADER_LEN 40
13
14#define RX_DESC_SIZE 24
15#define MAX_RECEIVE_BUFFER_SIZE 8192
16
17static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
18{
19 le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
20}
21
22static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
23{
24 le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
25}
26
27static inline void set_tx_desc_bmc(__le32 *__pdesc, u32 __val)
28{
29 le32p_replace_bits(__pdesc, __val, BIT(24));
30}
31
32static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val)
33{
34 le32p_replace_bits(__pdesc, __val, BIT(25));
35}
36
37static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
38{
39 le32p_replace_bits(__pdesc, __val, BIT(26));
40}
41
42static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
43{
44 le32p_replace_bits(__pdesc, __val, BIT(27));
45}
46
47static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
48{
49 le32p_replace_bits(__pdesc, __val, BIT(28));
50}
51
52static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
53{
54 le32p_replace_bits(__pdesc, __val, BIT(31));
55}
56
57static inline int get_tx_desc_own(__le32 *__pdesc)
58{
59 return le32_get_bits(*(__pdesc), BIT(31));
60}
61
62static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
63{
64 le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));
65}
66
67static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
68{
69 le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
70}
71
72static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val)
73{
74 le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));
75}
76
77static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
78{
79 le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
80}
81
82static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val)
83{
84 le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));
85}
86
87static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)
88{
89 le32p_replace_bits((__pdesc + 2), __val, BIT(12));
90}
91
92static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val)
93{
94 le32p_replace_bits((__pdesc + 2), __val, BIT(13));
95}
96
97static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val)
98{
99 le32p_replace_bits((__pdesc + 2), __val, BIT(17));
100}
101
102static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val)
103{
104 le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
105}
106
107static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val)
108{
109 le32p_replace_bits((__pdesc + 3), __val, BIT(8));
110}
111
112static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val)
113{
114 le32p_replace_bits((__pdesc + 3), __val, BIT(10));
115}
116
117static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val)
118{
119 le32p_replace_bits((__pdesc + 3), __val, BIT(11));
120}
121
122static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
123{
124 le32p_replace_bits((__pdesc + 3), __val, BIT(12));
125}
126
127static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val)
128{
129 le32p_replace_bits((__pdesc + 3), __val, BIT(13));
130}
131
132static inline void set_tx_desc_nav_use_hdr(__le32 *__pdesc, u32 __val)
133{
134 le32p_replace_bits((__pdesc + 3), __val, BIT(15));
135}
136
137static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val)
138{
139 le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));
140}
141
142
143static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
144{
145 le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));
146}
147
148static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
149{
150 le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));
151}
152
153static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val)
154{
155 le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));
156}
157
158static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
159{
160 le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));
161}
162
163
164static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
165{
166 le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));
167}
168
169static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val)
170{
171 le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 5));
172}
173
174static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
175{
176 le32p_replace_bits((__pdesc + 5), __val, BIT(12));
177}
178
179static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val)
180{
181 le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
182}
183
184
185static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
186{
187 le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
188}
189
190
191static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
192{
193 le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));
194}
195
196
197static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
198{
199 *(__pdesc + 10) = cpu_to_le32(__val);
200}
201
202
203static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
204{
205 *(__pdesc + 12) = cpu_to_le32(__val);
206}
207
208static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __val)
209{
210 le32p_replace_bits(__paddr, __val, GENMASK(3, 0));
211}
212
213static inline void set_earlymode_len0(__le32 *__paddr, u32 __val)
214{
215 le32p_replace_bits(__paddr, __val, GENMASK(18, 4));
216}
217
218static inline void set_earlymode_len1(__le32 *__paddr, u32 __val)
219{
220 le32p_replace_bits(__paddr, __val, GENMASK(17, 16));
221}
222
223static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __val)
224{
225 le32p_replace_bits(__paddr, __val, GENMASK(5, 2));
226}
227
228static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __val)
229{
230 le32p_replace_bits((__paddr + 1), __val, GENMASK(7, 0));
231}
232
233static inline void set_earlymode_len3(__le32 *__paddr, u32 __val)
234{
235 le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 17));
236}
237
238static inline void set_earlymode_len4(__le32 *__paddr, u32 __val)
239{
240 le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 20));
241}
242
243
244
245
246static inline void set_txbuffer_desc_len_with_offset(__le32 *__pdesc,
247 u8 __offset, u32 __val)
248{
249 le32p_replace_bits((__pdesc + 4 * __offset), __val,
250 GENMASK(15, 0));
251}
252
253static inline void set_txbuffer_desc_amsdu_with_offset(__le32 *__pdesc,
254 u8 __offset, u32 __val)
255{
256 le32p_replace_bits((__pdesc + 4 * __offset), __val, BIT(31));
257}
258
259static inline void set_txbuffer_desc_add_low_with_offset(__le32 *__pdesc,
260 u8 __offset,
261 u32 __val)
262{
263 *(__pdesc + 4 * __offset + 1) = cpu_to_le32(__val);
264}
265
266static inline void set_txbuffer_desc_add_high_with_offset(__le32 *pbd, u8 off,
267 u32 val, bool dma64)
268{
269 if (dma64)
270 *(pbd + 4 * off + 2) = cpu_to_le32(val);
271 else
272 *(pbd + 4 * off + 2) = 0;
273}
274
275static inline u32 get_txbuffer_desc_addr_low(__le32 *__pdesc, u8 __offset)
276{
277 return le32_to_cpu(*((__pdesc + 4 * __offset + 1)));
278}
279
280static inline u32 get_txbuffer_desc_addr_high(__le32 *pbd, u32 off, bool dma64)
281{
282 if (dma64)
283 return le32_to_cpu(*((pbd + 4 * off + 2)));
284 return 0;
285}
286
287
288static inline void set_tx_buff_desc_len_0(__le32 *__pdesc, u32 __val)
289{
290 le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
291}
292
293static inline void set_tx_buff_desc_psb(__le32 *__pdesc, u32 __val)
294{
295 le32p_replace_bits(__pdesc, __val, GENMASK(30, 16));
296}
297
298static inline void set_tx_buff_desc_own(__le32 *__pdesc, u32 __val)
299{
300 le32p_replace_bits(__pdesc, __val, BIT(31));
301}
302
303
304static inline void set_tx_buff_desc_addr_low_0(__le32 *__pdesc, u32 __val)
305{
306 *(__pdesc + 1) = cpu_to_le32(__val);
307}
308
309
310static inline void set_tx_buff_desc_addr_high_0(__le32 *pdesc, u32 val,
311 bool dma64)
312{
313 if (dma64)
314 *(pdesc + 2) = cpu_to_le32(val);
315 else
316 *(pdesc + 2) = 0;
317}
318
319
320
321
322static inline void set_rx_buffer_desc_data_length(__le32 *__status, u32 __val)
323{
324 le32p_replace_bits(__status, __val, GENMASK(13, 0));
325}
326
327static inline void set_rx_buffer_desc_ls(__le32 *__status, u32 __val)
328{
329 le32p_replace_bits(__status, __val, BIT(15));
330}
331
332static inline void set_rx_buffer_desc_fs(__le32 *__status, u32 __val)
333{
334 le32p_replace_bits(__status, __val, BIT(16));
335}
336
337static inline void set_rx_buffer_desc_total_length(__le32 *__status, u32 __val)
338{
339 le32p_replace_bits(__status, __val, GENMASK(30, 16));
340}
341
342static inline int get_rx_buffer_desc_ls(__le32 *__status)
343{
344 return le32_get_bits(*(__status), BIT(15));
345}
346
347static inline int get_rx_buffer_desc_fs(__le32 *__status)
348{
349 return le32_get_bits(*(__status), BIT(16));
350}
351
352static inline int get_rx_buffer_desc_total_length(__le32 *__status)
353{
354 return le32_get_bits(*(__status), GENMASK(30, 16));
355}
356
357
358static inline void set_rx_buffer_physical_low(__le32 *__status, u32 __val)
359{
360 *(__status + 1) = cpu_to_le32(__val);
361}
362
363
364static inline void set_rx_buffer_physical_high(__le32 *__rx_status_desc,
365 u32 __val, bool dma64)
366{
367 if (dma64)
368 *(__rx_status_desc + 2) = cpu_to_le32(__val);
369 else
370 *(__rx_status_desc + 2) = 0;
371}
372
373static inline int get_rx_desc_pkt_len(__le32 *__pdesc)
374{
375 return le32_get_bits(*__pdesc, GENMASK(13, 0));
376}
377
378static inline int get_rx_desc_crc32(__le32 *__pdesc)
379{
380 return le32_get_bits(*__pdesc, BIT(14));
381}
382
383static inline int get_rx_desc_icv(__le32 *__pdesc)
384{
385 return le32_get_bits(*__pdesc, BIT(15));
386}
387
388static inline int get_rx_desc_drv_info_size(__le32 *__pdesc)
389{
390 return le32_get_bits(*__pdesc, GENMASK(19, 16));
391}
392
393static inline int get_rx_desc_shift(__le32 *__pdesc)
394{
395 return le32_get_bits(*__pdesc, GENMASK(25, 24));
396}
397
398static inline int get_rx_desc_physt(__le32 *__pdesc)
399{
400 return le32_get_bits(*__pdesc, BIT(26));
401}
402
403static inline int get_rx_desc_swdec(__le32 *__pdesc)
404{
405 return le32_get_bits(*__pdesc, BIT(27));
406}
407
408static inline int get_rx_desc_own(__le32 *__pdesc)
409{
410 return le32_get_bits(*__pdesc, BIT(31));
411}
412
413static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val)
414{
415 le32p_replace_bits(__pdesc, __val, BIT(30));
416}
417
418static inline int get_rx_desc_macid(__le32 *__pdesc)
419{
420 return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));
421}
422
423static inline int get_rx_desc_paggr(__le32 *__pdesc)
424{
425 return le32_get_bits(*(__pdesc + 1), BIT(15));
426}
427
428static inline int get_rx_status_desc_rpt_sel(__le32 *__pdesc)
429{
430 return le32_get_bits(*(__pdesc + 2), BIT(28));
431}
432
433static inline int get_rx_desc_rxmcs(__le32 *__pdesc)
434{
435 return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));
436}
437
438static inline int get_rx_status_desc_pattern_match(__le32 *__pdesc)
439{
440 return le32_get_bits(*(__pdesc + 3), BIT(29));
441}
442
443static inline int get_rx_status_desc_unicast_match(__le32 *__pdesc)
444{
445 return le32_get_bits(*(__pdesc + 3), BIT(30));
446}
447
448static inline int get_rx_status_desc_magic_match(__le32 *__pdesc)
449{
450 return le32_get_bits(*(__pdesc + 3), BIT(31));
451}
452
453static inline u32 get_rx_desc_tsfl(__le32 *__pdesc)
454{
455 return le32_to_cpu(*((__pdesc + 5)));
456}
457
458static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc)
459{
460 return le32_to_cpu(*((__pdesc + 6)));
461}
462
463
464
465static inline u32 get_rx_rpt2_desc_macid_valid_1(__le32 *__status)
466{
467 return le32_to_cpu(*((__status + 4)));
468}
469
470static inline u32 get_rx_rpt2_desc_macid_valid_2(__le32 *__status)
471{
472 return le32_to_cpu(*((__status + 5)));
473}
474
475static inline void clear_pci_tx_desc_content(__le32 *__pdesc, int _size)
476{
477 if (_size > TX_DESC_NEXT_DESC_OFFSET)
478 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);
479 else
480 memset(__pdesc, 0, _size);
481}
482
483#define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\
484 (rxmcs == DESC_RATE1M ||\
485 rxmcs == DESC_RATE2M ||\
486 rxmcs == DESC_RATE5_5M ||\
487 rxmcs == DESC_RATE11M)
488
489#define IS_LITTLE_ENDIAN 1
490
491struct phy_rx_agc_info_t {
492 #if IS_LITTLE_ENDIAN
493 u8 gain:7, trsw:1;
494 #else
495 u8 trsw:1, gain:7;
496 #endif
497};
498
499struct phy_status_rpt {
500 struct phy_rx_agc_info_t path_agc[2];
501 u8 ch_corr[2];
502 u8 cck_sig_qual_ofdm_pwdb_all;
503 u8 cck_agc_rpt_ofdm_cfosho_a;
504 u8 cck_rpt_b_ofdm_cfosho_b;
505 u8 rsvd_1;
506 u8 noise_power_db_msb;
507 u8 path_cfotail[2];
508 u8 pcts_mask[2];
509 u8 stream_rxevm[2];
510 u8 path_rxsnr[2];
511 u8 noise_power_db_lsb;
512 u8 rsvd_2[3];
513 u8 stream_csi[2];
514 u8 stream_target_csi[2];
515 u8 sig_evm;
516 u8 rsvd_3;
517#if IS_LITTLE_ENDIAN
518 u8 antsel_rx_keep_2:1;
519 u8 sgi_en:1;
520 u8 rxsc:2;
521 u8 idle_long:1;
522 u8 r_ant_train_en:1;
523 u8 ant_sel_b:1;
524 u8 ant_sel:1;
525#else
526 u8 ant_sel:1;
527 u8 ant_sel_b:1;
528 u8 r_ant_train_en:1;
529 u8 idle_long:1;
530 u8 rxsc:2;
531 u8 sgi_en:1;
532 u8 antsel_rx_keep_2:1;
533#endif
534} __packed;
535
536struct rx_fwinfo {
537 u8 gain_trsw[4];
538 u8 pwdb_all;
539 u8 cfosho[4];
540 u8 cfotail[4];
541 s8 rxevm[2];
542 s8 rxsnr[4];
543 u8 pdsnr[2];
544 u8 csi_current[2];
545 u8 csi_target[2];
546 u8 sigevm;
547 u8 max_ex_pwr;
548 u8 ex_intf_flag:1;
549 u8 sgi_en:1;
550 u8 rxsc:2;
551 u8 reserve:4;
552} __packed;
553
554struct tx_desc {
555 u32 pktsize:16;
556 u32 offset:8;
557 u32 bmc:1;
558 u32 htc:1;
559 u32 lastseg:1;
560 u32 firstseg:1;
561 u32 linip:1;
562 u32 noacm:1;
563 u32 gf:1;
564 u32 own:1;
565
566 u32 macid:6;
567 u32 rsvd0:2;
568 u32 queuesel:5;
569 u32 rd_nav_ext:1;
570 u32 lsig_txop_en:1;
571 u32 pifs:1;
572 u32 rateid:4;
573 u32 nav_usehdr:1;
574 u32 en_descid:1;
575 u32 sectype:2;
576 u32 pktoffset:8;
577
578 u32 rts_rc:6;
579 u32 data_rc:6;
580 u32 agg_en:1;
581 u32 rdg_en:1;
582 u32 bar_retryht:2;
583 u32 agg_break:1;
584 u32 morefrag:1;
585 u32 raw:1;
586 u32 ccx:1;
587 u32 ampdudensity:3;
588 u32 bt_int:1;
589 u32 ant_sela:1;
590 u32 ant_selb:1;
591 u32 txant_cck:2;
592 u32 txant_l:2;
593 u32 txant_ht:2;
594
595 u32 nextheadpage:8;
596 u32 tailpage:8;
597 u32 seq:12;
598 u32 cpu_handle:1;
599 u32 tag1:1;
600 u32 trigger_int:1;
601 u32 hwseq_en:1;
602
603 u32 rtsrate:5;
604 u32 apdcfe:1;
605 u32 qos:1;
606 u32 hwseq_ssn:1;
607 u32 userrate:1;
608 u32 dis_rtsfb:1;
609 u32 dis_datafb:1;
610 u32 cts2self:1;
611 u32 rts_en:1;
612 u32 hwrts_en:1;
613 u32 portid:1;
614 u32 pwr_status:3;
615 u32 waitdcts:1;
616 u32 cts2ap_en:1;
617 u32 txsc:2;
618 u32 stbc:2;
619 u32 txshort:1;
620 u32 txbw:1;
621 u32 rtsshort:1;
622 u32 rtsbw:1;
623 u32 rtssc:2;
624 u32 rtsstbc:2;
625
626 u32 txrate:6;
627 u32 shortgi:1;
628 u32 ccxt:1;
629 u32 txrate_fb_lmt:5;
630 u32 rtsrate_fb_lmt:4;
631 u32 retrylmt_en:1;
632 u32 txretrylmt:6;
633 u32 usb_txaggnum:8;
634
635 u32 txagca:5;
636 u32 txagcb:5;
637 u32 usemaxlen:1;
638 u32 maxaggnum:5;
639 u32 mcsg1maxlen:4;
640 u32 mcsg2maxlen:4;
641 u32 mcsg3maxlen:4;
642 u32 mcs7sgimaxlen:4;
643
644 u32 txbuffersize:16;
645 u32 sw_offset30:8;
646 u32 sw_offset31:4;
647 u32 rsvd1:1;
648 u32 antsel_c:1;
649 u32 null_0:1;
650 u32 null_1:1;
651
652 u32 txbuffaddr;
653 u32 txbufferaddr64;
654 u32 nextdescaddress;
655 u32 nextdescaddress64;
656
657 u32 reserve_pass_pcie_mm_limit[4];
658} __packed;
659
660struct rx_desc {
661 u32 length:14;
662 u32 crc32:1;
663 u32 icverror:1;
664 u32 drv_infosize:4;
665 u32 security:3;
666 u32 qos:1;
667 u32 shift:2;
668 u32 phystatus:1;
669 u32 swdec:1;
670 u32 lastseg:1;
671 u32 firstseg:1;
672 u32 eor:1;
673 u32 own:1;
674
675 u32 macid:6;
676 u32 tid:4;
677 u32 hwrsvd:5;
678 u32 paggr:1;
679 u32 faggr:1;
680 u32 a1_fit:4;
681 u32 a2_fit:4;
682 u32 pam:1;
683 u32 pwr:1;
684 u32 moredata:1;
685 u32 morefrag:1;
686 u32 type:2;
687 u32 mc:1;
688 u32 bc:1;
689
690 u32 seq:12;
691 u32 frag:4;
692 u32 nextpktlen:14;
693 u32 nextind:1;
694 u32 rsvd:1;
695
696 u32 rxmcs:6;
697 u32 rxht:1;
698 u32 amsdu:1;
699 u32 splcp:1;
700 u32 bandwidth:1;
701 u32 htc:1;
702 u32 tcpchk_rpt:1;
703 u32 ipcchk_rpt:1;
704 u32 tcpchk_valid:1;
705 u32 hwpcerr:1;
706 u32 hwpcind:1;
707 u32 iv0:16;
708
709 u32 iv1;
710
711 u32 tsfl;
712
713 u32 bufferaddress;
714 u32 bufferaddress64;
715
716} __packed;
717
718void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
719 u8 queue_index);
720u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
721 u8 queue_index);
722u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
723void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
724 u8 *tx_bd_desc, u8 *desc, u8 queue_index,
725 struct sk_buff *skb, dma_addr_t addr);
726
727void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
728 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
729 u8 *pbd_desc_tx,
730 struct ieee80211_tx_info *info,
731 struct ieee80211_sta *sta,
732 struct sk_buff *skb,
733 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
734bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
735 struct rtl_stats *status,
736 struct ieee80211_rx_status *rx_status,
737 u8 *pdesc, struct sk_buff *skb);
738void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
739 u8 desc_name, u8 *val);
740
741u64 rtl92ee_get_desc(struct ieee80211_hw *hw,
742 u8 *pdesc, bool istx, u8 desc_name);
743bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
744void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
745void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
746 bool firstseg, bool lastseg,
747 struct sk_buff *skb);
748#endif
749
