1
2
3
4
5#ifndef __RTK_MAIN_H_
6#define __RTK_MAIN_H_
7
8#include <net/mac80211.h>
9#include <linux/vmalloc.h>
10#include <linux/firmware.h>
11#include <linux/average.h>
12#include <linux/bitops.h>
13#include <linux/bitfield.h>
14#include <linux/iopoll.h>
15#include <linux/interrupt.h>
16#include <linux/workqueue.h>
17
18#include "util.h"
19
20#define RTW_NAPI_WEIGHT_NUM 64
21#define RTW_MAX_MAC_ID_NUM 32
22#define RTW_MAX_SEC_CAM_NUM 32
23#define MAX_PG_CAM_BACKUP_NUM 8
24
25#define RTW_MAX_PATTERN_NUM 12
26#define RTW_MAX_PATTERN_MASK_SIZE 16
27#define RTW_MAX_PATTERN_SIZE 128
28
29#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
30
31#define RFREG_MASK 0xfffff
32#define INV_RF_DATA 0xffffffff
33#define TX_PAGE_SIZE_SHIFT 7
34
35#define RTW_CHANNEL_WIDTH_MAX 3
36#define RTW_RF_PATH_MAX 4
37#define HW_FEATURE_LEN 13
38
39#define RTW_TP_SHIFT 18
40
41extern bool rtw_bf_support;
42extern bool rtw_disable_lps_deep_mode;
43extern unsigned int rtw_debug_mask;
44extern const struct ieee80211_ops rtw_ops;
45
46#define RTW_MAX_CHANNEL_NUM_2G 14
47#define RTW_MAX_CHANNEL_NUM_5G 49
48
49struct rtw_dev;
50
51enum rtw_hci_type {
52 RTW_HCI_TYPE_PCIE,
53 RTW_HCI_TYPE_USB,
54 RTW_HCI_TYPE_SDIO,
55
56 RTW_HCI_TYPE_UNDEFINE,
57};
58
59struct rtw_hci {
60 struct rtw_hci_ops *ops;
61 enum rtw_hci_type type;
62
63 u32 rpwm_addr;
64 u32 cpwm_addr;
65
66 u8 bulkout_num;
67};
68
69#define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
70#define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
71#define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
72#define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
73
74#define IS_CH_5G_BAND_MID(channel) \
75 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
76
77#define IS_CH_2G_BAND(channel) ((channel) <= 14)
78#define IS_CH_5G_BAND(channel) \
79 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
80 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
81
82enum rtw_supported_band {
83 RTW_BAND_2G = 1 << 0,
84 RTW_BAND_5G = 1 << 1,
85 RTW_BAND_60G = 1 << 2,
86
87 RTW_BAND_MAX,
88};
89
90
91#define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
92
93enum rtw_bandwidth {
94 RTW_CHANNEL_WIDTH_20 = 0,
95 RTW_CHANNEL_WIDTH_40 = 1,
96 RTW_CHANNEL_WIDTH_80 = 2,
97 RTW_CHANNEL_WIDTH_160 = 3,
98 RTW_CHANNEL_WIDTH_80_80 = 4,
99 RTW_CHANNEL_WIDTH_5 = 5,
100 RTW_CHANNEL_WIDTH_10 = 6,
101};
102
103enum rtw_sc_offset {
104 RTW_SC_DONT_CARE = 0,
105 RTW_SC_20_UPPER = 1,
106 RTW_SC_20_LOWER = 2,
107 RTW_SC_20_UPMOST = 3,
108 RTW_SC_20_LOWEST = 4,
109 RTW_SC_40_UPPER = 9,
110 RTW_SC_40_LOWER = 10,
111};
112
113enum rtw_net_type {
114 RTW_NET_NO_LINK = 0,
115 RTW_NET_AD_HOC = 1,
116 RTW_NET_MGD_LINKED = 2,
117 RTW_NET_AP_MODE = 3,
118};
119
120enum rtw_rf_type {
121 RF_1T1R = 0,
122 RF_1T2R = 1,
123 RF_2T2R = 2,
124 RF_2T3R = 3,
125 RF_2T4R = 4,
126 RF_3T3R = 5,
127 RF_3T4R = 6,
128 RF_4T4R = 7,
129 RF_TYPE_MAX,
130};
131
132enum rtw_rf_path {
133 RF_PATH_A = 0,
134 RF_PATH_B = 1,
135 RF_PATH_C = 2,
136 RF_PATH_D = 3,
137};
138
139enum rtw_bb_path {
140 BB_PATH_A = BIT(0),
141 BB_PATH_B = BIT(1),
142 BB_PATH_C = BIT(2),
143 BB_PATH_D = BIT(3),
144
145 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
146 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
147 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
148 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
149 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
150 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
151
152 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
153 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
154 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
155 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
156
157 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
158};
159
160enum rtw_rate_section {
161 RTW_RATE_SECTION_CCK = 0,
162 RTW_RATE_SECTION_OFDM,
163 RTW_RATE_SECTION_HT_1S,
164 RTW_RATE_SECTION_HT_2S,
165 RTW_RATE_SECTION_VHT_1S,
166 RTW_RATE_SECTION_VHT_2S,
167
168
169 RTW_RATE_SECTION_MAX,
170};
171
172enum rtw_wireless_set {
173 WIRELESS_CCK = 0x00000001,
174 WIRELESS_OFDM = 0x00000002,
175 WIRELESS_HT = 0x00000004,
176 WIRELESS_VHT = 0x00000008,
177};
178
179#define HT_STBC_EN BIT(0)
180#define VHT_STBC_EN BIT(1)
181#define HT_LDPC_EN BIT(0)
182#define VHT_LDPC_EN BIT(1)
183
184enum rtw_chip_type {
185 RTW_CHIP_TYPE_8822B,
186 RTW_CHIP_TYPE_8822C,
187 RTW_CHIP_TYPE_8723D,
188 RTW_CHIP_TYPE_8821C,
189};
190
191enum rtw_tx_queue_type {
192
193 RTW_TX_QUEUE_BK = 0x0,
194 RTW_TX_QUEUE_BE = 0x1,
195 RTW_TX_QUEUE_VI = 0x2,
196 RTW_TX_QUEUE_VO = 0x3,
197
198 RTW_TX_QUEUE_BCN = 0x4,
199 RTW_TX_QUEUE_MGMT = 0x5,
200 RTW_TX_QUEUE_HI0 = 0x6,
201 RTW_TX_QUEUE_H2C = 0x7,
202
203 RTK_MAX_TX_QUEUE_NUM
204};
205
206enum rtw_rx_queue_type {
207 RTW_RX_QUEUE_MPDU = 0x0,
208 RTW_RX_QUEUE_C2H = 0x1,
209
210 RTK_MAX_RX_QUEUE_NUM
211};
212
213enum rtw_fw_type {
214 RTW_NORMAL_FW = 0x0,
215 RTW_WOWLAN_FW = 0x1,
216};
217
218enum rtw_rate_index {
219 RTW_RATEID_BGN_40M_2SS = 0,
220 RTW_RATEID_BGN_40M_1SS = 1,
221 RTW_RATEID_BGN_20M_2SS = 2,
222 RTW_RATEID_BGN_20M_1SS = 3,
223 RTW_RATEID_GN_N2SS = 4,
224 RTW_RATEID_GN_N1SS = 5,
225 RTW_RATEID_BG = 6,
226 RTW_RATEID_G = 7,
227 RTW_RATEID_B_20M = 8,
228 RTW_RATEID_ARFR0_AC_2SS = 9,
229 RTW_RATEID_ARFR1_AC_1SS = 10,
230 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
231 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
232 RTW_RATEID_ARFR4_AC_3SS = 13,
233 RTW_RATEID_ARFR5_N_3SS = 14,
234 RTW_RATEID_ARFR7_N_4SS = 15,
235 RTW_RATEID_ARFR6_AC_4SS = 16
236};
237
238enum rtw_trx_desc_rate {
239 DESC_RATE1M = 0x00,
240 DESC_RATE2M = 0x01,
241 DESC_RATE5_5M = 0x02,
242 DESC_RATE11M = 0x03,
243
244 DESC_RATE6M = 0x04,
245 DESC_RATE9M = 0x05,
246 DESC_RATE12M = 0x06,
247 DESC_RATE18M = 0x07,
248 DESC_RATE24M = 0x08,
249 DESC_RATE36M = 0x09,
250 DESC_RATE48M = 0x0a,
251 DESC_RATE54M = 0x0b,
252
253 DESC_RATEMCS0 = 0x0c,
254 DESC_RATEMCS1 = 0x0d,
255 DESC_RATEMCS2 = 0x0e,
256 DESC_RATEMCS3 = 0x0f,
257 DESC_RATEMCS4 = 0x10,
258 DESC_RATEMCS5 = 0x11,
259 DESC_RATEMCS6 = 0x12,
260 DESC_RATEMCS7 = 0x13,
261 DESC_RATEMCS8 = 0x14,
262 DESC_RATEMCS9 = 0x15,
263 DESC_RATEMCS10 = 0x16,
264 DESC_RATEMCS11 = 0x17,
265 DESC_RATEMCS12 = 0x18,
266 DESC_RATEMCS13 = 0x19,
267 DESC_RATEMCS14 = 0x1a,
268 DESC_RATEMCS15 = 0x1b,
269 DESC_RATEMCS16 = 0x1c,
270 DESC_RATEMCS17 = 0x1d,
271 DESC_RATEMCS18 = 0x1e,
272 DESC_RATEMCS19 = 0x1f,
273 DESC_RATEMCS20 = 0x20,
274 DESC_RATEMCS21 = 0x21,
275 DESC_RATEMCS22 = 0x22,
276 DESC_RATEMCS23 = 0x23,
277 DESC_RATEMCS24 = 0x24,
278 DESC_RATEMCS25 = 0x25,
279 DESC_RATEMCS26 = 0x26,
280 DESC_RATEMCS27 = 0x27,
281 DESC_RATEMCS28 = 0x28,
282 DESC_RATEMCS29 = 0x29,
283 DESC_RATEMCS30 = 0x2a,
284 DESC_RATEMCS31 = 0x2b,
285
286 DESC_RATEVHT1SS_MCS0 = 0x2c,
287 DESC_RATEVHT1SS_MCS1 = 0x2d,
288 DESC_RATEVHT1SS_MCS2 = 0x2e,
289 DESC_RATEVHT1SS_MCS3 = 0x2f,
290 DESC_RATEVHT1SS_MCS4 = 0x30,
291 DESC_RATEVHT1SS_MCS5 = 0x31,
292 DESC_RATEVHT1SS_MCS6 = 0x32,
293 DESC_RATEVHT1SS_MCS7 = 0x33,
294 DESC_RATEVHT1SS_MCS8 = 0x34,
295 DESC_RATEVHT1SS_MCS9 = 0x35,
296
297 DESC_RATEVHT2SS_MCS0 = 0x36,
298 DESC_RATEVHT2SS_MCS1 = 0x37,
299 DESC_RATEVHT2SS_MCS2 = 0x38,
300 DESC_RATEVHT2SS_MCS3 = 0x39,
301 DESC_RATEVHT2SS_MCS4 = 0x3a,
302 DESC_RATEVHT2SS_MCS5 = 0x3b,
303 DESC_RATEVHT2SS_MCS6 = 0x3c,
304 DESC_RATEVHT2SS_MCS7 = 0x3d,
305 DESC_RATEVHT2SS_MCS8 = 0x3e,
306 DESC_RATEVHT2SS_MCS9 = 0x3f,
307
308 DESC_RATEVHT3SS_MCS0 = 0x40,
309 DESC_RATEVHT3SS_MCS1 = 0x41,
310 DESC_RATEVHT3SS_MCS2 = 0x42,
311 DESC_RATEVHT3SS_MCS3 = 0x43,
312 DESC_RATEVHT3SS_MCS4 = 0x44,
313 DESC_RATEVHT3SS_MCS5 = 0x45,
314 DESC_RATEVHT3SS_MCS6 = 0x46,
315 DESC_RATEVHT3SS_MCS7 = 0x47,
316 DESC_RATEVHT3SS_MCS8 = 0x48,
317 DESC_RATEVHT3SS_MCS9 = 0x49,
318
319 DESC_RATEVHT4SS_MCS0 = 0x4a,
320 DESC_RATEVHT4SS_MCS1 = 0x4b,
321 DESC_RATEVHT4SS_MCS2 = 0x4c,
322 DESC_RATEVHT4SS_MCS3 = 0x4d,
323 DESC_RATEVHT4SS_MCS4 = 0x4e,
324 DESC_RATEVHT4SS_MCS5 = 0x4f,
325 DESC_RATEVHT4SS_MCS6 = 0x50,
326 DESC_RATEVHT4SS_MCS7 = 0x51,
327 DESC_RATEVHT4SS_MCS8 = 0x52,
328 DESC_RATEVHT4SS_MCS9 = 0x53,
329
330 DESC_RATE_MAX,
331};
332
333enum rtw_regulatory_domains {
334 RTW_REGD_FCC = 0,
335 RTW_REGD_MKK = 1,
336 RTW_REGD_ETSI = 2,
337 RTW_REGD_IC = 3,
338 RTW_REGD_KCC = 4,
339 RTW_REGD_ACMA = 5,
340 RTW_REGD_CHILE = 6,
341 RTW_REGD_UKRAINE = 7,
342 RTW_REGD_MEXICO = 8,
343 RTW_REGD_CN = 9,
344 RTW_REGD_WW,
345
346 RTW_REGD_MAX
347};
348
349enum rtw_txq_flags {
350 RTW_TXQ_AMPDU,
351 RTW_TXQ_BLOCK_BA,
352};
353
354enum rtw_flags {
355 RTW_FLAG_RUNNING,
356 RTW_FLAG_FW_RUNNING,
357 RTW_FLAG_SCANNING,
358 RTW_FLAG_INACTIVE_PS,
359 RTW_FLAG_LEISURE_PS,
360 RTW_FLAG_LEISURE_PS_DEEP,
361 RTW_FLAG_DIG_DISABLE,
362 RTW_FLAG_BUSY_TRAFFIC,
363 RTW_FLAG_WOWLAN,
364 RTW_FLAG_RESTARTING,
365
366 NUM_OF_RTW_FLAGS,
367};
368
369enum rtw_evm {
370 RTW_EVM_OFDM = 0,
371 RTW_EVM_1SS,
372 RTW_EVM_2SS_A,
373 RTW_EVM_2SS_B,
374
375 RTW_EVM_NUM
376};
377
378enum rtw_snr {
379 RTW_SNR_OFDM_A = 0,
380 RTW_SNR_OFDM_B,
381 RTW_SNR_OFDM_C,
382 RTW_SNR_OFDM_D,
383 RTW_SNR_1SS_A,
384 RTW_SNR_1SS_B,
385 RTW_SNR_1SS_C,
386 RTW_SNR_1SS_D,
387 RTW_SNR_2SS_A,
388 RTW_SNR_2SS_B,
389 RTW_SNR_2SS_C,
390 RTW_SNR_2SS_D,
391
392 RTW_SNR_NUM
393};
394
395enum rtw_wow_flags {
396 RTW_WOW_FLAG_EN_MAGIC_PKT,
397 RTW_WOW_FLAG_EN_REKEY_PKT,
398 RTW_WOW_FLAG_EN_DISCONNECT,
399
400
401 RTW_WOW_FLAG_MAX,
402};
403
404
405
406
407struct rtw_2g_1s_pwr_idx_diff {
408#ifdef __LITTLE_ENDIAN
409 s8 ofdm:4;
410 s8 bw20:4;
411#else
412 s8 bw20:4;
413 s8 ofdm:4;
414#endif
415} __packed;
416
417struct rtw_2g_ns_pwr_idx_diff {
418#ifdef __LITTLE_ENDIAN
419 s8 bw20:4;
420 s8 bw40:4;
421 s8 cck:4;
422 s8 ofdm:4;
423#else
424 s8 ofdm:4;
425 s8 cck:4;
426 s8 bw40:4;
427 s8 bw20:4;
428#endif
429} __packed;
430
431struct rtw_2g_txpwr_idx {
432 u8 cck_base[6];
433 u8 bw40_base[5];
434 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
435 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
436 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
437 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
438};
439
440struct rtw_5g_ht_1s_pwr_idx_diff {
441#ifdef __LITTLE_ENDIAN
442 s8 ofdm:4;
443 s8 bw20:4;
444#else
445 s8 bw20:4;
446 s8 ofdm:4;
447#endif
448} __packed;
449
450struct rtw_5g_ht_ns_pwr_idx_diff {
451#ifdef __LITTLE_ENDIAN
452 s8 bw20:4;
453 s8 bw40:4;
454#else
455 s8 bw40:4;
456 s8 bw20:4;
457#endif
458} __packed;
459
460struct rtw_5g_ofdm_ns_pwr_idx_diff {
461#ifdef __LITTLE_ENDIAN
462 s8 ofdm_3s:4;
463 s8 ofdm_2s:4;
464 s8 ofdm_4s:4;
465 s8 res:4;
466#else
467 s8 res:4;
468 s8 ofdm_4s:4;
469 s8 ofdm_2s:4;
470 s8 ofdm_3s:4;
471#endif
472} __packed;
473
474struct rtw_5g_vht_ns_pwr_idx_diff {
475#ifdef __LITTLE_ENDIAN
476 s8 bw160:4;
477 s8 bw80:4;
478#else
479 s8 bw80:4;
480 s8 bw160:4;
481#endif
482} __packed;
483
484struct rtw_5g_txpwr_idx {
485 u8 bw40_base[14];
486 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
487 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
488 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
489 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
490 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
491 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
492 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
493 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
494 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
495};
496
497struct rtw_txpwr_idx {
498 struct rtw_2g_txpwr_idx pwr_idx_2g;
499 struct rtw_5g_txpwr_idx pwr_idx_5g;
500};
501
502struct rtw_timer_list {
503 struct timer_list timer;
504 void (*function)(void *data);
505 void *args;
506};
507
508struct rtw_channel_params {
509 u8 center_chan;
510 u8 bandwidth;
511 u8 primary_chan_idx;
512
513
514
515 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
516};
517
518struct rtw_hw_reg {
519 u32 addr;
520 u32 mask;
521};
522
523struct rtw_ltecoex_addr {
524 u32 ctrl;
525 u32 wdata;
526 u32 rdata;
527};
528
529struct rtw_reg_domain {
530 u32 addr;
531 u32 mask;
532#define RTW_REG_DOMAIN_MAC32 0
533#define RTW_REG_DOMAIN_MAC16 1
534#define RTW_REG_DOMAIN_MAC8 2
535#define RTW_REG_DOMAIN_RF_A 3
536#define RTW_REG_DOMAIN_RF_B 4
537#define RTW_REG_DOMAIN_NL 0xFF
538 u8 domain;
539};
540
541struct rtw_rf_sipi_addr {
542 u32 hssi_1;
543 u32 hssi_2;
544 u32 lssi_read;
545 u32 lssi_read_pi;
546};
547
548struct rtw_backup_info {
549 u8 len;
550 u32 reg;
551 u32 val;
552};
553
554enum rtw_vif_port_set {
555 PORT_SET_MAC_ADDR = BIT(0),
556 PORT_SET_BSSID = BIT(1),
557 PORT_SET_NET_TYPE = BIT(2),
558 PORT_SET_AID = BIT(3),
559 PORT_SET_BCN_CTRL = BIT(4),
560};
561
562struct rtw_vif_port {
563 struct rtw_hw_reg mac_addr;
564 struct rtw_hw_reg bssid;
565 struct rtw_hw_reg net_type;
566 struct rtw_hw_reg aid;
567 struct rtw_hw_reg bcn_ctrl;
568};
569
570struct rtw_tx_pkt_info {
571 u32 tx_pkt_size;
572 u8 offset;
573 u8 pkt_offset;
574 u8 mac_id;
575 u8 rate_id;
576 u8 rate;
577 u8 qsel;
578 u8 bw;
579 u8 sec_type;
580 u8 sn;
581 bool ampdu_en;
582 u8 ampdu_factor;
583 u8 ampdu_density;
584 u16 seq;
585 bool stbc;
586 bool ldpc;
587 bool dis_rate_fallback;
588 bool bmc;
589 bool use_rate;
590 bool ls;
591 bool fs;
592 bool short_gi;
593 bool report;
594 bool rts;
595 bool dis_qselseq;
596 bool en_hwseq;
597 u8 hw_ssn_sel;
598 bool nav_use_hdr;
599 bool bt_null;
600};
601
602struct rtw_rx_pkt_stat {
603 bool phy_status;
604 bool icv_err;
605 bool crc_err;
606 bool decrypted;
607 bool is_c2h;
608
609 s32 signal_power;
610 u16 pkt_len;
611 u8 bw;
612 u8 drv_info_sz;
613 u8 shift;
614 u8 rate;
615 u8 mac_id;
616 u8 cam_id;
617 u8 ppdu_cnt;
618 u32 tsf_low;
619 s8 rx_power[RTW_RF_PATH_MAX];
620 u8 rssi;
621 u8 rxsc;
622 s8 rx_snr[RTW_RF_PATH_MAX];
623 u8 rx_evm[RTW_RF_PATH_MAX];
624 s8 cfo_tail[RTW_RF_PATH_MAX];
625
626 struct rtw_sta_info *si;
627 struct ieee80211_vif *vif;
628 struct ieee80211_hdr *hdr;
629};
630
631DECLARE_EWMA(tp, 10, 2);
632
633struct rtw_traffic_stats {
634
635 u64 tx_unicast;
636 u64 rx_unicast;
637
638
639 u64 tx_cnt;
640 u64 rx_cnt;
641
642
643 u32 tx_throughput;
644 u32 rx_throughput;
645 struct ewma_tp tx_ewma_tp;
646 struct ewma_tp rx_ewma_tp;
647};
648
649enum rtw_lps_mode {
650 RTW_MODE_ACTIVE = 0,
651 RTW_MODE_LPS = 1,
652 RTW_MODE_WMM_PS = 2,
653};
654
655enum rtw_lps_deep_mode {
656 LPS_DEEP_MODE_NONE = 0,
657 LPS_DEEP_MODE_LCLK = 1,
658 LPS_DEEP_MODE_PG = 2,
659};
660
661enum rtw_pwr_state {
662 RTW_RF_OFF = 0x0,
663 RTW_RF_ON = 0x4,
664 RTW_ALL_ON = 0xc,
665};
666
667struct rtw_lps_conf {
668 enum rtw_lps_mode mode;
669 enum rtw_lps_deep_mode deep_mode;
670 enum rtw_lps_deep_mode wow_deep_mode;
671 enum rtw_pwr_state state;
672 u8 awake_interval;
673 u8 rlbm;
674 u8 smart_ps;
675 u8 port_id;
676 bool sec_cam_backup;
677 bool pattern_cam_backup;
678};
679
680enum rtw_hw_key_type {
681 RTW_CAM_NONE = 0,
682 RTW_CAM_WEP40 = 1,
683 RTW_CAM_TKIP = 2,
684 RTW_CAM_AES = 4,
685 RTW_CAM_WEP104 = 5,
686};
687
688struct rtw_cam_entry {
689 bool valid;
690 bool group;
691 u8 addr[ETH_ALEN];
692 u8 hw_key_type;
693 struct ieee80211_key_conf *key;
694};
695
696struct rtw_sec_desc {
697
698 bool default_key_search;
699
700 u32 total_cam_num;
701 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
702 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
703};
704
705struct rtw_tx_report {
706
707 spinlock_t q_lock;
708 struct sk_buff_head queue;
709 atomic_t sn;
710 struct timer_list purge_timer;
711};
712
713struct rtw_ra_report {
714 struct rate_info txrate;
715 u32 bit_rate;
716 u8 desc_rate;
717};
718
719struct rtw_txq {
720 struct list_head list;
721
722 unsigned long flags;
723 unsigned long last_push;
724};
725
726#define RTW_BC_MC_MACID 1
727DECLARE_EWMA(rssi, 10, 16);
728
729struct rtw_sta_info {
730 struct ieee80211_sta *sta;
731 struct ieee80211_vif *vif;
732
733 struct ewma_rssi avg_rssi;
734 u8 rssi_level;
735
736 u8 mac_id;
737 u8 rate_id;
738 enum rtw_bandwidth bw_mode;
739 enum rtw_rf_type rf_type;
740 enum rtw_wireless_set wireless_set;
741 u8 stbc_en:2;
742 u8 ldpc_en:2;
743 bool sgi_enable;
744 bool vht_enable;
745 bool updated;
746 u8 init_ra_lv;
747 u64 ra_mask;
748
749 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
750
751 struct rtw_ra_report ra_report;
752
753 bool use_cfg_mask;
754 struct cfg80211_bitrate_mask *mask;
755};
756
757enum rtw_bfee_role {
758 RTW_BFEE_NONE,
759 RTW_BFEE_SU,
760 RTW_BFEE_MU
761};
762
763struct rtw_bfee {
764 enum rtw_bfee_role role;
765
766 u16 p_aid;
767 u8 g_id;
768 u8 mac_addr[ETH_ALEN];
769 u8 sound_dim;
770
771
772 u8 su_reg_index;
773
774
775 u16 aid;
776};
777
778struct rtw_bf_info {
779 u8 bfer_mu_cnt;
780 u8 bfer_su_cnt;
781 DECLARE_BITMAP(bfer_su_reg_maping, 2);
782 u8 cur_csi_rpt_rate;
783};
784
785struct rtw_vif {
786 enum rtw_net_type net_type;
787 u16 aid;
788 u8 mac_addr[ETH_ALEN];
789 u8 bssid[ETH_ALEN];
790 u8 port;
791 u8 bcn_ctrl;
792 struct list_head rsvd_page_list;
793 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
794 const struct rtw_vif_port *conf;
795
796 struct rtw_traffic_stats stats;
797
798 struct rtw_bfee bfee;
799};
800
801struct rtw_regulatory {
802 char alpha2[2];
803 u8 chplan;
804 u8 txpwr_regd;
805};
806
807struct rtw_chip_ops {
808 int (*mac_init)(struct rtw_dev *rtwdev);
809 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
810 void (*shutdown)(struct rtw_dev *rtwdev);
811 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
812 void (*phy_set_param)(struct rtw_dev *rtwdev);
813 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
814 u8 bandwidth, u8 primary_chan_idx);
815 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
816 struct rtw_rx_pkt_stat *pkt_stat,
817 struct ieee80211_rx_status *rx_status);
818 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
819 u32 addr, u32 mask);
820 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
821 u32 addr, u32 mask, u32 data);
822 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
823 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
824 u32 size);
825 int (*set_antenna)(struct rtw_dev *rtwdev,
826 u32 antenna_tx,
827 u32 antenna_rx);
828 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
829 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
830 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
831 void (*phy_calibration)(struct rtw_dev *rtwdev);
832 void (*dpk_track)(struct rtw_dev *rtwdev);
833 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
834 void (*pwr_track)(struct rtw_dev *rtwdev);
835 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
836 struct rtw_bfee *bfee, bool enable);
837 void (*set_gid_table)(struct rtw_dev *rtwdev,
838 struct ieee80211_vif *vif,
839 struct ieee80211_bss_conf *conf);
840 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
841 u8 fixrate_en, u8 *new_rate);
842 void (*cfo_init)(struct rtw_dev *rtwdev);
843 void (*cfo_track)(struct rtw_dev *rtwdev);
844 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
845 enum rtw_bb_path tx_path_1ss,
846 enum rtw_bb_path tx_path_cck,
847 bool is_tx2_path);
848
849
850 void (*coex_set_init)(struct rtw_dev *rtwdev);
851 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
852 u8 ctrl_type, u8 pos_type);
853 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
854 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
855 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
856 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
857 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
858};
859
860#define RTW_PWR_POLLING_CNT 20000
861
862#define RTW_PWR_CMD_READ 0x00
863#define RTW_PWR_CMD_WRITE 0x01
864#define RTW_PWR_CMD_POLLING 0x02
865#define RTW_PWR_CMD_DELAY 0x03
866#define RTW_PWR_CMD_END 0x04
867
868
869#define RTW_PWR_ADDR_MAC 0x00
870#define RTW_PWR_ADDR_USB 0x01
871#define RTW_PWR_ADDR_PCIE 0x02
872#define RTW_PWR_ADDR_SDIO 0x03
873
874#define RTW_PWR_INTF_SDIO_MSK BIT(0)
875#define RTW_PWR_INTF_USB_MSK BIT(1)
876#define RTW_PWR_INTF_PCI_MSK BIT(2)
877#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
878
879#define RTW_PWR_CUT_TEST_MSK BIT(0)
880#define RTW_PWR_CUT_A_MSK BIT(1)
881#define RTW_PWR_CUT_B_MSK BIT(2)
882#define RTW_PWR_CUT_C_MSK BIT(3)
883#define RTW_PWR_CUT_D_MSK BIT(4)
884#define RTW_PWR_CUT_E_MSK BIT(5)
885#define RTW_PWR_CUT_F_MSK BIT(6)
886#define RTW_PWR_CUT_G_MSK BIT(7)
887#define RTW_PWR_CUT_ALL_MSK 0xFF
888
889enum rtw_pwr_seq_cmd_delay_unit {
890 RTW_PWR_DELAY_US,
891 RTW_PWR_DELAY_MS,
892};
893
894struct rtw_pwr_seq_cmd {
895 u16 offset;
896 u8 cut_mask;
897 u8 intf_mask;
898 u8 base:4;
899 u8 cmd:4;
900 u8 mask;
901 u8 value;
902};
903
904enum rtw_chip_ver {
905 RTW_CHIP_VER_CUT_A = 0x00,
906 RTW_CHIP_VER_CUT_B = 0x01,
907 RTW_CHIP_VER_CUT_C = 0x02,
908 RTW_CHIP_VER_CUT_D = 0x03,
909 RTW_CHIP_VER_CUT_E = 0x04,
910 RTW_CHIP_VER_CUT_F = 0x05,
911 RTW_CHIP_VER_CUT_G = 0x06,
912};
913
914#define RTW_INTF_PHY_PLATFORM_ALL 0
915
916enum rtw_intf_phy_cut {
917 RTW_INTF_PHY_CUT_A = BIT(0),
918 RTW_INTF_PHY_CUT_B = BIT(1),
919 RTW_INTF_PHY_CUT_C = BIT(2),
920 RTW_INTF_PHY_CUT_D = BIT(3),
921 RTW_INTF_PHY_CUT_E = BIT(4),
922 RTW_INTF_PHY_CUT_F = BIT(5),
923 RTW_INTF_PHY_CUT_G = BIT(6),
924 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
925};
926
927enum rtw_ip_sel {
928 RTW_IP_SEL_PHY = 0,
929 RTW_IP_SEL_MAC = 1,
930 RTW_IP_SEL_DBI = 2,
931
932 RTW_IP_SEL_UNDEF = 0xFFFF
933};
934
935enum rtw_pq_map_id {
936 RTW_PQ_MAP_VO = 0x0,
937 RTW_PQ_MAP_VI = 0x1,
938 RTW_PQ_MAP_BE = 0x2,
939 RTW_PQ_MAP_BK = 0x3,
940 RTW_PQ_MAP_MG = 0x4,
941 RTW_PQ_MAP_HI = 0x5,
942 RTW_PQ_MAP_NUM = 0x6,
943
944 RTW_PQ_MAP_UNDEF,
945};
946
947enum rtw_dma_mapping {
948 RTW_DMA_MAPPING_EXTRA = 0,
949 RTW_DMA_MAPPING_LOW = 1,
950 RTW_DMA_MAPPING_NORMAL = 2,
951 RTW_DMA_MAPPING_HIGH = 3,
952
953 RTW_DMA_MAPPING_MAX,
954 RTW_DMA_MAPPING_UNDEF,
955};
956
957struct rtw_rqpn {
958 enum rtw_dma_mapping dma_map_vo;
959 enum rtw_dma_mapping dma_map_vi;
960 enum rtw_dma_mapping dma_map_be;
961 enum rtw_dma_mapping dma_map_bk;
962 enum rtw_dma_mapping dma_map_mg;
963 enum rtw_dma_mapping dma_map_hi;
964};
965
966struct rtw_prioq_addr {
967 u32 rsvd;
968 u32 avail;
969};
970
971struct rtw_prioq_addrs {
972 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
973 bool wsize;
974};
975
976struct rtw_page_table {
977 u16 hq_num;
978 u16 nq_num;
979 u16 lq_num;
980 u16 exq_num;
981 u16 gapq_num;
982};
983
984struct rtw_intf_phy_para {
985 u16 offset;
986 u16 value;
987 u16 ip_sel;
988 u16 cut_mask;
989 u16 platform;
990};
991
992struct rtw_wow_pattern {
993 u16 crc;
994 u8 type;
995 u8 valid;
996 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
997};
998
999struct rtw_pno_request {
1000 bool inited;
1001 u32 match_set_cnt;
1002 struct cfg80211_match_set *match_sets;
1003 u8 channel_cnt;
1004 struct ieee80211_channel *channels;
1005 struct cfg80211_sched_scan_plan scan_plan;
1006};
1007
1008struct rtw_wow_param {
1009 struct ieee80211_vif *wow_vif;
1010 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1011 u8 txpause;
1012 u8 pattern_cnt;
1013 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1014
1015 bool ips_enabled;
1016 struct rtw_pno_request pno_req;
1017};
1018
1019struct rtw_intf_phy_para_table {
1020 const struct rtw_intf_phy_para *usb2_para;
1021 const struct rtw_intf_phy_para *usb3_para;
1022 const struct rtw_intf_phy_para *gen1_para;
1023 const struct rtw_intf_phy_para *gen2_para;
1024 u8 n_usb2_para;
1025 u8 n_usb3_para;
1026 u8 n_gen1_para;
1027 u8 n_gen2_para;
1028};
1029
1030struct rtw_table {
1031 const void *data;
1032 const u32 size;
1033 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1034 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1035 u32 addr, u32 data);
1036 enum rtw_rf_path rf_path;
1037};
1038
1039static inline void rtw_load_table(struct rtw_dev *rtwdev,
1040 const struct rtw_table *tbl)
1041{
1042 (*tbl->parse)(rtwdev, tbl);
1043}
1044
1045enum rtw_rfe_fem {
1046 RTW_RFE_IFEM,
1047 RTW_RFE_EFEM,
1048 RTW_RFE_IFEM2G_EFEM5G,
1049 RTW_RFE_NUM,
1050};
1051
1052struct rtw_rfe_def {
1053 const struct rtw_table *phy_pg_tbl;
1054 const struct rtw_table *txpwr_lmt_tbl;
1055 const struct rtw_table *agc_btg_tbl;
1056};
1057
1058#define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1059 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1060 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1061 }
1062
1063#define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1064 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1065 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1066 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1067 }
1068
1069#define RTW_PWR_TRK_5G_1 0
1070#define RTW_PWR_TRK_5G_2 1
1071#define RTW_PWR_TRK_5G_3 2
1072#define RTW_PWR_TRK_5G_NUM 3
1073
1074#define RTW_PWR_TRK_TBL_SZ 30
1075
1076
1077
1078
1079
1080
1081
1082struct rtw_pwr_track_tbl {
1083 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1084 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1085 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1086 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1087 const u8 *pwrtrk_2gb_n;
1088 const u8 *pwrtrk_2gb_p;
1089 const u8 *pwrtrk_2ga_n;
1090 const u8 *pwrtrk_2ga_p;
1091 const u8 *pwrtrk_2g_cckb_n;
1092 const u8 *pwrtrk_2g_cckb_p;
1093 const u8 *pwrtrk_2g_ccka_n;
1094 const u8 *pwrtrk_2g_ccka_p;
1095 const s8 *pwrtrk_xtal_n;
1096 const s8 *pwrtrk_xtal_p;
1097};
1098
1099enum rtw_wlan_cpu {
1100 RTW_WCPU_11AC,
1101 RTW_WCPU_11N,
1102};
1103
1104enum rtw_fw_fifo_sel {
1105 RTW_FW_FIFO_SEL_TX,
1106 RTW_FW_FIFO_SEL_RX,
1107 RTW_FW_FIFO_SEL_RSVD_PAGE,
1108 RTW_FW_FIFO_SEL_REPORT,
1109 RTW_FW_FIFO_SEL_LLT,
1110 RTW_FW_FIFO_SEL_RXBUF_FW,
1111
1112 RTW_FW_FIFO_MAX,
1113};
1114
1115enum rtw_fwcd_item {
1116 RTW_FWCD_TLV,
1117 RTW_FWCD_REG,
1118 RTW_FWCD_ROM,
1119 RTW_FWCD_IMEM,
1120 RTW_FWCD_DMEM,
1121 RTW_FWCD_EMEM,
1122};
1123
1124
1125struct rtw_chip_info {
1126 struct rtw_chip_ops *ops;
1127 u8 id;
1128
1129 const char *fw_name;
1130 enum rtw_wlan_cpu wlan_cpu;
1131 u8 tx_pkt_desc_sz;
1132 u8 tx_buf_desc_sz;
1133 u8 rx_pkt_desc_sz;
1134 u8 rx_buf_desc_sz;
1135 u32 phy_efuse_size;
1136 u32 log_efuse_size;
1137 u32 ptct_efuse_size;
1138 u32 txff_size;
1139 u32 rxff_size;
1140 u32 fw_rxff_size;
1141 u8 band;
1142 u8 page_size;
1143 u8 csi_buf_pg_num;
1144 u8 dig_max;
1145 u8 dig_min;
1146 u8 txgi_factor;
1147 bool is_pwr_by_rate_dec;
1148 bool rx_ldpc;
1149 bool tx_stbc;
1150 u8 max_power_index;
1151
1152 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1153 const struct rtw_fwcd_segs *fwcd_segs;
1154
1155 u8 default_1ss_tx_path;
1156
1157 bool path_div_supported;
1158 bool ht_supported;
1159 bool vht_supported;
1160 u8 lps_deep_mode_supported;
1161
1162
1163 u8 sys_func_en;
1164 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1165 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1166 const struct rtw_rqpn *rqpn_table;
1167 const struct rtw_prioq_addrs *prioq_addrs;
1168 const struct rtw_page_table *page_table;
1169 const struct rtw_intf_phy_para_table *intf_table;
1170
1171 const struct rtw_hw_reg *dig;
1172 const struct rtw_hw_reg *dig_cck;
1173 u32 rf_base_addr[2];
1174 u32 rf_sipi_addr[2];
1175 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1176 u8 fix_rf_phy_num;
1177 const struct rtw_ltecoex_addr *ltecoex_addr;
1178
1179 const struct rtw_table *mac_tbl;
1180 const struct rtw_table *agc_tbl;
1181 const struct rtw_table *bb_tbl;
1182 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1183 const struct rtw_table *rfk_init_tbl;
1184
1185 const struct rtw_rfe_def *rfe_defs;
1186 u32 rfe_defs_size;
1187
1188 bool en_dis_dpd;
1189 u16 dpd_ratemask;
1190 u8 iqk_threshold;
1191 u8 lck_threshold;
1192 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1193
1194 u8 bfer_su_max_num;
1195 u8 bfer_mu_max_num;
1196
1197 const char *wow_fw_name;
1198 const struct wiphy_wowlan_support *wowlan_stub;
1199 const u8 max_sched_scan_ssids;
1200
1201
1202 u32 ch_param[3];
1203
1204
1205 u32 coex_para_ver;
1206 u8 bt_desired_ver;
1207 bool scbd_support;
1208 bool new_scbd10_def;
1209 bool ble_hid_profile_support;
1210 u8 pstdma_type;
1211 u8 bt_rssi_type;
1212 u8 ant_isolation;
1213 u8 rssi_tolerance;
1214 u8 table_sant_num;
1215 u8 table_nsant_num;
1216 u8 tdma_sant_num;
1217 u8 tdma_nsant_num;
1218 u8 bt_afh_span_bw20;
1219 u8 bt_afh_span_bw40;
1220 u8 afh_5g_num;
1221 u8 wl_rf_para_num;
1222 u8 coex_info_hw_regs_num;
1223 const u8 *bt_rssi_step;
1224 const u8 *wl_rssi_step;
1225 const struct coex_table_para *table_nsant;
1226 const struct coex_table_para *table_sant;
1227 const struct coex_tdma_para *tdma_sant;
1228 const struct coex_tdma_para *tdma_nsant;
1229 const struct coex_rf_para *wl_rf_para_tx;
1230 const struct coex_rf_para *wl_rf_para_rx;
1231 const struct coex_5g_afh_map *afh_5g;
1232 const struct rtw_hw_reg *btg_reg;
1233 const struct rtw_reg_domain *coex_info_hw_regs;
1234 u32 wl_fw_desired_ver;
1235};
1236
1237enum rtw_coex_bt_state_cnt {
1238 COEX_CNT_BT_RETRY,
1239 COEX_CNT_BT_REINIT,
1240 COEX_CNT_BT_REENABLE,
1241 COEX_CNT_BT_POPEVENT,
1242 COEX_CNT_BT_SETUPLINK,
1243 COEX_CNT_BT_IGNWLANACT,
1244 COEX_CNT_BT_INQ,
1245 COEX_CNT_BT_PAGE,
1246 COEX_CNT_BT_ROLESWITCH,
1247 COEX_CNT_BT_AFHUPDATE,
1248 COEX_CNT_BT_INFOUPDATE,
1249 COEX_CNT_BT_IQK,
1250 COEX_CNT_BT_IQKFAIL,
1251
1252 COEX_CNT_BT_MAX
1253};
1254
1255enum rtw_coex_wl_state_cnt {
1256 COEX_CNT_WL_SCANAP,
1257 COEX_CNT_WL_CONNPKT,
1258 COEX_CNT_WL_COEXRUN,
1259 COEX_CNT_WL_NOISY0,
1260 COEX_CNT_WL_NOISY1,
1261 COEX_CNT_WL_NOISY2,
1262 COEX_CNT_WL_5MS_NOEXTEND,
1263 COEX_CNT_WL_FW_NOTIFY,
1264
1265 COEX_CNT_WL_MAX
1266};
1267
1268struct rtw_coex_rfe {
1269 bool ant_switch_exist;
1270 bool ant_switch_diversity;
1271 bool ant_switch_with_bt;
1272 u8 rfe_module_type;
1273 u8 ant_switch_polarity;
1274
1275
1276 bool wlg_at_btg;
1277};
1278
1279#define COEX_WL_TDMA_PARA_LENGTH 5
1280
1281struct rtw_coex_dm {
1282 bool cur_ps_tdma_on;
1283 bool cur_wl_rx_low_gain_en;
1284 bool ignore_wl_act;
1285
1286 u8 reason;
1287 u8 bt_rssi_state[4];
1288 u8 wl_rssi_state[4];
1289 u8 wl_ch_info[3];
1290 u8 cur_ps_tdma;
1291 u8 cur_table;
1292 u8 ps_tdma_para[5];
1293 u8 cur_bt_pwr_lvl;
1294 u8 cur_bt_lna_lvl;
1295 u8 cur_wl_pwr_lvl;
1296 u8 bt_status;
1297 u32 cur_ant_pos_type;
1298 u32 cur_switch_status;
1299 u32 setting_tdma;
1300 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1301};
1302
1303#define COEX_BTINFO_SRC_WL_FW 0x0
1304#define COEX_BTINFO_SRC_BT_RSP 0x1
1305#define COEX_BTINFO_SRC_BT_ACT 0x2
1306#define COEX_BTINFO_SRC_BT_IQK 0x3
1307#define COEX_BTINFO_SRC_BT_SCBD 0x4
1308#define COEX_BTINFO_SRC_H2C60 0x5
1309#define COEX_BTINFO_SRC_MAX 0x6
1310
1311#define COEX_INFO_FTP BIT(7)
1312#define COEX_INFO_A2DP BIT(6)
1313#define COEX_INFO_HID BIT(5)
1314#define COEX_INFO_SCO_BUSY BIT(4)
1315#define COEX_INFO_ACL_BUSY BIT(3)
1316#define COEX_INFO_INQ_PAGE BIT(2)
1317#define COEX_INFO_SCO_ESCO BIT(1)
1318#define COEX_INFO_CONNECTION BIT(0)
1319#define COEX_BTINFO_LENGTH_MAX 10
1320#define COEX_BTINFO_LENGTH 7
1321
1322struct rtw_coex_stat {
1323 bool bt_disabled;
1324 bool bt_disabled_pre;
1325 bool bt_link_exist;
1326 bool bt_whck_test;
1327 bool bt_inq_page;
1328 bool bt_inq_remain;
1329 bool bt_inq;
1330 bool bt_page;
1331 bool bt_ble_voice;
1332 bool bt_ble_exist;
1333 bool bt_hfp_exist;
1334 bool bt_a2dp_exist;
1335 bool bt_hid_exist;
1336 bool bt_pan_exist;
1337 bool bt_opp_exist;
1338 bool bt_acl_busy;
1339 bool bt_fix_2M;
1340 bool bt_setup_link;
1341 bool bt_multi_link;
1342 bool bt_multi_link_pre;
1343 bool bt_multi_link_remain;
1344 bool bt_a2dp_sink;
1345 bool bt_a2dp_active;
1346 bool bt_reenable;
1347 bool bt_ble_scan_en;
1348 bool bt_init_scan;
1349 bool bt_slave;
1350 bool bt_418_hid_exist;
1351 bool bt_ble_hid_exist;
1352 bool bt_mailbox_reply;
1353
1354 bool wl_under_lps;
1355 bool wl_under_ips;
1356 bool wl_hi_pri_task1;
1357 bool wl_hi_pri_task2;
1358 bool wl_force_lps_ctrl;
1359 bool wl_gl_busy;
1360 bool wl_linkscan_proc;
1361 bool wl_ps_state_fail;
1362 bool wl_tx_limit_en;
1363 bool wl_ampdu_limit_en;
1364 bool wl_connected;
1365 bool wl_slot_extend;
1366 bool wl_cck_lock;
1367 bool wl_cck_lock_pre;
1368 bool wl_cck_lock_ever;
1369 bool wl_connecting;
1370 bool wl_slot_toggle;
1371 bool wl_slot_toggle_change;
1372
1373 u32 bt_supported_version;
1374 u32 bt_supported_feature;
1375 u32 hi_pri_tx;
1376 u32 hi_pri_rx;
1377 u32 lo_pri_tx;
1378 u32 lo_pri_rx;
1379 u32 patch_ver;
1380 u16 bt_reg_vendor_ae;
1381 u16 bt_reg_vendor_ac;
1382 s8 bt_rssi;
1383 u8 kt_ver;
1384 u8 gnt_workaround_state;
1385 u8 tdma_timer_base;
1386 u8 bt_profile_num;
1387 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1388 u8 bt_info_lb2;
1389 u8 bt_info_lb3;
1390 u8 bt_info_hb0;
1391 u8 bt_info_hb1;
1392 u8 bt_info_hb2;
1393 u8 bt_info_hb3;
1394 u8 bt_ble_scan_type;
1395 u8 bt_hid_pair_num;
1396 u8 bt_hid_slot;
1397 u8 bt_a2dp_bitpool;
1398 u8 bt_iqk_state;
1399
1400 u16 wl_beacon_interval;
1401 u8 wl_noisy_level;
1402 u8 wl_fw_dbg_info[10];
1403 u8 wl_fw_dbg_info_pre[10];
1404 u8 wl_rx_rate;
1405 u8 wl_tx_rate;
1406 u8 wl_rts_rx_rate;
1407 u8 wl_coex_mode;
1408 u8 wl_iot_peer;
1409 u8 ampdu_max_time;
1410 u8 wl_tput_dir;
1411
1412 u8 wl_toggle_para[6];
1413 u8 wl_toggle_interval;
1414
1415 u16 score_board;
1416 u16 retry_limit;
1417
1418
1419 u32 cnt_bt[COEX_CNT_BT_MAX];
1420
1421
1422 u32 cnt_wl[COEX_CNT_WL_MAX];
1423
1424
1425 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1426
1427 u32 darfrc;
1428 u32 darfrch;
1429};
1430
1431struct rtw_coex {
1432
1433 struct mutex mutex;
1434 struct sk_buff_head queue;
1435 wait_queue_head_t wait;
1436
1437 bool under_5g;
1438 bool stop_dm;
1439 bool freeze;
1440 bool freerun;
1441 bool wl_rf_off;
1442 bool manual_control;
1443
1444 struct rtw_coex_stat stat;
1445 struct rtw_coex_dm dm;
1446 struct rtw_coex_rfe rfe;
1447
1448 struct delayed_work bt_relink_work;
1449 struct delayed_work bt_reenable_work;
1450 struct delayed_work defreeze_work;
1451 struct delayed_work wl_remain_work;
1452 struct delayed_work bt_remain_work;
1453 struct delayed_work wl_connecting_work;
1454 struct delayed_work bt_multi_link_remain_work;
1455 struct delayed_work wl_ccklock_work;
1456
1457};
1458
1459#define DPK_RF_REG_NUM 7
1460#define DPK_RF_PATH_NUM 2
1461#define DPK_BB_REG_NUM 18
1462#define DPK_CHANNEL_WIDTH_80 1
1463
1464DECLARE_EWMA(thermal, 10, 4);
1465
1466struct rtw_dpk_info {
1467 bool is_dpk_pwr_on;
1468 bool is_reload;
1469
1470 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1471
1472 u8 thermal_dpk[DPK_RF_PATH_NUM];
1473 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1474
1475 u32 gnt_control;
1476 u32 gnt_value;
1477
1478 u8 result[RTW_RF_PATH_MAX];
1479 u8 dpk_txagc[RTW_RF_PATH_MAX];
1480 u32 coef[RTW_RF_PATH_MAX][20];
1481 u16 dpk_gs[RTW_RF_PATH_MAX];
1482 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1483 u8 pre_pwsf[RTW_RF_PATH_MAX];
1484
1485 u8 dpk_band;
1486 u8 dpk_ch;
1487 u8 dpk_bw;
1488};
1489
1490struct rtw_phy_cck_pd_reg {
1491 u32 reg_pd;
1492 u32 mask_pd;
1493 u32 reg_cs;
1494 u32 mask_cs;
1495};
1496
1497#define DACK_MSBK_BACKUP_NUM 0xf
1498#define DACK_DCK_BACKUP_NUM 0x2
1499
1500struct rtw_swing_table {
1501 const u8 *p[RTW_RF_PATH_MAX];
1502 const u8 *n[RTW_RF_PATH_MAX];
1503};
1504
1505struct rtw_pkt_count {
1506 u16 num_bcn_pkt;
1507 u16 num_qry_pkt[DESC_RATE_MAX];
1508};
1509
1510DECLARE_EWMA(evm, 10, 4);
1511DECLARE_EWMA(snr, 10, 4);
1512
1513struct rtw_iqk_info {
1514 bool done;
1515 struct {
1516 u32 s1_x;
1517 u32 s1_y;
1518 u32 s0_x;
1519 u32 s0_y;
1520 } result;
1521};
1522
1523enum rtw_rf_band {
1524 RF_BAND_2G_CCK,
1525 RF_BAND_2G_OFDM,
1526 RF_BAND_5G_L,
1527 RF_BAND_5G_M,
1528 RF_BAND_5G_H,
1529 RF_BAND_MAX
1530};
1531
1532#define RF_GAIN_NUM 11
1533#define RF_HW_OFFSET_NUM 10
1534
1535struct rtw_gapk_info {
1536 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1537 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1538 bool txgapk_bp_done;
1539 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1540 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1541 u8 read_txgain;
1542 u8 channel;
1543};
1544
1545struct rtw_cfo_track {
1546 bool is_adjust;
1547 u8 crystal_cap;
1548 s32 cfo_tail[RTW_RF_PATH_MAX];
1549 s32 cfo_cnt[RTW_RF_PATH_MAX];
1550 u32 packet_count;
1551 u32 packet_count_pre;
1552};
1553
1554#define RRSR_INIT_2G 0x15f
1555#define RRSR_INIT_5G 0x150
1556
1557enum rtw_dm_cap {
1558 RTW_DM_CAP_NA,
1559 RTW_DM_CAP_TXGAPK,
1560 RTW_DM_CAP_NUM
1561};
1562
1563struct rtw_dm_info {
1564 u32 cck_fa_cnt;
1565 u32 ofdm_fa_cnt;
1566 u32 total_fa_cnt;
1567 u32 cck_cca_cnt;
1568 u32 ofdm_cca_cnt;
1569 u32 total_cca_cnt;
1570
1571 u32 cck_ok_cnt;
1572 u32 cck_err_cnt;
1573 u32 ofdm_ok_cnt;
1574 u32 ofdm_err_cnt;
1575 u32 ht_ok_cnt;
1576 u32 ht_err_cnt;
1577 u32 vht_ok_cnt;
1578 u32 vht_err_cnt;
1579
1580 u8 min_rssi;
1581 u8 pre_min_rssi;
1582 u16 fa_history[4];
1583 u8 igi_history[4];
1584 u8 igi_bitmap;
1585 bool damping;
1586 u8 damping_cnt;
1587 u8 damping_rssi;
1588
1589 u8 cck_gi_u_bnd;
1590 u8 cck_gi_l_bnd;
1591
1592 u8 tx_rate;
1593 u32 rrsr_val_init;
1594 u32 rrsr_mask_min;
1595 u8 thermal_avg[RTW_RF_PATH_MAX];
1596 u8 thermal_meter_k;
1597 u8 thermal_meter_lck;
1598 s8 delta_power_index[RTW_RF_PATH_MAX];
1599 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1600 u8 default_ofdm_index;
1601 bool pwr_trk_triggered;
1602 bool pwr_trk_init_trigger;
1603 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1604 s8 txagc_remnant_cck;
1605 s8 txagc_remnant_ofdm;
1606
1607
1608 u32 dack_adck[RTW_RF_PATH_MAX];
1609 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1610 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1611
1612 struct rtw_dpk_info dpk_info;
1613 struct rtw_cfo_track cfo_track;
1614
1615
1616 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1617 u32 cck_fa_avg;
1618 u8 cck_pd_default;
1619
1620
1621 s8 rx_snr[RTW_RF_PATH_MAX];
1622 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1623 s16 cfo_tail[RTW_RF_PATH_MAX];
1624 u8 rssi[RTW_RF_PATH_MAX];
1625 u8 curr_rx_rate;
1626 struct rtw_pkt_count cur_pkt_count;
1627 struct rtw_pkt_count last_pkt_count;
1628 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1629 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1630
1631 u32 dm_flags;
1632 struct rtw_iqk_info iqk;
1633 struct rtw_gapk_info gapk;
1634 bool is_bt_iqk_timeout;
1635
1636 u8 scan_density;
1637};
1638
1639struct rtw_efuse {
1640 u32 size;
1641 u32 physical_size;
1642 u32 logical_size;
1643 u32 protect_size;
1644
1645 u8 addr[ETH_ALEN];
1646 u8 channel_plan;
1647 u8 country_code[2];
1648 u8 rf_board_option;
1649 u8 rfe_option;
1650 u8 power_track_type;
1651 u8 thermal_meter[RTW_RF_PATH_MAX];
1652 u8 thermal_meter_k;
1653 u8 crystal_cap;
1654 u8 ant_div_cfg;
1655 u8 ant_div_type;
1656 u8 regd;
1657 u8 afe;
1658
1659 u8 lna_type_2g;
1660 u8 lna_type_5g;
1661 u8 glna_type;
1662 u8 alna_type;
1663 bool ext_lna_2g;
1664 bool ext_lna_5g;
1665 u8 pa_type_2g;
1666 u8 pa_type_5g;
1667 u8 gpa_type;
1668 u8 apa_type;
1669 bool ext_pa_2g;
1670 bool ext_pa_5g;
1671 u8 tx_bb_swing_setting_2g;
1672 u8 tx_bb_swing_setting_5g;
1673
1674 bool btcoex;
1675
1676 bool share_ant;
1677 u8 bt_setting;
1678
1679 struct {
1680 u8 hci;
1681 u8 bw;
1682 u8 ptcl;
1683 u8 nss;
1684 u8 ant_num;
1685 } hw_cap;
1686
1687 struct rtw_txpwr_idx txpwr_idx_table[4];
1688};
1689
1690struct rtw_phy_cond {
1691#ifdef __LITTLE_ENDIAN
1692 u32 rfe:8;
1693 u32 intf:4;
1694 u32 pkg:4;
1695 u32 plat:4;
1696 u32 intf_rsvd:4;
1697 u32 cut:4;
1698 u32 branch:2;
1699 u32 neg:1;
1700 u32 pos:1;
1701#else
1702 u32 pos:1;
1703 u32 neg:1;
1704 u32 branch:2;
1705 u32 cut:4;
1706 u32 intf_rsvd:4;
1707 u32 plat:4;
1708 u32 pkg:4;
1709 u32 intf:4;
1710 u32 rfe:8;
1711#endif
1712
1713 #define INTF_PCIE BIT(0)
1714 #define INTF_USB BIT(1)
1715 #define INTF_SDIO BIT(2)
1716
1717 #define BRANCH_IF 0
1718 #define BRANCH_ELIF 1
1719 #define BRANCH_ELSE 2
1720 #define BRANCH_ENDIF 3
1721};
1722
1723struct rtw_fifo_conf {
1724
1725 u16 rsvd_boundary;
1726 u16 rsvd_pg_num;
1727 u16 rsvd_drv_pg_num;
1728 u16 txff_pg_num;
1729 u16 acq_pg_num;
1730 u16 rsvd_drv_addr;
1731 u16 rsvd_h2c_info_addr;
1732 u16 rsvd_h2c_sta_info_addr;
1733 u16 rsvd_h2cq_addr;
1734 u16 rsvd_cpu_instr_addr;
1735 u16 rsvd_fw_txbuf_addr;
1736 u16 rsvd_csibuf_addr;
1737 const struct rtw_rqpn *rqpn;
1738};
1739
1740struct rtw_fwcd_desc {
1741 u32 size;
1742 u8 *next;
1743 u8 *data;
1744};
1745
1746struct rtw_fwcd_segs {
1747 const u32 *segs;
1748 u8 num;
1749};
1750
1751#define FW_CD_TYPE 0xffff
1752#define FW_CD_LEN 4
1753#define FW_CD_VAL 0xaabbccdd
1754struct rtw_fw_state {
1755 const struct firmware *firmware;
1756 struct rtw_dev *rtwdev;
1757 struct completion completion;
1758 struct rtw_fwcd_desc fwcd_desc;
1759 u16 version;
1760 u8 sub_version;
1761 u8 sub_index;
1762 u16 h2c_version;
1763 u32 feature;
1764};
1765
1766struct rtw_hal {
1767 u32 rcr;
1768
1769 u32 chip_version;
1770 u8 cut_version;
1771 u8 mp_chip;
1772 u8 oem_id;
1773 struct rtw_phy_cond phy_cond;
1774
1775 u8 ps_mode;
1776 u8 current_channel;
1777 u8 current_band_width;
1778 u8 current_band_type;
1779
1780
1781
1782
1783 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1784
1785 u8 sec_ch_offset;
1786 u8 rf_type;
1787 u8 rf_path_num;
1788 u8 rf_phy_num;
1789 u32 antenna_tx;
1790 u32 antenna_rx;
1791 u8 bfee_sts_cap;
1792
1793
1794 struct mutex tx_power_mutex;
1795 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1796 [DESC_RATE_MAX];
1797 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1798 [DESC_RATE_MAX];
1799 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1800 [RTW_RATE_SECTION_MAX];
1801 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1802 [RTW_RATE_SECTION_MAX];
1803 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1804 [RTW_CHANNEL_WIDTH_MAX]
1805 [RTW_RATE_SECTION_MAX]
1806 [RTW_MAX_CHANNEL_NUM_2G];
1807 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1808 [RTW_CHANNEL_WIDTH_MAX]
1809 [RTW_RATE_SECTION_MAX]
1810 [RTW_MAX_CHANNEL_NUM_5G];
1811 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1812 [DESC_RATE_MAX];
1813};
1814
1815struct rtw_path_div {
1816 enum rtw_bb_path current_tx_path;
1817 u32 path_a_sum;
1818 u32 path_b_sum;
1819 u16 path_a_cnt;
1820 u16 path_b_cnt;
1821};
1822
1823struct rtw_dev {
1824 struct ieee80211_hw *hw;
1825 struct device *dev;
1826
1827 struct rtw_hci hci;
1828
1829 struct rtw_chip_info *chip;
1830 struct rtw_hal hal;
1831 struct rtw_fifo_conf fifo;
1832 struct rtw_fw_state fw;
1833 struct rtw_efuse efuse;
1834 struct rtw_sec_desc sec;
1835 struct rtw_traffic_stats stats;
1836 struct rtw_regulatory regd;
1837 struct rtw_bf_info bf_info;
1838
1839 struct rtw_dm_info dm_info;
1840 struct rtw_coex coex;
1841
1842
1843 struct mutex mutex;
1844
1845
1846 spinlock_t rf_lock;
1847
1848
1849 struct delayed_work watch_dog_work;
1850 u32 watch_dog_cnt;
1851
1852 struct list_head rsvd_page_list;
1853
1854
1855 struct sk_buff_head c2h_queue;
1856 struct work_struct c2h_work;
1857 struct work_struct fw_recovery_work;
1858
1859
1860 spinlock_t txq_lock;
1861 struct list_head txqs;
1862 struct workqueue_struct *tx_wq;
1863 struct work_struct tx_work;
1864 struct work_struct ba_work;
1865
1866 struct rtw_tx_report tx_report;
1867
1868 struct {
1869
1870 u8 last_box_num;
1871
1872 spinlock_t lock;
1873 u32 seq;
1874 } h2c;
1875
1876
1877 struct rtw_lps_conf lps_conf;
1878 bool ps_enabled;
1879 bool beacon_loss;
1880 struct completion lps_leave_check;
1881
1882 struct dentry *debugfs;
1883
1884 u8 sta_cnt;
1885 u32 rts_threshold;
1886
1887 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1888 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1889
1890 u8 mp_mode;
1891 struct rtw_path_div dm_path_div;
1892
1893 struct rtw_fw_state wow_fw;
1894 struct rtw_wow_param wow;
1895
1896 bool need_rfk;
1897 struct completion fw_scan_density;
1898
1899
1900 u8 priv[] __aligned(sizeof(void *));
1901};
1902
1903#include "hci.h"
1904
1905static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1906{
1907 return !!rtwdev->sta_cnt;
1908}
1909
1910static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
1911{
1912 void *p = rtwtxq;
1913
1914 return container_of(p, struct ieee80211_txq, drv_priv);
1915}
1916
1917static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
1918{
1919 void *p = rtwvif;
1920
1921 return container_of(p, struct ieee80211_vif, drv_priv);
1922}
1923
1924static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
1925 struct cfg80211_ssid *b)
1926{
1927 if (!a || !b || a->ssid_len != b->ssid_len)
1928 return false;
1929
1930 if (memcmp(a->ssid, b->ssid, a->ssid_len))
1931 return false;
1932
1933 return true;
1934}
1935
1936static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
1937{
1938 if (rtwdev->chip->ops->efuse_grant)
1939 rtwdev->chip->ops->efuse_grant(rtwdev, true);
1940}
1941
1942static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
1943{
1944 if (rtwdev->chip->ops->efuse_grant)
1945 rtwdev->chip->ops->efuse_grant(rtwdev, false);
1946}
1947
1948static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
1949{
1950 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
1951}
1952
1953static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
1954{
1955 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
1956}
1957
1958static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
1959{
1960 return rtwdev->chip->rx_ldpc;
1961}
1962
1963static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
1964{
1965 return rtwdev->chip->tx_stbc;
1966}
1967
1968static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
1969{
1970 clear_bit(mac_id, rtwdev->mac_id_map);
1971}
1972
1973static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
1974{
1975 if (rtwdev->chip->ops->dump_fw_crash)
1976 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
1977
1978 return 0;
1979}
1980
1981void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1982 struct rtw_channel_params *ch_param);
1983bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1984bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1985bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1986void rtw_restore_reg(struct rtw_dev *rtwdev,
1987 struct rtw_backup_info *bckp, u32 num);
1988void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
1989void rtw_set_channel(struct rtw_dev *rtwdev);
1990void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
1991void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1992 u32 config);
1993void rtw_tx_report_purge_timer(struct timer_list *t);
1994void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1995int rtw_core_start(struct rtw_dev *rtwdev);
1996void rtw_core_stop(struct rtw_dev *rtwdev);
1997int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1998int rtw_core_init(struct rtw_dev *rtwdev);
1999void rtw_core_deinit(struct rtw_dev *rtwdev);
2000int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2001void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2002u16 rtw_desc_to_bitrate(u8 desc_rate);
2003void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2004 struct ieee80211_bss_conf *conf);
2005int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2006 struct ieee80211_vif *vif);
2007void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2008 bool fw_exist);
2009void rtw_fw_recovery(struct rtw_dev *rtwdev);
2010void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2011int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2012 u32 fwcd_item);
2013int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2014
2015#endif
2016
