LXR linux/drivers/ntb/hw/amd/ntb_hw

   1/*
   2 * This file is provided under a dual BSD/GPLv2 license.  When using or
   3 *   redistributing this file, you may do so under either license.
   4 *
   5 *   GPL LICENSE SUMMARY
   6 *
   7 *   Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
   8 *
   9 *   This program is free software; you can redistribute it and/or modify
  10 *   it under the terms of version 2 of the GNU General Public License as
  11 *   published by the Free Software Foundation.
  12 *
  13 *   BSD LICENSE
  14 *
  15 *   Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
  16 *
  17 *   Redistribution and use in source and binary forms, with or without
  18 *   modification, are permitted provided that the following conditions
  19 *   are met:
  20 *
  21 *     * Redistributions of source code must retain the above copyright
  22 *       notice, this list of conditions and the following disclaimer.
  23 *     * Redistributions in binary form must reproduce the above copy
  24 *       notice, this list of conditions and the following disclaimer in
  25 *       the documentation and/or other materials provided with the
  26 *       distribution.
  27 *     * Neither the name of AMD Corporation nor the names of its
  28 *       contributors may be used to endorse or promote products derived
  29 *       from this software without specific prior written permission.
  30 *
  31 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 *
  43 * AMD PCIe NTB Linux driver
  44 *
  45 * Contact Information:
  46 * Xiangliang Yu <Xiangliang.Yu@amd.com>
  47 */
  48
  49#ifndef NTB_HW_AMD_H
  50#define NTB_HW_AMD_H
  51
  52#include <linux/ntb.h>
  53#include <linux/pci.h>
  54
  55#define AMD_LINK_HB_TIMEOUT     msecs_to_jiffies(1000)
  56#define NTB_LNK_STA_SPEED_MASK  0x000F0000
  57#define NTB_LNK_STA_WIDTH_MASK  0x03F00000
  58#define NTB_LNK_STA_SPEED(x)    (((x) & NTB_LNK_STA_SPEED_MASK) >> 16)
  59#define NTB_LNK_STA_WIDTH(x)    (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20)
  60
  61#ifndef read64
  62#ifdef readq
  63#define read64 readq
  64#else
  65#define read64 _read64
  66static inline u64 _read64(void __iomem *mmio)
  67{
  68        u64 low, high;
  69
  70        low = readl(mmio);
  71        high = readl(mmio + sizeof(u32));
  72        return low | (high << 32);
  73}
  74#endif
  75#endif
  76
  77#ifndef write64
  78#ifdef writeq
  79#define write64 writeq
  80#else
  81#define write64 _write64
  82static inline void _write64(u64 val, void __iomem *mmio)
  83{
  84        writel(val, mmio);
  85        writel(val >> 32, mmio + sizeof(u32));
  86}
  87#endif
  88#endif
  89
  90enum {
  91        /* AMD NTB Capability */
  92        AMD_DB_CNT              = 16,
  93        AMD_MSIX_VECTOR_CNT     = 24,
  94        AMD_SPADS_CNT           = 16,
  95
  96        /*  AMD NTB register offset */
  97        AMD_CNTL_OFFSET         = 0x200,
  98
  99        /* NTB control register bits */
 100        PMM_REG_CTL             = BIT(21),
 101        SMM_REG_CTL             = BIT(20),
 102        SMM_REG_ACC_PATH        = BIT(18),
 103        PMM_REG_ACC_PATH        = BIT(17),
 104        NTB_CLK_EN              = BIT(16),
 105
 106        AMD_STA_OFFSET          = 0x204,
 107        AMD_PGSLV_OFFSET        = 0x208,
 108        AMD_SPAD_MUX_OFFSET     = 0x20C,
 109        AMD_SPAD_OFFSET         = 0x210,
 110        AMD_RSMU_HCID           = 0x250,
 111        AMD_RSMU_SIID           = 0x254,
 112        AMD_PSION_OFFSET        = 0x300,
 113        AMD_SSION_OFFSET        = 0x330,
 114        AMD_MMINDEX_OFFSET      = 0x400,
 115        AMD_MMDATA_OFFSET       = 0x404,
 116        AMD_SIDEINFO_OFFSET     = 0x408,
 117
 118        AMD_SIDE_MASK           = BIT(0),
 119        AMD_SIDE_READY          = BIT(1),
 120
 121        /* limit register */
 122        AMD_ROMBARLMT_OFFSET    = 0x410,
 123        AMD_BAR1LMT_OFFSET      = 0x414,
 124        AMD_BAR23LMT_OFFSET     = 0x418,
 125        AMD_BAR45LMT_OFFSET     = 0x420,
 126        /* xlat address */
 127        AMD_POMBARXLAT_OFFSET   = 0x428,
 128        AMD_BAR1XLAT_OFFSET     = 0x430,
 129        AMD_BAR23XLAT_OFFSET    = 0x438,
 130        AMD_BAR45XLAT_OFFSET    = 0x440,
 131        /* doorbell and interrupt */
 132        AMD_DBFM_OFFSET         = 0x450,
 133        AMD_DBREQ_OFFSET        = 0x454,
 134        AMD_MIRRDBSTAT_OFFSET   = 0x458,
 135        AMD_DBMASK_OFFSET       = 0x45C,
 136        AMD_DBSTAT_OFFSET       = 0x460,
 137        AMD_INTMASK_OFFSET      = 0x470,
 138        AMD_INTSTAT_OFFSET      = 0x474,
 139
 140        /* event type */
 141        AMD_PEER_FLUSH_EVENT    = BIT(0),
 142        AMD_PEER_RESET_EVENT    = BIT(1),
 143        AMD_PEER_D3_EVENT       = BIT(2),
 144        AMD_PEER_PMETO_EVENT    = BIT(3),
 145        AMD_PEER_D0_EVENT       = BIT(4),
 146        AMD_LINK_UP_EVENT       = BIT(5),
 147        AMD_LINK_DOWN_EVENT     = BIT(6),
 148        AMD_EVENT_INTMASK       = (AMD_PEER_FLUSH_EVENT |
 149                                AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |
 150                                AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |
 151                                AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),
 152
 153        AMD_PMESTAT_OFFSET      = 0x480,
 154        AMD_PMSGTRIG_OFFSET     = 0x490,
 155        AMD_LTRLATENCY_OFFSET   = 0x494,
 156        AMD_FLUSHTRIG_OFFSET    = 0x498,
 157
 158        /* SMU register*/
 159        AMD_SMUACK_OFFSET       = 0x4A0,
 160        AMD_SINRST_OFFSET       = 0x4A4,
 161        AMD_RSPNUM_OFFSET       = 0x4A8,
 162        AMD_SMU_SPADMUTEX       = 0x4B0,
 163        AMD_SMU_SPADOFFSET      = 0x4B4,
 164
 165        AMD_PEER_OFFSET         = 0x400,
 166};
 167
 168struct ntb_dev_data {
 169        const unsigned char mw_count;
 170        const unsigned int mw_idx;
 171};
 172
 173struct amd_ntb_dev;
 174
 175struct amd_ntb_vec {
 176        struct amd_ntb_dev      *ndev;
 177        int                     num;
 178};
 179
 180struct amd_ntb_dev {
 181        struct ntb_dev ntb;
 182
 183        u32 ntb_side;
 184        u32 lnk_sta;
 185        u32 cntl_sta;
 186        u32 peer_sta;
 187
 188        struct ntb_dev_data *dev_data;
 189        unsigned char mw_count;
 190        unsigned char spad_count;
 191        unsigned char db_count;
 192        unsigned char msix_vec_count;
 193
 194        u64 db_valid_mask;
 195        u64 db_mask;
 196        u64 db_last_bit;
 197        u32 int_mask;
 198
 199        struct msix_entry *msix;
 200        struct amd_ntb_vec *vec;
 201
 202        /* synchronize rmw access of db_mask and hw reg */
 203        spinlock_t db_mask_lock;
 204
 205        void __iomem *self_mmio;
 206        void __iomem *peer_mmio;
 207        unsigned int self_spad;
 208        unsigned int peer_spad;
 209
 210        struct delayed_work hb_timer;
 211
 212        struct dentry *debugfs_dir;
 213        struct dentry *debugfs_info;
 214};
 215
 216#define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
 217#define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
 218
 219static void amd_set_side_info_reg(struct amd_ntb_dev *ndev, bool peer);
 220static void amd_clear_side_info_reg(struct amd_ntb_dev *ndev, bool peer);
 221static int amd_poll_link(struct amd_ntb_dev *ndev);
 222
 223#endif
 224