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5
6
7#include <linux/acpi.h>
8#include <linux/aer.h>
9#include <linux/async.h>
10#include <linux/blkdev.h>
11#include <linux/blk-mq.h>
12#include <linux/blk-mq-pci.h>
13#include <linux/dmi.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/once.h>
21#include <linux/pci.h>
22#include <linux/suspend.h>
23#include <linux/t10-pi.h>
24#include <linux/types.h>
25#include <linux/io-64-nonatomic-lo-hi.h>
26#include <linux/io-64-nonatomic-hi-lo.h>
27#include <linux/sed-opal.h>
28#include <linux/pci-p2pdma.h>
29
30#include "trace.h"
31#include "nvme.h"
32
33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
35
36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37
38
39
40
41
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
48static bool use_cmb_sqes = true;
49module_param(use_cmb_sqes, bool, 0444);
50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
56
57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
63#define NVME_PCI_MIN_QUEUE_SIZE 2
64#define NVME_PCI_MAX_QUEUE_SIZE 4095
65static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
66static const struct kernel_param_ops io_queue_depth_ops = {
67 .set = io_queue_depth_set,
68 .get = param_get_uint,
69};
70
71static unsigned int io_queue_depth = 1024;
72module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
73MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
74
75static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76{
77 unsigned int n;
78 int ret;
79
80 ret = kstrtouint(val, 10, &n);
81 if (ret != 0 || n > num_possible_cpus())
82 return -EINVAL;
83 return param_set_uint(val, kp);
84}
85
86static const struct kernel_param_ops io_queue_count_ops = {
87 .set = io_queue_count_set,
88 .get = param_get_uint,
89};
90
91static unsigned int write_queues;
92module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
93MODULE_PARM_DESC(write_queues,
94 "Number of queues to use for writes. If not set, reads and writes "
95 "will share a queue set.");
96
97static unsigned int poll_queues;
98module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
99MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100
101static bool noacpi;
102module_param(noacpi, bool, 0444);
103MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
104
105struct nvme_dev;
106struct nvme_queue;
107
108static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
109static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
110
111
112
113
114struct nvme_dev {
115 struct nvme_queue *queues;
116 struct blk_mq_tag_set tagset;
117 struct blk_mq_tag_set admin_tagset;
118 u32 __iomem *dbs;
119 struct device *dev;
120 struct dma_pool *prp_page_pool;
121 struct dma_pool *prp_small_pool;
122 unsigned online_queues;
123 unsigned max_qid;
124 unsigned io_queues[HCTX_MAX_TYPES];
125 unsigned int num_vecs;
126 u32 q_depth;
127 int io_sqes;
128 u32 db_stride;
129 void __iomem *bar;
130 unsigned long bar_mapped_size;
131 struct work_struct remove_work;
132 struct mutex shutdown_lock;
133 bool subsystem;
134 u64 cmb_size;
135 bool cmb_use_sqes;
136 u32 cmbsz;
137 u32 cmbloc;
138 struct nvme_ctrl ctrl;
139 u32 last_ps;
140 bool hmb;
141
142 mempool_t *iod_mempool;
143
144
145 u32 *dbbuf_dbs;
146 dma_addr_t dbbuf_dbs_dma_addr;
147 u32 *dbbuf_eis;
148 dma_addr_t dbbuf_eis_dma_addr;
149
150
151 u64 host_mem_size;
152 u32 nr_host_mem_descs;
153 dma_addr_t host_mem_descs_dma;
154 struct nvme_host_mem_buf_desc *host_mem_descs;
155 void **host_mem_desc_bufs;
156 unsigned int nr_allocated_queues;
157 unsigned int nr_write_queues;
158 unsigned int nr_poll_queues;
159
160 bool attrs_added;
161};
162
163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
167}
168
169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
184
185
186
187
188struct nvme_queue {
189 struct nvme_dev *dev;
190 spinlock_t sq_lock;
191 void *sq_cmds;
192
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
194 struct nvme_completion *cqes;
195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
197 u32 __iomem *q_db;
198 u32 q_depth;
199 u16 cq_vector;
200 u16 sq_tail;
201 u16 last_sq_tail;
202 u16 cq_head;
203 u16 qid;
204 u8 cq_phase;
205 u8 sqes;
206 unsigned long flags;
207#define NVMEQ_ENABLED 0
208#define NVMEQ_SQ_CMB 1
209#define NVMEQ_DELETE_ERROR 2
210#define NVMEQ_POLLED 3
211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
215 struct completion delete_done;
216};
217
218
219
220
221
222
223
224struct nvme_iod {
225 struct nvme_request req;
226 struct nvme_command cmd;
227 struct nvme_queue *nvmeq;
228 bool use_sgl;
229 int aborted;
230 int npages;
231 int nents;
232 dma_addr_t first_dma;
233 unsigned int dma_len;
234 dma_addr_t meta_dma;
235 struct scatterlist *sg;
236};
237
238static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
239{
240 return dev->nr_allocated_queues * 8 * dev->db_stride;
241}
242
243static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244{
245 unsigned int mem_size = nvme_dbbuf_size(dev);
246
247 if (dev->dbbuf_dbs)
248 return 0;
249
250 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 &dev->dbbuf_dbs_dma_addr,
252 GFP_KERNEL);
253 if (!dev->dbbuf_dbs)
254 return -ENOMEM;
255 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 &dev->dbbuf_eis_dma_addr,
257 GFP_KERNEL);
258 if (!dev->dbbuf_eis) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 return -ENOMEM;
263 }
264
265 return 0;
266}
267
268static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
269{
270 unsigned int mem_size = nvme_dbbuf_size(dev);
271
272 if (dev->dbbuf_dbs) {
273 dma_free_coherent(dev->dev, mem_size,
274 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 dev->dbbuf_dbs = NULL;
276 }
277 if (dev->dbbuf_eis) {
278 dma_free_coherent(dev->dev, mem_size,
279 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 dev->dbbuf_eis = NULL;
281 }
282}
283
284static void nvme_dbbuf_init(struct nvme_dev *dev,
285 struct nvme_queue *nvmeq, int qid)
286{
287 if (!dev->dbbuf_dbs || !qid)
288 return;
289
290 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
294}
295
296static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
297{
298 if (!nvmeq->qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = NULL;
302 nvmeq->dbbuf_cq_db = NULL;
303 nvmeq->dbbuf_sq_ei = NULL;
304 nvmeq->dbbuf_cq_ei = NULL;
305}
306
307static void nvme_dbbuf_set(struct nvme_dev *dev)
308{
309 struct nvme_command c = { };
310 unsigned int i;
311
312 if (!dev->dbbuf_dbs)
313 return;
314
315 c.dbbuf.opcode = nvme_admin_dbbuf;
316 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
317 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
318
319 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
320 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
321
322 nvme_dbbuf_dma_free(dev);
323
324 for (i = 1; i <= dev->online_queues; i++)
325 nvme_dbbuf_free(&dev->queues[i]);
326 }
327}
328
329static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
330{
331 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
332}
333
334
335static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
336 volatile u32 *dbbuf_ei)
337{
338 if (dbbuf_db) {
339 u16 old_value;
340
341
342
343
344
345 wmb();
346
347 old_value = *dbbuf_db;
348 *dbbuf_db = value;
349
350
351
352
353
354
355
356 mb();
357
358 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
359 return false;
360 }
361
362 return true;
363}
364
365
366
367
368
369
370static int nvme_pci_npages_prp(void)
371{
372 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
373 NVME_CTRL_PAGE_SIZE);
374 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
375}
376
377
378
379
380
381static int nvme_pci_npages_sgl(void)
382{
383 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
384 PAGE_SIZE);
385}
386
387static size_t nvme_pci_iod_alloc_size(void)
388{
389 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
390
391 return sizeof(__le64 *) * npages +
392 sizeof(struct scatterlist) * NVME_MAX_SEGS;
393}
394
395static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
397{
398 struct nvme_dev *dev = data;
399 struct nvme_queue *nvmeq = &dev->queues[0];
400
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404 hctx->driver_data = nvmeq;
405 return 0;
406}
407
408static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
410{
411 struct nvme_dev *dev = data;
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
416 return 0;
417}
418
419static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420 unsigned int hctx_idx, unsigned int numa_node)
421{
422 struct nvme_dev *dev = set->driver_data;
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
425 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
426
427 BUG_ON(!nvmeq);
428 iod->nvmeq = nvmeq;
429
430 nvme_req(req)->ctrl = &dev->ctrl;
431 nvme_req(req)->cmd = &iod->cmd;
432 return 0;
433}
434
435static int queue_irq_offset(struct nvme_dev *dev)
436{
437
438 if (dev->num_vecs > 1)
439 return 1;
440
441 return 0;
442}
443
444static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
445{
446 struct nvme_dev *dev = set->driver_data;
447 int i, qoff, offset;
448
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
452
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
455 BUG_ON(i == HCTX_TYPE_DEFAULT);
456 continue;
457 }
458
459
460
461
462
463 map->queue_offset = qoff;
464 if (i != HCTX_TYPE_POLL && offset)
465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 else
467 blk_mq_map_queues(map);
468 qoff += map->nr_queues;
469 offset += map->nr_queues;
470 }
471
472 return 0;
473}
474
475
476
477
478static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
479{
480 if (!write_sq) {
481 u16 next_tail = nvmeq->sq_tail + 1;
482
483 if (next_tail == nvmeq->q_depth)
484 next_tail = 0;
485 if (next_tail != nvmeq->last_sq_tail)
486 return;
487 }
488
489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
492 nvmeq->last_sq_tail = nvmeq->sq_tail;
493}
494
495
496
497
498
499
500
501static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
502 bool write_sq)
503{
504 spin_lock(&nvmeq->sq_lock);
505 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
506 cmd, sizeof(*cmd));
507 if (++nvmeq->sq_tail == nvmeq->q_depth)
508 nvmeq->sq_tail = 0;
509 nvme_write_sq_db(nvmeq, write_sq);
510 spin_unlock(&nvmeq->sq_lock);
511}
512
513static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
514{
515 struct nvme_queue *nvmeq = hctx->driver_data;
516
517 spin_lock(&nvmeq->sq_lock);
518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
520 spin_unlock(&nvmeq->sq_lock);
521}
522
523static void **nvme_pci_iod_list(struct request *req)
524{
525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
527}
528
529static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
530{
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
532 int nseg = blk_rq_nr_phys_segments(req);
533 unsigned int avg_seg_size;
534
535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
536
537 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
538 return false;
539 if (!iod->nvmeq->qid)
540 return false;
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
542 return false;
543 return true;
544}
545
546static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
547{
548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
551 int i;
552
553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
556
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
559 }
560}
561
562static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
563{
564 const int last_sg = SGES_PER_PAGE - 1;
565 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
566 dma_addr_t dma_addr = iod->first_dma;
567 int i;
568
569 for (i = 0; i < iod->npages; i++) {
570 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
571 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
572
573 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
574 dma_addr = next_dma_addr;
575 }
576}
577
578static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
579{
580 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
581
582 if (is_pci_p2pdma_page(sg_page(iod->sg)))
583 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
584 rq_dma_dir(req));
585 else
586 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
587}
588
589static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
590{
591 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
592
593 if (iod->dma_len) {
594 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
595 rq_dma_dir(req));
596 return;
597 }
598
599 WARN_ON_ONCE(!iod->nents);
600
601 nvme_unmap_sg(dev, req);
602 if (iod->npages == 0)
603 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
604 iod->first_dma);
605 else if (iod->use_sgl)
606 nvme_free_sgls(dev, req);
607 else
608 nvme_free_prps(dev, req);
609 mempool_free(iod->sg, dev->iod_mempool);
610}
611
612static void nvme_print_sgl(struct scatterlist *sgl, int nents)
613{
614 int i;
615 struct scatterlist *sg;
616
617 for_each_sg(sgl, sg, nents, i) {
618 dma_addr_t phys = sg_phys(sg);
619 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
620 "dma_address:%pad dma_length:%d\n",
621 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
622 sg_dma_len(sg));
623 }
624}
625
626static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
627 struct request *req, struct nvme_rw_command *cmnd)
628{
629 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
630 struct dma_pool *pool;
631 int length = blk_rq_payload_bytes(req);
632 struct scatterlist *sg = iod->sg;
633 int dma_len = sg_dma_len(sg);
634 u64 dma_addr = sg_dma_address(sg);
635 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
636 __le64 *prp_list;
637 void **list = nvme_pci_iod_list(req);
638 dma_addr_t prp_dma;
639 int nprps, i;
640
641 length -= (NVME_CTRL_PAGE_SIZE - offset);
642 if (length <= 0) {
643 iod->first_dma = 0;
644 goto done;
645 }
646
647 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
648 if (dma_len) {
649 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
650 } else {
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655
656 if (length <= NVME_CTRL_PAGE_SIZE) {
657 iod->first_dma = dma_addr;
658 goto done;
659 }
660
661 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
662 if (nprps <= (256 / 8)) {
663 pool = dev->prp_small_pool;
664 iod->npages = 0;
665 } else {
666 pool = dev->prp_page_pool;
667 iod->npages = 1;
668 }
669
670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
671 if (!prp_list) {
672 iod->first_dma = dma_addr;
673 iod->npages = -1;
674 return BLK_STS_RESOURCE;
675 }
676 list[0] = prp_list;
677 iod->first_dma = prp_dma;
678 i = 0;
679 for (;;) {
680 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
681 __le64 *old_prp_list = prp_list;
682 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
683 if (!prp_list)
684 goto free_prps;
685 list[iod->npages++] = prp_list;
686 prp_list[0] = old_prp_list[i - 1];
687 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
688 i = 1;
689 }
690 prp_list[i++] = cpu_to_le64(dma_addr);
691 dma_len -= NVME_CTRL_PAGE_SIZE;
692 dma_addr += NVME_CTRL_PAGE_SIZE;
693 length -= NVME_CTRL_PAGE_SIZE;
694 if (length <= 0)
695 break;
696 if (dma_len > 0)
697 continue;
698 if (unlikely(dma_len < 0))
699 goto bad_sgl;
700 sg = sg_next(sg);
701 dma_addr = sg_dma_address(sg);
702 dma_len = sg_dma_len(sg);
703 }
704done:
705 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
706 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
707 return BLK_STS_OK;
708free_prps:
709 nvme_free_prps(dev, req);
710 return BLK_STS_RESOURCE;
711bad_sgl:
712 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
713 "Invalid SGL for payload:%d nents:%d\n",
714 blk_rq_payload_bytes(req), iod->nents);
715 return BLK_STS_IOERR;
716}
717
718static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
719 struct scatterlist *sg)
720{
721 sge->addr = cpu_to_le64(sg_dma_address(sg));
722 sge->length = cpu_to_le32(sg_dma_len(sg));
723 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
724}
725
726static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
727 dma_addr_t dma_addr, int entries)
728{
729 sge->addr = cpu_to_le64(dma_addr);
730 if (entries < SGES_PER_PAGE) {
731 sge->length = cpu_to_le32(entries * sizeof(*sge));
732 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
733 } else {
734 sge->length = cpu_to_le32(PAGE_SIZE);
735 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
736 }
737}
738
739static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
740 struct request *req, struct nvme_rw_command *cmd, int entries)
741{
742 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
743 struct dma_pool *pool;
744 struct nvme_sgl_desc *sg_list;
745 struct scatterlist *sg = iod->sg;
746 dma_addr_t sgl_dma;
747 int i = 0;
748
749
750 cmd->flags = NVME_CMD_SGL_METABUF;
751
752 if (entries == 1) {
753 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
754 return BLK_STS_OK;
755 }
756
757 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
758 pool = dev->prp_small_pool;
759 iod->npages = 0;
760 } else {
761 pool = dev->prp_page_pool;
762 iod->npages = 1;
763 }
764
765 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
766 if (!sg_list) {
767 iod->npages = -1;
768 return BLK_STS_RESOURCE;
769 }
770
771 nvme_pci_iod_list(req)[0] = sg_list;
772 iod->first_dma = sgl_dma;
773
774 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
775
776 do {
777 if (i == SGES_PER_PAGE) {
778 struct nvme_sgl_desc *old_sg_desc = sg_list;
779 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
780
781 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
782 if (!sg_list)
783 goto free_sgls;
784
785 i = 0;
786 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
787 sg_list[i++] = *link;
788 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
789 }
790
791 nvme_pci_sgl_set_data(&sg_list[i++], sg);
792 sg = sg_next(sg);
793 } while (--entries > 0);
794
795 return BLK_STS_OK;
796free_sgls:
797 nvme_free_sgls(dev, req);
798 return BLK_STS_RESOURCE;
799}
800
801static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
803 struct bio_vec *bv)
804{
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
806 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
807 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
808
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
813
814 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
815 if (bv->bv_len > first_prp_len)
816 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
817 return BLK_STS_OK;
818}
819
820static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
821 struct request *req, struct nvme_rw_command *cmnd,
822 struct bio_vec *bv)
823{
824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
825
826 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
827 if (dma_mapping_error(dev->dev, iod->first_dma))
828 return BLK_STS_RESOURCE;
829 iod->dma_len = bv->bv_len;
830
831 cmnd->flags = NVME_CMD_SGL_METABUF;
832 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
833 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
834 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
835 return BLK_STS_OK;
836}
837
838static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
839 struct nvme_command *cmnd)
840{
841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
842 blk_status_t ret = BLK_STS_RESOURCE;
843 int nr_mapped;
844
845 if (blk_rq_nr_phys_segments(req) == 1) {
846 struct bio_vec bv = req_bvec(req);
847
848 if (!is_pci_p2pdma_page(bv.bv_page)) {
849 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
850 return nvme_setup_prp_simple(dev, req,
851 &cmnd->rw, &bv);
852
853 if (iod->nvmeq->qid && sgl_threshold &&
854 nvme_ctrl_sgl_supported(&dev->ctrl))
855 return nvme_setup_sgl_simple(dev, req,
856 &cmnd->rw, &bv);
857 }
858 }
859
860 iod->dma_len = 0;
861 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
862 if (!iod->sg)
863 return BLK_STS_RESOURCE;
864 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
865 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
866 if (!iod->nents)
867 goto out_free_sg;
868
869 if (is_pci_p2pdma_page(sg_page(iod->sg)))
870 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
871 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
872 else
873 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
874 rq_dma_dir(req), DMA_ATTR_NO_WARN);
875 if (!nr_mapped)
876 goto out_free_sg;
877
878 iod->use_sgl = nvme_pci_use_sgls(dev, req);
879 if (iod->use_sgl)
880 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
881 else
882 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
883 if (ret != BLK_STS_OK)
884 goto out_unmap_sg;
885 return BLK_STS_OK;
886
887out_unmap_sg:
888 nvme_unmap_sg(dev, req);
889out_free_sg:
890 mempool_free(iod->sg, dev->iod_mempool);
891 return ret;
892}
893
894static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
895 struct nvme_command *cmnd)
896{
897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
898
899 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
900 rq_dma_dir(req), 0);
901 if (dma_mapping_error(dev->dev, iod->meta_dma))
902 return BLK_STS_IOERR;
903 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
904 return BLK_STS_OK;
905}
906
907
908
909
910static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
911 const struct blk_mq_queue_data *bd)
912{
913 struct nvme_ns *ns = hctx->queue->queuedata;
914 struct nvme_queue *nvmeq = hctx->driver_data;
915 struct nvme_dev *dev = nvmeq->dev;
916 struct request *req = bd->rq;
917 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
918 struct nvme_command *cmnd = &iod->cmd;
919 blk_status_t ret;
920
921 iod->aborted = 0;
922 iod->npages = -1;
923 iod->nents = 0;
924
925
926
927
928
929 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
930 return BLK_STS_IOERR;
931
932 if (!nvme_check_ready(&dev->ctrl, req, true))
933 return nvme_fail_nonready_command(&dev->ctrl, req);
934
935 ret = nvme_setup_cmd(ns, req);
936 if (ret)
937 return ret;
938
939 if (blk_rq_nr_phys_segments(req)) {
940 ret = nvme_map_data(dev, req, cmnd);
941 if (ret)
942 goto out_free_cmd;
943 }
944
945 if (blk_integrity_rq(req)) {
946 ret = nvme_map_metadata(dev, req, cmnd);
947 if (ret)
948 goto out_unmap_data;
949 }
950
951 blk_mq_start_request(req);
952 nvme_submit_cmd(nvmeq, cmnd, bd->last);
953 return BLK_STS_OK;
954out_unmap_data:
955 nvme_unmap_data(dev, req);
956out_free_cmd:
957 nvme_cleanup_cmd(req);
958 return ret;
959}
960
961static void nvme_pci_complete_rq(struct request *req)
962{
963 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
964 struct nvme_dev *dev = iod->nvmeq->dev;
965
966 if (blk_integrity_rq(req))
967 dma_unmap_page(dev->dev, iod->meta_dma,
968 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
969 if (blk_rq_nr_phys_segments(req))
970 nvme_unmap_data(dev, req);
971 nvme_complete_rq(req);
972}
973
974
975static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
976{
977 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
978
979 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
980}
981
982static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
983{
984 u16 head = nvmeq->cq_head;
985
986 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
987 nvmeq->dbbuf_cq_ei))
988 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
989}
990
991static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
992{
993 if (!nvmeq->qid)
994 return nvmeq->dev->admin_tagset.tags[0];
995 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
996}
997
998static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
999{
1000 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1001 __u16 command_id = READ_ONCE(cqe->command_id);
1002 struct request *req;
1003
1004
1005
1006
1007
1008
1009
1010 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1011 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012 cqe->status, &cqe->result);
1013 return;
1014 }
1015
1016 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1017 if (unlikely(!req)) {
1018 dev_warn(nvmeq->dev->ctrl.device,
1019 "invalid id %d completed on queue %d\n",
1020 command_id, le16_to_cpu(cqe->sq_id));
1021 return;
1022 }
1023
1024 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1025 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1026 nvme_pci_complete_rq(req);
1027}
1028
1029static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1030{
1031 u32 tmp = nvmeq->cq_head + 1;
1032
1033 if (tmp == nvmeq->q_depth) {
1034 nvmeq->cq_head = 0;
1035 nvmeq->cq_phase ^= 1;
1036 } else {
1037 nvmeq->cq_head = tmp;
1038 }
1039}
1040
1041static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1042{
1043 int found = 0;
1044
1045 while (nvme_cqe_pending(nvmeq)) {
1046 found++;
1047
1048
1049
1050
1051 dma_rmb();
1052 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1053 nvme_update_cq_head(nvmeq);
1054 }
1055
1056 if (found)
1057 nvme_ring_cq_doorbell(nvmeq);
1058 return found;
1059}
1060
1061static irqreturn_t nvme_irq(int irq, void *data)
1062{
1063 struct nvme_queue *nvmeq = data;
1064
1065 if (nvme_process_cq(nvmeq))
1066 return IRQ_HANDLED;
1067 return IRQ_NONE;
1068}
1069
1070static irqreturn_t nvme_irq_check(int irq, void *data)
1071{
1072 struct nvme_queue *nvmeq = data;
1073
1074 if (nvme_cqe_pending(nvmeq))
1075 return IRQ_WAKE_THREAD;
1076 return IRQ_NONE;
1077}
1078
1079
1080
1081
1082
1083static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1084{
1085 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1086
1087 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1088
1089 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1090 nvme_process_cq(nvmeq);
1091 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1092}
1093
1094static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1095{
1096 struct nvme_queue *nvmeq = hctx->driver_data;
1097 bool found;
1098
1099 if (!nvme_cqe_pending(nvmeq))
1100 return 0;
1101
1102 spin_lock(&nvmeq->cq_poll_lock);
1103 found = nvme_process_cq(nvmeq);
1104 spin_unlock(&nvmeq->cq_poll_lock);
1105
1106 return found;
1107}
1108
1109static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1110{
1111 struct nvme_dev *dev = to_nvme_dev(ctrl);
1112 struct nvme_queue *nvmeq = &dev->queues[0];
1113 struct nvme_command c = { };
1114
1115 c.common.opcode = nvme_admin_async_event;
1116 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1117 nvme_submit_cmd(nvmeq, &c, true);
1118}
1119
1120static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1121{
1122 struct nvme_command c = { };
1123
1124 c.delete_queue.opcode = opcode;
1125 c.delete_queue.qid = cpu_to_le16(id);
1126
1127 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1128}
1129
1130static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1131 struct nvme_queue *nvmeq, s16 vector)
1132{
1133 struct nvme_command c = { };
1134 int flags = NVME_QUEUE_PHYS_CONTIG;
1135
1136 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1137 flags |= NVME_CQ_IRQ_ENABLED;
1138
1139
1140
1141
1142
1143 c.create_cq.opcode = nvme_admin_create_cq;
1144 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1145 c.create_cq.cqid = cpu_to_le16(qid);
1146 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1147 c.create_cq.cq_flags = cpu_to_le16(flags);
1148 c.create_cq.irq_vector = cpu_to_le16(vector);
1149
1150 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1151}
1152
1153static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1154 struct nvme_queue *nvmeq)
1155{
1156 struct nvme_ctrl *ctrl = &dev->ctrl;
1157 struct nvme_command c = { };
1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1159
1160
1161
1162
1163
1164
1165 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1166 flags |= NVME_SQ_PRIO_MEDIUM;
1167
1168
1169
1170
1171
1172 c.create_sq.opcode = nvme_admin_create_sq;
1173 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1174 c.create_sq.sqid = cpu_to_le16(qid);
1175 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1176 c.create_sq.sq_flags = cpu_to_le16(flags);
1177 c.create_sq.cqid = cpu_to_le16(qid);
1178
1179 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1180}
1181
1182static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1183{
1184 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1185}
1186
1187static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1188{
1189 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1190}
1191
1192static void abort_endio(struct request *req, blk_status_t error)
1193{
1194 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1195 struct nvme_queue *nvmeq = iod->nvmeq;
1196
1197 dev_warn(nvmeq->dev->ctrl.device,
1198 "Abort status: 0x%x", nvme_req(req)->status);
1199 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1200 blk_mq_free_request(req);
1201}
1202
1203static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1204{
1205
1206
1207
1208 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1209
1210
1211 switch (dev->ctrl.state) {
1212 case NVME_CTRL_RESETTING:
1213 case NVME_CTRL_CONNECTING:
1214 return false;
1215 default:
1216 break;
1217 }
1218
1219
1220
1221
1222 if (!(csts & NVME_CSTS_CFS) && !nssro)
1223 return false;
1224
1225 return true;
1226}
1227
1228static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1229{
1230
1231 u16 pci_status;
1232 int result;
1233
1234 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1235 &pci_status);
1236 if (result == PCIBIOS_SUCCESSFUL)
1237 dev_warn(dev->ctrl.device,
1238 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1239 csts, pci_status);
1240 else
1241 dev_warn(dev->ctrl.device,
1242 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1243 csts, result);
1244}
1245
1246static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1247{
1248 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1249 struct nvme_queue *nvmeq = iod->nvmeq;
1250 struct nvme_dev *dev = nvmeq->dev;
1251 struct request *abort_req;
1252 struct nvme_command cmd = { };
1253 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1254
1255
1256
1257
1258 mb();
1259 if (pci_channel_offline(to_pci_dev(dev->dev)))
1260 return BLK_EH_RESET_TIMER;
1261
1262
1263
1264
1265 if (nvme_should_reset(dev, csts)) {
1266 nvme_warn_reset(dev, csts);
1267 nvme_dev_disable(dev, false);
1268 nvme_reset_ctrl(&dev->ctrl);
1269 return BLK_EH_DONE;
1270 }
1271
1272
1273
1274
1275 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1276 nvme_poll(req->mq_hctx);
1277 else
1278 nvme_poll_irqdisable(nvmeq);
1279
1280 if (blk_mq_request_completed(req)) {
1281 dev_warn(dev->ctrl.device,
1282 "I/O %d QID %d timeout, completion polled\n",
1283 req->tag, nvmeq->qid);
1284 return BLK_EH_DONE;
1285 }
1286
1287
1288
1289
1290
1291
1292
1293 switch (dev->ctrl.state) {
1294 case NVME_CTRL_CONNECTING:
1295 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1296 fallthrough;
1297 case NVME_CTRL_DELETING:
1298 dev_warn_ratelimited(dev->ctrl.device,
1299 "I/O %d QID %d timeout, disable controller\n",
1300 req->tag, nvmeq->qid);
1301 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1302 nvme_dev_disable(dev, true);
1303 return BLK_EH_DONE;
1304 case NVME_CTRL_RESETTING:
1305 return BLK_EH_RESET_TIMER;
1306 default:
1307 break;
1308 }
1309
1310
1311
1312
1313
1314
1315 if (!nvmeq->qid || iod->aborted) {
1316 dev_warn(dev->ctrl.device,
1317 "I/O %d QID %d timeout, reset controller\n",
1318 req->tag, nvmeq->qid);
1319 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1320 nvme_dev_disable(dev, false);
1321 nvme_reset_ctrl(&dev->ctrl);
1322
1323 return BLK_EH_DONE;
1324 }
1325
1326 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1327 atomic_inc(&dev->ctrl.abort_limit);
1328 return BLK_EH_RESET_TIMER;
1329 }
1330 iod->aborted = 1;
1331
1332 cmd.abort.opcode = nvme_admin_abort_cmd;
1333 cmd.abort.cid = nvme_cid(req);
1334 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1335
1336 dev_warn(nvmeq->dev->ctrl.device,
1337 "I/O %d QID %d timeout, aborting\n",
1338 req->tag, nvmeq->qid);
1339
1340 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1341 BLK_MQ_REQ_NOWAIT);
1342 if (IS_ERR(abort_req)) {
1343 atomic_inc(&dev->ctrl.abort_limit);
1344 return BLK_EH_RESET_TIMER;
1345 }
1346
1347 abort_req->end_io_data = NULL;
1348 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1349
1350
1351
1352
1353
1354
1355 return BLK_EH_RESET_TIMER;
1356}
1357
1358static void nvme_free_queue(struct nvme_queue *nvmeq)
1359{
1360 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1361 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1362 if (!nvmeq->sq_cmds)
1363 return;
1364
1365 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1366 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1367 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1368 } else {
1369 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1370 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1371 }
1372}
1373
1374static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1375{
1376 int i;
1377
1378 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1379 dev->ctrl.queue_count--;
1380 nvme_free_queue(&dev->queues[i]);
1381 }
1382}
1383
1384
1385
1386
1387
1388static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1389{
1390 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1391 return 1;
1392
1393
1394 mb();
1395
1396 nvmeq->dev->online_queues--;
1397 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1398 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1399 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1400 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1401 return 0;
1402}
1403
1404static void nvme_suspend_io_queues(struct nvme_dev *dev)
1405{
1406 int i;
1407
1408 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1409 nvme_suspend_queue(&dev->queues[i]);
1410}
1411
1412static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1413{
1414 struct nvme_queue *nvmeq = &dev->queues[0];
1415
1416 if (shutdown)
1417 nvme_shutdown_ctrl(&dev->ctrl);
1418 else
1419 nvme_disable_ctrl(&dev->ctrl);
1420
1421 nvme_poll_irqdisable(nvmeq);
1422}
1423
1424
1425
1426
1427
1428
1429
1430static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1431{
1432 int i;
1433
1434 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1435 spin_lock(&dev->queues[i].cq_poll_lock);
1436 nvme_process_cq(&dev->queues[i]);
1437 spin_unlock(&dev->queues[i].cq_poll_lock);
1438 }
1439}
1440
1441static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1442 int entry_size)
1443{
1444 int q_depth = dev->q_depth;
1445 unsigned q_size_aligned = roundup(q_depth * entry_size,
1446 NVME_CTRL_PAGE_SIZE);
1447
1448 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1449 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1450
1451 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1452 q_depth = div_u64(mem_per_q, entry_size);
1453
1454
1455
1456
1457
1458
1459 if (q_depth < 64)
1460 return -ENOMEM;
1461 }
1462
1463 return q_depth;
1464}
1465
1466static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1467 int qid)
1468{
1469 struct pci_dev *pdev = to_pci_dev(dev->dev);
1470
1471 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1472 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1473 if (nvmeq->sq_cmds) {
1474 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1475 nvmeq->sq_cmds);
1476 if (nvmeq->sq_dma_addr) {
1477 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1478 return 0;
1479 }
1480
1481 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1482 }
1483 }
1484
1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1486 &nvmeq->sq_dma_addr, GFP_KERNEL);
1487 if (!nvmeq->sq_cmds)
1488 return -ENOMEM;
1489 return 0;
1490}
1491
1492static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1493{
1494 struct nvme_queue *nvmeq = &dev->queues[qid];
1495
1496 if (dev->ctrl.queue_count > qid)
1497 return 0;
1498
1499 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1500 nvmeq->q_depth = depth;
1501 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1502 &nvmeq->cq_dma_addr, GFP_KERNEL);
1503 if (!nvmeq->cqes)
1504 goto free_nvmeq;
1505
1506 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1507 goto free_cqdma;
1508
1509 nvmeq->dev = dev;
1510 spin_lock_init(&nvmeq->sq_lock);
1511 spin_lock_init(&nvmeq->cq_poll_lock);
1512 nvmeq->cq_head = 0;
1513 nvmeq->cq_phase = 1;
1514 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1515 nvmeq->qid = qid;
1516 dev->ctrl.queue_count++;
1517
1518 return 0;
1519
1520 free_cqdma:
1521 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1522 nvmeq->cq_dma_addr);
1523 free_nvmeq:
1524 return -ENOMEM;
1525}
1526
1527static int queue_request_irq(struct nvme_queue *nvmeq)
1528{
1529 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530 int nr = nvmeq->dev->ctrl.instance;
1531
1532 if (use_threaded_interrupts) {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1535 } else {
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538 }
1539}
1540
1541static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1542{
1543 struct nvme_dev *dev = nvmeq->dev;
1544
1545 nvmeq->sq_tail = 0;
1546 nvmeq->last_sq_tail = 0;
1547 nvmeq->cq_head = 0;
1548 nvmeq->cq_phase = 1;
1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1551 nvme_dbbuf_init(dev, nvmeq, qid);
1552 dev->online_queues++;
1553 wmb();
1554}
1555
1556
1557
1558
1559static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1560{
1561
1562
1563
1564 if (!mutex_trylock(&dev->shutdown_lock))
1565 return -ENODEV;
1566
1567
1568
1569
1570 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1571 mutex_unlock(&dev->shutdown_lock);
1572 return -ENODEV;
1573 }
1574
1575 return 0;
1576}
1577
1578static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1579{
1580 struct nvme_dev *dev = nvmeq->dev;
1581 int result;
1582 u16 vector = 0;
1583
1584 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1585
1586
1587
1588
1589
1590 if (!polled)
1591 vector = dev->num_vecs == 1 ? 0 : qid;
1592 else
1593 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1594
1595 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1596 if (result)
1597 return result;
1598
1599 result = adapter_alloc_sq(dev, qid, nvmeq);
1600 if (result < 0)
1601 return result;
1602 if (result)
1603 goto release_cq;
1604
1605 nvmeq->cq_vector = vector;
1606
1607 result = nvme_setup_io_queues_trylock(dev);
1608 if (result)
1609 return result;
1610 nvme_init_queue(nvmeq, qid);
1611 if (!polled) {
1612 result = queue_request_irq(nvmeq);
1613 if (result < 0)
1614 goto release_sq;
1615 }
1616
1617 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1618 mutex_unlock(&dev->shutdown_lock);
1619 return result;
1620
1621release_sq:
1622 dev->online_queues--;
1623 mutex_unlock(&dev->shutdown_lock);
1624 adapter_delete_sq(dev, qid);
1625release_cq:
1626 adapter_delete_cq(dev, qid);
1627 return result;
1628}
1629
1630static const struct blk_mq_ops nvme_mq_admin_ops = {
1631 .queue_rq = nvme_queue_rq,
1632 .complete = nvme_pci_complete_rq,
1633 .init_hctx = nvme_admin_init_hctx,
1634 .init_request = nvme_init_request,
1635 .timeout = nvme_timeout,
1636};
1637
1638static const struct blk_mq_ops nvme_mq_ops = {
1639 .queue_rq = nvme_queue_rq,
1640 .complete = nvme_pci_complete_rq,
1641 .commit_rqs = nvme_commit_rqs,
1642 .init_hctx = nvme_init_hctx,
1643 .init_request = nvme_init_request,
1644 .map_queues = nvme_pci_map_queues,
1645 .timeout = nvme_timeout,
1646 .poll = nvme_poll,
1647};
1648
1649static void nvme_dev_remove_admin(struct nvme_dev *dev)
1650{
1651 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1652
1653
1654
1655
1656
1657 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1658 blk_cleanup_queue(dev->ctrl.admin_q);
1659 blk_mq_free_tag_set(&dev->admin_tagset);
1660 }
1661}
1662
1663static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1664{
1665 if (!dev->ctrl.admin_q) {
1666 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1667 dev->admin_tagset.nr_hw_queues = 1;
1668
1669 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1670 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1671 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1672 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1673 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1674 dev->admin_tagset.driver_data = dev;
1675
1676 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1677 return -ENOMEM;
1678 dev->ctrl.admin_tagset = &dev->admin_tagset;
1679
1680 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1681 if (IS_ERR(dev->ctrl.admin_q)) {
1682 blk_mq_free_tag_set(&dev->admin_tagset);
1683 return -ENOMEM;
1684 }
1685 if (!blk_get_queue(dev->ctrl.admin_q)) {
1686 nvme_dev_remove_admin(dev);
1687 dev->ctrl.admin_q = NULL;
1688 return -ENODEV;
1689 }
1690 } else
1691 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1692
1693 return 0;
1694}
1695
1696static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1697{
1698 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1699}
1700
1701static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1702{
1703 struct pci_dev *pdev = to_pci_dev(dev->dev);
1704
1705 if (size <= dev->bar_mapped_size)
1706 return 0;
1707 if (size > pci_resource_len(pdev, 0))
1708 return -ENOMEM;
1709 if (dev->bar)
1710 iounmap(dev->bar);
1711 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1712 if (!dev->bar) {
1713 dev->bar_mapped_size = 0;
1714 return -ENOMEM;
1715 }
1716 dev->bar_mapped_size = size;
1717 dev->dbs = dev->bar + NVME_REG_DBS;
1718
1719 return 0;
1720}
1721
1722static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1723{
1724 int result;
1725 u32 aqa;
1726 struct nvme_queue *nvmeq;
1727
1728 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1729 if (result < 0)
1730 return result;
1731
1732 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1733 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1734
1735 if (dev->subsystem &&
1736 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1737 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1738
1739 result = nvme_disable_ctrl(&dev->ctrl);
1740 if (result < 0)
1741 return result;
1742
1743 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1744 if (result)
1745 return result;
1746
1747 dev->ctrl.numa_node = dev_to_node(dev->dev);
1748
1749 nvmeq = &dev->queues[0];
1750 aqa = nvmeq->q_depth - 1;
1751 aqa |= aqa << 16;
1752
1753 writel(aqa, dev->bar + NVME_REG_AQA);
1754 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1755 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1756
1757 result = nvme_enable_ctrl(&dev->ctrl);
1758 if (result)
1759 return result;
1760
1761 nvmeq->cq_vector = 0;
1762 nvme_init_queue(nvmeq, 0);
1763 result = queue_request_irq(nvmeq);
1764 if (result) {
1765 dev->online_queues--;
1766 return result;
1767 }
1768
1769 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1770 return result;
1771}
1772
1773static int nvme_create_io_queues(struct nvme_dev *dev)
1774{
1775 unsigned i, max, rw_queues;
1776 int ret = 0;
1777
1778 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1779 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1780 ret = -ENOMEM;
1781 break;
1782 }
1783 }
1784
1785 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1786 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1787 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1788 dev->io_queues[HCTX_TYPE_READ];
1789 } else {
1790 rw_queues = max;
1791 }
1792
1793 for (i = dev->online_queues; i <= max; i++) {
1794 bool polled = i > rw_queues;
1795
1796 ret = nvme_create_queue(&dev->queues[i], i, polled);
1797 if (ret)
1798 break;
1799 }
1800
1801
1802
1803
1804
1805
1806
1807 return ret >= 0 ? 0 : ret;
1808}
1809
1810static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1811{
1812 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1813
1814 return 1ULL << (12 + 4 * szu);
1815}
1816
1817static u32 nvme_cmb_size(struct nvme_dev *dev)
1818{
1819 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1820}
1821
1822static void nvme_map_cmb(struct nvme_dev *dev)
1823{
1824 u64 size, offset;
1825 resource_size_t bar_size;
1826 struct pci_dev *pdev = to_pci_dev(dev->dev);
1827 int bar;
1828
1829 if (dev->cmb_size)
1830 return;
1831
1832 if (NVME_CAP_CMBS(dev->ctrl.cap))
1833 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1834
1835 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1836 if (!dev->cmbsz)
1837 return;
1838 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1839
1840 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1841 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1842 bar = NVME_CMB_BIR(dev->cmbloc);
1843 bar_size = pci_resource_len(pdev, bar);
1844
1845 if (offset > bar_size)
1846 return;
1847
1848
1849
1850
1851
1852 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1853 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1854 (pci_bus_address(pdev, bar) + offset),
1855 dev->bar + NVME_REG_CMBMSC);
1856 }
1857
1858
1859
1860
1861
1862
1863 if (size > bar_size - offset)
1864 size = bar_size - offset;
1865
1866 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1867 dev_warn(dev->ctrl.device,
1868 "failed to register the CMB\n");
1869 return;
1870 }
1871
1872 dev->cmb_size = size;
1873 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1874
1875 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1876 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1877 pci_p2pmem_publish(pdev, true);
1878}
1879
1880static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1881{
1882 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1883 u64 dma_addr = dev->host_mem_descs_dma;
1884 struct nvme_command c = { };
1885 int ret;
1886
1887 c.features.opcode = nvme_admin_set_features;
1888 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1889 c.features.dword11 = cpu_to_le32(bits);
1890 c.features.dword12 = cpu_to_le32(host_mem_size);
1891 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1892 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1893 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1894
1895 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1896 if (ret) {
1897 dev_warn(dev->ctrl.device,
1898 "failed to set host mem (err %d, flags %#x).\n",
1899 ret, bits);
1900 } else
1901 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1902
1903 return ret;
1904}
1905
1906static void nvme_free_host_mem(struct nvme_dev *dev)
1907{
1908 int i;
1909
1910 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1911 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1912 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1913
1914 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1915 le64_to_cpu(desc->addr),
1916 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1917 }
1918
1919 kfree(dev->host_mem_desc_bufs);
1920 dev->host_mem_desc_bufs = NULL;
1921 dma_free_coherent(dev->dev,
1922 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1923 dev->host_mem_descs, dev->host_mem_descs_dma);
1924 dev->host_mem_descs = NULL;
1925 dev->nr_host_mem_descs = 0;
1926}
1927
1928static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1929 u32 chunk_size)
1930{
1931 struct nvme_host_mem_buf_desc *descs;
1932 u32 max_entries, len;
1933 dma_addr_t descs_dma;
1934 int i = 0;
1935 void **bufs;
1936 u64 size, tmp;
1937
1938 tmp = (preferred + chunk_size - 1);
1939 do_div(tmp, chunk_size);
1940 max_entries = tmp;
1941
1942 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1943 max_entries = dev->ctrl.hmmaxd;
1944
1945 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1946 &descs_dma, GFP_KERNEL);
1947 if (!descs)
1948 goto out;
1949
1950 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1951 if (!bufs)
1952 goto out_free_descs;
1953
1954 for (size = 0; size < preferred && i < max_entries; size += len) {
1955 dma_addr_t dma_addr;
1956
1957 len = min_t(u64, chunk_size, preferred - size);
1958 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1959 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1960 if (!bufs[i])
1961 break;
1962
1963 descs[i].addr = cpu_to_le64(dma_addr);
1964 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1965 i++;
1966 }
1967
1968 if (!size)
1969 goto out_free_bufs;
1970
1971 dev->nr_host_mem_descs = i;
1972 dev->host_mem_size = size;
1973 dev->host_mem_descs = descs;
1974 dev->host_mem_descs_dma = descs_dma;
1975 dev->host_mem_desc_bufs = bufs;
1976 return 0;
1977
1978out_free_bufs:
1979 while (--i >= 0) {
1980 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1981
1982 dma_free_attrs(dev->dev, size, bufs[i],
1983 le64_to_cpu(descs[i].addr),
1984 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1985 }
1986
1987 kfree(bufs);
1988out_free_descs:
1989 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1990 descs_dma);
1991out:
1992 dev->host_mem_descs = NULL;
1993 return -ENOMEM;
1994}
1995
1996static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1997{
1998 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1999 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2000 u64 chunk_size;
2001
2002
2003 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2004 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2005 if (!min || dev->host_mem_size >= min)
2006 return 0;
2007 nvme_free_host_mem(dev);
2008 }
2009 }
2010
2011 return -ENOMEM;
2012}
2013
2014static int nvme_setup_host_mem(struct nvme_dev *dev)
2015{
2016 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2017 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2018 u64 min = (u64)dev->ctrl.hmmin * 4096;
2019 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2020 int ret;
2021
2022 preferred = min(preferred, max);
2023 if (min > max) {
2024 dev_warn(dev->ctrl.device,
2025 "min host memory (%lld MiB) above limit (%d MiB).\n",
2026 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2027 nvme_free_host_mem(dev);
2028 return 0;
2029 }
2030
2031
2032
2033
2034 if (dev->host_mem_descs) {
2035 if (dev->host_mem_size >= min)
2036 enable_bits |= NVME_HOST_MEM_RETURN;
2037 else
2038 nvme_free_host_mem(dev);
2039 }
2040
2041 if (!dev->host_mem_descs) {
2042 if (nvme_alloc_host_mem(dev, min, preferred)) {
2043 dev_warn(dev->ctrl.device,
2044 "failed to allocate host memory buffer.\n");
2045 return 0;
2046 }
2047
2048 dev_info(dev->ctrl.device,
2049 "allocated %lld MiB host memory buffer.\n",
2050 dev->host_mem_size >> ilog2(SZ_1M));
2051 }
2052
2053 ret = nvme_set_host_mem(dev, enable_bits);
2054 if (ret)
2055 nvme_free_host_mem(dev);
2056 return ret;
2057}
2058
2059static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2060 char *buf)
2061{
2062 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2063
2064 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2065 ndev->cmbloc, ndev->cmbsz);
2066}
2067static DEVICE_ATTR_RO(cmb);
2068
2069static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2070 char *buf)
2071{
2072 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2073
2074 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2075}
2076static DEVICE_ATTR_RO(cmbloc);
2077
2078static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2079 char *buf)
2080{
2081 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2082
2083 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2084}
2085static DEVICE_ATTR_RO(cmbsz);
2086
2087static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2088 char *buf)
2089{
2090 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2091
2092 return sysfs_emit(buf, "%d\n", ndev->hmb);
2093}
2094
2095static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2096 const char *buf, size_t count)
2097{
2098 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2099 bool new;
2100 int ret;
2101
2102 if (strtobool(buf, &new) < 0)
2103 return -EINVAL;
2104
2105 if (new == ndev->hmb)
2106 return count;
2107
2108 if (new) {
2109 ret = nvme_setup_host_mem(ndev);
2110 } else {
2111 ret = nvme_set_host_mem(ndev, 0);
2112 if (!ret)
2113 nvme_free_host_mem(ndev);
2114 }
2115
2116 if (ret < 0)
2117 return ret;
2118
2119 return count;
2120}
2121static DEVICE_ATTR_RW(hmb);
2122
2123static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2124 struct attribute *a, int n)
2125{
2126 struct nvme_ctrl *ctrl =
2127 dev_get_drvdata(container_of(kobj, struct device, kobj));
2128 struct nvme_dev *dev = to_nvme_dev(ctrl);
2129
2130 if (a == &dev_attr_cmb.attr ||
2131 a == &dev_attr_cmbloc.attr ||
2132 a == &dev_attr_cmbsz.attr) {
2133 if (!dev->cmbsz)
2134 return 0;
2135 }
2136 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2137 return 0;
2138
2139 return a->mode;
2140}
2141
2142static struct attribute *nvme_pci_attrs[] = {
2143 &dev_attr_cmb.attr,
2144 &dev_attr_cmbloc.attr,
2145 &dev_attr_cmbsz.attr,
2146 &dev_attr_hmb.attr,
2147 NULL,
2148};
2149
2150static const struct attribute_group nvme_pci_attr_group = {
2151 .attrs = nvme_pci_attrs,
2152 .is_visible = nvme_pci_attrs_are_visible,
2153};
2154
2155
2156
2157
2158
2159static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2160{
2161 struct nvme_dev *dev = affd->priv;
2162 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175 if (!nrirqs) {
2176 nrirqs = 1;
2177 nr_read_queues = 0;
2178 } else if (nrirqs == 1 || !nr_write_queues) {
2179 nr_read_queues = 0;
2180 } else if (nr_write_queues >= nrirqs) {
2181 nr_read_queues = 1;
2182 } else {
2183 nr_read_queues = nrirqs - nr_write_queues;
2184 }
2185
2186 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2187 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2188 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2189 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2190 affd->nr_sets = nr_read_queues ? 2 : 1;
2191}
2192
2193static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2194{
2195 struct pci_dev *pdev = to_pci_dev(dev->dev);
2196 struct irq_affinity affd = {
2197 .pre_vectors = 1,
2198 .calc_sets = nvme_calc_irq_sets,
2199 .priv = dev,
2200 };
2201 unsigned int irq_queues, poll_queues;
2202
2203
2204
2205
2206
2207 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2208 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2209
2210
2211
2212
2213
2214 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2215 dev->io_queues[HCTX_TYPE_READ] = 0;
2216
2217
2218
2219
2220
2221
2222 irq_queues = 1;
2223 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2224 irq_queues += (nr_io_queues - poll_queues);
2225 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2226 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2227}
2228
2229static void nvme_disable_io_queues(struct nvme_dev *dev)
2230{
2231 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2232 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2233}
2234
2235static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2236{
2237
2238
2239
2240
2241 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2242 return 1;
2243 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2244}
2245
2246static int nvme_setup_io_queues(struct nvme_dev *dev)
2247{
2248 struct nvme_queue *adminq = &dev->queues[0];
2249 struct pci_dev *pdev = to_pci_dev(dev->dev);
2250 unsigned int nr_io_queues;
2251 unsigned long size;
2252 int result;
2253
2254
2255
2256
2257
2258 dev->nr_write_queues = write_queues;
2259 dev->nr_poll_queues = poll_queues;
2260
2261 nr_io_queues = dev->nr_allocated_queues - 1;
2262 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2263 if (result < 0)
2264 return result;
2265
2266 if (nr_io_queues == 0)
2267 return 0;
2268
2269
2270
2271
2272
2273
2274
2275
2276 result = nvme_setup_io_queues_trylock(dev);
2277 if (result)
2278 return result;
2279 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2280 pci_free_irq(pdev, 0, adminq);
2281
2282 if (dev->cmb_use_sqes) {
2283 result = nvme_cmb_qdepth(dev, nr_io_queues,
2284 sizeof(struct nvme_command));
2285 if (result > 0)
2286 dev->q_depth = result;
2287 else
2288 dev->cmb_use_sqes = false;
2289 }
2290
2291 do {
2292 size = db_bar_size(dev, nr_io_queues);
2293 result = nvme_remap_bar(dev, size);
2294 if (!result)
2295 break;
2296 if (!--nr_io_queues) {
2297 result = -ENOMEM;
2298 goto out_unlock;
2299 }
2300 } while (1);
2301 adminq->q_db = dev->dbs;
2302
2303 retry:
2304
2305 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2306 pci_free_irq(pdev, 0, adminq);
2307
2308
2309
2310
2311
2312 pci_free_irq_vectors(pdev);
2313
2314 result = nvme_setup_irqs(dev, nr_io_queues);
2315 if (result <= 0) {
2316 result = -EIO;
2317 goto out_unlock;
2318 }
2319
2320 dev->num_vecs = result;
2321 result = max(result - 1, 1);
2322 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2323
2324
2325
2326
2327
2328
2329
2330 result = queue_request_irq(adminq);
2331 if (result)
2332 goto out_unlock;
2333 set_bit(NVMEQ_ENABLED, &adminq->flags);
2334 mutex_unlock(&dev->shutdown_lock);
2335
2336 result = nvme_create_io_queues(dev);
2337 if (result || dev->online_queues < 2)
2338 return result;
2339
2340 if (dev->online_queues - 1 < dev->max_qid) {
2341 nr_io_queues = dev->online_queues - 1;
2342 nvme_disable_io_queues(dev);
2343 result = nvme_setup_io_queues_trylock(dev);
2344 if (result)
2345 return result;
2346 nvme_suspend_io_queues(dev);
2347 goto retry;
2348 }
2349 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2350 dev->io_queues[HCTX_TYPE_DEFAULT],
2351 dev->io_queues[HCTX_TYPE_READ],
2352 dev->io_queues[HCTX_TYPE_POLL]);
2353 return 0;
2354out_unlock:
2355 mutex_unlock(&dev->shutdown_lock);
2356 return result;
2357}
2358
2359static void nvme_del_queue_end(struct request *req, blk_status_t error)
2360{
2361 struct nvme_queue *nvmeq = req->end_io_data;
2362
2363 blk_mq_free_request(req);
2364 complete(&nvmeq->delete_done);
2365}
2366
2367static void nvme_del_cq_end(struct request *req, blk_status_t error)
2368{
2369 struct nvme_queue *nvmeq = req->end_io_data;
2370
2371 if (error)
2372 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2373
2374 nvme_del_queue_end(req, error);
2375}
2376
2377static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2378{
2379 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2380 struct request *req;
2381 struct nvme_command cmd = { };
2382
2383 cmd.delete_queue.opcode = opcode;
2384 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2385
2386 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2387 if (IS_ERR(req))
2388 return PTR_ERR(req);
2389
2390 req->end_io_data = nvmeq;
2391
2392 init_completion(&nvmeq->delete_done);
2393 blk_execute_rq_nowait(NULL, req, false,
2394 opcode == nvme_admin_delete_cq ?
2395 nvme_del_cq_end : nvme_del_queue_end);
2396 return 0;
2397}
2398
2399static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2400{
2401 int nr_queues = dev->online_queues - 1, sent = 0;
2402 unsigned long timeout;
2403
2404 retry:
2405 timeout = NVME_ADMIN_TIMEOUT;
2406 while (nr_queues > 0) {
2407 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2408 break;
2409 nr_queues--;
2410 sent++;
2411 }
2412 while (sent) {
2413 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2414
2415 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2416 timeout);
2417 if (timeout == 0)
2418 return false;
2419
2420 sent--;
2421 if (nr_queues)
2422 goto retry;
2423 }
2424 return true;
2425}
2426
2427static void nvme_dev_add(struct nvme_dev *dev)
2428{
2429 int ret;
2430
2431 if (!dev->ctrl.tagset) {
2432 dev->tagset.ops = &nvme_mq_ops;
2433 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2434 dev->tagset.nr_maps = 2;
2435 if (dev->io_queues[HCTX_TYPE_POLL])
2436 dev->tagset.nr_maps++;
2437 dev->tagset.timeout = NVME_IO_TIMEOUT;
2438 dev->tagset.numa_node = dev->ctrl.numa_node;
2439 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2440 BLK_MQ_MAX_DEPTH) - 1;
2441 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2442 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2443 dev->tagset.driver_data = dev;
2444
2445
2446
2447
2448
2449
2450 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2451 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2452
2453 ret = blk_mq_alloc_tag_set(&dev->tagset);
2454 if (ret) {
2455 dev_warn(dev->ctrl.device,
2456 "IO queues tagset allocation failed %d\n", ret);
2457 return;
2458 }
2459 dev->ctrl.tagset = &dev->tagset;
2460 } else {
2461 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2462
2463
2464 nvme_free_queues(dev, dev->online_queues);
2465 }
2466
2467 nvme_dbbuf_set(dev);
2468}
2469
2470static int nvme_pci_enable(struct nvme_dev *dev)
2471{
2472 int result = -ENOMEM;
2473 struct pci_dev *pdev = to_pci_dev(dev->dev);
2474 int dma_address_bits = 64;
2475
2476 if (pci_enable_device_mem(pdev))
2477 return result;
2478
2479 pci_set_master(pdev);
2480
2481 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2482 dma_address_bits = 48;
2483 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2484 goto disable;
2485
2486 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2487 result = -ENODEV;
2488 goto disable;
2489 }
2490
2491
2492
2493
2494
2495
2496 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2497 if (result < 0)
2498 return result;
2499
2500 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2501
2502 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2503 io_queue_depth);
2504 dev->ctrl.sqsize = dev->q_depth - 1;
2505 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2506 dev->dbs = dev->bar + 4096;
2507
2508
2509
2510
2511
2512
2513 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2514 dev->io_sqes = 7;
2515 else
2516 dev->io_sqes = NVME_NVM_IOSQES;
2517
2518
2519
2520
2521
2522 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2523 dev->q_depth = 2;
2524 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2525 "set queue depth=%u to work around controller resets\n",
2526 dev->q_depth);
2527 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2528 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2529 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2530 dev->q_depth = 64;
2531 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2532 "set queue depth=%u\n", dev->q_depth);
2533 }
2534
2535
2536
2537
2538
2539 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2540 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2541 dev->q_depth = NVME_AQ_DEPTH + 2;
2542 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2543 dev->q_depth);
2544 }
2545
2546
2547 nvme_map_cmb(dev);
2548
2549 pci_enable_pcie_error_reporting(pdev);
2550 pci_save_state(pdev);
2551 return 0;
2552
2553 disable:
2554 pci_disable_device(pdev);
2555 return result;
2556}
2557
2558static void nvme_dev_unmap(struct nvme_dev *dev)
2559{
2560 if (dev->bar)
2561 iounmap(dev->bar);
2562 pci_release_mem_regions(to_pci_dev(dev->dev));
2563}
2564
2565static void nvme_pci_disable(struct nvme_dev *dev)
2566{
2567 struct pci_dev *pdev = to_pci_dev(dev->dev);
2568
2569 pci_free_irq_vectors(pdev);
2570
2571 if (pci_is_enabled(pdev)) {
2572 pci_disable_pcie_error_reporting(pdev);
2573 pci_disable_device(pdev);
2574 }
2575}
2576
2577static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2578{
2579 bool dead = true, freeze = false;
2580 struct pci_dev *pdev = to_pci_dev(dev->dev);
2581
2582 mutex_lock(&dev->shutdown_lock);
2583 if (pci_is_enabled(pdev)) {
2584 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2585
2586 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2587 dev->ctrl.state == NVME_CTRL_RESETTING) {
2588 freeze = true;
2589 nvme_start_freeze(&dev->ctrl);
2590 }
2591 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2592 pdev->error_state != pci_channel_io_normal);
2593 }
2594
2595
2596
2597
2598
2599 if (!dead && shutdown && freeze)
2600 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2601
2602 nvme_stop_queues(&dev->ctrl);
2603
2604 if (!dead && dev->ctrl.queue_count > 0) {
2605 nvme_disable_io_queues(dev);
2606 nvme_disable_admin_queue(dev, shutdown);
2607 }
2608 nvme_suspend_io_queues(dev);
2609 nvme_suspend_queue(&dev->queues[0]);
2610 nvme_pci_disable(dev);
2611 nvme_reap_pending_cqes(dev);
2612
2613 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2614 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2615 blk_mq_tagset_wait_completed_request(&dev->tagset);
2616 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2617
2618
2619
2620
2621
2622
2623 if (shutdown) {
2624 nvme_start_queues(&dev->ctrl);
2625 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2626 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2627 }
2628 mutex_unlock(&dev->shutdown_lock);
2629}
2630
2631static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2632{
2633 if (!nvme_wait_reset(&dev->ctrl))
2634 return -EBUSY;
2635 nvme_dev_disable(dev, shutdown);
2636 return 0;
2637}
2638
2639static int nvme_setup_prp_pools(struct nvme_dev *dev)
2640{
2641 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2642 NVME_CTRL_PAGE_SIZE,
2643 NVME_CTRL_PAGE_SIZE, 0);
2644 if (!dev->prp_page_pool)
2645 return -ENOMEM;
2646
2647
2648 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2649 256, 256, 0);
2650 if (!dev->prp_small_pool) {
2651 dma_pool_destroy(dev->prp_page_pool);
2652 return -ENOMEM;
2653 }
2654 return 0;
2655}
2656
2657static void nvme_release_prp_pools(struct nvme_dev *dev)
2658{
2659 dma_pool_destroy(dev->prp_page_pool);
2660 dma_pool_destroy(dev->prp_small_pool);
2661}
2662
2663static void nvme_free_tagset(struct nvme_dev *dev)
2664{
2665 if (dev->tagset.tags)
2666 blk_mq_free_tag_set(&dev->tagset);
2667 dev->ctrl.tagset = NULL;
2668}
2669
2670static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2671{
2672 struct nvme_dev *dev = to_nvme_dev(ctrl);
2673
2674 nvme_dbbuf_dma_free(dev);
2675 nvme_free_tagset(dev);
2676 if (dev->ctrl.admin_q)
2677 blk_put_queue(dev->ctrl.admin_q);
2678 free_opal_dev(dev->ctrl.opal_dev);
2679 mempool_destroy(dev->iod_mempool);
2680 put_device(dev->dev);
2681 kfree(dev->queues);
2682 kfree(dev);
2683}
2684
2685static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2686{
2687
2688
2689
2690
2691 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2692 nvme_get_ctrl(&dev->ctrl);
2693 nvme_dev_disable(dev, false);
2694 nvme_kill_queues(&dev->ctrl);
2695 if (!queue_work(nvme_wq, &dev->remove_work))
2696 nvme_put_ctrl(&dev->ctrl);
2697}
2698
2699static void nvme_reset_work(struct work_struct *work)
2700{
2701 struct nvme_dev *dev =
2702 container_of(work, struct nvme_dev, ctrl.reset_work);
2703 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2704 int result;
2705
2706 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2707 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2708 dev->ctrl.state);
2709 result = -ENODEV;
2710 goto out;
2711 }
2712
2713
2714
2715
2716
2717 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2718 nvme_dev_disable(dev, false);
2719 nvme_sync_queues(&dev->ctrl);
2720
2721 mutex_lock(&dev->shutdown_lock);
2722 result = nvme_pci_enable(dev);
2723 if (result)
2724 goto out_unlock;
2725
2726 result = nvme_pci_configure_admin_queue(dev);
2727 if (result)
2728 goto out_unlock;
2729
2730 result = nvme_alloc_admin_tags(dev);
2731 if (result)
2732 goto out_unlock;
2733
2734
2735
2736
2737
2738 dev->ctrl.max_hw_sectors = min_t(u32,
2739 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2740 dev->ctrl.max_segments = NVME_MAX_SEGS;
2741
2742
2743
2744
2745 dma_set_max_seg_size(dev->dev, 0xffffffff);
2746 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2747
2748 mutex_unlock(&dev->shutdown_lock);
2749
2750
2751
2752
2753
2754 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2755 dev_warn(dev->ctrl.device,
2756 "failed to mark controller CONNECTING\n");
2757 result = -EBUSY;
2758 goto out;
2759 }
2760
2761
2762
2763
2764
2765 dev->ctrl.max_integrity_segments = 1;
2766
2767 result = nvme_init_ctrl_finish(&dev->ctrl);
2768 if (result)
2769 goto out;
2770
2771 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2772 if (!dev->ctrl.opal_dev)
2773 dev->ctrl.opal_dev =
2774 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2775 else if (was_suspend)
2776 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2777 } else {
2778 free_opal_dev(dev->ctrl.opal_dev);
2779 dev->ctrl.opal_dev = NULL;
2780 }
2781
2782 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2783 result = nvme_dbbuf_dma_alloc(dev);
2784 if (result)
2785 dev_warn(dev->dev,
2786 "unable to allocate dma for dbbuf\n");
2787 }
2788
2789 if (dev->ctrl.hmpre) {
2790 result = nvme_setup_host_mem(dev);
2791 if (result < 0)
2792 goto out;
2793 }
2794
2795 result = nvme_setup_io_queues(dev);
2796 if (result)
2797 goto out;
2798
2799
2800
2801
2802
2803 if (dev->online_queues < 2) {
2804 dev_warn(dev->ctrl.device, "IO queues not created\n");
2805 nvme_kill_queues(&dev->ctrl);
2806 nvme_remove_namespaces(&dev->ctrl);
2807 nvme_free_tagset(dev);
2808 } else {
2809 nvme_start_queues(&dev->ctrl);
2810 nvme_wait_freeze(&dev->ctrl);
2811 nvme_dev_add(dev);
2812 nvme_unfreeze(&dev->ctrl);
2813 }
2814
2815
2816
2817
2818
2819 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2820 dev_warn(dev->ctrl.device,
2821 "failed to mark controller live state\n");
2822 result = -ENODEV;
2823 goto out;
2824 }
2825
2826 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2827 &nvme_pci_attr_group))
2828 dev->attrs_added = true;
2829
2830 nvme_start_ctrl(&dev->ctrl);
2831 return;
2832
2833 out_unlock:
2834 mutex_unlock(&dev->shutdown_lock);
2835 out:
2836 if (result)
2837 dev_warn(dev->ctrl.device,
2838 "Removing after probe failure status: %d\n", result);
2839 nvme_remove_dead_ctrl(dev);
2840}
2841
2842static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2843{
2844 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2845 struct pci_dev *pdev = to_pci_dev(dev->dev);
2846
2847 if (pci_get_drvdata(pdev))
2848 device_release_driver(&pdev->dev);
2849 nvme_put_ctrl(&dev->ctrl);
2850}
2851
2852static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2853{
2854 *val = readl(to_nvme_dev(ctrl)->bar + off);
2855 return 0;
2856}
2857
2858static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2859{
2860 writel(val, to_nvme_dev(ctrl)->bar + off);
2861 return 0;
2862}
2863
2864static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2865{
2866 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2867 return 0;
2868}
2869
2870static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2871{
2872 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2873
2874 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2875}
2876
2877static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2878 .name = "pcie",
2879 .module = THIS_MODULE,
2880 .flags = NVME_F_METADATA_SUPPORTED |
2881 NVME_F_PCI_P2PDMA,
2882 .reg_read32 = nvme_pci_reg_read32,
2883 .reg_write32 = nvme_pci_reg_write32,
2884 .reg_read64 = nvme_pci_reg_read64,
2885 .free_ctrl = nvme_pci_free_ctrl,
2886 .submit_async_event = nvme_pci_submit_async_event,
2887 .get_address = nvme_pci_get_address,
2888};
2889
2890static int nvme_dev_map(struct nvme_dev *dev)
2891{
2892 struct pci_dev *pdev = to_pci_dev(dev->dev);
2893
2894 if (pci_request_mem_regions(pdev, "nvme"))
2895 return -ENODEV;
2896
2897 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2898 goto release;
2899
2900 return 0;
2901 release:
2902 pci_release_mem_regions(pdev);
2903 return -ENODEV;
2904}
2905
2906static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2907{
2908 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2909
2910
2911
2912
2913
2914
2915
2916
2917 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2918 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2919 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2920 return NVME_QUIRK_NO_DEEPEST_PS;
2921 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2922
2923
2924
2925
2926
2927
2928 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2929 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2930 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2931 return NVME_QUIRK_NO_APST;
2932 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2933 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2934 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2935
2936
2937
2938
2939
2940
2941 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2942 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2943 return NVME_QUIRK_SIMPLE_SUSPEND;
2944 }
2945
2946 return 0;
2947}
2948
2949static void nvme_async_probe(void *data, async_cookie_t cookie)
2950{
2951 struct nvme_dev *dev = data;
2952
2953 flush_work(&dev->ctrl.reset_work);
2954 flush_work(&dev->ctrl.scan_work);
2955 nvme_put_ctrl(&dev->ctrl);
2956}
2957
2958static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2959{
2960 int node, result = -ENOMEM;
2961 struct nvme_dev *dev;
2962 unsigned long quirks = id->driver_data;
2963 size_t alloc_size;
2964
2965 node = dev_to_node(&pdev->dev);
2966 if (node == NUMA_NO_NODE)
2967 set_dev_node(&pdev->dev, first_memory_node);
2968
2969 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2970 if (!dev)
2971 return -ENOMEM;
2972
2973 dev->nr_write_queues = write_queues;
2974 dev->nr_poll_queues = poll_queues;
2975 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2976 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2977 sizeof(struct nvme_queue), GFP_KERNEL, node);
2978 if (!dev->queues)
2979 goto free;
2980
2981 dev->dev = get_device(&pdev->dev);
2982 pci_set_drvdata(pdev, dev);
2983
2984 result = nvme_dev_map(dev);
2985 if (result)
2986 goto put_pci;
2987
2988 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2989 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2990 mutex_init(&dev->shutdown_lock);
2991
2992 result = nvme_setup_prp_pools(dev);
2993 if (result)
2994 goto unmap;
2995
2996 quirks |= check_vendor_combination_bug(pdev);
2997
2998 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2999
3000
3001
3002
3003 dev_info(&pdev->dev,
3004 "platform quirk: setting simple suspend\n");
3005 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3006 }
3007
3008
3009
3010
3011
3012 alloc_size = nvme_pci_iod_alloc_size();
3013 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3014
3015 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3016 mempool_kfree,
3017 (void *) alloc_size,
3018 GFP_KERNEL, node);
3019 if (!dev->iod_mempool) {
3020 result = -ENOMEM;
3021 goto release_pools;
3022 }
3023
3024 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3025 quirks);
3026 if (result)
3027 goto release_mempool;
3028
3029 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3030
3031 nvme_reset_ctrl(&dev->ctrl);
3032 async_schedule(nvme_async_probe, dev);
3033
3034 return 0;
3035
3036 release_mempool:
3037 mempool_destroy(dev->iod_mempool);
3038 release_pools:
3039 nvme_release_prp_pools(dev);
3040 unmap:
3041 nvme_dev_unmap(dev);
3042 put_pci:
3043 put_device(dev->dev);
3044 free:
3045 kfree(dev->queues);
3046 kfree(dev);
3047 return result;
3048}
3049
3050static void nvme_reset_prepare(struct pci_dev *pdev)
3051{
3052 struct nvme_dev *dev = pci_get_drvdata(pdev);
3053
3054
3055
3056
3057
3058
3059 nvme_disable_prepare_reset(dev, false);
3060 nvme_sync_queues(&dev->ctrl);
3061}
3062
3063static void nvme_reset_done(struct pci_dev *pdev)
3064{
3065 struct nvme_dev *dev = pci_get_drvdata(pdev);
3066
3067 if (!nvme_try_sched_reset(&dev->ctrl))
3068 flush_work(&dev->ctrl.reset_work);
3069}
3070
3071static void nvme_shutdown(struct pci_dev *pdev)
3072{
3073 struct nvme_dev *dev = pci_get_drvdata(pdev);
3074
3075 nvme_disable_prepare_reset(dev, true);
3076}
3077
3078static void nvme_remove_attrs(struct nvme_dev *dev)
3079{
3080 if (dev->attrs_added)
3081 sysfs_remove_group(&dev->ctrl.device->kobj,
3082 &nvme_pci_attr_group);
3083}
3084
3085
3086
3087
3088
3089
3090static void nvme_remove(struct pci_dev *pdev)
3091{
3092 struct nvme_dev *dev = pci_get_drvdata(pdev);
3093
3094 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3095 pci_set_drvdata(pdev, NULL);
3096
3097 if (!pci_device_is_present(pdev)) {
3098 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3099 nvme_dev_disable(dev, true);
3100 }
3101
3102 flush_work(&dev->ctrl.reset_work);
3103 nvme_stop_ctrl(&dev->ctrl);
3104 nvme_remove_namespaces(&dev->ctrl);
3105 nvme_dev_disable(dev, true);
3106 nvme_remove_attrs(dev);
3107 nvme_free_host_mem(dev);
3108 nvme_dev_remove_admin(dev);
3109 nvme_free_queues(dev, 0);
3110 nvme_release_prp_pools(dev);
3111 nvme_dev_unmap(dev);
3112 nvme_uninit_ctrl(&dev->ctrl);
3113}
3114
3115#ifdef CONFIG_PM_SLEEP
3116static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3117{
3118 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3119}
3120
3121static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3122{
3123 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3124}
3125
3126static int nvme_resume(struct device *dev)
3127{
3128 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3129 struct nvme_ctrl *ctrl = &ndev->ctrl;
3130
3131 if (ndev->last_ps == U32_MAX ||
3132 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3133 goto reset;
3134 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3135 goto reset;
3136
3137 return 0;
3138reset:
3139 return nvme_try_sched_reset(ctrl);
3140}
3141
3142static int nvme_suspend(struct device *dev)
3143{
3144 struct pci_dev *pdev = to_pci_dev(dev);
3145 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3146 struct nvme_ctrl *ctrl = &ndev->ctrl;
3147 int ret = -EBUSY;
3148
3149 ndev->last_ps = U32_MAX;
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164 if (pm_suspend_via_firmware() || !ctrl->npss ||
3165 !pcie_aspm_enabled(pdev) ||
3166 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3167 return nvme_disable_prepare_reset(ndev, true);
3168
3169 nvme_start_freeze(ctrl);
3170 nvme_wait_freeze(ctrl);
3171 nvme_sync_queues(ctrl);
3172
3173 if (ctrl->state != NVME_CTRL_LIVE)
3174 goto unfreeze;
3175
3176
3177
3178
3179
3180
3181 if (ndev->hmb) {
3182 ret = nvme_set_host_mem(ndev, 0);
3183 if (ret < 0)
3184 goto unfreeze;
3185 }
3186
3187 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3188 if (ret < 0)
3189 goto unfreeze;
3190
3191
3192
3193
3194
3195
3196 pci_save_state(pdev);
3197
3198 ret = nvme_set_power_state(ctrl, ctrl->npss);
3199 if (ret < 0)
3200 goto unfreeze;
3201
3202 if (ret) {
3203
3204 pci_load_saved_state(pdev, NULL);
3205
3206
3207
3208
3209
3210 ret = nvme_disable_prepare_reset(ndev, true);
3211 ctrl->npss = 0;
3212 }
3213unfreeze:
3214 nvme_unfreeze(ctrl);
3215 return ret;
3216}
3217
3218static int nvme_simple_suspend(struct device *dev)
3219{
3220 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3221
3222 return nvme_disable_prepare_reset(ndev, true);
3223}
3224
3225static int nvme_simple_resume(struct device *dev)
3226{
3227 struct pci_dev *pdev = to_pci_dev(dev);
3228 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3229
3230 return nvme_try_sched_reset(&ndev->ctrl);
3231}
3232
3233static const struct dev_pm_ops nvme_dev_pm_ops = {
3234 .suspend = nvme_suspend,
3235 .resume = nvme_resume,
3236 .freeze = nvme_simple_suspend,
3237 .thaw = nvme_simple_resume,
3238 .poweroff = nvme_simple_suspend,
3239 .restore = nvme_simple_resume,
3240};
3241#endif
3242
3243static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3244 pci_channel_state_t state)
3245{
3246 struct nvme_dev *dev = pci_get_drvdata(pdev);
3247
3248
3249
3250
3251
3252
3253 switch (state) {
3254 case pci_channel_io_normal:
3255 return PCI_ERS_RESULT_CAN_RECOVER;
3256 case pci_channel_io_frozen:
3257 dev_warn(dev->ctrl.device,
3258 "frozen state error detected, reset controller\n");
3259 nvme_dev_disable(dev, false);
3260 return PCI_ERS_RESULT_NEED_RESET;
3261 case pci_channel_io_perm_failure:
3262 dev_warn(dev->ctrl.device,
3263 "failure state error detected, request disconnect\n");
3264 return PCI_ERS_RESULT_DISCONNECT;
3265 }
3266 return PCI_ERS_RESULT_NEED_RESET;
3267}
3268
3269static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3270{
3271 struct nvme_dev *dev = pci_get_drvdata(pdev);
3272
3273 dev_info(dev->ctrl.device, "restart after slot reset\n");
3274 pci_restore_state(pdev);
3275 nvme_reset_ctrl(&dev->ctrl);
3276 return PCI_ERS_RESULT_RECOVERED;
3277}
3278
3279static void nvme_error_resume(struct pci_dev *pdev)
3280{
3281 struct nvme_dev *dev = pci_get_drvdata(pdev);
3282
3283 flush_work(&dev->ctrl.reset_work);
3284}
3285
3286static const struct pci_error_handlers nvme_err_handler = {
3287 .error_detected = nvme_error_detected,
3288 .slot_reset = nvme_slot_reset,
3289 .resume = nvme_error_resume,
3290 .reset_prepare = nvme_reset_prepare,
3291 .reset_done = nvme_reset_done,
3292};
3293
3294static const struct pci_device_id nvme_id_table[] = {
3295 { PCI_VDEVICE(INTEL, 0x0953),
3296 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3297 NVME_QUIRK_DEALLOCATE_ZEROES, },
3298 { PCI_VDEVICE(INTEL, 0x0a53),
3299 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3300 NVME_QUIRK_DEALLOCATE_ZEROES, },
3301 { PCI_VDEVICE(INTEL, 0x0a54),
3302 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3303 NVME_QUIRK_DEALLOCATE_ZEROES, },
3304 { PCI_VDEVICE(INTEL, 0x0a55),
3305 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3306 NVME_QUIRK_DEALLOCATE_ZEROES, },
3307 { PCI_VDEVICE(INTEL, 0xf1a5),
3308 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3309 NVME_QUIRK_MEDIUM_PRIO_SQ |
3310 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3311 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3312 { PCI_VDEVICE(INTEL, 0xf1a6),
3313 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3314 { PCI_VDEVICE(INTEL, 0x5845),
3315 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3316 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3317 { PCI_DEVICE(0x126f, 0x2263),
3318 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3319 { PCI_DEVICE(0x1bb1, 0x0100),
3320 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3321 NVME_QUIRK_NO_NS_DESC_LIST, },
3322 { PCI_DEVICE(0x1c58, 0x0003),
3323 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3324 { PCI_DEVICE(0x1c58, 0x0023),
3325 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3326 { PCI_DEVICE(0x1c5f, 0x0540),
3327 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3328 { PCI_DEVICE(0x144d, 0xa821),
3329 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3330 { PCI_DEVICE(0x144d, 0xa822),
3331 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3332 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3333 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3334 { PCI_DEVICE(0x1987, 0x5016),
3335 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3336 { PCI_DEVICE(0x1b4b, 0x1092),
3337 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3338 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3339 { PCI_DEVICE(0x10ec, 0x5762),
3340 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3341 { PCI_DEVICE(0x1cc1, 0x8201),
3342 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3343 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3344 { PCI_DEVICE(0x1c5c, 0x1504),
3345 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3346 { PCI_DEVICE(0x15b7, 0x2001),
3347 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3348 { PCI_DEVICE(0x1d97, 0x2263),
3349 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3350 { PCI_DEVICE(0x2646, 0x2262),
3351 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3352 { PCI_DEVICE(0x2646, 0x2263),
3353 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3354 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3355 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3356 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3357 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3358 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3359 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3360 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3361 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3362 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3363 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3364 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3365 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3366 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3367 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3368 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3369 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3370 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3371 NVME_QUIRK_128_BYTES_SQES |
3372 NVME_QUIRK_SHARED_TAGS |
3373 NVME_QUIRK_SKIP_CID_GEN },
3374
3375 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3376 { 0, }
3377};
3378MODULE_DEVICE_TABLE(pci, nvme_id_table);
3379
3380static struct pci_driver nvme_driver = {
3381 .name = "nvme",
3382 .id_table = nvme_id_table,
3383 .probe = nvme_probe,
3384 .remove = nvme_remove,
3385 .shutdown = nvme_shutdown,
3386#ifdef CONFIG_PM_SLEEP
3387 .driver = {
3388 .pm = &nvme_dev_pm_ops,
3389 },
3390#endif
3391 .sriov_configure = pci_sriov_configure_simple,
3392 .err_handler = &nvme_err_handler,
3393};
3394
3395static int __init nvme_init(void)
3396{
3397 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3398 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3399 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3400 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3401
3402 return pci_register_driver(&nvme_driver);
3403}
3404
3405static void __exit nvme_exit(void)
3406{
3407 pci_unregister_driver(&nvme_driver);
3408 flush_workqueue(nvme_wq);
3409}
3410
3411MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3412MODULE_LICENSE("GPL");
3413MODULE_VERSION("1.0");
3414module_init(nvme_init);
3415module_exit(nvme_exit);
3416