linux/drivers/parisc/lba_pci.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3**
   4**  PCI Lower Bus Adapter (LBA) manager
   5**
   6**      (c) Copyright 1999,2000 Grant Grundler
   7**      (c) Copyright 1999,2000 Hewlett-Packard Company
   8**
   9**
  10**
  11** This module primarily provides access to PCI bus (config/IOport
  12** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
  13** with 4 digit model numbers - eg C3000 (and A400...sigh).
  14**
  15** LBA driver isn't as simple as the Dino driver because:
  16**   (a) this chip has substantial bug fixes between revisions
  17**       (Only one Dino bug has a software workaround :^(  )
  18**   (b) has more options which we don't (yet) support (DMA hints, OLARD)
  19**   (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
  20**   (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
  21**       (dino only deals with "Legacy" PDC)
  22**
  23** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
  24** (I/O SAPIC is integratd in the LBA chip).
  25**
  26** FIXME: Add support to SBA and LBA drivers for DMA hint sets
  27** FIXME: Add support for PCI card hot-plug (OLARD).
  28*/
  29
  30#include <linux/delay.h>
  31#include <linux/types.h>
  32#include <linux/kernel.h>
  33#include <linux/spinlock.h>
  34#include <linux/init.h>         /* for __init */
  35#include <linux/pci.h>
  36#include <linux/ioport.h>
  37#include <linux/slab.h>
  38
  39#include <asm/byteorder.h>
  40#include <asm/pdc.h>
  41#include <asm/pdcpat.h>
  42#include <asm/page.h>
  43
  44#include <asm/ropes.h>
  45#include <asm/hardware.h>       /* for register_parisc_driver() stuff */
  46#include <asm/parisc-device.h>
  47#include <asm/io.h>             /* read/write stuff */
  48
  49#include "iommu.h"
  50
  51#undef DEBUG_LBA        /* general stuff */
  52#undef DEBUG_LBA_PORT   /* debug I/O Port access */
  53#undef DEBUG_LBA_CFG    /* debug Config Space Access (ie PCI Bus walk) */
  54#undef DEBUG_LBA_PAT    /* debug PCI Resource Mgt code - PDC PAT only */
  55
  56#undef FBB_SUPPORT      /* Fast Back-Back xfers - NOT READY YET */
  57
  58
  59#ifdef DEBUG_LBA
  60#define DBG(x...)       printk(x)
  61#else
  62#define DBG(x...)
  63#endif
  64
  65#ifdef DEBUG_LBA_PORT
  66#define DBG_PORT(x...)  printk(x)
  67#else
  68#define DBG_PORT(x...)
  69#endif
  70
  71#ifdef DEBUG_LBA_CFG
  72#define DBG_CFG(x...)   printk(x)
  73#else
  74#define DBG_CFG(x...)
  75#endif
  76
  77#ifdef DEBUG_LBA_PAT
  78#define DBG_PAT(x...)   printk(x)
  79#else
  80#define DBG_PAT(x...)
  81#endif
  82
  83
  84/*
  85** Config accessor functions only pass in the 8-bit bus number and not
  86** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
  87** number based on what firmware wrote into the scratch register.
  88**
  89** The "secondary" bus number is set to this before calling
  90** pci_register_ops(). If any PPB's are present, the scan will
  91** discover them and update the "secondary" and "subordinate"
  92** fields in the pci_bus structure.
  93**
  94** Changes in the configuration *may* result in a different
  95** bus number for each LBA depending on what firmware does.
  96*/
  97
  98#define MODULE_NAME "LBA"
  99
 100/* non-postable I/O port space, densely packed */
 101#define LBA_PORT_BASE   (PCI_F_EXTEND | 0xfee00000UL)
 102static void __iomem *astro_iop_base __read_mostly;
 103
 104static u32 lba_t32;
 105
 106/* lba flags */
 107#define LBA_FLAG_SKIP_PROBE     0x10
 108
 109#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
 110
 111static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba)
 112{
 113        return container_of(hba, struct lba_device, hba);
 114}
 115
 116/*
 117** Only allow 8 subsidiary busses per LBA
 118** Problem is the PCI bus numbering is globally shared.
 119*/
 120#define LBA_MAX_NUM_BUSES 8
 121
 122/************************************
 123 * LBA register read and write support
 124 *
 125 * BE WARNED: register writes are posted.
 126 *  (ie follow writes which must reach HW with a read)
 127 */
 128#define READ_U8(addr)  __raw_readb(addr)
 129#define READ_U16(addr) __raw_readw(addr)
 130#define READ_U32(addr) __raw_readl(addr)
 131#define WRITE_U8(value, addr)  __raw_writeb(value, addr)
 132#define WRITE_U16(value, addr) __raw_writew(value, addr)
 133#define WRITE_U32(value, addr) __raw_writel(value, addr)
 134
 135#define READ_REG8(addr)  readb(addr)
 136#define READ_REG16(addr) readw(addr)
 137#define READ_REG32(addr) readl(addr)
 138#define READ_REG64(addr) readq(addr)
 139#define WRITE_REG8(value, addr)  writeb(value, addr)
 140#define WRITE_REG16(value, addr) writew(value, addr)
 141#define WRITE_REG32(value, addr) writel(value, addr)
 142
 143
 144#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
 145#define LBA_CFG_BUS(tok)  ((u8) ((tok)>>16))
 146#define LBA_CFG_DEV(tok)  ((u8) ((tok)>>11) & 0x1f)
 147#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
 148
 149
 150/*
 151** Extract LBA (Rope) number from HPA
 152** REVISIT: 16 ropes for Stretch/Ike?
 153*/
 154#define ROPES_PER_IOC   8
 155#define LBA_NUM(x)    ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
 156
 157
 158static void
 159lba_dump_res(struct resource *r, int d)
 160{
 161        int i;
 162
 163        if (NULL == r)
 164                return;
 165
 166        printk(KERN_DEBUG "(%p)", r->parent);
 167        for (i = d; i ; --i) printk(" ");
 168        printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
 169                (long)r->start, (long)r->end, r->flags);
 170        lba_dump_res(r->child, d+2);
 171        lba_dump_res(r->sibling, d);
 172}
 173
 174
 175/*
 176** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
 177** workaround for cfg cycles:
 178**      -- preserve  LBA state
 179**      -- prevent any DMA from occurring
 180**      -- turn on smart mode
 181**      -- probe with config writes before doing config reads
 182**      -- check ERROR_STATUS
 183**      -- clear ERROR_STATUS
 184**      -- restore LBA state
 185**
 186** The workaround is only used for device discovery.
 187*/
 188
 189static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
 190{
 191        u8 first_bus = d->hba.hba_bus->busn_res.start;
 192        u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
 193
 194        if ((bus < first_bus) ||
 195            (bus > last_sub_bus) ||
 196            ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
 197                return 0;
 198        }
 199
 200        return 1;
 201}
 202
 203
 204
 205#define LBA_CFG_SETUP(d, tok) {                         \
 206    /* Save contents of error config register.  */                      \
 207    error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);             \
 208\
 209    /* Save contents of status control register.  */                    \
 210    status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);               \
 211\
 212    /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA          \
 213    ** arbitration for full bus walks.                                  \
 214    */                                                                  \
 215        /* Save contents of arb mask register. */                       \
 216        arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);         \
 217\
 218        /*                                                              \
 219         * Turn off all device arbitration bits (i.e. everything        \
 220         * except arbitration enable bit).                              \
 221         */                                                             \
 222        WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);              \
 223\
 224    /*                                                                  \
 225     * Set the smart mode bit so that master aborts don't cause         \
 226     * LBA to go into PCI fatal mode (required).                        \
 227     */                                                                 \
 228    WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);    \
 229}
 230
 231
 232#define LBA_CFG_PROBE(d, tok) {                         \
 233    /*                                                                  \
 234     * Setup Vendor ID write and read back the address register         \
 235     * to make sure that LBA is the bus master.                         \
 236     */                                                                 \
 237    WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
 238    /*                                                                  \
 239     * Read address register to ensure that LBA is the bus master,      \
 240     * which implies that DMA traffic has stopped when DMA arb is off.  \
 241     */                                                                 \
 242    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);        \
 243    /*                                                                  \
 244     * Generate a cfg write cycle (will have no affect on               \
 245     * Vendor ID register since read-only).                             \
 246     */                                                                 \
 247    WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);             \
 248    /*                                                                  \
 249     * Make sure write has completed before proceeding further,         \
 250     * i.e. before setting clear enable.                                \
 251     */                                                                 \
 252    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);        \
 253}
 254
 255
 256/*
 257 * HPREVISIT:
 258 *   -- Can't tell if config cycle got the error.
 259 *
 260 *              OV bit is broken until rev 4.0, so can't use OV bit and
 261 *              LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
 262 *
 263 *              As of rev 4.0, no longer need the error check.
 264 *
 265 *   -- Even if we could tell, we still want to return -1
 266 *      for **ANY** error (not just master abort).
 267 *
 268 *   -- Only clear non-fatal errors (we don't want to bring
 269 *      LBA out of pci-fatal mode).
 270 *
 271 *              Actually, there is still a race in which
 272 *              we could be clearing a fatal error.  We will
 273 *              live with this during our initial bus walk
 274 *              until rev 4.0 (no driver activity during
 275 *              initial bus walk).  The initial bus walk
 276 *              has race conditions concerning the use of
 277 *              smart mode as well.
 278 */
 279
 280#define LBA_MASTER_ABORT_ERROR 0xc
 281#define LBA_FATAL_ERROR 0x10
 282
 283#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) {               \
 284    u32 error_status = 0;                                               \
 285    /*                                                                  \
 286     * Set clear enable (CE) bit. Unset by HW when new                  \
 287     * errors are logged -- LBA HW ERS section 14.3.3).         \
 288     */                                                                 \
 289    WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
 290    error_status = READ_REG32(base + LBA_ERROR_STATUS);         \
 291    if ((error_status & 0x1f) != 0) {                                   \
 292        /*                                                              \
 293         * Fail the config read request.                                \
 294         */                                                             \
 295        error = 1;                                                      \
 296        if ((error_status & LBA_FATAL_ERROR) == 0) {                    \
 297            /*                                                          \
 298             * Clear error status (if fatal bit not set) by setting     \
 299             * clear error log bit (CL).                                \
 300             */                                                         \
 301            WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
 302        }                                                               \
 303    }                                                                   \
 304}
 305
 306#define LBA_CFG_TR4_ADDR_SETUP(d, addr)                                 \
 307        WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
 308
 309#define LBA_CFG_ADDR_SETUP(d, addr) {                                   \
 310    WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);  \
 311    /*                                                                  \
 312     * Read address register to ensure that LBA is the bus master,      \
 313     * which implies that DMA traffic has stopped when DMA arb is off.  \
 314     */                                                                 \
 315    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);        \
 316}
 317
 318
 319#define LBA_CFG_RESTORE(d, base) {                                      \
 320    /*                                                                  \
 321     * Restore status control register (turn off clear enable).         \
 322     */                                                                 \
 323    WRITE_REG32(status_control, base + LBA_STAT_CTL);                   \
 324    /*                                                                  \
 325     * Restore error config register (turn off smart mode).             \
 326     */                                                                 \
 327    WRITE_REG32(error_config, base + LBA_ERROR_CONFIG);                 \
 328        /*                                                              \
 329         * Restore arb mask register (reenables DMA arbitration).       \
 330         */                                                             \
 331        WRITE_REG32(arb_mask, base + LBA_ARB_MASK);                     \
 332}
 333
 334
 335
 336static unsigned int
 337lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
 338{
 339        u32 data = ~0U;
 340        int error = 0;
 341        u32 arb_mask = 0;       /* used by LBA_CFG_SETUP/RESTORE */
 342        u32 error_config = 0;   /* used by LBA_CFG_SETUP/RESTORE */
 343        u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
 344
 345        LBA_CFG_SETUP(d, tok);
 346        LBA_CFG_PROBE(d, tok);
 347        LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
 348        if (!error) {
 349                void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 350
 351                LBA_CFG_ADDR_SETUP(d, tok | reg);
 352                switch (size) {
 353                case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
 354                case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
 355                case 4: data = READ_REG32(data_reg); break;
 356                }
 357        }
 358        LBA_CFG_RESTORE(d, d->hba.base_addr);
 359        return(data);
 360}
 361
 362
 363static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
 364{
 365        struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 366        u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 367        u32 tok = LBA_CFG_TOK(local_bus, devfn);
 368        void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 369
 370        if ((pos > 255) || (devfn > 255))
 371                return -EINVAL;
 372
 373/* FIXME: B2K/C3600 workaround is always use old method... */
 374        /* if (!LBA_SKIP_PROBE(d)) */ {
 375                /* original - Generate config cycle on broken elroy
 376                  with risk we will miss PCI bus errors. */
 377                *data = lba_rd_cfg(d, tok, pos, size);
 378                DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
 379                return 0;
 380        }
 381
 382        if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
 383                DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
 384                /* either don't want to look or know device isn't present. */
 385                *data = ~0U;
 386                return(0);
 387        }
 388
 389        /* Basic Algorithm
 390        ** Should only get here on fully working LBA rev.
 391        ** This is how simple the code should have been.
 392        */
 393        LBA_CFG_ADDR_SETUP(d, tok | pos);
 394        switch(size) {
 395        case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
 396        case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
 397        case 4: *data = READ_REG32(data_reg); break;
 398        }
 399        DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
 400        return 0;
 401}
 402
 403
 404static void
 405lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
 406{
 407        int error = 0;
 408        u32 arb_mask = 0;
 409        u32 error_config = 0;
 410        u32 status_control = 0;
 411        void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 412
 413        LBA_CFG_SETUP(d, tok);
 414        LBA_CFG_ADDR_SETUP(d, tok | reg);
 415        switch (size) {
 416        case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
 417        case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
 418        case 4: WRITE_REG32(data, data_reg);             break;
 419        }
 420        LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
 421        LBA_CFG_RESTORE(d, d->hba.base_addr);
 422}
 423
 424
 425/*
 426 * LBA 4.0 config write code implements non-postable semantics
 427 * by doing a read of CONFIG ADDR after the write.
 428 */
 429
 430static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
 431{
 432        struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 433        u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 434        u32 tok = LBA_CFG_TOK(local_bus,devfn);
 435
 436        if ((pos > 255) || (devfn > 255))
 437                return -EINVAL;
 438
 439        if (!LBA_SKIP_PROBE(d)) {
 440                /* Original Workaround */
 441                lba_wr_cfg(d, tok, pos, (u32) data, size);
 442                DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
 443                return 0;
 444        }
 445
 446        if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
 447                DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
 448                return 1; /* New Workaround */
 449        }
 450
 451        DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
 452
 453        /* Basic Algorithm */
 454        LBA_CFG_ADDR_SETUP(d, tok | pos);
 455        switch(size) {
 456        case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
 457                   break;
 458        case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
 459                   break;
 460        case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
 461                   break;
 462        }
 463        /* flush posted write */
 464        lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
 465        return 0;
 466}
 467
 468
 469static struct pci_ops elroy_cfg_ops = {
 470        .read =         elroy_cfg_read,
 471        .write =        elroy_cfg_write,
 472};
 473
 474/*
 475 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
 476 * TR4.0 as no additional bugs were found in this areea between Elroy and
 477 * Mercury
 478 */
 479
 480static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
 481{
 482        struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 483        u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 484        u32 tok = LBA_CFG_TOK(local_bus, devfn);
 485        void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 486
 487        if ((pos > 255) || (devfn > 255))
 488                return -EINVAL;
 489
 490        LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
 491        switch(size) {
 492        case 1:
 493                *data = READ_REG8(data_reg + (pos & 3));
 494                break;
 495        case 2:
 496                *data = READ_REG16(data_reg + (pos & 2));
 497                break;
 498        case 4:
 499                *data = READ_REG32(data_reg);             break;
 500                break;
 501        }
 502
 503        DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
 504        return 0;
 505}
 506
 507/*
 508 * LBA 4.0 config write code implements non-postable semantics
 509 * by doing a read of CONFIG ADDR after the write.
 510 */
 511
 512static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
 513{
 514        struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 515        void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 516        u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 517        u32 tok = LBA_CFG_TOK(local_bus,devfn);
 518
 519        if ((pos > 255) || (devfn > 255))
 520                return -EINVAL;
 521
 522        DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
 523
 524        LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
 525        switch(size) {
 526        case 1:
 527                WRITE_REG8 (data, data_reg + (pos & 3));
 528                break;
 529        case 2:
 530                WRITE_REG16(data, data_reg + (pos & 2));
 531                break;
 532        case 4:
 533                WRITE_REG32(data, data_reg);
 534                break;
 535        }
 536
 537        /* flush posted write */
 538        lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
 539        return 0;
 540}
 541
 542static struct pci_ops mercury_cfg_ops = {
 543        .read =         mercury_cfg_read,
 544        .write =        mercury_cfg_write,
 545};
 546
 547
 548static void
 549lba_bios_init(void)
 550{
 551        DBG(MODULE_NAME ": lba_bios_init\n");
 552}
 553
 554
 555#ifdef CONFIG_64BIT
 556
 557/*
 558 * truncate_pat_collision:  Deal with overlaps or outright collisions
 559 *                      between PAT PDC reported ranges.
 560 *
 561 *   Broken PA8800 firmware will report lmmio range that
 562 *   overlaps with CPU HPA. Just truncate the lmmio range.
 563 *
 564 *   BEWARE: conflicts with this lmmio range may be an
 565 *   elmmio range which is pointing down another rope.
 566 *
 567 *  FIXME: only deals with one collision per range...theoretically we
 568 *  could have several. Supporting more than one collision will get messy.
 569 */
 570static unsigned long
 571truncate_pat_collision(struct resource *root, struct resource *new)
 572{
 573        unsigned long start = new->start;
 574        unsigned long end = new->end;
 575        struct resource *tmp = root->child;
 576
 577        if (end <= start || start < root->start || !tmp)
 578                return 0;
 579
 580        /* find first overlap */
 581        while (tmp && tmp->end < start)
 582                tmp = tmp->sibling;
 583
 584        /* no entries overlap */
 585        if (!tmp)  return 0;
 586
 587        /* found one that starts behind the new one
 588        ** Don't need to do anything.
 589        */
 590        if (tmp->start >= end) return 0;
 591
 592        if (tmp->start <= start) {
 593                /* "front" of new one overlaps */
 594                new->start = tmp->end + 1;
 595
 596                if (tmp->end >= end) {
 597                        /* AACCKK! totally overlaps! drop this range. */
 598                        return 1;
 599                }
 600        } 
 601
 602        if (tmp->end < end ) {
 603                /* "end" of new one overlaps */
 604                new->end = tmp->start - 1;
 605        }
 606
 607        printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
 608                                        "to [%lx,%lx]\n",
 609                        start, end,
 610                        (long)new->start, (long)new->end );
 611
 612        return 0;       /* truncation successful */
 613}
 614
 615/*
 616 * extend_lmmio_len: extend lmmio range to maximum length
 617 *
 618 * This is needed at least on C8000 systems to get the ATI FireGL card
 619 * working. On other systems we will currently not extend the lmmio space.
 620 */
 621static unsigned long
 622extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
 623{
 624        struct resource *tmp;
 625
 626        /* exit if not a C8000 */
 627        if (boot_cpu_data.cpu_type < mako)
 628                return end;
 629
 630        pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
 631                end - start, lba_len);
 632
 633        lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
 634
 635        pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
 636
 637
 638        end += lba_len;
 639        if (end < start) /* fix overflow */
 640                end = -1ULL;
 641
 642        pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
 643
 644        /* first overlap */
 645        for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
 646                pr_debug("LBA: testing %pR\n", tmp);
 647                if (tmp->start == start)
 648                        continue; /* ignore ourself */
 649                if (tmp->end < start)
 650                        continue;
 651                if (tmp->start > end)
 652                        continue;
 653                if (end >= tmp->start)
 654                        end = tmp->start - 1;
 655        }
 656
 657        pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
 658
 659        /* return new end */
 660        return end;
 661}
 662
 663#else
 664#define truncate_pat_collision(r,n)  (0)
 665#endif
 666
 667static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
 668{
 669        int idx;
 670        struct resource *r;
 671
 672        for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
 673                r = &dev->resource[idx];
 674                if (!r->flags)
 675                        continue;
 676                if (r->parent)  /* Already allocated */
 677                        continue;
 678                if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
 679                        /*
 680                         * Something is wrong with the region.
 681                         * Invalidate the resource to prevent
 682                         * child resource allocations in this
 683                         * range.
 684                         */
 685                        r->start = r->end = 0;
 686                        r->flags = 0;
 687                }
 688        }
 689}
 690
 691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
 692{
 693        struct pci_bus *child;
 694
 695        /* Depth-First Search on bus tree */
 696        if (bus->self)
 697                pcibios_allocate_bridge_resources(bus->self);
 698        list_for_each_entry(child, &bus->children, node)
 699                pcibios_allocate_bus_resources(child);
 700}
 701
 702
 703/*
 704** The algorithm is generic code.
 705** But it needs to access local data structures to get the IRQ base.
 706** Could make this a "pci_fixup_irq(bus, region)" but not sure
 707** it's worth it.
 708**
 709** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
 710** Resources aren't allocated until recursive buswalk below HBA is completed.
 711*/
 712static void
 713lba_fixup_bus(struct pci_bus *bus)
 714{
 715        struct pci_dev *dev;
 716#ifdef FBB_SUPPORT
 717        u16 status;
 718#endif
 719        struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
 720
 721        DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
 722                bus, (int)bus->busn_res.start, bus->bridge->platform_data);
 723
 724        /*
 725        ** Properly Setup MMIO resources for this bus.
 726        ** pci_alloc_primary_bus() mangles this.
 727        */
 728        if (bus->parent) {
 729                /* PCI-PCI Bridge */
 730                pci_read_bridge_bases(bus);
 731
 732                /* check and allocate bridge resources */
 733                pcibios_allocate_bus_resources(bus);
 734        } else {
 735                /* Host-PCI Bridge */
 736                int err;
 737
 738                DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
 739                        ldev->hba.io_space.name,
 740                        ldev->hba.io_space.start, ldev->hba.io_space.end,
 741                        ldev->hba.io_space.flags);
 742                DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
 743                        ldev->hba.lmmio_space.name,
 744                        ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
 745                        ldev->hba.lmmio_space.flags);
 746
 747                err = request_resource(&ioport_resource, &(ldev->hba.io_space));
 748                if (err < 0) {
 749                        lba_dump_res(&ioport_resource, 2);
 750                        BUG();
 751                }
 752
 753                if (ldev->hba.elmmio_space.flags) {
 754                        err = request_resource(&iomem_resource,
 755                                        &(ldev->hba.elmmio_space));
 756                        if (err < 0) {
 757
 758                                printk("FAILED: lba_fixup_bus() request for "
 759                                                "elmmio_space [%lx/%lx]\n",
 760                                                (long)ldev->hba.elmmio_space.start,
 761                                                (long)ldev->hba.elmmio_space.end);
 762
 763                                /* lba_dump_res(&iomem_resource, 2); */
 764                                /* BUG(); */
 765                        }
 766                }
 767
 768                if (ldev->hba.lmmio_space.flags) {
 769                        err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
 770                        if (err < 0) {
 771                                printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
 772                                        "lmmio_space [%lx/%lx]\n",
 773                                        (long)ldev->hba.lmmio_space.start,
 774                                        (long)ldev->hba.lmmio_space.end);
 775                        }
 776                }
 777
 778#ifdef CONFIG_64BIT
 779                /* GMMIO is  distributed range. Every LBA/Rope gets part it. */
 780                if (ldev->hba.gmmio_space.flags) {
 781                        err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
 782                        if (err < 0) {
 783                                printk("FAILED: lba_fixup_bus() request for "
 784                                        "gmmio_space [%lx/%lx]\n",
 785                                        (long)ldev->hba.gmmio_space.start,
 786                                        (long)ldev->hba.gmmio_space.end);
 787                                lba_dump_res(&iomem_resource, 2);
 788                                BUG();
 789                        }
 790                }
 791#endif
 792
 793        }
 794
 795        list_for_each_entry(dev, &bus->devices, bus_list) {
 796                int i;
 797
 798                DBG("lba_fixup_bus() %s\n", pci_name(dev));
 799
 800                /* Virtualize Device/Bridge Resources. */
 801                for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
 802                        struct resource *res = &dev->resource[i];
 803
 804                        /* If resource not allocated - skip it */
 805                        if (!res->start)
 806                                continue;
 807
 808                        /*
 809                        ** FIXME: this will result in whinging for devices
 810                        ** that share expansion ROMs (think quad tulip), but
 811                        ** isn't harmful.
 812                        */
 813                        pci_claim_resource(dev, i);
 814                }
 815
 816#ifdef FBB_SUPPORT
 817                /*
 818                ** If one device does not support FBB transfers,
 819                ** No one on the bus can be allowed to use them.
 820                */
 821                (void) pci_read_config_word(dev, PCI_STATUS, &status);
 822                bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
 823#endif
 824
 825                /*
 826                ** P2PB's have no IRQs. ignore them.
 827                */
 828                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 829                        pcibios_init_bridge(dev);
 830                        continue;
 831                }
 832
 833                /* Adjust INTERRUPT_LINE for this dev */
 834                iosapic_fixup_irq(ldev->iosapic_obj, dev);
 835        }
 836
 837#ifdef FBB_SUPPORT
 838/* FIXME/REVISIT - finish figuring out to set FBB on both
 839** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
 840** Can't fixup here anyway....garr...
 841*/
 842        if (fbb_enable) {
 843                if (bus->parent) {
 844                        u8 control;
 845                        /* enable on PPB */
 846                        (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
 847                        (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
 848
 849                } else {
 850                        /* enable on LBA */
 851                }
 852                fbb_enable = PCI_COMMAND_FAST_BACK;
 853        }
 854
 855        /* Lastly enable FBB/PERR/SERR on all devices too */
 856        list_for_each_entry(dev, &bus->devices, bus_list) {
 857                (void) pci_read_config_word(dev, PCI_COMMAND, &status);
 858                status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
 859                (void) pci_write_config_word(dev, PCI_COMMAND, status);
 860        }
 861#endif
 862}
 863
 864
 865static struct pci_bios_ops lba_bios_ops = {
 866        .init =         lba_bios_init,
 867        .fixup_bus =    lba_fixup_bus,
 868};
 869
 870
 871
 872
 873/*******************************************************
 874**
 875** LBA Sprockets "I/O Port" Space Accessor Functions
 876**
 877** This set of accessor functions is intended for use with
 878** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
 879**
 880** Many PCI devices don't require use of I/O port space (eg Tulip,
 881** NCR720) since they export the same registers to both MMIO and
 882** I/O port space. In general I/O port space is slower than
 883** MMIO since drivers are designed so PIO writes can be posted.
 884**
 885********************************************************/
 886
 887#define LBA_PORT_IN(size, mask) \
 888static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
 889{ \
 890        u##size t; \
 891        t = READ_REG##size(astro_iop_base + addr); \
 892        DBG_PORT(" 0x%x\n", t); \
 893        return (t); \
 894}
 895
 896LBA_PORT_IN( 8, 3)
 897LBA_PORT_IN(16, 2)
 898LBA_PORT_IN(32, 0)
 899
 900
 901
 902/*
 903** BUG X4107:  Ordering broken - DMA RD return can bypass PIO WR
 904**
 905** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
 906** guarantee non-postable completion semantics - not avoid X4107.
 907** The READ_U32 only guarantees the write data gets to elroy but
 908** out to the PCI bus. We can't read stuff from I/O port space
 909** since we don't know what has side-effects. Attempting to read
 910** from configuration space would be suicidal given the number of
 911** bugs in that elroy functionality.
 912**
 913**      Description:
 914**          DMA read results can improperly pass PIO writes (X4107).  The
 915**          result of this bug is that if a processor modifies a location in
 916**          memory after having issued PIO writes, the PIO writes are not
 917**          guaranteed to be completed before a PCI device is allowed to see
 918**          the modified data in a DMA read.
 919**
 920**          Note that IKE bug X3719 in TR1 IKEs will result in the same
 921**          symptom.
 922**
 923**      Workaround:
 924**          The workaround for this bug is to always follow a PIO write with
 925**          a PIO read to the same bus before starting DMA on that PCI bus.
 926**
 927*/
 928#define LBA_PORT_OUT(size, mask) \
 929static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 930{ \
 931        DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
 932        WRITE_REG##size(val, astro_iop_base + addr); \
 933        if (LBA_DEV(d)->hw_rev < 3) \
 934                lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
 935}
 936
 937LBA_PORT_OUT( 8, 3)
 938LBA_PORT_OUT(16, 2)
 939LBA_PORT_OUT(32, 0)
 940
 941
 942static struct pci_port_ops lba_astro_port_ops = {
 943        .inb =  lba_astro_in8,
 944        .inw =  lba_astro_in16,
 945        .inl =  lba_astro_in32,
 946        .outb = lba_astro_out8,
 947        .outw = lba_astro_out16,
 948        .outl = lba_astro_out32
 949};
 950
 951
 952#ifdef CONFIG_64BIT
 953#define PIOP_TO_GMMIO(lba, addr) \
 954        ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
 955
 956/*******************************************************
 957**
 958** LBA PAT "I/O Port" Space Accessor Functions
 959**
 960** This set of accessor functions is intended for use with
 961** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
 962**
 963** This uses the PIOP space located in the first 64MB of GMMIO.
 964** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
 965** bits 1:0 stay the same.  bits 15:2 become 25:12.
 966** Then add the base and we can generate an I/O Port cycle.
 967********************************************************/
 968#undef LBA_PORT_IN
 969#define LBA_PORT_IN(size, mask) \
 970static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
 971{ \
 972        u##size t; \
 973        DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
 974        t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
 975        DBG_PORT(" 0x%x\n", t); \
 976        return (t); \
 977}
 978
 979LBA_PORT_IN( 8, 3)
 980LBA_PORT_IN(16, 2)
 981LBA_PORT_IN(32, 0)
 982
 983
 984#undef LBA_PORT_OUT
 985#define LBA_PORT_OUT(size, mask) \
 986static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
 987{ \
 988        void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
 989        DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
 990        WRITE_REG##size(val, where); \
 991        /* flush the I/O down to the elroy at least */ \
 992        lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
 993}
 994
 995LBA_PORT_OUT( 8, 3)
 996LBA_PORT_OUT(16, 2)
 997LBA_PORT_OUT(32, 0)
 998
 999
1000static struct pci_port_ops lba_pat_port_ops = {
1001        .inb =  lba_pat_in8,
1002        .inw =  lba_pat_in16,
1003        .inl =  lba_pat_in32,
1004        .outb = lba_pat_out8,
1005        .outw = lba_pat_out16,
1006        .outl = lba_pat_out32
1007};
1008
1009
1010
1011/*
1012** make range information from PDC available to PCI subsystem.
1013** We make the PDC call here in order to get the PCI bus range
1014** numbers. The rest will get forwarded in pcibios_fixup_bus().
1015** We don't have a struct pci_bus assigned to us yet.
1016*/
1017static void
1018lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1019{
1020        unsigned long bytecnt;
1021        long io_count;
1022        long status;    /* PDC return status */
1023        long pa_count;
1024        pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell;    /* PA_VIEW */
1025        pdc_pat_cell_mod_maddr_block_t *io_pdc_cell;    /* IO_VIEW */
1026        int i;
1027
1028        pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
1029        if (!pa_pdc_cell)
1030                return;
1031
1032        io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
1033        if (!io_pdc_cell) {
1034                kfree(pa_pdc_cell);
1035                return;
1036        }
1037
1038        /* return cell module (IO view) */
1039        status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1040                                PA_VIEW, pa_pdc_cell);
1041        pa_count = pa_pdc_cell->mod[1];
1042
1043        status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1044                                IO_VIEW, io_pdc_cell);
1045        io_count = io_pdc_cell->mod[1];
1046
1047        /* We've already done this once for device discovery...*/
1048        if (status != PDC_OK) {
1049                panic("pdc_pat_cell_module() call failed for LBA!\n");
1050        }
1051
1052        if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) {
1053                panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1054        }
1055
1056        /*
1057        ** Inspect the resources PAT tells us about
1058        */
1059        for (i = 0; i < pa_count; i++) {
1060                struct {
1061                        unsigned long type;
1062                        unsigned long start;
1063                        unsigned long end;      /* aka finish */
1064                } *p, *io;
1065                struct resource *r;
1066
1067                p = (void *) &(pa_pdc_cell->mod[2+i*3]);
1068                io = (void *) &(io_pdc_cell->mod[2+i*3]);
1069
1070                /* Convert the PAT range data to PCI "struct resource" */
1071                switch(p->type & 0xff) {
1072                case PAT_PBNUM:
1073                        lba_dev->hba.bus_num.start = p->start;
1074                        lba_dev->hba.bus_num.end   = p->end;
1075                        lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
1076                        break;
1077
1078                case PAT_LMMIO:
1079                        /* used to fix up pre-initialized MEM BARs */
1080                        if (!lba_dev->hba.lmmio_space.flags) {
1081                                unsigned long lba_len;
1082
1083                                lba_len = ~READ_REG32(lba_dev->hba.base_addr
1084                                                + LBA_LMMIO_MASK);
1085                                if ((p->end - p->start) != lba_len)
1086                                        p->end = extend_lmmio_len(p->start,
1087                                                p->end, lba_len);
1088
1089                                sprintf(lba_dev->hba.lmmio_name,
1090                                                "PCI%02x LMMIO",
1091                                                (int)lba_dev->hba.bus_num.start);
1092                                lba_dev->hba.lmmio_space_offset = p->start -
1093                                        io->start;
1094                                r = &lba_dev->hba.lmmio_space;
1095                                r->name = lba_dev->hba.lmmio_name;
1096                        } else if (!lba_dev->hba.elmmio_space.flags) {
1097                                sprintf(lba_dev->hba.elmmio_name,
1098                                                "PCI%02x ELMMIO",
1099                                                (int)lba_dev->hba.bus_num.start);
1100                                r = &lba_dev->hba.elmmio_space;
1101                                r->name = lba_dev->hba.elmmio_name;
1102                        } else {
1103                                printk(KERN_WARNING MODULE_NAME
1104                                        " only supports 2 LMMIO resources!\n");
1105                                break;
1106                        }
1107
1108                        r->start  = p->start;
1109                        r->end    = p->end;
1110                        r->flags  = IORESOURCE_MEM;
1111                        r->parent = r->sibling = r->child = NULL;
1112                        break;
1113
1114                case PAT_GMMIO:
1115                        /* MMIO space > 4GB phys addr; for 64-bit BAR */
1116                        sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1117                                        (int)lba_dev->hba.bus_num.start);
1118                        r = &lba_dev->hba.gmmio_space;
1119                        r->name  = lba_dev->hba.gmmio_name;
1120                        r->start  = p->start;
1121                        r->end    = p->end;
1122                        r->flags  = IORESOURCE_MEM;
1123                        r->parent = r->sibling = r->child = NULL;
1124                        break;
1125
1126                case PAT_NPIOP:
1127                        printk(KERN_WARNING MODULE_NAME
1128                                " range[%d] : ignoring NPIOP (0x%lx)\n",
1129                                i, p->start);
1130                        break;
1131
1132                case PAT_PIOP:
1133                        /*
1134                        ** Postable I/O port space is per PCI host adapter.
1135                        ** base of 64MB PIOP region
1136                        */
1137                        lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024);
1138
1139                        sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1140                                        (int)lba_dev->hba.bus_num.start);
1141                        r = &lba_dev->hba.io_space;
1142                        r->name  = lba_dev->hba.io_name;
1143                        r->start  = HBA_PORT_BASE(lba_dev->hba.hba_num);
1144                        r->end    = r->start + HBA_PORT_SPACE_SIZE - 1;
1145                        r->flags  = IORESOURCE_IO;
1146                        r->parent = r->sibling = r->child = NULL;
1147                        break;
1148
1149                default:
1150                        printk(KERN_WARNING MODULE_NAME
1151                                " range[%d] : unknown pat range type (0x%lx)\n",
1152                                i, p->type & 0xff);
1153                        break;
1154                }
1155        }
1156
1157        kfree(pa_pdc_cell);
1158        kfree(io_pdc_cell);
1159}
1160#else
1161/* keep compiler from complaining about missing declarations */
1162#define lba_pat_port_ops lba_astro_port_ops
1163#define lba_pat_resources(pa_dev, lba_dev)
1164#endif  /* CONFIG_64BIT */
1165
1166
1167extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1168extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1169
1170
1171static void
1172lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1173{
1174        struct resource *r;
1175        int lba_num;
1176
1177        lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1178
1179        /*
1180        ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1181        ** represents bus->secondary and the second byte represents
1182        ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1183        ** PCI bus walk *should* end up with the same result.
1184        ** FIXME: But we don't have sanity checks in PCI or LBA.
1185        */
1186        lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1187        r = &(lba_dev->hba.bus_num);
1188        r->name = "LBA PCI Busses";
1189        r->start = lba_num & 0xff;
1190        r->end = (lba_num>>8) & 0xff;
1191        r->flags = IORESOURCE_BUS;
1192
1193        /* Set up local PCI Bus resources - we don't need them for
1194        ** Legacy boxes but it's nice to see in /proc/iomem.
1195        */
1196        r = &(lba_dev->hba.lmmio_space);
1197        sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1198                                        (int)lba_dev->hba.bus_num.start);
1199        r->name  = lba_dev->hba.lmmio_name;
1200
1201#if 1
1202        /* We want the CPU -> IO routing of addresses.
1203         * The SBA BASE/MASK registers control CPU -> IO routing.
1204         * Ask SBA what is routed to this rope/LBA.
1205         */
1206        sba_distributed_lmmio(pa_dev, r);
1207#else
1208        /*
1209         * The LBA BASE/MASK registers control IO -> System routing.
1210         *
1211         * The following code works but doesn't get us what we want.
1212         * Well, only because firmware (v5.0) on C3000 doesn't program
1213         * the LBA BASE/MASE registers to be the exact inverse of 
1214         * the corresponding SBA registers. Other Astro/Pluto
1215         * based platform firmware may do it right.
1216         *
1217         * Should someone want to mess with MSI, they may need to
1218         * reprogram LBA BASE/MASK registers. Thus preserve the code
1219         * below until MSI is known to work on C3000/A500/N4000/RP3440.
1220         *
1221         * Using the code below, /proc/iomem shows:
1222         * ...
1223         * f0000000-f0ffffff : PCI00 LMMIO
1224         *   f05d0000-f05d0000 : lcd_data
1225         *   f05d0008-f05d0008 : lcd_cmd
1226         * f1000000-f1ffffff : PCI01 LMMIO
1227         * f4000000-f4ffffff : PCI02 LMMIO
1228         *   f4000000-f4001fff : sym53c8xx
1229         *   f4002000-f4003fff : sym53c8xx
1230         *   f4004000-f40043ff : sym53c8xx
1231         *   f4005000-f40053ff : sym53c8xx
1232         *   f4007000-f4007fff : ohci_hcd
1233         *   f4008000-f40083ff : tulip
1234         * f6000000-f6ffffff : PCI03 LMMIO
1235         * f8000000-fbffffff : PCI00 ELMMIO
1236         *   fa100000-fa4fffff : stifb mmio
1237         *   fb000000-fb1fffff : stifb fb
1238         *
1239         * But everything listed under PCI02 actually lives under PCI00.
1240         * This is clearly wrong.
1241         *
1242         * Asking SBA how things are routed tells the correct story:
1243         * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1244         * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1245         * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1246         * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1247         * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1248         *
1249         * Which looks like this in /proc/iomem:
1250         * f4000000-f47fffff : PCI00 LMMIO
1251         *   f4000000-f4001fff : sym53c8xx
1252         *   ...[deteled core devices - same as above]...
1253         *   f4008000-f40083ff : tulip
1254         * f4800000-f4ffffff : PCI01 LMMIO
1255         * f6000000-f67fffff : PCI02 LMMIO
1256         * f7000000-f77fffff : PCI03 LMMIO
1257         * f9000000-f9ffffff : PCI02 ELMMIO
1258         * fa000000-fbffffff : PCI03 ELMMIO
1259         *   fa100000-fa4fffff : stifb mmio
1260         *   fb000000-fb1fffff : stifb fb
1261         *
1262         * ie all Built-in core are under now correctly under PCI00.
1263         * The "PCI02 ELMMIO" directed range is for:
1264         *  +-[02]---03.0  3Dfx Interactive, Inc. Voodoo 2
1265         *
1266         * All is well now.
1267         */
1268        r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1269        if (r->start & 1) {
1270                unsigned long rsize;
1271
1272                r->flags = IORESOURCE_MEM;
1273                /* mmio_mask also clears Enable bit */
1274                r->start &= mmio_mask;
1275                r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
1276                rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1277
1278                /*
1279                ** Each rope only gets part of the distributed range.
1280                ** Adjust "window" for this rope.
1281                */
1282                rsize /= ROPES_PER_IOC;
1283                r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
1284                r->end = r->start + rsize;
1285        } else {
1286                r->end = r->start = 0;  /* Not enabled. */
1287        }
1288#endif
1289
1290        /*
1291        ** "Directed" ranges are used when the "distributed range" isn't
1292        ** sufficient for all devices below a given LBA.  Typically devices
1293        ** like graphics cards or X25 may need a directed range when the
1294        ** bus has multiple slots (ie multiple devices) or the device
1295        ** needs more than the typical 4 or 8MB a distributed range offers.
1296        **
1297        ** The main reason for ignoring it now frigging complications.
1298        ** Directed ranges may overlap (and have precedence) over
1299        ** distributed ranges. Or a distributed range assigned to a unused
1300        ** rope may be used by a directed range on a different rope.
1301        ** Support for graphics devices may require fixing this
1302        ** since they may be assigned a directed range which overlaps
1303        ** an existing (but unused portion of) distributed range.
1304        */
1305        r = &(lba_dev->hba.elmmio_space);
1306        sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1307                                        (int)lba_dev->hba.bus_num.start);
1308        r->name  = lba_dev->hba.elmmio_name;
1309
1310#if 1
1311        /* See comment which precedes call to sba_directed_lmmio() */
1312        sba_directed_lmmio(pa_dev, r);
1313#else
1314        r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1315
1316        if (r->start & 1) {
1317                unsigned long rsize;
1318                r->flags = IORESOURCE_MEM;
1319                /* mmio_mask also clears Enable bit */
1320                r->start &= mmio_mask;
1321                r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
1322                rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1323                r->end = r->start + ~rsize;
1324        }
1325#endif
1326
1327        r = &(lba_dev->hba.io_space);
1328        sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1329                                        (int)lba_dev->hba.bus_num.start);
1330        r->name  = lba_dev->hba.io_name;
1331        r->flags = IORESOURCE_IO;
1332        r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1333        r->end   = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1334
1335        /* Virtualize the I/O Port space ranges */
1336        lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1337        r->start |= lba_num;
1338        r->end   |= lba_num;
1339}
1340
1341
1342/**************************************************************************
1343**
1344**   LBA initialization code (HW and SW)
1345**
1346**   o identify LBA chip itself
1347**   o initialize LBA chip modes (HardFail)
1348**   o FIXME: initialize DMA hints for reasonable defaults
1349**   o enable configuration functions
1350**   o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1351**
1352**************************************************************************/
1353
1354static int __init
1355lba_hw_init(struct lba_device *d)
1356{
1357        u32 stat;
1358        u32 bus_reset;  /* PDC_PAT_BUG */
1359
1360#if 0
1361        printk(KERN_DEBUG "LBA %lx  STAT_CTL %Lx  ERROR_CFG %Lx  STATUS %Lx DMA_CTL %Lx\n",
1362                d->hba.base_addr,
1363                READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1364                READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1365                READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1366                READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1367        printk(KERN_DEBUG "     ARB mask %Lx  pri %Lx  mode %Lx  mtlt %Lx\n",
1368                READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1369                READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1370                READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1371                READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1372        printk(KERN_DEBUG "     HINT cfg 0x%Lx\n",
1373                READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1374        printk(KERN_DEBUG "     HINT reg ");
1375        { int i;
1376        for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1377                printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1378        }
1379        printk("\n");
1380#endif  /* DEBUG_LBA_PAT */
1381
1382#ifdef CONFIG_64BIT
1383/*
1384 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1385 * Only N-Class and up can really make use of Get slot status.
1386 * maybe L-class too but I've never played with it there.
1387 */
1388#endif
1389
1390        /* PDC_PAT_BUG: exhibited in rev 40.48  on L2000 */
1391        bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1392        if (bus_reset) {
1393                printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1394        }
1395
1396        stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1397        if (stat & LBA_SMART_MODE) {
1398                printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1399                stat &= ~LBA_SMART_MODE;
1400                WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1401        }
1402
1403
1404        /*
1405         * Hard Fail vs. Soft Fail on PCI "Master Abort".
1406         *
1407         * "Master Abort" means the MMIO transaction timed out - usually due to
1408         * the device not responding to an MMIO read. We would like HF to be
1409         * enabled to find driver problems, though it means the system will
1410         * crash with a HPMC.
1411         *
1412         * In SoftFail mode "~0L" is returned as a result of a timeout on the
1413         * pci bus. This is like how PCI busses on x86 and most other
1414         * architectures behave.  In order to increase compatibility with
1415         * existing (x86) PCI hardware and existing Linux drivers we enable
1416         * Soft Faul mode on PA-RISC now too.
1417         */
1418        stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1419#if defined(ENABLE_HARDFAIL)
1420        WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1421#else
1422        WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1423#endif
1424
1425        /*
1426        ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1427        ** if it's not already set. If we just cleared the PCI Bus Reset
1428        ** signal, wait a bit for the PCI devices to recover and setup.
1429        */
1430        if (bus_reset)
1431                mdelay(pci_post_reset_delay);
1432
1433        if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1434                /*
1435                ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1436                ** B2000/C3600/J6000 also have this problem?
1437                ** 
1438                ** Elroys with hot pluggable slots don't get configured
1439                ** correctly if the slot is empty.  ARB_MASK is set to 0
1440                ** and we can't master transactions on the bus if it's
1441                ** not at least one. 0x3 enables elroy and first slot.
1442                */
1443                printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1444                WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1445        }
1446
1447        /*
1448        ** FIXME: Hint registers are programmed with default hint
1449        ** values by firmware. Hints should be sane even if we
1450        ** can't reprogram them the way drivers want.
1451        */
1452        return 0;
1453}
1454
1455/*
1456 * Unfortunately, when firmware numbers busses, it doesn't take into account
1457 * Cardbus bridges.  So we have to renumber the busses to suit ourselves.
1458 * Elroy/Mercury don't actually know what bus number they're attached to;
1459 * we use bus 0 to indicate the directly attached bus and any other bus
1460 * number will be taken care of by the PCI-PCI bridge.
1461 */
1462static unsigned int lba_next_bus = 0;
1463
1464/*
1465 * Determine if lba should claim this chip (return 0) or not (return 1).
1466 * If so, initialize the chip and tell other partners in crime they
1467 * have work to do.
1468 */
1469static int __init
1470lba_driver_probe(struct parisc_device *dev)
1471{
1472        struct lba_device *lba_dev;
1473        LIST_HEAD(resources);
1474        struct pci_bus *lba_bus;
1475        struct pci_ops *cfg_ops;
1476        u32 func_class;
1477        void *tmp_obj;
1478        char *version;
1479        void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
1480        int max;
1481
1482        /* Read HW Rev First */
1483        func_class = READ_REG32(addr + LBA_FCLASS);
1484
1485        if (IS_ELROY(dev)) {    
1486                func_class &= 0xf;
1487                switch (func_class) {
1488                case 0: version = "TR1.0"; break;
1489                case 1: version = "TR2.0"; break;
1490                case 2: version = "TR2.1"; break;
1491                case 3: version = "TR2.2"; break;
1492                case 4: version = "TR3.0"; break;
1493                case 5: version = "TR4.0"; break;
1494                default: version = "TR4+";
1495                }
1496
1497                printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
1498                       version, func_class & 0xf, (long)dev->hpa.start);
1499
1500                if (func_class < 2) {
1501                        printk(KERN_WARNING "Can't support LBA older than "
1502                                "TR2.1 - continuing under adversity.\n");
1503                }
1504
1505#if 0
1506/* Elroy TR4.0 should work with simple algorithm.
1507   But it doesn't.  Still missing something. *sigh*
1508*/
1509                if (func_class > 4) {
1510                        cfg_ops = &mercury_cfg_ops;
1511                } else
1512#endif
1513                {
1514                        cfg_ops = &elroy_cfg_ops;
1515                }
1516
1517        } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1518                int major, minor;
1519
1520                func_class &= 0xff;
1521                major = func_class >> 4, minor = func_class & 0xf;
1522
1523                /* We could use one printk for both Elroy and Mercury,
1524                 * but for the mask for func_class.
1525                 */ 
1526                printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1527                       IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
1528                       minor, func_class, (long)dev->hpa.start);
1529
1530                cfg_ops = &mercury_cfg_ops;
1531        } else {
1532                printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
1533                        (long)dev->hpa.start);
1534                return -ENODEV;
1535        }
1536
1537        /* Tell I/O SAPIC driver we have a IRQ handler/region. */
1538        tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
1539
1540        /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1541        **      have an IRT entry will get NULL back from iosapic code.
1542        */
1543        
1544        lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
1545        if (!lba_dev) {
1546                printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1547                return(1);
1548        }
1549
1550
1551        /* ---------- First : initialize data we already have --------- */
1552
1553        lba_dev->hw_rev = func_class;
1554        lba_dev->hba.base_addr = addr;
1555        lba_dev->hba.dev = dev;
1556        lba_dev->iosapic_obj = tmp_obj;  /* save interrupt handle */
1557        lba_dev->hba.iommu = sba_get_iommu(dev);  /* get iommu data */
1558        parisc_set_drvdata(dev, lba_dev);
1559
1560        /* ------------ Second : initialize common stuff ---------- */
1561        pci_bios = &lba_bios_ops;
1562        pcibios_register_hba(&lba_dev->hba);
1563        spin_lock_init(&lba_dev->lba_lock);
1564
1565        if (lba_hw_init(lba_dev))
1566                return(1);
1567
1568        /* ---------- Third : setup I/O Port and MMIO resources  --------- */
1569
1570        if (is_pdc_pat()) {
1571                /* PDC PAT firmware uses PIOP region of GMMIO space. */
1572                pci_port = &lba_pat_port_ops;
1573                /* Go ask PDC PAT what resources this LBA has */
1574                lba_pat_resources(dev, lba_dev);
1575        } else {
1576                if (!astro_iop_base) {
1577                        /* Sprockets PDC uses NPIOP region */
1578                        astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024);
1579                        pci_port = &lba_astro_port_ops;
1580                }
1581
1582                /* Poke the chip a bit for /proc output */
1583                lba_legacy_resources(dev, lba_dev);
1584        }
1585
1586        if (lba_dev->hba.bus_num.start < lba_next_bus)
1587                lba_dev->hba.bus_num.start = lba_next_bus;
1588
1589        /*   Overlaps with elmmio can (and should) fail here.
1590         *   We will prune (or ignore) the distributed range.
1591         *
1592         *   FIXME: SBA code should register all elmmio ranges first.
1593         *      that would take care of elmmio ranges routed
1594         *      to a different rope (already discovered) from
1595         *      getting registered *after* LBA code has already
1596         *      registered it's distributed lmmio range.
1597         */
1598        if (truncate_pat_collision(&iomem_resource,
1599                                   &(lba_dev->hba.lmmio_space))) {
1600                printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
1601                                (long)lba_dev->hba.lmmio_space.start,
1602                                (long)lba_dev->hba.lmmio_space.end);
1603                lba_dev->hba.lmmio_space.flags = 0;
1604        }
1605
1606        pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
1607                                HBA_PORT_BASE(lba_dev->hba.hba_num));
1608        if (lba_dev->hba.elmmio_space.flags)
1609                pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
1610                                        lba_dev->hba.lmmio_space_offset);
1611        if (lba_dev->hba.lmmio_space.flags)
1612                pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
1613                                        lba_dev->hba.lmmio_space_offset);
1614        if (lba_dev->hba.gmmio_space.flags) {
1615                /* Not registering GMMIO space - according to docs it's not
1616                 * even used on HP-UX. */
1617                /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
1618        }
1619
1620        pci_add_resource(&resources, &lba_dev->hba.bus_num);
1621
1622        dev->dev.platform_data = lba_dev;
1623        lba_bus = lba_dev->hba.hba_bus =
1624                pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
1625                                    cfg_ops, NULL, &resources);
1626        if (!lba_bus) {
1627                pci_free_resource_list(&resources);
1628                return 0;
1629        }
1630
1631        max = pci_scan_child_bus(lba_bus);
1632
1633        /* This is in lieu of calling pci_assign_unassigned_resources() */
1634        if (is_pdc_pat()) {
1635                /* assign resources to un-initialized devices */
1636
1637                DBG_PAT("LBA pci_bus_size_bridges()\n");
1638                pci_bus_size_bridges(lba_bus);
1639
1640                DBG_PAT("LBA pci_bus_assign_resources()\n");
1641                pci_bus_assign_resources(lba_bus);
1642
1643#ifdef DEBUG_LBA_PAT
1644                DBG_PAT("\nLBA PIOP resource tree\n");
1645                lba_dump_res(&lba_dev->hba.io_space, 2);
1646                DBG_PAT("\nLBA LMMIO resource tree\n");
1647                lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1648#endif
1649        }
1650
1651        /*
1652        ** Once PCI register ops has walked the bus, access to config
1653        ** space is restricted. Avoids master aborts on config cycles.
1654        ** Early LBA revs go fatal on *any* master abort.
1655        */
1656        if (cfg_ops == &elroy_cfg_ops) {
1657                lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1658        }
1659
1660        lba_next_bus = max + 1;
1661        pci_bus_add_devices(lba_bus);
1662
1663        /* Whew! Finally done! Tell services we got this one covered. */
1664        return 0;
1665}
1666
1667static const struct parisc_device_id lba_tbl[] __initconst = {
1668        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1669        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1670        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1671        { 0, }
1672};
1673
1674static struct parisc_driver lba_driver __refdata = {
1675        .name =         MODULE_NAME,
1676        .id_table =     lba_tbl,
1677        .probe =        lba_driver_probe,
1678};
1679
1680/*
1681** One time initialization to let the world know the LBA was found.
1682** Must be called exactly once before pci_init().
1683*/
1684void __init lba_init(void)
1685{
1686        register_parisc_driver(&lba_driver);
1687}
1688
1689/*
1690** Initialize the IBASE/IMASK registers for LBA (Elroy).
1691** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1692** sba_iommu is responsible for locking (none needed at init time).
1693*/
1694void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1695{
1696        void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096);
1697
1698        imask <<= 2;    /* adjust for hints - 2 more bits */
1699
1700        /* Make sure we aren't trying to set bits that aren't writeable. */
1701        WARN_ON((ibase & 0x001fffff) != 0);
1702        WARN_ON((imask & 0x001fffff) != 0);
1703        
1704        DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask);
1705        WRITE_REG32( imask, base_addr + LBA_IMASK);
1706        WRITE_REG32( ibase, base_addr + LBA_IBASE);
1707        iounmap(base_addr);
1708}
1709
1710
1711/*
1712 * The design of the Diva management card in rp34x0 machines (rp3410, rp3440)
1713 * seems rushed, so that many built-in components simply don't work.
1714 * The following quirks disable the serial AUX port and the built-in ATI RV100
1715 * Radeon 7000 graphics card which both don't have any external connectors and
1716 * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as
1717 * such makes those machines the only PARISC machines on which we can't use
1718 * ttyS0 as boot console.
1719 */
1720static void quirk_diva_ati_card(struct pci_dev *dev)
1721{
1722        if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1723            dev->subsystem_device != 0x1292)
1724                return;
1725
1726        dev_info(&dev->dev, "Hiding Diva built-in ATI card");
1727        dev->device = 0;
1728}
1729DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY,
1730        quirk_diva_ati_card);
1731
1732static void quirk_diva_aux_disable(struct pci_dev *dev)
1733{
1734        if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1735            dev->subsystem_device != 0x1291)
1736                return;
1737
1738        dev_info(&dev->dev, "Hiding Diva built-in AUX serial device");
1739        dev->device = 0;
1740}
1741DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
1742        quirk_diva_aux_disable);
1743
1744static void quirk_tosca_aux_disable(struct pci_dev *dev)
1745{
1746        if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1747            dev->subsystem_device != 0x104a)
1748                return;
1749
1750        dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device");
1751        dev->device = 0;
1752}
1753DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
1754        quirk_tosca_aux_disable);
1755