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11#include <linux/irqchip/chained_irq.h>
12#include <linux/irqdomain.h>
13#include <linux/msi.h>
14#include <linux/of_address.h>
15#include <linux/of_pci.h>
16#include <linux/pci_regs.h>
17#include <linux/platform_device.h>
18
19#include "../../pci.h"
20#include "pcie-designware.h"
21
22static struct pci_ops dw_pcie_ops;
23static struct pci_ops dw_child_pcie_ops;
24
25static void dw_msi_ack_irq(struct irq_data *d)
26{
27 irq_chip_ack_parent(d);
28}
29
30static void dw_msi_mask_irq(struct irq_data *d)
31{
32 pci_msi_mask_irq(d);
33 irq_chip_mask_parent(d);
34}
35
36static void dw_msi_unmask_irq(struct irq_data *d)
37{
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
40}
41
42static struct irq_chip dw_pcie_msi_irq_chip = {
43 .name = "PCI-MSI",
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
47};
48
49static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
53};
54
55
56irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
57{
58 int i, pos;
59 unsigned long val;
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
63
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
65
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
69 if (!status)
70 continue;
71
72 ret = IRQ_HANDLED;
73 val = status;
74 pos = 0;
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 generic_handle_domain_irq(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
79 pos);
80 pos++;
81 }
82 }
83
84 return ret;
85}
86
87
88static void dw_chained_msi_isr(struct irq_desc *desc)
89{
90 struct irq_chip *chip = irq_desc_get_chip(desc);
91 struct pcie_port *pp;
92
93 chained_irq_enter(chip, desc);
94
95 pp = irq_desc_get_handler_data(desc);
96 dw_handle_msi_irq(pp);
97
98 chained_irq_exit(chip, desc);
99}
100
101static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
102{
103 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
105 u64 msi_target;
106
107 msi_target = (u64)pp->msi_data;
108
109 msg->address_lo = lower_32_bits(msi_target);
110 msg->address_hi = upper_32_bits(msi_target);
111
112 msg->data = d->hwirq;
113
114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
115 (int)d->hwirq, msg->address_hi, msg->address_lo);
116}
117
118static int dw_pci_msi_set_affinity(struct irq_data *d,
119 const struct cpumask *mask, bool force)
120{
121 return -EINVAL;
122}
123
124static void dw_pci_bottom_mask(struct irq_data *d)
125{
126 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
128 unsigned int res, bit, ctrl;
129 unsigned long flags;
130
131 raw_spin_lock_irqsave(&pp->lock, flags);
132
133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
136
137 pp->irq_mask[ctrl] |= BIT(bit);
138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
139
140 raw_spin_unlock_irqrestore(&pp->lock, flags);
141}
142
143static void dw_pci_bottom_unmask(struct irq_data *d)
144{
145 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
147 unsigned int res, bit, ctrl;
148 unsigned long flags;
149
150 raw_spin_lock_irqsave(&pp->lock, flags);
151
152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
155
156 pp->irq_mask[ctrl] &= ~BIT(bit);
157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
158
159 raw_spin_unlock_irqrestore(&pp->lock, flags);
160}
161
162static void dw_pci_bottom_ack(struct irq_data *d)
163{
164 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
166 unsigned int res, bit, ctrl;
167
168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
171
172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
173}
174
175static struct irq_chip dw_pci_msi_bottom_irq_chip = {
176 .name = "DWPCI-MSI",
177 .irq_ack = dw_pci_bottom_ack,
178 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
179 .irq_set_affinity = dw_pci_msi_set_affinity,
180 .irq_mask = dw_pci_bottom_mask,
181 .irq_unmask = dw_pci_bottom_unmask,
182};
183
184static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
185 unsigned int virq, unsigned int nr_irqs,
186 void *args)
187{
188 struct pcie_port *pp = domain->host_data;
189 unsigned long flags;
190 u32 i;
191 int bit;
192
193 raw_spin_lock_irqsave(&pp->lock, flags);
194
195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
196 order_base_2(nr_irqs));
197
198 raw_spin_unlock_irqrestore(&pp->lock, flags);
199
200 if (bit < 0)
201 return -ENOSPC;
202
203 for (i = 0; i < nr_irqs; i++)
204 irq_domain_set_info(domain, virq + i, bit + i,
205 pp->msi_irq_chip,
206 pp, handle_edge_irq,
207 NULL, NULL);
208
209 return 0;
210}
211
212static void dw_pcie_irq_domain_free(struct irq_domain *domain,
213 unsigned int virq, unsigned int nr_irqs)
214{
215 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
216 struct pcie_port *pp = domain->host_data;
217 unsigned long flags;
218
219 raw_spin_lock_irqsave(&pp->lock, flags);
220
221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
222 order_base_2(nr_irqs));
223
224 raw_spin_unlock_irqrestore(&pp->lock, flags);
225}
226
227static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
228 .alloc = dw_pcie_irq_domain_alloc,
229 .free = dw_pcie_irq_domain_free,
230};
231
232int dw_pcie_allocate_domains(struct pcie_port *pp)
233{
234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
236
237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
238 &dw_pcie_msi_domain_ops, pp);
239 if (!pp->irq_domain) {
240 dev_err(pci->dev, "Failed to create IRQ domain\n");
241 return -ENOMEM;
242 }
243
244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
245
246 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
247 &dw_pcie_msi_domain_info,
248 pp->irq_domain);
249 if (!pp->msi_domain) {
250 dev_err(pci->dev, "Failed to create MSI domain\n");
251 irq_domain_remove(pp->irq_domain);
252 return -ENOMEM;
253 }
254
255 return 0;
256}
257
258static void dw_pcie_free_msi(struct pcie_port *pp)
259{
260 if (pp->msi_irq)
261 irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
262
263 irq_domain_remove(pp->msi_domain);
264 irq_domain_remove(pp->irq_domain);
265
266 if (pp->msi_data) {
267 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
268 struct device *dev = pci->dev;
269
270 dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg),
271 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
272 }
273}
274
275static void dw_pcie_msi_init(struct pcie_port *pp)
276{
277 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
278 u64 msi_target = (u64)pp->msi_data;
279
280 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
281 return;
282
283
284 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
285 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
286}
287
288int dw_pcie_host_init(struct pcie_port *pp)
289{
290 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
291 struct device *dev = pci->dev;
292 struct device_node *np = dev->of_node;
293 struct platform_device *pdev = to_platform_device(dev);
294 struct resource_entry *win;
295 struct pci_host_bridge *bridge;
296 struct resource *cfg_res;
297 int ret;
298
299 raw_spin_lock_init(&pci->pp.lock);
300
301 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
302 if (cfg_res) {
303 pp->cfg0_size = resource_size(cfg_res);
304 pp->cfg0_base = cfg_res->start;
305
306 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
307 if (IS_ERR(pp->va_cfg0_base))
308 return PTR_ERR(pp->va_cfg0_base);
309 } else {
310 dev_err(dev, "Missing *config* reg space\n");
311 return -ENODEV;
312 }
313
314 if (!pci->dbi_base) {
315 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
316 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
317 if (IS_ERR(pci->dbi_base))
318 return PTR_ERR(pci->dbi_base);
319 }
320
321 bridge = devm_pci_alloc_host_bridge(dev, 0);
322 if (!bridge)
323 return -ENOMEM;
324
325 pp->bridge = bridge;
326
327
328 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
329 if (win) {
330 pp->io_size = resource_size(win->res);
331 pp->io_bus_addr = win->res->start - win->offset;
332 pp->io_base = pci_pio_to_address(win->res->start);
333 }
334
335 if (pci->link_gen < 1)
336 pci->link_gen = of_pci_get_max_link_speed(np);
337
338 if (pci_msi_enabled()) {
339 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
340 of_property_read_bool(np, "msi-parent") ||
341 of_property_read_bool(np, "msi-map"));
342
343 if (!pp->num_vectors) {
344 pp->num_vectors = MSI_DEF_NUM_VECTORS;
345 } else if (pp->num_vectors > MAX_MSI_IRQS) {
346 dev_err(dev, "Invalid number of vectors\n");
347 return -EINVAL;
348 }
349
350 if (pp->ops->msi_host_init) {
351 ret = pp->ops->msi_host_init(pp);
352 if (ret < 0)
353 return ret;
354 } else if (pp->has_msi_ctrl) {
355 if (!pp->msi_irq) {
356 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
357 if (pp->msi_irq < 0) {
358 pp->msi_irq = platform_get_irq(pdev, 0);
359 if (pp->msi_irq < 0)
360 return pp->msi_irq;
361 }
362 }
363
364 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
365
366 ret = dw_pcie_allocate_domains(pp);
367 if (ret)
368 return ret;
369
370 if (pp->msi_irq > 0)
371 irq_set_chained_handler_and_data(pp->msi_irq,
372 dw_chained_msi_isr,
373 pp);
374
375 ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
376 if (ret)
377 dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
378
379 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
380 sizeof(pp->msi_msg),
381 DMA_FROM_DEVICE,
382 DMA_ATTR_SKIP_CPU_SYNC);
383 if (dma_mapping_error(pci->dev, pp->msi_data)) {
384 dev_err(pci->dev, "Failed to map MSI data\n");
385 pp->msi_data = 0;
386 goto err_free_msi;
387 }
388 }
389 }
390
391
392 bridge->ops = &dw_pcie_ops;
393 bridge->child_ops = &dw_child_pcie_ops;
394
395 if (pp->ops->host_init) {
396 ret = pp->ops->host_init(pp);
397 if (ret)
398 goto err_free_msi;
399 }
400 dw_pcie_iatu_detect(pci);
401
402 dw_pcie_setup_rc(pp);
403
404 if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
405 ret = pci->ops->start_link(pci);
406 if (ret)
407 goto err_free_msi;
408 }
409
410
411 dw_pcie_wait_for_link(pci);
412
413 bridge->sysdata = pp;
414
415 ret = pci_host_probe(bridge);
416 if (!ret)
417 return 0;
418
419err_free_msi:
420 if (pp->has_msi_ctrl)
421 dw_pcie_free_msi(pp);
422 return ret;
423}
424EXPORT_SYMBOL_GPL(dw_pcie_host_init);
425
426void dw_pcie_host_deinit(struct pcie_port *pp)
427{
428 pci_stop_root_bus(pp->bridge->bus);
429 pci_remove_root_bus(pp->bridge->bus);
430 if (pp->has_msi_ctrl)
431 dw_pcie_free_msi(pp);
432}
433EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
434
435static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
436 unsigned int devfn, int where)
437{
438 int type;
439 u32 busdev;
440 struct pcie_port *pp = bus->sysdata;
441 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442
443
444
445
446
447
448
449
450
451 if (!dw_pcie_link_up(pci))
452 return NULL;
453
454 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
455 PCIE_ATU_FUNC(PCI_FUNC(devfn));
456
457 if (pci_is_root_bus(bus->parent))
458 type = PCIE_ATU_TYPE_CFG0;
459 else
460 type = PCIE_ATU_TYPE_CFG1;
461
462
463 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size);
464
465 return pp->va_cfg0_base + where;
466}
467
468static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
469 int where, int size, u32 *val)
470{
471 int ret;
472 struct pcie_port *pp = bus->sysdata;
473 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
474
475 ret = pci_generic_config_read(bus, devfn, where, size, val);
476
477 if (!ret && pci->io_cfg_atu_shared)
478 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
479 pp->io_bus_addr, pp->io_size);
480
481 return ret;
482}
483
484static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
485 int where, int size, u32 val)
486{
487 int ret;
488 struct pcie_port *pp = bus->sysdata;
489 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
490
491 ret = pci_generic_config_write(bus, devfn, where, size, val);
492
493 if (!ret && pci->io_cfg_atu_shared)
494 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
495 pp->io_bus_addr, pp->io_size);
496
497 return ret;
498}
499
500static struct pci_ops dw_child_pcie_ops = {
501 .map_bus = dw_pcie_other_conf_map_bus,
502 .read = dw_pcie_rd_other_conf,
503 .write = dw_pcie_wr_other_conf,
504};
505
506void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
507{
508 struct pcie_port *pp = bus->sysdata;
509 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
510
511 if (PCI_SLOT(devfn) > 0)
512 return NULL;
513
514 return pci->dbi_base + where;
515}
516EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
517
518static struct pci_ops dw_pcie_ops = {
519 .map_bus = dw_pcie_own_conf_map_bus,
520 .read = pci_generic_config_read,
521 .write = pci_generic_config_write,
522};
523
524void dw_pcie_setup_rc(struct pcie_port *pp)
525{
526 int i;
527 u32 val, ctrl, num_ctrls;
528 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
529
530
531
532
533
534 dw_pcie_dbi_ro_wr_en(pci);
535
536 dw_pcie_setup(pci);
537
538 if (pp->has_msi_ctrl) {
539 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
540
541
542 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
543 pp->irq_mask[ctrl] = ~0;
544 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
545 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
546 pp->irq_mask[ctrl]);
547 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
548 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
549 ~0);
550 }
551 }
552
553 dw_pcie_msi_init(pp);
554
555
556 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
557 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
558
559
560 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
561 val &= 0xffff00ff;
562 val |= 0x00000100;
563 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
564
565
566 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
567 val &= 0xff000000;
568 val |= 0x00ff0100;
569 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
570
571
572 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
573 val &= 0xffff0000;
574 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
575 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
576 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
577
578
579 for (i = 0; i < pci->num_ob_windows; i++)
580 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
581
582
583
584
585
586
587 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
588 int atu_idx = 0;
589 struct resource_entry *entry;
590
591
592 resource_list_for_each_entry(entry, &pp->bridge->windows) {
593 if (resource_type(entry->res) != IORESOURCE_MEM)
594 continue;
595
596 if (pci->num_ob_windows <= ++atu_idx)
597 break;
598
599 dw_pcie_prog_outbound_atu(pci, atu_idx,
600 PCIE_ATU_TYPE_MEM, entry->res->start,
601 entry->res->start - entry->offset,
602 resource_size(entry->res));
603 }
604
605 if (pp->io_size) {
606 if (pci->num_ob_windows > ++atu_idx)
607 dw_pcie_prog_outbound_atu(pci, atu_idx,
608 PCIE_ATU_TYPE_IO, pp->io_base,
609 pp->io_bus_addr, pp->io_size);
610 else
611 pci->io_cfg_atu_shared = true;
612 }
613
614 if (pci->num_ob_windows <= atu_idx)
615 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
616 pci->num_ob_windows);
617 }
618
619 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
620
621
622 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
623
624 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
625 val |= PORT_LOGIC_SPEED_CHANGE;
626 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
627
628 dw_pcie_dbi_ro_wr_dis(pci);
629}
630EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
631
