LXR linux/drivers/pci/controller/pci-ftpci100.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Support for Faraday Technology FTPC100 PCI Controller
   4 *
   5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   6 *
   7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
   8 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
   9 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  10 * Based on SL2312 PCI controller code
  11 * Storlink (C) 2003
  12 */
  13
  14#include <linux/init.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/kernel.h>
  18#include <linux/of_address.h>
  19#include <linux/of_device.h>
  20#include <linux/of_irq.h>
  21#include <linux/of_pci.h>
  22#include <linux/pci.h>
  23#include <linux/platform_device.h>
  24#include <linux/slab.h>
  25#include <linux/irqdomain.h>
  26#include <linux/irqchip/chained_irq.h>
  27#include <linux/bitops.h>
  28#include <linux/irq.h>
  29#include <linux/clk.h>
  30
  31#include "../pci.h"
  32
  33/*
  34 * Special configuration registers directly in the first few words
  35 * in I/O space.
  36 */
  37#define FTPCI_IOSIZE    0x00
  38#define FTPCI_PROT      0x04 /* AHB protection */
  39#define FTPCI_CTRL      0x08 /* PCI control signal */
  40#define FTPCI_SOFTRST   0x10 /* Soft reset counter and response error enable */
  41#define FTPCI_CONFIG    0x28 /* PCI configuration command register */
  42#define FTPCI_DATA      0x2C
  43
  44#define FARADAY_PCI_STATUS_CMD          0x04 /* Status and command */
  45#define FARADAY_PCI_PMC                 0x40 /* Power management control */
  46#define FARADAY_PCI_PMCSR               0x44 /* Power management status */
  47#define FARADAY_PCI_CTRL1               0x48 /* Control register 1 */
  48#define FARADAY_PCI_CTRL2               0x4C /* Control register 2 */
  49#define FARADAY_PCI_MEM1_BASE_SIZE      0x50 /* Memory base and size #1 */
  50#define FARADAY_PCI_MEM2_BASE_SIZE      0x54 /* Memory base and size #2 */
  51#define FARADAY_PCI_MEM3_BASE_SIZE      0x58 /* Memory base and size #3 */
  52
  53#define PCI_STATUS_66MHZ_CAPABLE        BIT(21)
  54
  55/* Bits 31..28 gives INTD..INTA status */
  56#define PCI_CTRL2_INTSTS_SHIFT          28
  57#define PCI_CTRL2_INTMASK_CMDERR        BIT(27)
  58#define PCI_CTRL2_INTMASK_PARERR        BIT(26)
  59/* Bits 25..22 masks INTD..INTA */
  60#define PCI_CTRL2_INTMASK_SHIFT         22
  61#define PCI_CTRL2_INTMASK_MABRT_RX      BIT(21)
  62#define PCI_CTRL2_INTMASK_TABRT_RX      BIT(20)
  63#define PCI_CTRL2_INTMASK_TABRT_TX      BIT(19)
  64#define PCI_CTRL2_INTMASK_RETRY4        BIT(18)
  65#define PCI_CTRL2_INTMASK_SERR_RX       BIT(17)
  66#define PCI_CTRL2_INTMASK_PERR_RX       BIT(16)
  67/* Bit 15 reserved */
  68#define PCI_CTRL2_MSTPRI_REQ6           BIT(14)
  69#define PCI_CTRL2_MSTPRI_REQ5           BIT(13)
  70#define PCI_CTRL2_MSTPRI_REQ4           BIT(12)
  71#define PCI_CTRL2_MSTPRI_REQ3           BIT(11)
  72#define PCI_CTRL2_MSTPRI_REQ2           BIT(10)
  73#define PCI_CTRL2_MSTPRI_REQ1           BIT(9)
  74#define PCI_CTRL2_MSTPRI_REQ0           BIT(8)
  75/* Bits 7..4 reserved */
  76/* Bits 3..0 TRDYW */
  77
  78/*
  79 * Memory configs:
  80 * Bit 31..20 defines the PCI side memory base
  81 * Bit 19..16 (4 bits) defines the size per below
  82 */
  83#define FARADAY_PCI_MEMBASE_MASK        0xfff00000
  84#define FARADAY_PCI_MEMSIZE_1MB         0x0
  85#define FARADAY_PCI_MEMSIZE_2MB         0x1
  86#define FARADAY_PCI_MEMSIZE_4MB         0x2
  87#define FARADAY_PCI_MEMSIZE_8MB         0x3
  88#define FARADAY_PCI_MEMSIZE_16MB        0x4
  89#define FARADAY_PCI_MEMSIZE_32MB        0x5
  90#define FARADAY_PCI_MEMSIZE_64MB        0x6
  91#define FARADAY_PCI_MEMSIZE_128MB       0x7
  92#define FARADAY_PCI_MEMSIZE_256MB       0x8
  93#define FARADAY_PCI_MEMSIZE_512MB       0x9
  94#define FARADAY_PCI_MEMSIZE_1GB         0xa
  95#define FARADAY_PCI_MEMSIZE_2GB         0xb
  96#define FARADAY_PCI_MEMSIZE_SHIFT       16
  97
  98/*
  99 * The DMA base is set to 0x0 for all memory segments, it reflects the
 100 * fact that the memory of the host system starts at 0x0.
 101 */
 102#define FARADAY_PCI_DMA_MEM1_BASE       0x00000000
 103#define FARADAY_PCI_DMA_MEM2_BASE       0x00000000
 104#define FARADAY_PCI_DMA_MEM3_BASE       0x00000000
 105
 106/* Defines for PCI configuration command register */
 107#define PCI_CONF_ENABLE         BIT(31)
 108#define PCI_CONF_WHERE(r)       ((r) & 0xFC)
 109#define PCI_CONF_BUS(b)         (((b) & 0xFF) << 16)
 110#define PCI_CONF_DEVICE(d)      (((d) & 0x1F) << 11)
 111#define PCI_CONF_FUNCTION(f)    (((f) & 0x07) << 8)
 112
 113/**
 114 * struct faraday_pci_variant - encodes IP block differences
 115 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
 116 *      embedded in the host bridge.
 117 */
 118struct faraday_pci_variant {
 119        bool cascaded_irq;
 120};
 121
 122struct faraday_pci {
 123        struct device *dev;
 124        void __iomem *base;
 125        struct irq_domain *irqdomain;
 126        struct pci_bus *bus;
 127        struct clk *bus_clk;
 128};
 129
 130static int faraday_res_to_memcfg(resource_size_t mem_base,
 131                                 resource_size_t mem_size, u32 *val)
 132{
 133        u32 outval;
 134
 135        switch (mem_size) {
 136        case SZ_1M:
 137                outval = FARADAY_PCI_MEMSIZE_1MB;
 138                break;
 139        case SZ_2M:
 140                outval = FARADAY_PCI_MEMSIZE_2MB;
 141                break;
 142        case SZ_4M:
 143                outval = FARADAY_PCI_MEMSIZE_4MB;
 144                break;
 145        case SZ_8M:
 146                outval = FARADAY_PCI_MEMSIZE_8MB;
 147                break;
 148        case SZ_16M:
 149                outval = FARADAY_PCI_MEMSIZE_16MB;
 150                break;
 151        case SZ_32M:
 152                outval = FARADAY_PCI_MEMSIZE_32MB;
 153                break;
 154        case SZ_64M:
 155                outval = FARADAY_PCI_MEMSIZE_64MB;
 156                break;
 157        case SZ_128M:
 158                outval = FARADAY_PCI_MEMSIZE_128MB;
 159                break;
 160        case SZ_256M:
 161                outval = FARADAY_PCI_MEMSIZE_256MB;
 162                break;
 163        case SZ_512M:
 164                outval = FARADAY_PCI_MEMSIZE_512MB;
 165                break;
 166        case SZ_1G:
 167                outval = FARADAY_PCI_MEMSIZE_1GB;
 168                break;
 169        case SZ_2G:
 170                outval = FARADAY_PCI_MEMSIZE_2GB;
 171                break;
 172        default:
 173                return -EINVAL;
 174        }
 175        outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
 176
 177        /* This is probably not good */
 178        if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
 179                pr_warn("truncated PCI memory base\n");
 180        /* Translate to bridge side address space */
 181        outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
 182        pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
 183                 &mem_base, &mem_size, outval);
 184
 185        *val = outval;
 186        return 0;
 187}
 188
 189static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
 190                                       unsigned int fn, int config, int size,
 191                                       u32 *value)
 192{
 193        writel(PCI_CONF_BUS(bus_number) |
 194                        PCI_CONF_DEVICE(PCI_SLOT(fn)) |
 195                        PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
 196                        PCI_CONF_WHERE(config) |
 197                        PCI_CONF_ENABLE,
 198                        p->base + FTPCI_CONFIG);
 199
 200        *value = readl(p->base + FTPCI_DATA);
 201
 202        if (size == 1)
 203                *value = (*value >> (8 * (config & 3))) & 0xFF;
 204        else if (size == 2)
 205                *value = (*value >> (8 * (config & 3))) & 0xFFFF;
 206
 207        return PCIBIOS_SUCCESSFUL;
 208}
 209
 210static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
 211                                   int config, int size, u32 *value)
 212{
 213        struct faraday_pci *p = bus->sysdata;
 214
 215        dev_dbg(&bus->dev,
 216                "[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
 217                PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
 218
 219        return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
 220}
 221
 222static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
 223                                         unsigned int fn, int config, int size,
 224                                         u32 value)
 225{
 226        int ret = PCIBIOS_SUCCESSFUL;
 227
 228        writel(PCI_CONF_BUS(bus_number) |
 229                        PCI_CONF_DEVICE(PCI_SLOT(fn)) |
 230                        PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
 231                        PCI_CONF_WHERE(config) |
 232                        PCI_CONF_ENABLE,
 233                        p->base + FTPCI_CONFIG);
 234
 235        switch (size) {
 236        case 4:
 237                writel(value, p->base + FTPCI_DATA);
 238                break;
 239        case 2:
 240                writew(value, p->base + FTPCI_DATA + (config & 3));
 241                break;
 242        case 1:
 243                writeb(value, p->base + FTPCI_DATA + (config & 3));
 244                break;
 245        default:
 246                ret = PCIBIOS_BAD_REGISTER_NUMBER;
 247        }
 248
 249        return ret;
 250}
 251
 252static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
 253                                    int config, int size, u32 value)
 254{
 255        struct faraday_pci *p = bus->sysdata;
 256
 257        dev_dbg(&bus->dev,
 258                "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
 259                PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
 260
 261        return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
 262                                            value);
 263}
 264
 265static struct pci_ops faraday_pci_ops = {
 266        .read   = faraday_pci_read_config,
 267        .write  = faraday_pci_write_config,
 268};
 269
 270static void faraday_pci_ack_irq(struct irq_data *d)
 271{
 272        struct faraday_pci *p = irq_data_get_irq_chip_data(d);
 273        unsigned int reg;
 274
 275        faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
 276        reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
 277        reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
 278        faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
 279}
 280
 281static void faraday_pci_mask_irq(struct irq_data *d)
 282{
 283        struct faraday_pci *p = irq_data_get_irq_chip_data(d);
 284        unsigned int reg;
 285
 286        faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
 287        reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
 288                 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
 289        faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
 290}
 291
 292static void faraday_pci_unmask_irq(struct irq_data *d)
 293{
 294        struct faraday_pci *p = irq_data_get_irq_chip_data(d);
 295        unsigned int reg;
 296
 297        faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
 298        reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
 299        reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
 300        faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
 301}
 302
 303static void faraday_pci_irq_handler(struct irq_desc *desc)
 304{
 305        struct faraday_pci *p = irq_desc_get_handler_data(desc);
 306        struct irq_chip *irqchip = irq_desc_get_chip(desc);
 307        unsigned int irq_stat, reg, i;
 308
 309        faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
 310        irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
 311
 312        chained_irq_enter(irqchip, desc);
 313
 314        for (i = 0; i < 4; i++) {
 315                if ((irq_stat & BIT(i)) == 0)
 316                        continue;
 317                generic_handle_domain_irq(p->irqdomain, i);
 318        }
 319
 320        chained_irq_exit(irqchip, desc);
 321}
 322
 323static struct irq_chip faraday_pci_irq_chip = {
 324        .name = "PCI",
 325        .irq_ack = faraday_pci_ack_irq,
 326        .irq_mask = faraday_pci_mask_irq,
 327        .irq_unmask = faraday_pci_unmask_irq,
 328};
 329
 330static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
 331                               irq_hw_number_t hwirq)
 332{
 333        irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
 334        irq_set_chip_data(irq, domain->host_data);
 335
 336        return 0;
 337}
 338
 339static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
 340        .map = faraday_pci_irq_map,
 341};
 342
 343static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
 344{
 345        struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
 346        int irq;
 347        int i;
 348
 349        if (!intc) {
 350                dev_err(p->dev, "missing child interrupt-controller node\n");
 351                return -EINVAL;
 352        }
 353
 354        /* All PCI IRQs cascade off this one */
 355        irq = of_irq_get(intc, 0);
 356        if (irq <= 0) {
 357                dev_err(p->dev, "failed to get parent IRQ\n");
 358                of_node_put(intc);
 359                return irq ?: -EINVAL;
 360        }
 361
 362        p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
 363                                             &faraday_pci_irqdomain_ops, p);
 364        of_node_put(intc);
 365        if (!p->irqdomain) {
 366                dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
 367                return -EINVAL;
 368        }
 369
 370        irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
 371
 372        for (i = 0; i < 4; i++)
 373                irq_create_mapping(p->irqdomain, i);
 374
 375        return 0;
 376}
 377
 378static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p)
 379{
 380        struct device *dev = p->dev;
 381        struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
 382        struct resource_entry *entry;
 383        u32 confreg[3] = {
 384                FARADAY_PCI_MEM1_BASE_SIZE,
 385                FARADAY_PCI_MEM2_BASE_SIZE,
 386                FARADAY_PCI_MEM3_BASE_SIZE,
 387        };
 388        int i = 0;
 389        u32 val;
 390
 391        resource_list_for_each_entry(entry, &bridge->dma_ranges) {
 392                u64 pci_addr = entry->res->start - entry->offset;
 393                u64 end = entry->res->end - entry->offset;
 394                int ret;
 395
 396                ret = faraday_res_to_memcfg(pci_addr,
 397                                            resource_size(entry->res), &val);
 398                if (ret) {
 399                        dev_err(dev,
 400                                "DMA range %d: illegal MEM resource size\n", i);
 401                        return -EINVAL;
 402                }
 403
 404                dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
 405                         i + 1, pci_addr, end, val);
 406                if (i <= 2) {
 407                        faraday_raw_pci_write_config(p, 0, 0, confreg[i],
 408                                                     4, val);
 409                } else {
 410                        dev_err(dev, "ignore extraneous dma-range %d\n", i);
 411                        break;
 412                }
 413
 414                i++;
 415        }
 416
 417        return 0;
 418}
 419
 420static int faraday_pci_probe(struct platform_device *pdev)
 421{
 422        struct device *dev = &pdev->dev;
 423        const struct faraday_pci_variant *variant =
 424                of_device_get_match_data(dev);
 425        struct resource_entry *win;
 426        struct faraday_pci *p;
 427        struct resource *io;
 428        struct pci_host_bridge *host;
 429        struct clk *clk;
 430        unsigned char max_bus_speed = PCI_SPEED_33MHz;
 431        unsigned char cur_bus_speed = PCI_SPEED_33MHz;
 432        int ret;
 433        u32 val;
 434
 435        host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
 436        if (!host)
 437                return -ENOMEM;
 438
 439        host->ops = &faraday_pci_ops;
 440        p = pci_host_bridge_priv(host);
 441        host->sysdata = p;
 442        p->dev = dev;
 443
 444        /* Retrieve and enable optional clocks */
 445        clk = devm_clk_get(dev, "PCLK");
 446        if (IS_ERR(clk))
 447                return PTR_ERR(clk);
 448        ret = clk_prepare_enable(clk);
 449        if (ret) {
 450                dev_err(dev, "could not prepare PCLK\n");
 451                return ret;
 452        }
 453        p->bus_clk = devm_clk_get(dev, "PCICLK");
 454        if (IS_ERR(p->bus_clk))
 455                return PTR_ERR(p->bus_clk);
 456        ret = clk_prepare_enable(p->bus_clk);
 457        if (ret) {
 458                dev_err(dev, "could not prepare PCICLK\n");
 459                return ret;
 460        }
 461
 462        p->base = devm_platform_ioremap_resource(pdev, 0);
 463        if (IS_ERR(p->base))
 464                return PTR_ERR(p->base);
 465
 466        win = resource_list_first_type(&host->windows, IORESOURCE_IO);
 467        if (win) {
 468                io = win->res;
 469                if (!faraday_res_to_memcfg(io->start - win->offset,
 470                                           resource_size(io), &val)) {
 471                        /* setup I/O space size */
 472                        writel(val, p->base + FTPCI_IOSIZE);
 473                } else {
 474                        dev_err(dev, "illegal IO mem size\n");
 475                        return -EINVAL;
 476                }
 477        }
 478
 479        /* Setup hostbridge */
 480        val = readl(p->base + FTPCI_CTRL);
 481        val |= PCI_COMMAND_IO;
 482        val |= PCI_COMMAND_MEMORY;
 483        val |= PCI_COMMAND_MASTER;
 484        writel(val, p->base + FTPCI_CTRL);
 485        /* Mask and clear all interrupts */
 486        faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
 487        if (variant->cascaded_irq) {
 488                ret = faraday_pci_setup_cascaded_irq(p);
 489                if (ret) {
 490                        dev_err(dev, "failed to setup cascaded IRQ\n");
 491                        return ret;
 492                }
 493        }
 494
 495        /* Check bus clock if we can gear up to 66 MHz */
 496        if (!IS_ERR(p->bus_clk)) {
 497                unsigned long rate;
 498                u32 val;
 499
 500                faraday_raw_pci_read_config(p, 0, 0,
 501                                            FARADAY_PCI_STATUS_CMD, 4, &val);
 502                rate = clk_get_rate(p->bus_clk);
 503
 504                if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
 505                        dev_info(dev, "33MHz bus is 66MHz capable\n");
 506                        max_bus_speed = PCI_SPEED_66MHz;
 507                        ret = clk_set_rate(p->bus_clk, 66000000);
 508                        if (ret)
 509                                dev_err(dev, "failed to set bus clock\n");
 510                } else {
 511                        dev_info(dev, "33MHz only bus\n");
 512                        max_bus_speed = PCI_SPEED_33MHz;
 513                }
 514
 515                /* Bumping the clock may fail so read back the rate */
 516                rate = clk_get_rate(p->bus_clk);
 517                if (rate == 33000000)
 518                        cur_bus_speed = PCI_SPEED_33MHz;
 519                if (rate == 66000000)
 520                        cur_bus_speed = PCI_SPEED_66MHz;
 521        }
 522
 523        ret = faraday_pci_parse_map_dma_ranges(p);
 524        if (ret)
 525                return ret;
 526
 527        ret = pci_scan_root_bus_bridge(host);
 528        if (ret) {
 529                dev_err(dev, "failed to scan host: %d\n", ret);
 530                return ret;
 531        }
 532        p->bus = host->bus;
 533        p->bus->max_bus_speed = max_bus_speed;
 534        p->bus->cur_bus_speed = cur_bus_speed;
 535
 536        pci_bus_assign_resources(p->bus);
 537        pci_bus_add_devices(p->bus);
 538
 539        return 0;
 540}
 541
 542/*
 543 * We encode bridge variants here, we have at least two so it doesn't
 544 * hurt to have infrastructure to encompass future variants as well.
 545 */
 546static const struct faraday_pci_variant faraday_regular = {
 547        .cascaded_irq = true,
 548};
 549
 550static const struct faraday_pci_variant faraday_dual = {
 551        .cascaded_irq = false,
 552};
 553
 554static const struct of_device_id faraday_pci_of_match[] = {
 555        {
 556                .compatible = "faraday,ftpci100",
 557                .data = &faraday_regular,
 558        },
 559        {
 560                .compatible = "faraday,ftpci100-dual",
 561                .data = &faraday_dual,
 562        },
 563        {},
 564};
 565
 566static struct platform_driver faraday_pci_driver = {
 567        .driver = {
 568                .name = "ftpci100",
 569                .of_match_table = of_match_ptr(faraday_pci_of_match),
 570                .suppress_bind_attrs = true,
 571        },
 572        .probe  = faraday_pci_probe,
 573};
 574builtin_platform_driver(faraday_pci_driver);
 575