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40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/pci-ecam.h>
44#include <linux/delay.h>
45#include <linux/semaphore.h>
46#include <linux/irqdomain.h>
47#include <asm/irqdomain.h>
48#include <asm/apic.h>
49#include <linux/irq.h>
50#include <linux/msi.h>
51#include <linux/hyperv.h>
52#include <linux/refcount.h>
53#include <asm/mshyperv.h>
54
55
56
57
58
59
60#define PCI_MAKE_VERSION(major, minor) ((u32)(((major) << 16) | (minor)))
61#define PCI_MAJOR_VERSION(version) ((u32)(version) >> 16)
62#define PCI_MINOR_VERSION(version) ((u32)(version) & 0xff)
63
64enum pci_protocol_version_t {
65 PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1),
66 PCI_PROTOCOL_VERSION_1_2 = PCI_MAKE_VERSION(1, 2),
67 PCI_PROTOCOL_VERSION_1_3 = PCI_MAKE_VERSION(1, 3),
68 PCI_PROTOCOL_VERSION_1_4 = PCI_MAKE_VERSION(1, 4),
69};
70
71#define CPU_AFFINITY_ALL -1ULL
72
73
74
75
76
77static enum pci_protocol_version_t pci_protocol_versions[] = {
78 PCI_PROTOCOL_VERSION_1_4,
79 PCI_PROTOCOL_VERSION_1_3,
80 PCI_PROTOCOL_VERSION_1_2,
81 PCI_PROTOCOL_VERSION_1_1,
82};
83
84#define PCI_CONFIG_MMIO_LENGTH 0x2000
85#define CFG_PAGE_OFFSET 0x1000
86#define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
87
88#define MAX_SUPPORTED_MSI_MESSAGES 0x400
89
90#define STATUS_REVISION_MISMATCH 0xC0000059
91
92
93#define SLOT_NAME_SIZE 11
94
95
96
97
98
99enum pci_message_type {
100
101
102
103 PCI_MESSAGE_BASE = 0x42490000,
104 PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
105 PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
106 PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
107 PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
108 PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
109 PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
110 PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
111 PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
112 PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
113 PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
114 PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
115 PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
116 PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
117 PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
118 PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
119 PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
120 PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
121 PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
122 PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
123 PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
124 PCI_RESOURCES_ASSIGNED2 = PCI_MESSAGE_BASE + 0x16,
125 PCI_CREATE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x17,
126 PCI_DELETE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x18,
127 PCI_BUS_RELATIONS2 = PCI_MESSAGE_BASE + 0x19,
128 PCI_RESOURCES_ASSIGNED3 = PCI_MESSAGE_BASE + 0x1A,
129 PCI_CREATE_INTERRUPT_MESSAGE3 = PCI_MESSAGE_BASE + 0x1B,
130 PCI_MESSAGE_MAXIMUM
131};
132
133
134
135
136
137union pci_version {
138 struct {
139 u16 minor_version;
140 u16 major_version;
141 } parts;
142 u32 version;
143} __packed;
144
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147
148
149
150
151union win_slot_encoding {
152 struct {
153 u32 dev:5;
154 u32 func:3;
155 u32 reserved:24;
156 } bits;
157 u32 slot;
158} __packed;
159
160
161
162
163struct pci_function_description {
164 u16 v_id;
165 u16 d_id;
166 u8 rev;
167 u8 prog_intf;
168 u8 subclass;
169 u8 base_class;
170 u32 subsystem_id;
171 union win_slot_encoding win_slot;
172 u32 ser;
173} __packed;
174
175enum pci_device_description_flags {
176 HV_PCI_DEVICE_FLAG_NONE = 0x0,
177 HV_PCI_DEVICE_FLAG_NUMA_AFFINITY = 0x1,
178};
179
180struct pci_function_description2 {
181 u16 v_id;
182 u16 d_id;
183 u8 rev;
184 u8 prog_intf;
185 u8 subclass;
186 u8 base_class;
187 u32 subsystem_id;
188 union win_slot_encoding win_slot;
189 u32 ser;
190 u32 flags;
191 u16 virtual_numa_node;
192 u16 reserved;
193} __packed;
194
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210
211struct hv_msi_desc {
212 u8 vector;
213 u8 delivery_mode;
214 u16 vector_count;
215 u32 reserved;
216 u64 cpu_mask;
217} __packed;
218
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233
234
235struct hv_msi_desc2 {
236 u8 vector;
237 u8 delivery_mode;
238 u16 vector_count;
239 u16 processor_count;
240 u16 processor_array[32];
241} __packed;
242
243
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246
247
248
249struct hv_msi_desc3 {
250 u32 vector;
251 u8 delivery_mode;
252 u8 reserved;
253 u16 vector_count;
254 u16 processor_count;
255 u16 processor_array[32];
256} __packed;
257
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267
268
269
270struct tran_int_desc {
271 u16 reserved;
272 u16 vector_count;
273 u32 data;
274 u64 address;
275} __packed;
276
277
278
279
280
281
282struct pci_message {
283 u32 type;
284} __packed;
285
286struct pci_child_message {
287 struct pci_message message_type;
288 union win_slot_encoding wslot;
289} __packed;
290
291struct pci_incoming_message {
292 struct vmpacket_descriptor hdr;
293 struct pci_message message_type;
294} __packed;
295
296struct pci_response {
297 struct vmpacket_descriptor hdr;
298 s32 status;
299} __packed;
300
301struct pci_packet {
302 void (*completion_func)(void *context, struct pci_response *resp,
303 int resp_packet_size);
304 void *compl_ctxt;
305
306 struct pci_message message[];
307};
308
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320
321
322
323struct pci_version_request {
324 struct pci_message message_type;
325 u32 protocol_version;
326} __packed;
327
328
329
330
331
332
333struct pci_bus_d0_entry {
334 struct pci_message message_type;
335 u32 reserved;
336 u64 mmio_base;
337} __packed;
338
339struct pci_bus_relations {
340 struct pci_incoming_message incoming;
341 u32 device_count;
342 struct pci_function_description func[];
343} __packed;
344
345struct pci_bus_relations2 {
346 struct pci_incoming_message incoming;
347 u32 device_count;
348 struct pci_function_description2 func[];
349} __packed;
350
351struct pci_q_res_req_response {
352 struct vmpacket_descriptor hdr;
353 s32 status;
354 u32 probed_bar[PCI_STD_NUM_BARS];
355} __packed;
356
357struct pci_set_power {
358 struct pci_message message_type;
359 union win_slot_encoding wslot;
360 u32 power_state;
361 u32 reserved;
362} __packed;
363
364struct pci_set_power_response {
365 struct vmpacket_descriptor hdr;
366 s32 status;
367 union win_slot_encoding wslot;
368 u32 resultant_state;
369 u32 reserved;
370} __packed;
371
372struct pci_resources_assigned {
373 struct pci_message message_type;
374 union win_slot_encoding wslot;
375 u8 memory_range[0x14][6];
376 u32 msi_descriptors;
377 u32 reserved[4];
378} __packed;
379
380struct pci_resources_assigned2 {
381 struct pci_message message_type;
382 union win_slot_encoding wslot;
383 u8 memory_range[0x14][6];
384 u32 msi_descriptor_count;
385 u8 reserved[70];
386} __packed;
387
388struct pci_create_interrupt {
389 struct pci_message message_type;
390 union win_slot_encoding wslot;
391 struct hv_msi_desc int_desc;
392} __packed;
393
394struct pci_create_int_response {
395 struct pci_response response;
396 u32 reserved;
397 struct tran_int_desc int_desc;
398} __packed;
399
400struct pci_create_interrupt2 {
401 struct pci_message message_type;
402 union win_slot_encoding wslot;
403 struct hv_msi_desc2 int_desc;
404} __packed;
405
406struct pci_create_interrupt3 {
407 struct pci_message message_type;
408 union win_slot_encoding wslot;
409 struct hv_msi_desc3 int_desc;
410} __packed;
411
412struct pci_delete_interrupt {
413 struct pci_message message_type;
414 union win_slot_encoding wslot;
415 struct tran_int_desc int_desc;
416} __packed;
417
418
419
420
421struct pci_read_block {
422 struct pci_message message_type;
423 u32 block_id;
424 union win_slot_encoding wslot;
425 u32 bytes_requested;
426} __packed;
427
428struct pci_read_block_response {
429 struct vmpacket_descriptor hdr;
430 u32 status;
431 u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
432} __packed;
433
434
435
436
437struct pci_write_block {
438 struct pci_message message_type;
439 u32 block_id;
440 union win_slot_encoding wslot;
441 u32 byte_count;
442 u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
443} __packed;
444
445struct pci_dev_inval_block {
446 struct pci_incoming_message incoming;
447 union win_slot_encoding wslot;
448 u64 block_mask;
449} __packed;
450
451struct pci_dev_incoming {
452 struct pci_incoming_message incoming;
453 union win_slot_encoding wslot;
454} __packed;
455
456struct pci_eject_response {
457 struct pci_message message_type;
458 union win_slot_encoding wslot;
459 u32 status;
460} __packed;
461
462static int pci_ring_size = (4 * PAGE_SIZE);
463
464
465
466
467
468enum hv_pcibus_state {
469 hv_pcibus_init = 0,
470 hv_pcibus_probed,
471 hv_pcibus_installed,
472 hv_pcibus_removing,
473 hv_pcibus_maximum
474};
475
476struct hv_pcibus_device {
477#ifdef CONFIG_X86
478 struct pci_sysdata sysdata;
479#elif defined(CONFIG_ARM64)
480 struct pci_config_window sysdata;
481#endif
482 struct pci_host_bridge *bridge;
483 struct fwnode_handle *fwnode;
484
485 enum pci_protocol_version_t protocol_version;
486 enum hv_pcibus_state state;
487 struct hv_device *hdev;
488 resource_size_t low_mmio_space;
489 resource_size_t high_mmio_space;
490 struct resource *mem_config;
491 struct resource *low_mmio_res;
492 struct resource *high_mmio_res;
493 struct completion *survey_event;
494 struct pci_bus *pci_bus;
495 spinlock_t config_lock;
496 spinlock_t device_list_lock;
497 void __iomem *cfg_addr;
498
499 struct list_head children;
500 struct list_head dr_list;
501
502 struct msi_domain_info msi_info;
503 struct irq_domain *irq_domain;
504
505 spinlock_t retarget_msi_interrupt_lock;
506
507 struct workqueue_struct *wq;
508
509
510 int wslot_res_allocated;
511
512
513 struct hv_retarget_device_interrupt retarget_msi_interrupt_params;
514
515
516
517
518};
519
520
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522
523
524
525struct hv_dr_work {
526 struct work_struct wrk;
527 struct hv_pcibus_device *bus;
528};
529
530struct hv_pcidev_description {
531 u16 v_id;
532 u16 d_id;
533 u8 rev;
534 u8 prog_intf;
535 u8 subclass;
536 u8 base_class;
537 u32 subsystem_id;
538 union win_slot_encoding win_slot;
539 u32 ser;
540 u32 flags;
541 u16 virtual_numa_node;
542};
543
544struct hv_dr_state {
545 struct list_head list_entry;
546 u32 device_count;
547 struct hv_pcidev_description func[];
548};
549
550enum hv_pcichild_state {
551 hv_pcichild_init = 0,
552 hv_pcichild_requirements,
553 hv_pcichild_resourced,
554 hv_pcichild_ejecting,
555 hv_pcichild_maximum
556};
557
558struct hv_pci_dev {
559
560 struct list_head list_entry;
561 refcount_t refs;
562 enum hv_pcichild_state state;
563 struct pci_slot *pci_slot;
564 struct hv_pcidev_description desc;
565 bool reported_missing;
566 struct hv_pcibus_device *hbus;
567 struct work_struct wrk;
568
569 void (*block_invalidate)(void *context, u64 block_mask);
570 void *invalidate_context;
571
572
573
574
575
576 u32 probed_bar[PCI_STD_NUM_BARS];
577};
578
579struct hv_pci_compl {
580 struct completion host_event;
581 s32 completion_status;
582};
583
584static void hv_pci_onchannelcallback(void *context);
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595
596static void hv_pci_generic_compl(void *context, struct pci_response *resp,
597 int resp_packet_size)
598{
599 struct hv_pci_compl *comp_pkt = context;
600
601 if (resp_packet_size >= offsetofend(struct pci_response, status))
602 comp_pkt->completion_status = resp->status;
603 else
604 comp_pkt->completion_status = -1;
605
606 complete(&comp_pkt->host_event);
607}
608
609static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
610 u32 wslot);
611
612static void get_pcichild(struct hv_pci_dev *hpdev)
613{
614 refcount_inc(&hpdev->refs);
615}
616
617static void put_pcichild(struct hv_pci_dev *hpdev)
618{
619 if (refcount_dec_and_test(&hpdev->refs))
620 kfree(hpdev);
621}
622
623
624
625
626
627static int wait_for_response(struct hv_device *hdev,
628 struct completion *comp)
629{
630 while (true) {
631 if (hdev->channel->rescind) {
632 dev_warn_once(&hdev->device, "The device is gone.\n");
633 return -ENODEV;
634 }
635
636 if (wait_for_completion_timeout(comp, HZ / 10))
637 break;
638 }
639
640 return 0;
641}
642
643
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649
650
651static u32 devfn_to_wslot(int devfn)
652{
653 union win_slot_encoding wslot;
654
655 wslot.slot = 0;
656 wslot.bits.dev = PCI_SLOT(devfn);
657 wslot.bits.func = PCI_FUNC(devfn);
658
659 return wslot.slot;
660}
661
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669
670static int wslot_to_devfn(u32 wslot)
671{
672 union win_slot_encoding slot_no;
673
674 slot_no.slot = wslot;
675 return PCI_DEVFN(slot_no.bits.dev, slot_no.bits.func);
676}
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693static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where,
694 int size, u32 *val)
695{
696 unsigned long flags;
697 void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
698
699
700
701
702 if (where + size <= PCI_COMMAND) {
703 memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size);
704 } else if (where >= PCI_CLASS_REVISION && where + size <=
705 PCI_CACHE_LINE_SIZE) {
706 memcpy(val, ((u8 *)&hpdev->desc.rev) + where -
707 PCI_CLASS_REVISION, size);
708 } else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where + size <=
709 PCI_ROM_ADDRESS) {
710 memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where -
711 PCI_SUBSYSTEM_VENDOR_ID, size);
712 } else if (where >= PCI_ROM_ADDRESS && where + size <=
713 PCI_CAPABILITY_LIST) {
714
715 *val = 0;
716 } else if (where >= PCI_INTERRUPT_LINE && where + size <=
717 PCI_INTERRUPT_PIN) {
718
719
720
721
722
723 *val = 0;
724 } else if (where + size <= CFG_PAGE_SIZE) {
725 spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
726
727 writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
728
729 mb();
730
731 switch (size) {
732 case 1:
733 *val = readb(addr);
734 break;
735 case 2:
736 *val = readw(addr);
737 break;
738 default:
739 *val = readl(addr);
740 break;
741 }
742
743
744
745
746 mb();
747 spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
748 } else {
749 dev_err(&hpdev->hbus->hdev->device,
750 "Attempt to read beyond a function's config space.\n");
751 }
752}
753
754static u16 hv_pcifront_get_vendor_id(struct hv_pci_dev *hpdev)
755{
756 u16 ret;
757 unsigned long flags;
758 void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET +
759 PCI_VENDOR_ID;
760
761 spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
762
763
764 writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
765
766 mb();
767
768 ret = readw(addr);
769
770
771
772
773
774 spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
775
776 return ret;
777}
778
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784
785
786static void _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where,
787 int size, u32 val)
788{
789 unsigned long flags;
790 void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
791
792 if (where >= PCI_SUBSYSTEM_VENDOR_ID &&
793 where + size <= PCI_CAPABILITY_LIST) {
794
795 } else if (where >= PCI_COMMAND && where + size <= CFG_PAGE_SIZE) {
796 spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
797
798 writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
799
800 wmb();
801
802 switch (size) {
803 case 1:
804 writeb(val, addr);
805 break;
806 case 2:
807 writew(val, addr);
808 break;
809 default:
810 writel(val, addr);
811 break;
812 }
813
814
815
816
817 mb();
818 spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
819 } else {
820 dev_err(&hpdev->hbus->hdev->device,
821 "Attempt to write beyond a function's config space.\n");
822 }
823}
824
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834
835
836static int hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn,
837 int where, int size, u32 *val)
838{
839 struct hv_pcibus_device *hbus =
840 container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
841 struct hv_pci_dev *hpdev;
842
843 hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
844 if (!hpdev)
845 return PCIBIOS_DEVICE_NOT_FOUND;
846
847 _hv_pcifront_read_config(hpdev, where, size, val);
848
849 put_pcichild(hpdev);
850 return PCIBIOS_SUCCESSFUL;
851}
852
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861
862
863
864static int hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn,
865 int where, int size, u32 val)
866{
867 struct hv_pcibus_device *hbus =
868 container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
869 struct hv_pci_dev *hpdev;
870
871 hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
872 if (!hpdev)
873 return PCIBIOS_DEVICE_NOT_FOUND;
874
875 _hv_pcifront_write_config(hpdev, where, size, val);
876
877 put_pcichild(hpdev);
878 return PCIBIOS_SUCCESSFUL;
879}
880
881
882static struct pci_ops hv_pcifront_ops = {
883 .read = hv_pcifront_read_config,
884 .write = hv_pcifront_write_config,
885};
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911
912struct hv_read_config_compl {
913 struct hv_pci_compl comp_pkt;
914 void *buf;
915 unsigned int len;
916 unsigned int bytes_returned;
917};
918
919
920
921
922
923
924
925
926static void hv_pci_read_config_compl(void *context, struct pci_response *resp,
927 int resp_packet_size)
928{
929 struct hv_read_config_compl *comp = context;
930 struct pci_read_block_response *read_resp =
931 (struct pci_read_block_response *)resp;
932 unsigned int data_len, hdr_len;
933
934 hdr_len = offsetof(struct pci_read_block_response, bytes);
935 if (resp_packet_size < hdr_len) {
936 comp->comp_pkt.completion_status = -1;
937 goto out;
938 }
939
940 data_len = resp_packet_size - hdr_len;
941 if (data_len > 0 && read_resp->status == 0) {
942 comp->bytes_returned = min(comp->len, data_len);
943 memcpy(comp->buf, read_resp->bytes, comp->bytes_returned);
944 } else {
945 comp->bytes_returned = 0;
946 }
947
948 comp->comp_pkt.completion_status = read_resp->status;
949out:
950 complete(&comp->comp_pkt.host_event);
951}
952
953
954
955
956
957
958
959
960
961
962
963
964static int hv_read_config_block(struct pci_dev *pdev, void *buf,
965 unsigned int len, unsigned int block_id,
966 unsigned int *bytes_returned)
967{
968 struct hv_pcibus_device *hbus =
969 container_of(pdev->bus->sysdata, struct hv_pcibus_device,
970 sysdata);
971 struct {
972 struct pci_packet pkt;
973 char buf[sizeof(struct pci_read_block)];
974 } pkt;
975 struct hv_read_config_compl comp_pkt;
976 struct pci_read_block *read_blk;
977 int ret;
978
979 if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
980 return -EINVAL;
981
982 init_completion(&comp_pkt.comp_pkt.host_event);
983 comp_pkt.buf = buf;
984 comp_pkt.len = len;
985
986 memset(&pkt, 0, sizeof(pkt));
987 pkt.pkt.completion_func = hv_pci_read_config_compl;
988 pkt.pkt.compl_ctxt = &comp_pkt;
989 read_blk = (struct pci_read_block *)&pkt.pkt.message;
990 read_blk->message_type.type = PCI_READ_BLOCK;
991 read_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
992 read_blk->block_id = block_id;
993 read_blk->bytes_requested = len;
994
995 ret = vmbus_sendpacket(hbus->hdev->channel, read_blk,
996 sizeof(*read_blk), (unsigned long)&pkt.pkt,
997 VM_PKT_DATA_INBAND,
998 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
999 if (ret)
1000 return ret;
1001
1002 ret = wait_for_response(hbus->hdev, &comp_pkt.comp_pkt.host_event);
1003 if (ret)
1004 return ret;
1005
1006 if (comp_pkt.comp_pkt.completion_status != 0 ||
1007 comp_pkt.bytes_returned == 0) {
1008 dev_err(&hbus->hdev->device,
1009 "Read Config Block failed: 0x%x, bytes_returned=%d\n",
1010 comp_pkt.comp_pkt.completion_status,
1011 comp_pkt.bytes_returned);
1012 return -EIO;
1013 }
1014
1015 *bytes_returned = comp_pkt.bytes_returned;
1016 return 0;
1017}
1018
1019
1020
1021
1022
1023
1024
1025
1026static void hv_pci_write_config_compl(void *context, struct pci_response *resp,
1027 int resp_packet_size)
1028{
1029 struct hv_pci_compl *comp_pkt = context;
1030
1031 comp_pkt->completion_status = resp->status;
1032 complete(&comp_pkt->host_event);
1033}
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045static int hv_write_config_block(struct pci_dev *pdev, void *buf,
1046 unsigned int len, unsigned int block_id)
1047{
1048 struct hv_pcibus_device *hbus =
1049 container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1050 sysdata);
1051 struct {
1052 struct pci_packet pkt;
1053 char buf[sizeof(struct pci_write_block)];
1054 u32 reserved;
1055 } pkt;
1056 struct hv_pci_compl comp_pkt;
1057 struct pci_write_block *write_blk;
1058 u32 pkt_size;
1059 int ret;
1060
1061 if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
1062 return -EINVAL;
1063
1064 init_completion(&comp_pkt.host_event);
1065
1066 memset(&pkt, 0, sizeof(pkt));
1067 pkt.pkt.completion_func = hv_pci_write_config_compl;
1068 pkt.pkt.compl_ctxt = &comp_pkt;
1069 write_blk = (struct pci_write_block *)&pkt.pkt.message;
1070 write_blk->message_type.type = PCI_WRITE_BLOCK;
1071 write_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
1072 write_blk->block_id = block_id;
1073 write_blk->byte_count = len;
1074 memcpy(write_blk->bytes, buf, len);
1075 pkt_size = offsetof(struct pci_write_block, bytes) + len;
1076
1077
1078
1079
1080
1081
1082
1083 pkt_size += sizeof(pkt.reserved);
1084
1085 ret = vmbus_sendpacket(hbus->hdev->channel, write_blk, pkt_size,
1086 (unsigned long)&pkt.pkt, VM_PKT_DATA_INBAND,
1087 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1088 if (ret)
1089 return ret;
1090
1091 ret = wait_for_response(hbus->hdev, &comp_pkt.host_event);
1092 if (ret)
1093 return ret;
1094
1095 if (comp_pkt.completion_status != 0) {
1096 dev_err(&hbus->hdev->device,
1097 "Write Config Block failed: 0x%x\n",
1098 comp_pkt.completion_status);
1099 return -EIO;
1100 }
1101
1102 return 0;
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114static int hv_register_block_invalidate(struct pci_dev *pdev, void *context,
1115 void (*block_invalidate)(void *context,
1116 u64 block_mask))
1117{
1118 struct hv_pcibus_device *hbus =
1119 container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1120 sysdata);
1121 struct hv_pci_dev *hpdev;
1122
1123 hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1124 if (!hpdev)
1125 return -ENODEV;
1126
1127 hpdev->block_invalidate = block_invalidate;
1128 hpdev->invalidate_context = context;
1129
1130 put_pcichild(hpdev);
1131 return 0;
1132
1133}
1134
1135
1136static void hv_int_desc_free(struct hv_pci_dev *hpdev,
1137 struct tran_int_desc *int_desc)
1138{
1139 struct pci_delete_interrupt *int_pkt;
1140 struct {
1141 struct pci_packet pkt;
1142 u8 buffer[sizeof(struct pci_delete_interrupt)];
1143 } ctxt;
1144
1145 memset(&ctxt, 0, sizeof(ctxt));
1146 int_pkt = (struct pci_delete_interrupt *)&ctxt.pkt.message;
1147 int_pkt->message_type.type =
1148 PCI_DELETE_INTERRUPT_MESSAGE;
1149 int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
1150 int_pkt->int_desc = *int_desc;
1151 vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt, sizeof(*int_pkt),
1152 (unsigned long)&ctxt.pkt, VM_PKT_DATA_INBAND, 0);
1153 kfree(int_desc);
1154}
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
1168 unsigned int irq)
1169{
1170 struct hv_pcibus_device *hbus;
1171 struct hv_pci_dev *hpdev;
1172 struct pci_dev *pdev;
1173 struct tran_int_desc *int_desc;
1174 struct irq_data *irq_data = irq_domain_get_irq_data(domain, irq);
1175 struct msi_desc *msi = irq_data_get_msi_desc(irq_data);
1176
1177 pdev = msi_desc_to_pci_dev(msi);
1178 hbus = info->data;
1179 int_desc = irq_data_get_irq_chip_data(irq_data);
1180 if (!int_desc)
1181 return;
1182
1183 irq_data->chip_data = NULL;
1184 hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1185 if (!hpdev) {
1186 kfree(int_desc);
1187 return;
1188 }
1189
1190 hv_int_desc_free(hpdev, int_desc);
1191 put_pcichild(hpdev);
1192}
1193
1194static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
1195 bool force)
1196{
1197 struct irq_data *parent = data->parent_data;
1198
1199 return parent->chip->irq_set_affinity(parent, dest, force);
1200}
1201
1202static void hv_irq_mask(struct irq_data *data)
1203{
1204 pci_msi_mask_irq(data);
1205}
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217static void hv_irq_unmask(struct irq_data *data)
1218{
1219 struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
1220 struct irq_cfg *cfg = irqd_cfg(data);
1221 struct hv_retarget_device_interrupt *params;
1222 struct hv_pcibus_device *hbus;
1223 struct cpumask *dest;
1224 cpumask_var_t tmp;
1225 struct pci_bus *pbus;
1226 struct pci_dev *pdev;
1227 unsigned long flags;
1228 u32 var_size = 0;
1229 int cpu, nr_bank;
1230 u64 res;
1231
1232 dest = irq_data_get_effective_affinity_mask(data);
1233 pdev = msi_desc_to_pci_dev(msi_desc);
1234 pbus = pdev->bus;
1235 hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1236
1237 spin_lock_irqsave(&hbus->retarget_msi_interrupt_lock, flags);
1238
1239 params = &hbus->retarget_msi_interrupt_params;
1240 memset(params, 0, sizeof(*params));
1241 params->partition_id = HV_PARTITION_ID_SELF;
1242 params->int_entry.source = HV_INTERRUPT_SOURCE_MSI;
1243 hv_set_msi_entry_from_desc(¶ms->int_entry.msi_entry, msi_desc);
1244 params->device_id = (hbus->hdev->dev_instance.b[5] << 24) |
1245 (hbus->hdev->dev_instance.b[4] << 16) |
1246 (hbus->hdev->dev_instance.b[7] << 8) |
1247 (hbus->hdev->dev_instance.b[6] & 0xf8) |
1248 PCI_FUNC(pdev->devfn);
1249 params->int_target.vector = cfg->vector;
1250
1251
1252
1253
1254
1255
1256
1257
1258 if (hbus->protocol_version >= PCI_PROTOCOL_VERSION_1_2) {
1259
1260
1261
1262
1263
1264
1265
1266 params->int_target.flags |=
1267 HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET;
1268
1269 if (!alloc_cpumask_var(&tmp, GFP_ATOMIC)) {
1270 res = 1;
1271 goto exit_unlock;
1272 }
1273
1274 cpumask_and(tmp, dest, cpu_online_mask);
1275 nr_bank = cpumask_to_vpset(¶ms->int_target.vp_set, tmp);
1276 free_cpumask_var(tmp);
1277
1278 if (nr_bank <= 0) {
1279 res = 1;
1280 goto exit_unlock;
1281 }
1282
1283
1284
1285
1286
1287
1288 var_size = 1 + nr_bank;
1289 } else {
1290 for_each_cpu_and(cpu, dest, cpu_online_mask) {
1291 params->int_target.vp_mask |=
1292 (1ULL << hv_cpu_number_to_vp_number(cpu));
1293 }
1294 }
1295
1296 res = hv_do_hypercall(HVCALL_RETARGET_INTERRUPT | (var_size << 17),
1297 params, NULL);
1298
1299exit_unlock:
1300 spin_unlock_irqrestore(&hbus->retarget_msi_interrupt_lock, flags);
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318 if (!hv_result_success(res) && hbus->state != hv_pcibus_removing)
1319 dev_err(&hbus->hdev->device,
1320 "%s() failed: %#llx", __func__, res);
1321
1322 pci_msi_unmask_irq(data);
1323}
1324
1325struct compose_comp_ctxt {
1326 struct hv_pci_compl comp_pkt;
1327 struct tran_int_desc int_desc;
1328};
1329
1330static void hv_pci_compose_compl(void *context, struct pci_response *resp,
1331 int resp_packet_size)
1332{
1333 struct compose_comp_ctxt *comp_pkt = context;
1334 struct pci_create_int_response *int_resp =
1335 (struct pci_create_int_response *)resp;
1336
1337 comp_pkt->comp_pkt.completion_status = resp->status;
1338 comp_pkt->int_desc = int_resp->int_desc;
1339 complete(&comp_pkt->comp_pkt.host_event);
1340}
1341
1342static u32 hv_compose_msi_req_v1(
1343 struct pci_create_interrupt *int_pkt, struct cpumask *affinity,
1344 u32 slot, u8 vector)
1345{
1346 int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1347 int_pkt->wslot.slot = slot;
1348 int_pkt->int_desc.vector = vector;
1349 int_pkt->int_desc.vector_count = 1;
1350 int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
1351
1352
1353
1354
1355
1356 int_pkt->int_desc.cpu_mask = CPU_AFFINITY_ALL;
1357
1358 return sizeof(*int_pkt);
1359}
1360
1361
1362
1363
1364
1365static int hv_compose_msi_req_get_cpu(struct cpumask *affinity)
1366{
1367 return cpumask_first_and(affinity, cpu_online_mask);
1368}
1369
1370static u32 hv_compose_msi_req_v2(
1371 struct pci_create_interrupt2 *int_pkt, struct cpumask *affinity,
1372 u32 slot, u8 vector)
1373{
1374 int cpu;
1375
1376 int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE2;
1377 int_pkt->wslot.slot = slot;
1378 int_pkt->int_desc.vector = vector;
1379 int_pkt->int_desc.vector_count = 1;
1380 int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
1381 cpu = hv_compose_msi_req_get_cpu(affinity);
1382 int_pkt->int_desc.processor_array[0] =
1383 hv_cpu_number_to_vp_number(cpu);
1384 int_pkt->int_desc.processor_count = 1;
1385
1386 return sizeof(*int_pkt);
1387}
1388
1389static u32 hv_compose_msi_req_v3(
1390 struct pci_create_interrupt3 *int_pkt, struct cpumask *affinity,
1391 u32 slot, u32 vector)
1392{
1393 int cpu;
1394
1395 int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE3;
1396 int_pkt->wslot.slot = slot;
1397 int_pkt->int_desc.vector = vector;
1398 int_pkt->int_desc.reserved = 0;
1399 int_pkt->int_desc.vector_count = 1;
1400 int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
1401 cpu = hv_compose_msi_req_get_cpu(affinity);
1402 int_pkt->int_desc.processor_array[0] =
1403 hv_cpu_number_to_vp_number(cpu);
1404 int_pkt->int_desc.processor_count = 1;
1405
1406 return sizeof(*int_pkt);
1407}
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1421{
1422 struct irq_cfg *cfg = irqd_cfg(data);
1423 struct hv_pcibus_device *hbus;
1424 struct vmbus_channel *channel;
1425 struct hv_pci_dev *hpdev;
1426 struct pci_bus *pbus;
1427 struct pci_dev *pdev;
1428 struct cpumask *dest;
1429 struct compose_comp_ctxt comp;
1430 struct tran_int_desc *int_desc;
1431 struct {
1432 struct pci_packet pci_pkt;
1433 union {
1434 struct pci_create_interrupt v1;
1435 struct pci_create_interrupt2 v2;
1436 struct pci_create_interrupt3 v3;
1437 } int_pkts;
1438 } __packed ctxt;
1439
1440 u32 size;
1441 int ret;
1442
1443 pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
1444 dest = irq_data_get_effective_affinity_mask(data);
1445 pbus = pdev->bus;
1446 hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1447 channel = hbus->hdev->channel;
1448 hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1449 if (!hpdev)
1450 goto return_null_message;
1451
1452
1453 if (data->chip_data) {
1454 int_desc = data->chip_data;
1455 data->chip_data = NULL;
1456 hv_int_desc_free(hpdev, int_desc);
1457 }
1458
1459 int_desc = kzalloc(sizeof(*int_desc), GFP_ATOMIC);
1460 if (!int_desc)
1461 goto drop_reference;
1462
1463 memset(&ctxt, 0, sizeof(ctxt));
1464 init_completion(&comp.comp_pkt.host_event);
1465 ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
1466 ctxt.pci_pkt.compl_ctxt = ∁
1467
1468 switch (hbus->protocol_version) {
1469 case PCI_PROTOCOL_VERSION_1_1:
1470 size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
1471 dest,
1472 hpdev->desc.win_slot.slot,
1473 cfg->vector);
1474 break;
1475
1476 case PCI_PROTOCOL_VERSION_1_2:
1477 case PCI_PROTOCOL_VERSION_1_3:
1478 size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
1479 dest,
1480 hpdev->desc.win_slot.slot,
1481 cfg->vector);
1482 break;
1483
1484 case PCI_PROTOCOL_VERSION_1_4:
1485 size = hv_compose_msi_req_v3(&ctxt.int_pkts.v3,
1486 dest,
1487 hpdev->desc.win_slot.slot,
1488 cfg->vector);
1489 break;
1490
1491 default:
1492
1493
1494
1495
1496 dev_err(&hbus->hdev->device,
1497 "Unexpected vPCI protocol, update driver.");
1498 goto free_int_desc;
1499 }
1500
1501 ret = vmbus_sendpacket(hpdev->hbus->hdev->channel, &ctxt.int_pkts,
1502 size, (unsigned long)&ctxt.pci_pkt,
1503 VM_PKT_DATA_INBAND,
1504 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1505 if (ret) {
1506 dev_err(&hbus->hdev->device,
1507 "Sending request for interrupt failed: 0x%x",
1508 comp.comp_pkt.completion_status);
1509 goto free_int_desc;
1510 }
1511
1512
1513
1514
1515
1516 tasklet_disable_in_atomic(&channel->callback_event);
1517
1518
1519
1520
1521
1522 while (!try_wait_for_completion(&comp.comp_pkt.host_event)) {
1523 unsigned long flags;
1524
1525
1526 if (hv_pcifront_get_vendor_id(hpdev) == 0xFFFF) {
1527 dev_err_once(&hbus->hdev->device,
1528 "the device has gone\n");
1529 goto enable_tasklet;
1530 }
1531
1532
1533
1534
1535
1536
1537
1538
1539 spin_lock_irqsave(&channel->sched_lock, flags);
1540 if (unlikely(channel->onchannel_callback == NULL)) {
1541 spin_unlock_irqrestore(&channel->sched_lock, flags);
1542 goto enable_tasklet;
1543 }
1544 hv_pci_onchannelcallback(hbus);
1545 spin_unlock_irqrestore(&channel->sched_lock, flags);
1546
1547 if (hpdev->state == hv_pcichild_ejecting) {
1548 dev_err_once(&hbus->hdev->device,
1549 "the device is being ejected\n");
1550 goto enable_tasklet;
1551 }
1552
1553 udelay(100);
1554 }
1555
1556 tasklet_enable(&channel->callback_event);
1557
1558 if (comp.comp_pkt.completion_status < 0) {
1559 dev_err(&hbus->hdev->device,
1560 "Request for interrupt failed: 0x%x",
1561 comp.comp_pkt.completion_status);
1562 goto free_int_desc;
1563 }
1564
1565
1566
1567
1568
1569
1570 *int_desc = comp.int_desc;
1571 data->chip_data = int_desc;
1572
1573
1574 msg->address_hi = comp.int_desc.address >> 32;
1575 msg->address_lo = comp.int_desc.address & 0xffffffff;
1576 msg->data = comp.int_desc.data;
1577
1578 put_pcichild(hpdev);
1579 return;
1580
1581enable_tasklet:
1582 tasklet_enable(&channel->callback_event);
1583free_int_desc:
1584 kfree(int_desc);
1585drop_reference:
1586 put_pcichild(hpdev);
1587return_null_message:
1588 msg->address_hi = 0;
1589 msg->address_lo = 0;
1590 msg->data = 0;
1591}
1592
1593
1594static struct irq_chip hv_msi_irq_chip = {
1595 .name = "Hyper-V PCIe MSI",
1596 .irq_compose_msi_msg = hv_compose_msi_msg,
1597 .irq_set_affinity = hv_set_affinity,
1598 .irq_ack = irq_chip_ack_parent,
1599 .irq_mask = hv_irq_mask,
1600 .irq_unmask = hv_irq_unmask,
1601};
1602
1603static struct msi_domain_ops hv_msi_ops = {
1604 .msi_prepare = pci_msi_prepare,
1605 .msi_free = hv_msi_free,
1606};
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
1622{
1623 hbus->msi_info.chip = &hv_msi_irq_chip;
1624 hbus->msi_info.ops = &hv_msi_ops;
1625 hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
1626 MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
1627 MSI_FLAG_PCI_MSIX);
1628 hbus->msi_info.handler = handle_edge_irq;
1629 hbus->msi_info.handler_name = "edge";
1630 hbus->msi_info.data = hbus;
1631 hbus->irq_domain = pci_msi_create_irq_domain(hbus->fwnode,
1632 &hbus->msi_info,
1633 x86_vector_domain);
1634 if (!hbus->irq_domain) {
1635 dev_err(&hbus->hdev->device,
1636 "Failed to build an MSI IRQ domain\n");
1637 return -ENODEV;
1638 }
1639
1640 dev_set_msi_domain(&hbus->bridge->dev, hbus->irq_domain);
1641
1642 return 0;
1643}
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659static u64 get_bar_size(u64 bar_val)
1660{
1661 return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
1662 PAGE_SIZE);
1663}
1664
1665
1666
1667
1668
1669static void survey_child_resources(struct hv_pcibus_device *hbus)
1670{
1671 struct hv_pci_dev *hpdev;
1672 resource_size_t bar_size = 0;
1673 unsigned long flags;
1674 struct completion *event;
1675 u64 bar_val;
1676 int i;
1677
1678
1679 event = xchg(&hbus->survey_event, NULL);
1680 if (!event)
1681 return;
1682
1683
1684 if (hbus->low_mmio_space || hbus->high_mmio_space) {
1685 complete(event);
1686 return;
1687 }
1688
1689 spin_lock_irqsave(&hbus->device_list_lock, flags);
1690
1691
1692
1693
1694
1695
1696 list_for_each_entry(hpdev, &hbus->children, list_entry) {
1697 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1698 if (hpdev->probed_bar[i] & PCI_BASE_ADDRESS_SPACE_IO)
1699 dev_err(&hbus->hdev->device,
1700 "There's an I/O BAR in this list!\n");
1701
1702 if (hpdev->probed_bar[i] != 0) {
1703
1704
1705
1706
1707
1708 bar_val = hpdev->probed_bar[i];
1709 if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
1710 bar_val |=
1711 ((u64)hpdev->probed_bar[++i] << 32);
1712 else
1713 bar_val |= 0xffffffff00000000ULL;
1714
1715 bar_size = get_bar_size(bar_val);
1716
1717 if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
1718 hbus->high_mmio_space += bar_size;
1719 else
1720 hbus->low_mmio_space += bar_size;
1721 }
1722 }
1723 }
1724
1725 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
1726 complete(event);
1727}
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741static void prepopulate_bars(struct hv_pcibus_device *hbus)
1742{
1743 resource_size_t high_size = 0;
1744 resource_size_t low_size = 0;
1745 resource_size_t high_base = 0;
1746 resource_size_t low_base = 0;
1747 resource_size_t bar_size;
1748 struct hv_pci_dev *hpdev;
1749 unsigned long flags;
1750 u64 bar_val;
1751 u32 command;
1752 bool high;
1753 int i;
1754
1755 if (hbus->low_mmio_space) {
1756 low_size = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
1757 low_base = hbus->low_mmio_res->start;
1758 }
1759
1760 if (hbus->high_mmio_space) {
1761 high_size = 1ULL <<
1762 (63 - __builtin_clzll(hbus->high_mmio_space));
1763 high_base = hbus->high_mmio_res->start;
1764 }
1765
1766 spin_lock_irqsave(&hbus->device_list_lock, flags);
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 list_for_each_entry(hpdev, &hbus->children, list_entry) {
1780 _hv_pcifront_read_config(hpdev, PCI_COMMAND, 2, &command);
1781 command &= ~PCI_COMMAND_MEMORY;
1782 _hv_pcifront_write_config(hpdev, PCI_COMMAND, 2, command);
1783 }
1784
1785
1786 do {
1787 list_for_each_entry(hpdev, &hbus->children, list_entry) {
1788 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1789 bar_val = hpdev->probed_bar[i];
1790 if (bar_val == 0)
1791 continue;
1792 high = bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64;
1793 if (high) {
1794 bar_val |=
1795 ((u64)hpdev->probed_bar[i + 1]
1796 << 32);
1797 } else {
1798 bar_val |= 0xffffffffULL << 32;
1799 }
1800 bar_size = get_bar_size(bar_val);
1801 if (high) {
1802 if (high_size != bar_size) {
1803 i++;
1804 continue;
1805 }
1806 _hv_pcifront_write_config(hpdev,
1807 PCI_BASE_ADDRESS_0 + (4 * i),
1808 4,
1809 (u32)(high_base & 0xffffff00));
1810 i++;
1811 _hv_pcifront_write_config(hpdev,
1812 PCI_BASE_ADDRESS_0 + (4 * i),
1813 4, (u32)(high_base >> 32));
1814 high_base += bar_size;
1815 } else {
1816 if (low_size != bar_size)
1817 continue;
1818 _hv_pcifront_write_config(hpdev,
1819 PCI_BASE_ADDRESS_0 + (4 * i),
1820 4,
1821 (u32)(low_base & 0xffffff00));
1822 low_base += bar_size;
1823 }
1824 }
1825 if (high_size <= 1 && low_size <= 1) {
1826
1827 _hv_pcifront_read_config(hpdev, PCI_COMMAND, 2,
1828 &command);
1829 command |= PCI_COMMAND_MEMORY;
1830 _hv_pcifront_write_config(hpdev, PCI_COMMAND, 2,
1831 command);
1832 break;
1833 }
1834 }
1835
1836 high_size >>= 1;
1837 low_size >>= 1;
1838 } while (high_size || low_size);
1839
1840 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
1841}
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852static void hv_pci_assign_slots(struct hv_pcibus_device *hbus)
1853{
1854 struct hv_pci_dev *hpdev;
1855 char name[SLOT_NAME_SIZE];
1856 int slot_nr;
1857
1858 list_for_each_entry(hpdev, &hbus->children, list_entry) {
1859 if (hpdev->pci_slot)
1860 continue;
1861
1862 slot_nr = PCI_SLOT(wslot_to_devfn(hpdev->desc.win_slot.slot));
1863 snprintf(name, SLOT_NAME_SIZE, "%u", hpdev->desc.ser);
1864 hpdev->pci_slot = pci_create_slot(hbus->bridge->bus, slot_nr,
1865 name, NULL);
1866 if (IS_ERR(hpdev->pci_slot)) {
1867 pr_warn("pci_create slot %s failed\n", name);
1868 hpdev->pci_slot = NULL;
1869 }
1870 }
1871}
1872
1873
1874
1875
1876static void hv_pci_remove_slots(struct hv_pcibus_device *hbus)
1877{
1878 struct hv_pci_dev *hpdev;
1879
1880 list_for_each_entry(hpdev, &hbus->children, list_entry) {
1881 if (!hpdev->pci_slot)
1882 continue;
1883 pci_destroy_slot(hpdev->pci_slot);
1884 hpdev->pci_slot = NULL;
1885 }
1886}
1887
1888
1889
1890
1891static void hv_pci_assign_numa_node(struct hv_pcibus_device *hbus)
1892{
1893 struct pci_dev *dev;
1894 struct pci_bus *bus = hbus->bridge->bus;
1895 struct hv_pci_dev *hv_dev;
1896
1897 list_for_each_entry(dev, &bus->devices, bus_list) {
1898 hv_dev = get_pcichild_wslot(hbus, devfn_to_wslot(dev->devfn));
1899 if (!hv_dev)
1900 continue;
1901
1902 if (hv_dev->desc.flags & HV_PCI_DEVICE_FLAG_NUMA_AFFINITY)
1903 set_dev_node(&dev->dev, hv_dev->desc.virtual_numa_node);
1904
1905 put_pcichild(hv_dev);
1906 }
1907}
1908
1909
1910
1911
1912
1913
1914
1915static int create_root_hv_pci_bus(struct hv_pcibus_device *hbus)
1916{
1917 int error;
1918 struct pci_host_bridge *bridge = hbus->bridge;
1919
1920 bridge->dev.parent = &hbus->hdev->device;
1921 bridge->sysdata = &hbus->sysdata;
1922 bridge->ops = &hv_pcifront_ops;
1923
1924 error = pci_scan_root_bus_bridge(bridge);
1925 if (error)
1926 return error;
1927
1928 pci_lock_rescan_remove();
1929 hv_pci_assign_numa_node(hbus);
1930 pci_bus_assign_resources(bridge->bus);
1931 hv_pci_assign_slots(hbus);
1932 pci_bus_add_devices(bridge->bus);
1933 pci_unlock_rescan_remove();
1934 hbus->state = hv_pcibus_installed;
1935 return 0;
1936}
1937
1938struct q_res_req_compl {
1939 struct completion host_event;
1940 struct hv_pci_dev *hpdev;
1941};
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952static void q_resource_requirements(void *context, struct pci_response *resp,
1953 int resp_packet_size)
1954{
1955 struct q_res_req_compl *completion = context;
1956 struct pci_q_res_req_response *q_res_req =
1957 (struct pci_q_res_req_response *)resp;
1958 int i;
1959
1960 if (resp->status < 0) {
1961 dev_err(&completion->hpdev->hbus->hdev->device,
1962 "query resource requirements failed: %x\n",
1963 resp->status);
1964 } else {
1965 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1966 completion->hpdev->probed_bar[i] =
1967 q_res_req->probed_bar[i];
1968 }
1969 }
1970
1971 complete(&completion->host_event);
1972}
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985static struct hv_pci_dev *new_pcichild_device(struct hv_pcibus_device *hbus,
1986 struct hv_pcidev_description *desc)
1987{
1988 struct hv_pci_dev *hpdev;
1989 struct pci_child_message *res_req;
1990 struct q_res_req_compl comp_pkt;
1991 struct {
1992 struct pci_packet init_packet;
1993 u8 buffer[sizeof(struct pci_child_message)];
1994 } pkt;
1995 unsigned long flags;
1996 int ret;
1997
1998 hpdev = kzalloc(sizeof(*hpdev), GFP_KERNEL);
1999 if (!hpdev)
2000 return NULL;
2001
2002 hpdev->hbus = hbus;
2003
2004 memset(&pkt, 0, sizeof(pkt));
2005 init_completion(&comp_pkt.host_event);
2006 comp_pkt.hpdev = hpdev;
2007 pkt.init_packet.compl_ctxt = &comp_pkt;
2008 pkt.init_packet.completion_func = q_resource_requirements;
2009 res_req = (struct pci_child_message *)&pkt.init_packet.message;
2010 res_req->message_type.type = PCI_QUERY_RESOURCE_REQUIREMENTS;
2011 res_req->wslot.slot = desc->win_slot.slot;
2012
2013 ret = vmbus_sendpacket(hbus->hdev->channel, res_req,
2014 sizeof(struct pci_child_message),
2015 (unsigned long)&pkt.init_packet,
2016 VM_PKT_DATA_INBAND,
2017 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2018 if (ret)
2019 goto error;
2020
2021 if (wait_for_response(hbus->hdev, &comp_pkt.host_event))
2022 goto error;
2023
2024 hpdev->desc = *desc;
2025 refcount_set(&hpdev->refs, 1);
2026 get_pcichild(hpdev);
2027 spin_lock_irqsave(&hbus->device_list_lock, flags);
2028
2029 list_add_tail(&hpdev->list_entry, &hbus->children);
2030 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2031 return hpdev;
2032
2033error:
2034 kfree(hpdev);
2035 return NULL;
2036}
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
2052 u32 wslot)
2053{
2054 unsigned long flags;
2055 struct hv_pci_dev *iter, *hpdev = NULL;
2056
2057 spin_lock_irqsave(&hbus->device_list_lock, flags);
2058 list_for_each_entry(iter, &hbus->children, list_entry) {
2059 if (iter->desc.win_slot.slot == wslot) {
2060 hpdev = iter;
2061 get_pcichild(hpdev);
2062 break;
2063 }
2064 }
2065 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2066
2067 return hpdev;
2068}
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093static void pci_devices_present_work(struct work_struct *work)
2094{
2095 u32 child_no;
2096 bool found;
2097 struct hv_pcidev_description *new_desc;
2098 struct hv_pci_dev *hpdev;
2099 struct hv_pcibus_device *hbus;
2100 struct list_head removed;
2101 struct hv_dr_work *dr_wrk;
2102 struct hv_dr_state *dr = NULL;
2103 unsigned long flags;
2104
2105 dr_wrk = container_of(work, struct hv_dr_work, wrk);
2106 hbus = dr_wrk->bus;
2107 kfree(dr_wrk);
2108
2109 INIT_LIST_HEAD(&removed);
2110
2111
2112 spin_lock_irqsave(&hbus->device_list_lock, flags);
2113 while (!list_empty(&hbus->dr_list)) {
2114 dr = list_first_entry(&hbus->dr_list, struct hv_dr_state,
2115 list_entry);
2116 list_del(&dr->list_entry);
2117
2118
2119 if (!list_empty(&hbus->dr_list)) {
2120 kfree(dr);
2121 continue;
2122 }
2123 }
2124 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2125
2126 if (!dr)
2127 return;
2128
2129
2130 spin_lock_irqsave(&hbus->device_list_lock, flags);
2131 list_for_each_entry(hpdev, &hbus->children, list_entry) {
2132 hpdev->reported_missing = true;
2133 }
2134 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2135
2136
2137 for (child_no = 0; child_no < dr->device_count; child_no++) {
2138 found = false;
2139 new_desc = &dr->func[child_no];
2140
2141 spin_lock_irqsave(&hbus->device_list_lock, flags);
2142 list_for_each_entry(hpdev, &hbus->children, list_entry) {
2143 if ((hpdev->desc.win_slot.slot == new_desc->win_slot.slot) &&
2144 (hpdev->desc.v_id == new_desc->v_id) &&
2145 (hpdev->desc.d_id == new_desc->d_id) &&
2146 (hpdev->desc.ser == new_desc->ser)) {
2147 hpdev->reported_missing = false;
2148 found = true;
2149 }
2150 }
2151 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2152
2153 if (!found) {
2154 hpdev = new_pcichild_device(hbus, new_desc);
2155 if (!hpdev)
2156 dev_err(&hbus->hdev->device,
2157 "couldn't record a child device.\n");
2158 }
2159 }
2160
2161
2162 spin_lock_irqsave(&hbus->device_list_lock, flags);
2163 do {
2164 found = false;
2165 list_for_each_entry(hpdev, &hbus->children, list_entry) {
2166 if (hpdev->reported_missing) {
2167 found = true;
2168 put_pcichild(hpdev);
2169 list_move_tail(&hpdev->list_entry, &removed);
2170 break;
2171 }
2172 }
2173 } while (found);
2174 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2175
2176
2177 while (!list_empty(&removed)) {
2178 hpdev = list_first_entry(&removed, struct hv_pci_dev,
2179 list_entry);
2180 list_del(&hpdev->list_entry);
2181
2182 if (hpdev->pci_slot)
2183 pci_destroy_slot(hpdev->pci_slot);
2184
2185 put_pcichild(hpdev);
2186 }
2187
2188 switch (hbus->state) {
2189 case hv_pcibus_installed:
2190
2191
2192
2193
2194 pci_lock_rescan_remove();
2195 pci_scan_child_bus(hbus->bridge->bus);
2196 hv_pci_assign_numa_node(hbus);
2197 hv_pci_assign_slots(hbus);
2198 pci_unlock_rescan_remove();
2199 break;
2200
2201 case hv_pcibus_init:
2202 case hv_pcibus_probed:
2203 survey_child_resources(hbus);
2204 break;
2205
2206 default:
2207 break;
2208 }
2209
2210 kfree(dr);
2211}
2212
2213
2214
2215
2216
2217
2218
2219
2220static int hv_pci_start_relations_work(struct hv_pcibus_device *hbus,
2221 struct hv_dr_state *dr)
2222{
2223 struct hv_dr_work *dr_wrk;
2224 unsigned long flags;
2225 bool pending_dr;
2226
2227 if (hbus->state == hv_pcibus_removing) {
2228 dev_info(&hbus->hdev->device,
2229 "PCI VMBus BUS_RELATIONS: ignored\n");
2230 return -ENOENT;
2231 }
2232
2233 dr_wrk = kzalloc(sizeof(*dr_wrk), GFP_NOWAIT);
2234 if (!dr_wrk)
2235 return -ENOMEM;
2236
2237 INIT_WORK(&dr_wrk->wrk, pci_devices_present_work);
2238 dr_wrk->bus = hbus;
2239
2240 spin_lock_irqsave(&hbus->device_list_lock, flags);
2241
2242
2243
2244
2245
2246 pending_dr = !list_empty(&hbus->dr_list);
2247 list_add_tail(&dr->list_entry, &hbus->dr_list);
2248 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2249
2250 if (pending_dr)
2251 kfree(dr_wrk);
2252 else
2253 queue_work(hbus->wq, &dr_wrk->wrk);
2254
2255 return 0;
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267static void hv_pci_devices_present(struct hv_pcibus_device *hbus,
2268 struct pci_bus_relations *relations)
2269{
2270 struct hv_dr_state *dr;
2271 int i;
2272
2273 dr = kzalloc(struct_size(dr, func, relations->device_count),
2274 GFP_NOWAIT);
2275 if (!dr)
2276 return;
2277
2278 dr->device_count = relations->device_count;
2279 for (i = 0; i < dr->device_count; i++) {
2280 dr->func[i].v_id = relations->func[i].v_id;
2281 dr->func[i].d_id = relations->func[i].d_id;
2282 dr->func[i].rev = relations->func[i].rev;
2283 dr->func[i].prog_intf = relations->func[i].prog_intf;
2284 dr->func[i].subclass = relations->func[i].subclass;
2285 dr->func[i].base_class = relations->func[i].base_class;
2286 dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2287 dr->func[i].win_slot = relations->func[i].win_slot;
2288 dr->func[i].ser = relations->func[i].ser;
2289 }
2290
2291 if (hv_pci_start_relations_work(hbus, dr))
2292 kfree(dr);
2293}
2294
2295
2296
2297
2298
2299
2300
2301
2302static void hv_pci_devices_present2(struct hv_pcibus_device *hbus,
2303 struct pci_bus_relations2 *relations)
2304{
2305 struct hv_dr_state *dr;
2306 int i;
2307
2308 dr = kzalloc(struct_size(dr, func, relations->device_count),
2309 GFP_NOWAIT);
2310 if (!dr)
2311 return;
2312
2313 dr->device_count = relations->device_count;
2314 for (i = 0; i < dr->device_count; i++) {
2315 dr->func[i].v_id = relations->func[i].v_id;
2316 dr->func[i].d_id = relations->func[i].d_id;
2317 dr->func[i].rev = relations->func[i].rev;
2318 dr->func[i].prog_intf = relations->func[i].prog_intf;
2319 dr->func[i].subclass = relations->func[i].subclass;
2320 dr->func[i].base_class = relations->func[i].base_class;
2321 dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2322 dr->func[i].win_slot = relations->func[i].win_slot;
2323 dr->func[i].ser = relations->func[i].ser;
2324 dr->func[i].flags = relations->func[i].flags;
2325 dr->func[i].virtual_numa_node =
2326 relations->func[i].virtual_numa_node;
2327 }
2328
2329 if (hv_pci_start_relations_work(hbus, dr))
2330 kfree(dr);
2331}
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342static void hv_eject_device_work(struct work_struct *work)
2343{
2344 struct pci_eject_response *ejct_pkt;
2345 struct hv_pcibus_device *hbus;
2346 struct hv_pci_dev *hpdev;
2347 struct pci_dev *pdev;
2348 unsigned long flags;
2349 int wslot;
2350 struct {
2351 struct pci_packet pkt;
2352 u8 buffer[sizeof(struct pci_eject_response)];
2353 } ctxt;
2354
2355 hpdev = container_of(work, struct hv_pci_dev, wrk);
2356 hbus = hpdev->hbus;
2357
2358 WARN_ON(hpdev->state != hv_pcichild_ejecting);
2359
2360
2361
2362
2363
2364
2365
2366 wslot = wslot_to_devfn(hpdev->desc.win_slot.slot);
2367 pdev = pci_get_domain_bus_and_slot(hbus->bridge->domain_nr, 0, wslot);
2368 if (pdev) {
2369 pci_lock_rescan_remove();
2370 pci_stop_and_remove_bus_device(pdev);
2371 pci_dev_put(pdev);
2372 pci_unlock_rescan_remove();
2373 }
2374
2375 spin_lock_irqsave(&hbus->device_list_lock, flags);
2376 list_del(&hpdev->list_entry);
2377 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2378
2379 if (hpdev->pci_slot)
2380 pci_destroy_slot(hpdev->pci_slot);
2381
2382 memset(&ctxt, 0, sizeof(ctxt));
2383 ejct_pkt = (struct pci_eject_response *)&ctxt.pkt.message;
2384 ejct_pkt->message_type.type = PCI_EJECTION_COMPLETE;
2385 ejct_pkt->wslot.slot = hpdev->desc.win_slot.slot;
2386 vmbus_sendpacket(hbus->hdev->channel, ejct_pkt,
2387 sizeof(*ejct_pkt), (unsigned long)&ctxt.pkt,
2388 VM_PKT_DATA_INBAND, 0);
2389
2390
2391 put_pcichild(hpdev);
2392
2393 put_pcichild(hpdev);
2394 put_pcichild(hpdev);
2395
2396}
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406static void hv_pci_eject_device(struct hv_pci_dev *hpdev)
2407{
2408 struct hv_pcibus_device *hbus = hpdev->hbus;
2409 struct hv_device *hdev = hbus->hdev;
2410
2411 if (hbus->state == hv_pcibus_removing) {
2412 dev_info(&hdev->device, "PCI VMBus EJECT: ignored\n");
2413 return;
2414 }
2415
2416 hpdev->state = hv_pcichild_ejecting;
2417 get_pcichild(hpdev);
2418 INIT_WORK(&hpdev->wrk, hv_eject_device_work);
2419 queue_work(hbus->wq, &hpdev->wrk);
2420}
2421
2422
2423
2424
2425
2426
2427
2428
2429static void hv_pci_onchannelcallback(void *context)
2430{
2431 const int packet_size = 0x100;
2432 int ret;
2433 struct hv_pcibus_device *hbus = context;
2434 u32 bytes_recvd;
2435 u64 req_id;
2436 struct vmpacket_descriptor *desc;
2437 unsigned char *buffer;
2438 int bufferlen = packet_size;
2439 struct pci_packet *comp_packet;
2440 struct pci_response *response;
2441 struct pci_incoming_message *new_message;
2442 struct pci_bus_relations *bus_rel;
2443 struct pci_bus_relations2 *bus_rel2;
2444 struct pci_dev_inval_block *inval;
2445 struct pci_dev_incoming *dev_message;
2446 struct hv_pci_dev *hpdev;
2447
2448 buffer = kmalloc(bufferlen, GFP_ATOMIC);
2449 if (!buffer)
2450 return;
2451
2452 while (1) {
2453 ret = vmbus_recvpacket_raw(hbus->hdev->channel, buffer,
2454 bufferlen, &bytes_recvd, &req_id);
2455
2456 if (ret == -ENOBUFS) {
2457 kfree(buffer);
2458
2459 bufferlen = bytes_recvd;
2460 buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
2461 if (!buffer)
2462 return;
2463 continue;
2464 }
2465
2466
2467 if (ret || !bytes_recvd)
2468 break;
2469
2470
2471
2472
2473
2474 if (bytes_recvd <= sizeof(struct pci_response))
2475 continue;
2476 desc = (struct vmpacket_descriptor *)buffer;
2477
2478 switch (desc->type) {
2479 case VM_PKT_COMP:
2480
2481
2482
2483
2484
2485 comp_packet = (struct pci_packet *)req_id;
2486 response = (struct pci_response *)buffer;
2487 comp_packet->completion_func(comp_packet->compl_ctxt,
2488 response,
2489 bytes_recvd);
2490 break;
2491
2492 case VM_PKT_DATA_INBAND:
2493
2494 new_message = (struct pci_incoming_message *)buffer;
2495 switch (new_message->message_type.type) {
2496 case PCI_BUS_RELATIONS:
2497
2498 bus_rel = (struct pci_bus_relations *)buffer;
2499 if (bytes_recvd <
2500 struct_size(bus_rel, func,
2501 bus_rel->device_count)) {
2502 dev_err(&hbus->hdev->device,
2503 "bus relations too small\n");
2504 break;
2505 }
2506
2507 hv_pci_devices_present(hbus, bus_rel);
2508 break;
2509
2510 case PCI_BUS_RELATIONS2:
2511
2512 bus_rel2 = (struct pci_bus_relations2 *)buffer;
2513 if (bytes_recvd <
2514 struct_size(bus_rel2, func,
2515 bus_rel2->device_count)) {
2516 dev_err(&hbus->hdev->device,
2517 "bus relations v2 too small\n");
2518 break;
2519 }
2520
2521 hv_pci_devices_present2(hbus, bus_rel2);
2522 break;
2523
2524 case PCI_EJECT:
2525
2526 dev_message = (struct pci_dev_incoming *)buffer;
2527 hpdev = get_pcichild_wslot(hbus,
2528 dev_message->wslot.slot);
2529 if (hpdev) {
2530 hv_pci_eject_device(hpdev);
2531 put_pcichild(hpdev);
2532 }
2533 break;
2534
2535 case PCI_INVALIDATE_BLOCK:
2536
2537 inval = (struct pci_dev_inval_block *)buffer;
2538 hpdev = get_pcichild_wslot(hbus,
2539 inval->wslot.slot);
2540 if (hpdev) {
2541 if (hpdev->block_invalidate) {
2542 hpdev->block_invalidate(
2543 hpdev->invalidate_context,
2544 inval->block_mask);
2545 }
2546 put_pcichild(hpdev);
2547 }
2548 break;
2549
2550 default:
2551 dev_warn(&hbus->hdev->device,
2552 "Unimplemented protocol message %x\n",
2553 new_message->message_type.type);
2554 break;
2555 }
2556 break;
2557
2558 default:
2559 dev_err(&hbus->hdev->device,
2560 "unhandled packet type %d, tid %llx len %d\n",
2561 desc->type, req_id, bytes_recvd);
2562 break;
2563 }
2564 }
2565
2566 kfree(buffer);
2567}
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588static int hv_pci_protocol_negotiation(struct hv_device *hdev,
2589 enum pci_protocol_version_t version[],
2590 int num_version)
2591{
2592 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2593 struct pci_version_request *version_req;
2594 struct hv_pci_compl comp_pkt;
2595 struct pci_packet *pkt;
2596 int ret;
2597 int i;
2598
2599
2600
2601
2602
2603
2604
2605 pkt = kzalloc(sizeof(*pkt) + sizeof(*version_req), GFP_KERNEL);
2606 if (!pkt)
2607 return -ENOMEM;
2608
2609 init_completion(&comp_pkt.host_event);
2610 pkt->completion_func = hv_pci_generic_compl;
2611 pkt->compl_ctxt = &comp_pkt;
2612 version_req = (struct pci_version_request *)&pkt->message;
2613 version_req->message_type.type = PCI_QUERY_PROTOCOL_VERSION;
2614
2615 for (i = 0; i < num_version; i++) {
2616 version_req->protocol_version = version[i];
2617 ret = vmbus_sendpacket(hdev->channel, version_req,
2618 sizeof(struct pci_version_request),
2619 (unsigned long)pkt, VM_PKT_DATA_INBAND,
2620 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2621 if (!ret)
2622 ret = wait_for_response(hdev, &comp_pkt.host_event);
2623
2624 if (ret) {
2625 dev_err(&hdev->device,
2626 "PCI Pass-through VSP failed to request version: %d",
2627 ret);
2628 goto exit;
2629 }
2630
2631 if (comp_pkt.completion_status >= 0) {
2632 hbus->protocol_version = version[i];
2633 dev_info(&hdev->device,
2634 "PCI VMBus probing: Using version %#x\n",
2635 hbus->protocol_version);
2636 goto exit;
2637 }
2638
2639 if (comp_pkt.completion_status != STATUS_REVISION_MISMATCH) {
2640 dev_err(&hdev->device,
2641 "PCI Pass-through VSP failed version request: %#x",
2642 comp_pkt.completion_status);
2643 ret = -EPROTO;
2644 goto exit;
2645 }
2646
2647 reinit_completion(&comp_pkt.host_event);
2648 }
2649
2650 dev_err(&hdev->device,
2651 "PCI pass-through VSP failed to find supported version");
2652 ret = -EPROTO;
2653
2654exit:
2655 kfree(pkt);
2656 return ret;
2657}
2658
2659
2660
2661
2662
2663
2664static void hv_pci_free_bridge_windows(struct hv_pcibus_device *hbus)
2665{
2666
2667
2668
2669
2670
2671 if (hbus->low_mmio_space && hbus->low_mmio_res) {
2672 hbus->low_mmio_res->flags |= IORESOURCE_BUSY;
2673 vmbus_free_mmio(hbus->low_mmio_res->start,
2674 resource_size(hbus->low_mmio_res));
2675 }
2676
2677 if (hbus->high_mmio_space && hbus->high_mmio_res) {
2678 hbus->high_mmio_res->flags |= IORESOURCE_BUSY;
2679 vmbus_free_mmio(hbus->high_mmio_res->start,
2680 resource_size(hbus->high_mmio_res));
2681 }
2682}
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709static int hv_pci_allocate_bridge_windows(struct hv_pcibus_device *hbus)
2710{
2711 resource_size_t align;
2712 int ret;
2713
2714 if (hbus->low_mmio_space) {
2715 align = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
2716 ret = vmbus_allocate_mmio(&hbus->low_mmio_res, hbus->hdev, 0,
2717 (u64)(u32)0xffffffff,
2718 hbus->low_mmio_space,
2719 align, false);
2720 if (ret) {
2721 dev_err(&hbus->hdev->device,
2722 "Need %#llx of low MMIO space. Consider reconfiguring the VM.\n",
2723 hbus->low_mmio_space);
2724 return ret;
2725 }
2726
2727
2728 hbus->low_mmio_res->flags |= IORESOURCE_WINDOW;
2729 hbus->low_mmio_res->flags &= ~IORESOURCE_BUSY;
2730 pci_add_resource(&hbus->bridge->windows, hbus->low_mmio_res);
2731 }
2732
2733 if (hbus->high_mmio_space) {
2734 align = 1ULL << (63 - __builtin_clzll(hbus->high_mmio_space));
2735 ret = vmbus_allocate_mmio(&hbus->high_mmio_res, hbus->hdev,
2736 0x100000000, -1,
2737 hbus->high_mmio_space, align,
2738 false);
2739 if (ret) {
2740 dev_err(&hbus->hdev->device,
2741 "Need %#llx of high MMIO space. Consider reconfiguring the VM.\n",
2742 hbus->high_mmio_space);
2743 goto release_low_mmio;
2744 }
2745
2746
2747 hbus->high_mmio_res->flags |= IORESOURCE_WINDOW;
2748 hbus->high_mmio_res->flags &= ~IORESOURCE_BUSY;
2749 pci_add_resource(&hbus->bridge->windows, hbus->high_mmio_res);
2750 }
2751
2752 return 0;
2753
2754release_low_mmio:
2755 if (hbus->low_mmio_res) {
2756 vmbus_free_mmio(hbus->low_mmio_res->start,
2757 resource_size(hbus->low_mmio_res));
2758 }
2759
2760 return ret;
2761}
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772static int hv_allocate_config_window(struct hv_pcibus_device *hbus)
2773{
2774 int ret;
2775
2776
2777
2778
2779
2780 ret = vmbus_allocate_mmio(&hbus->mem_config, hbus->hdev, 0, -1,
2781 PCI_CONFIG_MMIO_LENGTH, 0x1000, false);
2782 if (ret)
2783 return ret;
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793 hbus->mem_config->flags |= IORESOURCE_BUSY;
2794
2795 return 0;
2796}
2797
2798static void hv_free_config_window(struct hv_pcibus_device *hbus)
2799{
2800 vmbus_free_mmio(hbus->mem_config->start, PCI_CONFIG_MMIO_LENGTH);
2801}
2802
2803static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs);
2804
2805
2806
2807
2808
2809
2810
2811static int hv_pci_enter_d0(struct hv_device *hdev)
2812{
2813 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2814 struct pci_bus_d0_entry *d0_entry;
2815 struct hv_pci_compl comp_pkt;
2816 struct pci_packet *pkt;
2817 int ret;
2818
2819
2820
2821
2822
2823
2824
2825 pkt = kzalloc(sizeof(*pkt) + sizeof(*d0_entry), GFP_KERNEL);
2826 if (!pkt)
2827 return -ENOMEM;
2828
2829 init_completion(&comp_pkt.host_event);
2830 pkt->completion_func = hv_pci_generic_compl;
2831 pkt->compl_ctxt = &comp_pkt;
2832 d0_entry = (struct pci_bus_d0_entry *)&pkt->message;
2833 d0_entry->message_type.type = PCI_BUS_D0ENTRY;
2834 d0_entry->mmio_base = hbus->mem_config->start;
2835
2836 ret = vmbus_sendpacket(hdev->channel, d0_entry, sizeof(*d0_entry),
2837 (unsigned long)pkt, VM_PKT_DATA_INBAND,
2838 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2839 if (!ret)
2840 ret = wait_for_response(hdev, &comp_pkt.host_event);
2841
2842 if (ret)
2843 goto exit;
2844
2845 if (comp_pkt.completion_status < 0) {
2846 dev_err(&hdev->device,
2847 "PCI Pass-through VSP failed D0 Entry with status %x\n",
2848 comp_pkt.completion_status);
2849 ret = -EPROTO;
2850 goto exit;
2851 }
2852
2853 ret = 0;
2854
2855exit:
2856 kfree(pkt);
2857 return ret;
2858}
2859
2860
2861
2862
2863
2864
2865
2866
2867static int hv_pci_query_relations(struct hv_device *hdev)
2868{
2869 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2870 struct pci_message message;
2871 struct completion comp;
2872 int ret;
2873
2874
2875 init_completion(&comp);
2876 if (cmpxchg(&hbus->survey_event, NULL, &comp))
2877 return -ENOTEMPTY;
2878
2879 memset(&message, 0, sizeof(message));
2880 message.type = PCI_QUERY_BUS_RELATIONS;
2881
2882 ret = vmbus_sendpacket(hdev->channel, &message, sizeof(message),
2883 0, VM_PKT_DATA_INBAND, 0);
2884 if (!ret)
2885 ret = wait_for_response(hdev, &comp);
2886
2887 return ret;
2888}
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907static int hv_send_resources_allocated(struct hv_device *hdev)
2908{
2909 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2910 struct pci_resources_assigned *res_assigned;
2911 struct pci_resources_assigned2 *res_assigned2;
2912 struct hv_pci_compl comp_pkt;
2913 struct hv_pci_dev *hpdev;
2914 struct pci_packet *pkt;
2915 size_t size_res;
2916 int wslot;
2917 int ret;
2918
2919 size_res = (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2)
2920 ? sizeof(*res_assigned) : sizeof(*res_assigned2);
2921
2922 pkt = kmalloc(sizeof(*pkt) + size_res, GFP_KERNEL);
2923 if (!pkt)
2924 return -ENOMEM;
2925
2926 ret = 0;
2927
2928 for (wslot = 0; wslot < 256; wslot++) {
2929 hpdev = get_pcichild_wslot(hbus, wslot);
2930 if (!hpdev)
2931 continue;
2932
2933 memset(pkt, 0, sizeof(*pkt) + size_res);
2934 init_completion(&comp_pkt.host_event);
2935 pkt->completion_func = hv_pci_generic_compl;
2936 pkt->compl_ctxt = &comp_pkt;
2937
2938 if (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2) {
2939 res_assigned =
2940 (struct pci_resources_assigned *)&pkt->message;
2941 res_assigned->message_type.type =
2942 PCI_RESOURCES_ASSIGNED;
2943 res_assigned->wslot.slot = hpdev->desc.win_slot.slot;
2944 } else {
2945 res_assigned2 =
2946 (struct pci_resources_assigned2 *)&pkt->message;
2947 res_assigned2->message_type.type =
2948 PCI_RESOURCES_ASSIGNED2;
2949 res_assigned2->wslot.slot = hpdev->desc.win_slot.slot;
2950 }
2951 put_pcichild(hpdev);
2952
2953 ret = vmbus_sendpacket(hdev->channel, &pkt->message,
2954 size_res, (unsigned long)pkt,
2955 VM_PKT_DATA_INBAND,
2956 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2957 if (!ret)
2958 ret = wait_for_response(hdev, &comp_pkt.host_event);
2959 if (ret)
2960 break;
2961
2962 if (comp_pkt.completion_status < 0) {
2963 ret = -EPROTO;
2964 dev_err(&hdev->device,
2965 "resource allocated returned 0x%x",
2966 comp_pkt.completion_status);
2967 break;
2968 }
2969
2970 hbus->wslot_res_allocated = wslot;
2971 }
2972
2973 kfree(pkt);
2974 return ret;
2975}
2976
2977
2978
2979
2980
2981
2982
2983
2984static int hv_send_resources_released(struct hv_device *hdev)
2985{
2986 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2987 struct pci_child_message pkt;
2988 struct hv_pci_dev *hpdev;
2989 int wslot;
2990 int ret;
2991
2992 for (wslot = hbus->wslot_res_allocated; wslot >= 0; wslot--) {
2993 hpdev = get_pcichild_wslot(hbus, wslot);
2994 if (!hpdev)
2995 continue;
2996
2997 memset(&pkt, 0, sizeof(pkt));
2998 pkt.message_type.type = PCI_RESOURCES_RELEASED;
2999 pkt.wslot.slot = hpdev->desc.win_slot.slot;
3000
3001 put_pcichild(hpdev);
3002
3003 ret = vmbus_sendpacket(hdev->channel, &pkt, sizeof(pkt), 0,
3004 VM_PKT_DATA_INBAND, 0);
3005 if (ret)
3006 return ret;
3007
3008 hbus->wslot_res_allocated = wslot - 1;
3009 }
3010
3011 hbus->wslot_res_allocated = -1;
3012
3013 return 0;
3014}
3015
3016#define HVPCI_DOM_MAP_SIZE (64 * 1024)
3017static DECLARE_BITMAP(hvpci_dom_map, HVPCI_DOM_MAP_SIZE);
3018
3019
3020
3021
3022
3023#define HVPCI_DOM_INVALID 0
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034static u16 hv_get_dom_num(u16 dom)
3035{
3036 unsigned int i;
3037
3038 if (test_and_set_bit(dom, hvpci_dom_map) == 0)
3039 return dom;
3040
3041 for_each_clear_bit(i, hvpci_dom_map, HVPCI_DOM_MAP_SIZE) {
3042 if (test_and_set_bit(i, hvpci_dom_map) == 0)
3043 return i;
3044 }
3045
3046 return HVPCI_DOM_INVALID;
3047}
3048
3049
3050
3051
3052
3053static void hv_put_dom_num(u16 dom)
3054{
3055 clear_bit(dom, hvpci_dom_map);
3056}
3057
3058
3059
3060
3061
3062
3063
3064
3065static int hv_pci_probe(struct hv_device *hdev,
3066 const struct hv_vmbus_device_id *dev_id)
3067{
3068 struct pci_host_bridge *bridge;
3069 struct hv_pcibus_device *hbus;
3070 u16 dom_req, dom;
3071 char *name;
3072 bool enter_d0_retry = true;
3073 int ret;
3074
3075
3076
3077
3078
3079 BUILD_BUG_ON(sizeof(*hbus) > HV_HYP_PAGE_SIZE);
3080
3081 bridge = devm_pci_alloc_host_bridge(&hdev->device, 0);
3082 if (!bridge)
3083 return -ENOMEM;
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103 hbus = kzalloc(HV_HYP_PAGE_SIZE, GFP_KERNEL);
3104 if (!hbus)
3105 return -ENOMEM;
3106
3107 hbus->bridge = bridge;
3108 hbus->state = hv_pcibus_init;
3109 hbus->wslot_res_allocated = -1;
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124 dom_req = hdev->dev_instance.b[5] << 8 | hdev->dev_instance.b[4];
3125 dom = hv_get_dom_num(dom_req);
3126
3127 if (dom == HVPCI_DOM_INVALID) {
3128 dev_err(&hdev->device,
3129 "Unable to use dom# 0x%hx or other numbers", dom_req);
3130 ret = -EINVAL;
3131 goto free_bus;
3132 }
3133
3134 if (dom != dom_req)
3135 dev_info(&hdev->device,
3136 "PCI dom# 0x%hx has collision, using 0x%hx",
3137 dom_req, dom);
3138
3139 hbus->bridge->domain_nr = dom;
3140#ifdef CONFIG_X86
3141 hbus->sysdata.domain = dom;
3142#endif
3143
3144 hbus->hdev = hdev;
3145 INIT_LIST_HEAD(&hbus->children);
3146 INIT_LIST_HEAD(&hbus->dr_list);
3147 spin_lock_init(&hbus->config_lock);
3148 spin_lock_init(&hbus->device_list_lock);
3149 spin_lock_init(&hbus->retarget_msi_interrupt_lock);
3150 hbus->wq = alloc_ordered_workqueue("hv_pci_%x", 0,
3151 hbus->bridge->domain_nr);
3152 if (!hbus->wq) {
3153 ret = -ENOMEM;
3154 goto free_dom;
3155 }
3156
3157 ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
3158 hv_pci_onchannelcallback, hbus);
3159 if (ret)
3160 goto destroy_wq;
3161
3162 hv_set_drvdata(hdev, hbus);
3163
3164 ret = hv_pci_protocol_negotiation(hdev, pci_protocol_versions,
3165 ARRAY_SIZE(pci_protocol_versions));
3166 if (ret)
3167 goto close;
3168
3169 ret = hv_allocate_config_window(hbus);
3170 if (ret)
3171 goto close;
3172
3173 hbus->cfg_addr = ioremap(hbus->mem_config->start,
3174 PCI_CONFIG_MMIO_LENGTH);
3175 if (!hbus->cfg_addr) {
3176 dev_err(&hdev->device,
3177 "Unable to map a virtual address for config space\n");
3178 ret = -ENOMEM;
3179 goto free_config;
3180 }
3181
3182 name = kasprintf(GFP_KERNEL, "%pUL", &hdev->dev_instance);
3183 if (!name) {
3184 ret = -ENOMEM;
3185 goto unmap;
3186 }
3187
3188 hbus->fwnode = irq_domain_alloc_named_fwnode(name);
3189 kfree(name);
3190 if (!hbus->fwnode) {
3191 ret = -ENOMEM;
3192 goto unmap;
3193 }
3194
3195 ret = hv_pcie_init_irq_domain(hbus);
3196 if (ret)
3197 goto free_fwnode;
3198
3199retry:
3200 ret = hv_pci_query_relations(hdev);
3201 if (ret)
3202 goto free_irq_domain;
3203
3204 ret = hv_pci_enter_d0(hdev);
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218 if (ret == -EPROTO && enter_d0_retry) {
3219 enter_d0_retry = false;
3220
3221 dev_err(&hdev->device, "Retrying D0 Entry\n");
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231 hbus->wslot_res_allocated = 255;
3232 ret = hv_pci_bus_exit(hdev, true);
3233
3234 if (ret == 0)
3235 goto retry;
3236
3237 dev_err(&hdev->device,
3238 "Retrying D0 failed with ret %d\n", ret);
3239 }
3240 if (ret)
3241 goto free_irq_domain;
3242
3243 ret = hv_pci_allocate_bridge_windows(hbus);
3244 if (ret)
3245 goto exit_d0;
3246
3247 ret = hv_send_resources_allocated(hdev);
3248 if (ret)
3249 goto free_windows;
3250
3251 prepopulate_bars(hbus);
3252
3253 hbus->state = hv_pcibus_probed;
3254
3255 ret = create_root_hv_pci_bus(hbus);
3256 if (ret)
3257 goto free_windows;
3258
3259 return 0;
3260
3261free_windows:
3262 hv_pci_free_bridge_windows(hbus);
3263exit_d0:
3264 (void) hv_pci_bus_exit(hdev, true);
3265free_irq_domain:
3266 irq_domain_remove(hbus->irq_domain);
3267free_fwnode:
3268 irq_domain_free_fwnode(hbus->fwnode);
3269unmap:
3270 iounmap(hbus->cfg_addr);
3271free_config:
3272 hv_free_config_window(hbus);
3273close:
3274 vmbus_close(hdev->channel);
3275destroy_wq:
3276 destroy_workqueue(hbus->wq);
3277free_dom:
3278 hv_put_dom_num(hbus->bridge->domain_nr);
3279free_bus:
3280 kfree(hbus);
3281 return ret;
3282}
3283
3284static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs)
3285{
3286 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3287 struct {
3288 struct pci_packet teardown_packet;
3289 u8 buffer[sizeof(struct pci_message)];
3290 } pkt;
3291 struct hv_pci_compl comp_pkt;
3292 struct hv_pci_dev *hpdev, *tmp;
3293 unsigned long flags;
3294 int ret;
3295
3296
3297
3298
3299
3300 if (hdev->channel->rescind)
3301 return 0;
3302
3303 if (!keep_devs) {
3304 struct list_head removed;
3305
3306
3307 INIT_LIST_HEAD(&removed);
3308 spin_lock_irqsave(&hbus->device_list_lock, flags);
3309 list_for_each_entry_safe(hpdev, tmp, &hbus->children, list_entry)
3310 list_move_tail(&hpdev->list_entry, &removed);
3311 spin_unlock_irqrestore(&hbus->device_list_lock, flags);
3312
3313
3314 list_for_each_entry_safe(hpdev, tmp, &removed, list_entry) {
3315 list_del(&hpdev->list_entry);
3316 if (hpdev->pci_slot)
3317 pci_destroy_slot(hpdev->pci_slot);
3318
3319 put_pcichild(hpdev);
3320 put_pcichild(hpdev);
3321 }
3322 }
3323
3324 ret = hv_send_resources_released(hdev);
3325 if (ret) {
3326 dev_err(&hdev->device,
3327 "Couldn't send resources released packet(s)\n");
3328 return ret;
3329 }
3330
3331 memset(&pkt.teardown_packet, 0, sizeof(pkt.teardown_packet));
3332 init_completion(&comp_pkt.host_event);
3333 pkt.teardown_packet.completion_func = hv_pci_generic_compl;
3334 pkt.teardown_packet.compl_ctxt = &comp_pkt;
3335 pkt.teardown_packet.message[0].type = PCI_BUS_D0EXIT;
3336
3337 ret = vmbus_sendpacket(hdev->channel, &pkt.teardown_packet.message,
3338 sizeof(struct pci_message),
3339 (unsigned long)&pkt.teardown_packet,
3340 VM_PKT_DATA_INBAND,
3341 VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3342 if (ret)
3343 return ret;
3344
3345 if (wait_for_completion_timeout(&comp_pkt.host_event, 10 * HZ) == 0)
3346 return -ETIMEDOUT;
3347
3348 return 0;
3349}
3350
3351
3352
3353
3354
3355
3356
3357static int hv_pci_remove(struct hv_device *hdev)
3358{
3359 struct hv_pcibus_device *hbus;
3360 int ret;
3361
3362 hbus = hv_get_drvdata(hdev);
3363 if (hbus->state == hv_pcibus_installed) {
3364 tasklet_disable(&hdev->channel->callback_event);
3365 hbus->state = hv_pcibus_removing;
3366 tasklet_enable(&hdev->channel->callback_event);
3367 destroy_workqueue(hbus->wq);
3368 hbus->wq = NULL;
3369
3370
3371
3372
3373
3374
3375
3376 pci_lock_rescan_remove();
3377 pci_stop_root_bus(hbus->bridge->bus);
3378 hv_pci_remove_slots(hbus);
3379 pci_remove_root_bus(hbus->bridge->bus);
3380 pci_unlock_rescan_remove();
3381 }
3382
3383 ret = hv_pci_bus_exit(hdev, false);
3384
3385 vmbus_close(hdev->channel);
3386
3387 iounmap(hbus->cfg_addr);
3388 hv_free_config_window(hbus);
3389 hv_pci_free_bridge_windows(hbus);
3390 irq_domain_remove(hbus->irq_domain);
3391 irq_domain_free_fwnode(hbus->fwnode);
3392
3393 hv_put_dom_num(hbus->bridge->domain_nr);
3394
3395 kfree(hbus);
3396 return ret;
3397}
3398
3399static int hv_pci_suspend(struct hv_device *hdev)
3400{
3401 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3402 enum hv_pcibus_state old_state;
3403 int ret;
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423 tasklet_disable(&hdev->channel->callback_event);
3424
3425
3426 old_state = hbus->state;
3427 if (hbus->state == hv_pcibus_installed)
3428 hbus->state = hv_pcibus_removing;
3429
3430 tasklet_enable(&hdev->channel->callback_event);
3431
3432 if (old_state != hv_pcibus_installed)
3433 return -EINVAL;
3434
3435 flush_workqueue(hbus->wq);
3436
3437 ret = hv_pci_bus_exit(hdev, true);
3438 if (ret)
3439 return ret;
3440
3441 vmbus_close(hdev->channel);
3442
3443 return 0;
3444}
3445
3446static int hv_pci_restore_msi_msg(struct pci_dev *pdev, void *arg)
3447{
3448 struct msi_desc *entry;
3449 struct irq_data *irq_data;
3450
3451 for_each_pci_msi_entry(entry, pdev) {
3452 irq_data = irq_get_irq_data(entry->irq);
3453 if (WARN_ON_ONCE(!irq_data))
3454 return -EINVAL;
3455
3456 hv_compose_msi_msg(irq_data, &entry->msg);
3457 }
3458
3459 return 0;
3460}
3461
3462
3463
3464
3465
3466
3467
3468
3469static void hv_pci_restore_msi_state(struct hv_pcibus_device *hbus)
3470{
3471 pci_walk_bus(hbus->bridge->bus, hv_pci_restore_msi_msg, NULL);
3472}
3473
3474static int hv_pci_resume(struct hv_device *hdev)
3475{
3476 struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3477 enum pci_protocol_version_t version[1];
3478 int ret;
3479
3480 hbus->state = hv_pcibus_init;
3481
3482 ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
3483 hv_pci_onchannelcallback, hbus);
3484 if (ret)
3485 return ret;
3486
3487
3488 version[0] = hbus->protocol_version;
3489 ret = hv_pci_protocol_negotiation(hdev, version, 1);
3490 if (ret)
3491 goto out;
3492
3493 ret = hv_pci_query_relations(hdev);
3494 if (ret)
3495 goto out;
3496
3497 ret = hv_pci_enter_d0(hdev);
3498 if (ret)
3499 goto out;
3500
3501 ret = hv_send_resources_allocated(hdev);
3502 if (ret)
3503 goto out;
3504
3505 prepopulate_bars(hbus);
3506
3507 hv_pci_restore_msi_state(hbus);
3508
3509 hbus->state = hv_pcibus_installed;
3510 return 0;
3511out:
3512 vmbus_close(hdev->channel);
3513 return ret;
3514}
3515
3516static const struct hv_vmbus_device_id hv_pci_id_table[] = {
3517
3518
3519 { HV_PCIE_GUID, },
3520 { },
3521};
3522
3523MODULE_DEVICE_TABLE(vmbus, hv_pci_id_table);
3524
3525static struct hv_driver hv_pci_drv = {
3526 .name = "hv_pci",
3527 .id_table = hv_pci_id_table,
3528 .probe = hv_pci_probe,
3529 .remove = hv_pci_remove,
3530 .suspend = hv_pci_suspend,
3531 .resume = hv_pci_resume,
3532};
3533
3534static void __exit exit_hv_pci_drv(void)
3535{
3536 vmbus_driver_unregister(&hv_pci_drv);
3537
3538 hvpci_block_ops.read_block = NULL;
3539 hvpci_block_ops.write_block = NULL;
3540 hvpci_block_ops.reg_blk_invalidate = NULL;
3541}
3542
3543static int __init init_hv_pci_drv(void)
3544{
3545 if (!hv_is_hyperv_initialized())
3546 return -ENODEV;
3547
3548
3549 set_bit(HVPCI_DOM_INVALID, hvpci_dom_map);
3550
3551
3552 hvpci_block_ops.read_block = hv_read_config_block;
3553 hvpci_block_ops.write_block = hv_write_config_block;
3554 hvpci_block_ops.reg_blk_invalidate = hv_register_block_invalidate;
3555
3556 return vmbus_driver_register(&hv_pci_drv);
3557}
3558
3559module_init(init_hv_pci_drv);
3560module_exit(exit_hv_pci_drv);
3561
3562MODULE_DESCRIPTION("Hyper-V PCI");
3563MODULE_LICENSE("GPL v2");
3564