1
2
3
4#include <linux/bitfield.h>
5#include <linux/bitops.h>
6#include <linux/clk.h>
7#include <linux/compiler.h>
8#include <linux/delay.h>
9#include <linux/init.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/log2.h>
18#include <linux/module.h>
19#include <linux/msi.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/of_pci.h>
23#include <linux/of_platform.h>
24#include <linux/pci.h>
25#include <linux/pci-ecam.h>
26#include <linux/printk.h>
27#include <linux/reset.h>
28#include <linux/sizes.h>
29#include <linux/slab.h>
30#include <linux/string.h>
31#include <linux/types.h>
32
33#include "../pci.h"
34
35
36#define BRCM_PCIE_CAP_REGS 0x00ac
37
38
39#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
40#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
41#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
42
43#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
44#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
45
46#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
47#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
48
49#define PCIE_RC_DL_MDIO_ADDR 0x1100
50#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
51#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
52
53#define PCIE_MISC_MISC_CTRL 0x4008
54#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
55#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
56#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
57
58#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
59#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
60#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
61#define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
62
63#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
64#define PCIE_MEM_WIN0_LO(win) \
65 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
66
67#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
68#define PCIE_MEM_WIN0_HI(win) \
69 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
70
71#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
72#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
73
74#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
75#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
76#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
77
78#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
79#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
80
81#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
82#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
83
84#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
85#define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
86#define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
87
88#define PCIE_MISC_PCIE_CTRL 0x4064
89#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
90#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
91
92#define PCIE_MISC_PCIE_STATUS 0x4068
93#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
94#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
95#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
96#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
97
98#define PCIE_MISC_REVISION 0x406c
99#define BRCM_PCIE_HW_REV_33 0x0303
100#define BRCM_PCIE_HW_REV_3_20 0x0320
101
102#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
103#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
104#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
105#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
106 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
107
108#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
109#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
110#define PCIE_MEM_WIN0_BASE_HI(win) \
111 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
112
113#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
114#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
115#define PCIE_MEM_WIN0_LIMIT_HI(win) \
116 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
117
118#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
119#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
120#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
121
122
123#define PCIE_INTR2_CPU_BASE 0x4300
124#define PCIE_MSI_INTR2_BASE 0x4500
125
126#define MSI_INT_STATUS 0x0
127#define MSI_INT_CLR 0x8
128#define MSI_INT_MASK_SET 0x10
129#define MSI_INT_MASK_CLR 0x14
130
131#define PCIE_EXT_CFG_DATA 0x8000
132#define PCIE_EXT_CFG_INDEX 0x9000
133
134#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
135#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
136
137#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
138#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
139#define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
140#define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
141
142
143#define BRCM_NUM_PCIE_OUT_WINS 0x4
144#define BRCM_INT_PCI_MSI_NR 32
145#define BRCM_INT_PCI_MSI_LEGACY_NR 8
146#define BRCM_INT_PCI_MSI_SHIFT 0
147
148
149#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
150#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
151
152
153#define MDIO_PORT0 0x0
154#define MDIO_DATA_MASK 0x7fffffff
155#define MDIO_PORT_MASK 0xf0000
156#define MDIO_REGAD_MASK 0xffff
157#define MDIO_CMD_MASK 0xfff00000
158#define MDIO_CMD_READ 0x1
159#define MDIO_CMD_WRITE 0x0
160#define MDIO_DATA_DONE_MASK 0x80000000
161#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
162#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
163#define SSC_REGS_ADDR 0x1100
164#define SET_ADDR_OFFSET 0x1f
165#define SSC_CNTL_OFFSET 0x2
166#define SSC_CNTL_OVRD_EN_MASK 0x8000
167#define SSC_CNTL_OVRD_VAL_MASK 0x4000
168#define SSC_STATUS_OFFSET 0x1
169#define SSC_STATUS_SSC_MASK 0x400
170#define SSC_STATUS_PLL_LOCK_MASK 0x800
171#define PCIE_BRCM_MAX_MEMC 3
172
173#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
174#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
175#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
176
177
178#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
179#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
180#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
181#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
182#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
183#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
184#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
185#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
186
187
188struct brcm_pcie;
189static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
190static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
191static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
192static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
193static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
194
195enum {
196 RGR1_SW_INIT_1,
197 EXT_CFG_INDEX,
198 EXT_CFG_DATA,
199};
200
201enum {
202 RGR1_SW_INIT_1_INIT_MASK,
203 RGR1_SW_INIT_1_INIT_SHIFT,
204};
205
206enum pcie_type {
207 GENERIC,
208 BCM4908,
209 BCM7278,
210 BCM2711,
211};
212
213struct pcie_cfg_data {
214 const int *offsets;
215 const enum pcie_type type;
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
217 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
218};
219
220static const int pcie_offsets[] = {
221 [RGR1_SW_INIT_1] = 0x9210,
222 [EXT_CFG_INDEX] = 0x9000,
223 [EXT_CFG_DATA] = 0x9004,
224};
225
226static const struct pcie_cfg_data generic_cfg = {
227 .offsets = pcie_offsets,
228 .type = GENERIC,
229 .perst_set = brcm_pcie_perst_set_generic,
230 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
231};
232
233static const struct pcie_cfg_data bcm4908_cfg = {
234 .offsets = pcie_offsets,
235 .type = BCM4908,
236 .perst_set = brcm_pcie_perst_set_4908,
237 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
238};
239
240static const int pcie_offset_bcm7278[] = {
241 [RGR1_SW_INIT_1] = 0xc010,
242 [EXT_CFG_INDEX] = 0x9000,
243 [EXT_CFG_DATA] = 0x9004,
244};
245
246static const struct pcie_cfg_data bcm7278_cfg = {
247 .offsets = pcie_offset_bcm7278,
248 .type = BCM7278,
249 .perst_set = brcm_pcie_perst_set_7278,
250 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
251};
252
253static const struct pcie_cfg_data bcm2711_cfg = {
254 .offsets = pcie_offsets,
255 .type = BCM2711,
256 .perst_set = brcm_pcie_perst_set_generic,
257 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
258};
259
260struct brcm_msi {
261 struct device *dev;
262 void __iomem *base;
263 struct device_node *np;
264 struct irq_domain *msi_domain;
265 struct irq_domain *inner_domain;
266 struct mutex lock;
267 u64 target_addr;
268 int irq;
269
270 unsigned long used;
271 bool legacy;
272
273 int legacy_shift;
274 int nr;
275
276 void __iomem *intr_base;
277};
278
279
280struct brcm_pcie {
281 struct device *dev;
282 void __iomem *base;
283 struct clk *clk;
284 struct device_node *np;
285 bool ssc;
286 int gen;
287 u64 msi_target_addr;
288 struct brcm_msi *msi;
289 const int *reg_offsets;
290 enum pcie_type type;
291 struct reset_control *rescal;
292 struct reset_control *perst_reset;
293 int num_memc;
294 u64 memc_size[PCIE_BRCM_MAX_MEMC];
295 u32 hw_rev;
296 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
297 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
298};
299
300
301
302
303
304static int brcm_pcie_encode_ibar_size(u64 size)
305{
306 int log2_in = ilog2(size);
307
308 if (log2_in >= 12 && log2_in <= 15)
309
310 return (log2_in - 12) + 0x1c;
311 else if (log2_in >= 16 && log2_in <= 35)
312
313 return log2_in - 15;
314
315 return 0;
316}
317
318static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
319{
320 u32 pkt = 0;
321
322 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
323 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
324 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
325
326 return pkt;
327}
328
329
330static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
331{
332 int tries;
333 u32 data;
334
335 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
336 base + PCIE_RC_DL_MDIO_ADDR);
337 readl(base + PCIE_RC_DL_MDIO_ADDR);
338
339 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
340 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
341 udelay(10);
342 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
343 }
344
345 *val = FIELD_GET(MDIO_DATA_MASK, data);
346 return MDIO_RD_DONE(data) ? 0 : -EIO;
347}
348
349
350static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
351 u8 regad, u16 wrdata)
352{
353 int tries;
354 u32 data;
355
356 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
357 base + PCIE_RC_DL_MDIO_ADDR);
358 readl(base + PCIE_RC_DL_MDIO_ADDR);
359 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
360
361 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
362 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
363 udelay(10);
364 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
365 }
366
367 return MDIO_WT_DONE(data) ? 0 : -EIO;
368}
369
370
371
372
373
374static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
375{
376 int pll, ssc;
377 int ret;
378 u32 tmp;
379
380 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
381 SSC_REGS_ADDR);
382 if (ret < 0)
383 return ret;
384
385 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
386 SSC_CNTL_OFFSET, &tmp);
387 if (ret < 0)
388 return ret;
389
390 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
391 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
392 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
393 SSC_CNTL_OFFSET, tmp);
394 if (ret < 0)
395 return ret;
396
397 usleep_range(1000, 2000);
398 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
399 SSC_STATUS_OFFSET, &tmp);
400 if (ret < 0)
401 return ret;
402
403 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
404 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
405
406 return ssc && pll ? 0 : -EIO;
407}
408
409
410static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
411{
412 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
413 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
414
415 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
416 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
417
418 lnkctl2 = (lnkctl2 & ~0xf) | gen;
419 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
420}
421
422static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
423 unsigned int win, u64 cpu_addr,
424 u64 pcie_addr, u64 size)
425{
426 u32 cpu_addr_mb_high, limit_addr_mb_high;
427 phys_addr_t cpu_addr_mb, limit_addr_mb;
428 int high_addr_shift;
429 u32 tmp;
430
431
432 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
433 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
434
435
436 cpu_addr_mb = cpu_addr / SZ_1M;
437 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
438
439 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
440 u32p_replace_bits(&tmp, cpu_addr_mb,
441 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
442 u32p_replace_bits(&tmp, limit_addr_mb,
443 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
444 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
445
446
447 high_addr_shift =
448 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
449
450 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
451 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
452 u32p_replace_bits(&tmp, cpu_addr_mb_high,
453 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
454 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
455
456 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
457 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
458 u32p_replace_bits(&tmp, limit_addr_mb_high,
459 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
460 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
461}
462
463static struct irq_chip brcm_msi_irq_chip = {
464 .name = "BRCM STB PCIe MSI",
465 .irq_ack = irq_chip_ack_parent,
466 .irq_mask = pci_msi_mask_irq,
467 .irq_unmask = pci_msi_unmask_irq,
468};
469
470static struct msi_domain_info brcm_msi_domain_info = {
471
472 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
473 .chip = &brcm_msi_irq_chip,
474};
475
476static void brcm_pcie_msi_isr(struct irq_desc *desc)
477{
478 struct irq_chip *chip = irq_desc_get_chip(desc);
479 unsigned long status;
480 struct brcm_msi *msi;
481 struct device *dev;
482 u32 bit;
483
484 chained_irq_enter(chip, desc);
485 msi = irq_desc_get_handler_data(desc);
486 dev = msi->dev;
487
488 status = readl(msi->intr_base + MSI_INT_STATUS);
489 status >>= msi->legacy_shift;
490
491 for_each_set_bit(bit, &status, msi->nr) {
492 int ret;
493 ret = generic_handle_domain_irq(msi->inner_domain, bit);
494 if (ret)
495 dev_dbg(dev, "unexpected MSI\n");
496 }
497
498 chained_irq_exit(chip, desc);
499}
500
501static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
502{
503 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
504
505 msg->address_lo = lower_32_bits(msi->target_addr);
506 msg->address_hi = upper_32_bits(msi->target_addr);
507 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
508}
509
510static int brcm_msi_set_affinity(struct irq_data *irq_data,
511 const struct cpumask *mask, bool force)
512{
513 return -EINVAL;
514}
515
516static void brcm_msi_ack_irq(struct irq_data *data)
517{
518 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
519 const int shift_amt = data->hwirq + msi->legacy_shift;
520
521 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
522}
523
524
525static struct irq_chip brcm_msi_bottom_irq_chip = {
526 .name = "BRCM STB MSI",
527 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
528 .irq_set_affinity = brcm_msi_set_affinity,
529 .irq_ack = brcm_msi_ack_irq,
530};
531
532static int brcm_msi_alloc(struct brcm_msi *msi)
533{
534 int hwirq;
535
536 mutex_lock(&msi->lock);
537 hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0);
538 mutex_unlock(&msi->lock);
539
540 return hwirq;
541}
542
543static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
544{
545 mutex_lock(&msi->lock);
546 bitmap_release_region(&msi->used, hwirq, 0);
547 mutex_unlock(&msi->lock);
548}
549
550static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
551 unsigned int nr_irqs, void *args)
552{
553 struct brcm_msi *msi = domain->host_data;
554 int hwirq;
555
556 hwirq = brcm_msi_alloc(msi);
557
558 if (hwirq < 0)
559 return hwirq;
560
561 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
562 &brcm_msi_bottom_irq_chip, domain->host_data,
563 handle_edge_irq, NULL, NULL);
564 return 0;
565}
566
567static void brcm_irq_domain_free(struct irq_domain *domain,
568 unsigned int virq, unsigned int nr_irqs)
569{
570 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
571 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
572
573 brcm_msi_free(msi, d->hwirq);
574}
575
576static const struct irq_domain_ops msi_domain_ops = {
577 .alloc = brcm_irq_domain_alloc,
578 .free = brcm_irq_domain_free,
579};
580
581static int brcm_allocate_domains(struct brcm_msi *msi)
582{
583 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
584 struct device *dev = msi->dev;
585
586 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
587 if (!msi->inner_domain) {
588 dev_err(dev, "failed to create IRQ domain\n");
589 return -ENOMEM;
590 }
591
592 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
593 &brcm_msi_domain_info,
594 msi->inner_domain);
595 if (!msi->msi_domain) {
596 dev_err(dev, "failed to create MSI domain\n");
597 irq_domain_remove(msi->inner_domain);
598 return -ENOMEM;
599 }
600
601 return 0;
602}
603
604static void brcm_free_domains(struct brcm_msi *msi)
605{
606 irq_domain_remove(msi->msi_domain);
607 irq_domain_remove(msi->inner_domain);
608}
609
610static void brcm_msi_remove(struct brcm_pcie *pcie)
611{
612 struct brcm_msi *msi = pcie->msi;
613
614 if (!msi)
615 return;
616 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
617 brcm_free_domains(msi);
618}
619
620static void brcm_msi_set_regs(struct brcm_msi *msi)
621{
622 u32 val = __GENMASK(31, msi->legacy_shift);
623
624 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
625 writel(val, msi->intr_base + MSI_INT_CLR);
626
627
628
629
630
631 writel(lower_32_bits(msi->target_addr) | 0x1,
632 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
633 writel(upper_32_bits(msi->target_addr),
634 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
635
636 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
637 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
638}
639
640static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
641{
642 struct brcm_msi *msi;
643 int irq, ret;
644 struct device *dev = pcie->dev;
645
646 irq = irq_of_parse_and_map(dev->of_node, 1);
647 if (irq <= 0) {
648 dev_err(dev, "cannot map MSI interrupt\n");
649 return -ENODEV;
650 }
651
652 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
653 if (!msi)
654 return -ENOMEM;
655
656 mutex_init(&msi->lock);
657 msi->dev = dev;
658 msi->base = pcie->base;
659 msi->np = pcie->np;
660 msi->target_addr = pcie->msi_target_addr;
661 msi->irq = irq;
662 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
663
664 if (msi->legacy) {
665 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
666 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
667 msi->legacy_shift = 24;
668 } else {
669 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
670 msi->nr = BRCM_INT_PCI_MSI_NR;
671 msi->legacy_shift = 0;
672 }
673
674 ret = brcm_allocate_domains(msi);
675 if (ret)
676 return ret;
677
678 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
679
680 brcm_msi_set_regs(msi);
681 pcie->msi = msi;
682
683 return 0;
684}
685
686
687static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
688{
689 void __iomem *base = pcie->base;
690 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
691
692 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
693}
694
695static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
696{
697 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
698 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
699 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
700
701 return dla && plu;
702}
703
704static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
705 int where)
706{
707 struct brcm_pcie *pcie = bus->sysdata;
708 void __iomem *base = pcie->base;
709 int idx;
710
711
712 if (pci_is_root_bus(bus))
713 return PCI_SLOT(devfn) ? NULL : base + where;
714
715
716 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
717 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
718 return base + PCIE_EXT_CFG_DATA + where;
719}
720
721static struct pci_ops brcm_pcie_ops = {
722 .map_bus = brcm_pcie_map_conf,
723 .read = pci_generic_config_read,
724 .write = pci_generic_config_write,
725};
726
727static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
728{
729 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
730 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
731
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
733 tmp = (tmp & ~mask) | ((val << shift) & mask);
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
735}
736
737static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
738{
739 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
740 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
741
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
743 tmp = (tmp & ~mask) | ((val << shift) & mask);
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
745}
746
747static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
748{
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
750 return;
751
752 if (val)
753 reset_control_assert(pcie->perst_reset);
754 else
755 reset_control_deassert(pcie->perst_reset);
756}
757
758static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
759{
760 u32 tmp;
761
762
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
764 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
766}
767
768static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
769{
770 u32 tmp;
771
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
773 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
775}
776
777static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
778 u64 *rc_bar2_size,
779 u64 *rc_bar2_offset)
780{
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
782 struct resource_entry *entry;
783 struct device *dev = pcie->dev;
784 u64 lowest_pcie_addr = ~(u64)0;
785 int ret, i = 0;
786 u64 size = 0;
787
788 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
789 u64 pcie_beg = entry->res->start - entry->offset;
790
791 size += entry->res->end - entry->res->start + 1;
792 if (pcie_beg < lowest_pcie_addr)
793 lowest_pcie_addr = pcie_beg;
794 }
795
796 if (lowest_pcie_addr == ~(u64)0) {
797 dev_err(dev, "DT node has no dma-ranges\n");
798 return -EINVAL;
799 }
800
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
802 PCIE_BRCM_MAX_MEMC);
803
804 if (ret <= 0) {
805
806 pcie->num_memc = 1;
807 pcie->memc_size[0] = 1ULL << fls64(size - 1);
808 } else {
809 pcie->num_memc = ret;
810 }
811
812
813 for (i = 0, size = 0; i < pcie->num_memc; i++)
814 size += pcie->memc_size[i];
815
816
817 *rc_bar2_offset = lowest_pcie_addr;
818
819 *rc_bar2_size = 1ULL << fls64(size - 1);
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
855 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
856 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
857 *rc_bar2_size, *rc_bar2_offset);
858 return -EINVAL;
859 }
860
861 return 0;
862}
863
864static int brcm_pcie_setup(struct brcm_pcie *pcie)
865{
866 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
867 u64 rc_bar2_offset, rc_bar2_size;
868 void __iomem *base = pcie->base;
869 struct device *dev = pcie->dev;
870 struct resource_entry *entry;
871 bool ssc_good = false;
872 struct resource *res;
873 int num_out_wins = 0;
874 u16 nlw, cls, lnksta;
875 int i, ret, memc;
876 u32 tmp, burst, aspm_support;
877
878
879 pcie->bridge_sw_init_set(pcie, 1);
880 usleep_range(100, 200);
881
882
883 pcie->bridge_sw_init_set(pcie, 0);
884
885 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
886 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
887 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
888
889 usleep_range(100, 200);
890
891
892
893
894
895
896 if (pcie->type == BCM2711)
897 burst = 0x0;
898 else if (pcie->type == BCM7278)
899 burst = 0x3;
900 else
901 burst = 0x2;
902
903
904 tmp = readl(base + PCIE_MISC_MISC_CTRL);
905 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
906 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
907 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
908 writel(tmp, base + PCIE_MISC_MISC_CTRL);
909
910 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
911 &rc_bar2_offset);
912 if (ret)
913 return ret;
914
915 tmp = lower_32_bits(rc_bar2_offset);
916 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
917 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
918 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
919 writel(upper_32_bits(rc_bar2_offset),
920 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
921
922 tmp = readl(base + PCIE_MISC_MISC_CTRL);
923 for (memc = 0; memc < pcie->num_memc; memc++) {
924 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
925
926 if (memc == 0)
927 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
928 else if (memc == 1)
929 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
930 else if (memc == 2)
931 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
932 }
933 writel(tmp, base + PCIE_MISC_MISC_CTRL);
934
935
936
937
938
939
940
941
942 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
943 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
944 else
945 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
946
947
948 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
949 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
950 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
951
952
953 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
954 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
955 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
956
957 if (pcie->gen)
958 brcm_pcie_set_gen(pcie, pcie->gen);
959
960
961 pcie->perst_set(pcie, 0);
962
963
964
965
966
967 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
968 msleep(5);
969
970 if (!brcm_pcie_link_up(pcie)) {
971 dev_err(dev, "link down\n");
972 return -ENODEV;
973 }
974
975 if (!brcm_pcie_rc_mode(pcie)) {
976 dev_err(dev, "PCIe misconfigured; is in EP mode\n");
977 return -EINVAL;
978 }
979
980 resource_list_for_each_entry(entry, &bridge->windows) {
981 res = entry->res;
982
983 if (resource_type(res) != IORESOURCE_MEM)
984 continue;
985
986 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
987 dev_err(pcie->dev, "too many outbound wins\n");
988 return -EINVAL;
989 }
990
991 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
992 res->start - entry->offset,
993 resource_size(res));
994 num_out_wins++;
995 }
996
997
998 aspm_support = PCIE_LINK_STATE_L1;
999 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1000 aspm_support |= PCIE_LINK_STATE_L0S;
1001 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1002 u32p_replace_bits(&tmp, aspm_support,
1003 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1004 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1005
1006
1007
1008
1009
1010 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1011 u32p_replace_bits(&tmp, 0x060400,
1012 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
1013 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1014
1015 if (pcie->ssc) {
1016 ret = brcm_pcie_set_ssc(pcie);
1017 if (ret == 0)
1018 ssc_good = true;
1019 else
1020 dev_err(dev, "failed attempt to enter ssc mode\n");
1021 }
1022
1023 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1024 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1025 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1026 dev_info(dev, "link up, %s x%u %s\n",
1027 pci_speed_string(pcie_link_speed[cls]), nlw,
1028 ssc_good ? "(SSC)" : "(!SSC)");
1029
1030
1031 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1032 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1033 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1034 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1035
1036
1037
1038
1039
1040 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1041 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1042 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1043
1044 return 0;
1045}
1046
1047
1048static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1049{
1050 void __iomem *base = pcie->base;
1051 int l23, i;
1052 u32 tmp;
1053
1054
1055 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1056 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1057 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1058
1059
1060 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1061 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1062 for (i = 0; i < 15 && !l23; i++) {
1063 usleep_range(2000, 2400);
1064 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1065 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1066 tmp);
1067 }
1068
1069 if (!l23)
1070 dev_err(pcie->dev, "failed to enter low-power link state\n");
1071}
1072
1073static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1074{
1075 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1076 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1077 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1078 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1079 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1080 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1081 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1082 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1083 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1084 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1085 u32 tmp, combined_mask = 0;
1086 u32 val;
1087 void __iomem *base = pcie->base;
1088 int i, ret;
1089
1090 for (i = beg; i != end; start ? i++ : i--) {
1091 val = start ? BIT_MASK(shifts[i]) : 0;
1092 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1093 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1094 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1095 usleep_range(50, 200);
1096 combined_mask |= masks[i];
1097 }
1098
1099 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1100 val = start ? combined_mask : 0;
1101
1102 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1103 if (ret)
1104 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1105
1106 return ret;
1107}
1108
1109static inline int brcm_phy_start(struct brcm_pcie *pcie)
1110{
1111 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1112}
1113
1114static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1115{
1116 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1117}
1118
1119static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1120{
1121 void __iomem *base = pcie->base;
1122 int tmp;
1123
1124 if (brcm_pcie_link_up(pcie))
1125 brcm_pcie_enter_l23(pcie);
1126
1127 pcie->perst_set(pcie, 1);
1128
1129
1130 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1131 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1132 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1133
1134
1135 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1136 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1137 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1138
1139
1140 pcie->bridge_sw_init_set(pcie, 1);
1141}
1142
1143static int brcm_pcie_suspend(struct device *dev)
1144{
1145 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1146 int ret;
1147
1148 brcm_pcie_turn_off(pcie);
1149 ret = brcm_phy_stop(pcie);
1150 reset_control_rearm(pcie->rescal);
1151 clk_disable_unprepare(pcie->clk);
1152
1153 return ret;
1154}
1155
1156static int brcm_pcie_resume(struct device *dev)
1157{
1158 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1159 void __iomem *base;
1160 u32 tmp;
1161 int ret;
1162
1163 base = pcie->base;
1164 clk_prepare_enable(pcie->clk);
1165
1166 ret = reset_control_reset(pcie->rescal);
1167 if (ret)
1168 goto err_disable_clk;
1169
1170 ret = brcm_phy_start(pcie);
1171 if (ret)
1172 goto err_reset;
1173
1174
1175 pcie->bridge_sw_init_set(pcie, 0);
1176
1177
1178 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1179 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1180 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1181
1182
1183 udelay(100);
1184
1185 ret = brcm_pcie_setup(pcie);
1186 if (ret)
1187 goto err_reset;
1188
1189 if (pcie->msi)
1190 brcm_msi_set_regs(pcie->msi);
1191
1192 return 0;
1193
1194err_reset:
1195 reset_control_rearm(pcie->rescal);
1196err_disable_clk:
1197 clk_disable_unprepare(pcie->clk);
1198 return ret;
1199}
1200
1201static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1202{
1203 brcm_msi_remove(pcie);
1204 brcm_pcie_turn_off(pcie);
1205 brcm_phy_stop(pcie);
1206 reset_control_rearm(pcie->rescal);
1207 clk_disable_unprepare(pcie->clk);
1208}
1209
1210static int brcm_pcie_remove(struct platform_device *pdev)
1211{
1212 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1213 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1214
1215 pci_stop_root_bus(bridge->bus);
1216 pci_remove_root_bus(bridge->bus);
1217 __brcm_pcie_remove(pcie);
1218
1219 return 0;
1220}
1221
1222static const struct of_device_id brcm_pcie_match[] = {
1223 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1224 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1225 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1226 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1227 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1228 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1229 {},
1230};
1231
1232static int brcm_pcie_probe(struct platform_device *pdev)
1233{
1234 struct device_node *np = pdev->dev.of_node, *msi_np;
1235 struct pci_host_bridge *bridge;
1236 const struct pcie_cfg_data *data;
1237 struct brcm_pcie *pcie;
1238 int ret;
1239
1240 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1241 if (!bridge)
1242 return -ENOMEM;
1243
1244 data = of_device_get_match_data(&pdev->dev);
1245 if (!data) {
1246 pr_err("failed to look up compatible string\n");
1247 return -EINVAL;
1248 }
1249
1250 pcie = pci_host_bridge_priv(bridge);
1251 pcie->dev = &pdev->dev;
1252 pcie->np = np;
1253 pcie->reg_offsets = data->offsets;
1254 pcie->type = data->type;
1255 pcie->perst_set = data->perst_set;
1256 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1257
1258 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1259 if (IS_ERR(pcie->base))
1260 return PTR_ERR(pcie->base);
1261
1262 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1263 if (IS_ERR(pcie->clk))
1264 return PTR_ERR(pcie->clk);
1265
1266 ret = of_pci_get_max_link_speed(np);
1267 pcie->gen = (ret < 0) ? 0 : ret;
1268
1269 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1270
1271 ret = clk_prepare_enable(pcie->clk);
1272 if (ret) {
1273 dev_err(&pdev->dev, "could not enable clock\n");
1274 return ret;
1275 }
1276 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1277 if (IS_ERR(pcie->rescal)) {
1278 clk_disable_unprepare(pcie->clk);
1279 return PTR_ERR(pcie->rescal);
1280 }
1281 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1282 if (IS_ERR(pcie->perst_reset)) {
1283 clk_disable_unprepare(pcie->clk);
1284 return PTR_ERR(pcie->perst_reset);
1285 }
1286
1287 ret = reset_control_reset(pcie->rescal);
1288 if (ret)
1289 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1290
1291 ret = brcm_phy_start(pcie);
1292 if (ret) {
1293 reset_control_rearm(pcie->rescal);
1294 clk_disable_unprepare(pcie->clk);
1295 return ret;
1296 }
1297
1298 ret = brcm_pcie_setup(pcie);
1299 if (ret)
1300 goto fail;
1301
1302 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1303 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1304 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1305 ret = -ENODEV;
1306 goto fail;
1307 }
1308
1309 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1310 if (pci_msi_enabled() && msi_np == pcie->np) {
1311 ret = brcm_pcie_enable_msi(pcie);
1312 if (ret) {
1313 dev_err(pcie->dev, "probe of internal MSI failed");
1314 goto fail;
1315 }
1316 }
1317
1318 bridge->ops = &brcm_pcie_ops;
1319 bridge->sysdata = pcie;
1320
1321 platform_set_drvdata(pdev, pcie);
1322
1323 return pci_host_probe(bridge);
1324fail:
1325 __brcm_pcie_remove(pcie);
1326 return ret;
1327}
1328
1329MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1330
1331static const struct dev_pm_ops brcm_pcie_pm_ops = {
1332 .suspend = brcm_pcie_suspend,
1333 .resume = brcm_pcie_resume,
1334};
1335
1336static struct platform_driver brcm_pcie_driver = {
1337 .probe = brcm_pcie_probe,
1338 .remove = brcm_pcie_remove,
1339 .driver = {
1340 .name = "brcm-pcie",
1341 .of_match_table = brcm_pcie_match,
1342 .pm = &brcm_pcie_pm_ops,
1343 },
1344};
1345module_platform_driver(brcm_pcie_driver);
1346
1347MODULE_LICENSE("GPL");
1348MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1349MODULE_AUTHOR("Broadcom");
1350