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10#include <linux/clk.h>
11#include <linux/irqchip/chained_irq.h>
12#include <linux/module.h>
13#include <linux/msi.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/of_pci.h>
17#include <linux/pci-ecam.h>
18#include <linux/platform_device.h>
19
20#include "../pci.h"
21
22
23#define MC_NUM_MSI_IRQS 32
24#define MC_NUM_MSI_IRQS_CODED 5
25
26
27#define MC_PCIE1_BRIDGE_ADDR 0x00008000u
28#define MC_PCIE1_CTRL_ADDR 0x0000a000u
29
30#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
31#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
32
33
34#define SEC_ERROR_CNT 0x20
35#define DED_ERROR_CNT 0x24
36#define SEC_ERROR_INT 0x28
37#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
38#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
39#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
40#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
41#define NUM_SEC_ERROR_INTS (4)
42#define SEC_ERROR_INT_MASK 0x2c
43#define DED_ERROR_INT 0x30
44#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
45#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
46#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
47#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
48#define NUM_DED_ERROR_INTS (4)
49#define DED_ERROR_INT_MASK 0x34
50#define ECC_CONTROL 0x38
51#define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
52#define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
53#define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
54#define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
55#define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
56#define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
57#define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
58#define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
59#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
60#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
61#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
62#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
63#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
64#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
65#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
66#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
67#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
68#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
69#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
70#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
71#define LTSSM_STATE 0x5c
72#define LTSSM_L0_STATE 0x10
73#define PCIE_EVENT_INT 0x14c
74#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
75#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
76#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
77#define PCIE_EVENT_INT_MASK GENMASK(2, 0)
78#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
79#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
80#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
81#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
82#define PCIE_EVENT_INT_ENB_SHIFT 16
83#define NUM_PCIE_EVENTS (3)
84
85
86#define PCIE_PCI_IDS_DW1 0x9c
87
88
89#define MC_MSI_CAP_CTRL_OFFSET 0xe0u
90#define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1)
91#define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4)
92
93#define IMASK_LOCAL 0x180
94#define DMA_END_ENGINE_0_MASK 0x00000000u
95#define DMA_END_ENGINE_0_SHIFT 0
96#define DMA_END_ENGINE_1_MASK 0x00000000u
97#define DMA_END_ENGINE_1_SHIFT 1
98#define DMA_ERROR_ENGINE_0_MASK 0x00000100u
99#define DMA_ERROR_ENGINE_0_SHIFT 8
100#define DMA_ERROR_ENGINE_1_MASK 0x00000200u
101#define DMA_ERROR_ENGINE_1_SHIFT 9
102#define A_ATR_EVT_POST_ERR_MASK 0x00010000u
103#define A_ATR_EVT_POST_ERR_SHIFT 16
104#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
105#define A_ATR_EVT_FETCH_ERR_SHIFT 17
106#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
107#define A_ATR_EVT_DISCARD_ERR_SHIFT 18
108#define A_ATR_EVT_DOORBELL_MASK 0x00000000u
109#define A_ATR_EVT_DOORBELL_SHIFT 19
110#define P_ATR_EVT_POST_ERR_MASK 0x00100000u
111#define P_ATR_EVT_POST_ERR_SHIFT 20
112#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
113#define P_ATR_EVT_FETCH_ERR_SHIFT 21
114#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
115#define P_ATR_EVT_DISCARD_ERR_SHIFT 22
116#define P_ATR_EVT_DOORBELL_MASK 0x00000000u
117#define P_ATR_EVT_DOORBELL_SHIFT 23
118#define PM_MSI_INT_INTA_MASK 0x01000000u
119#define PM_MSI_INT_INTA_SHIFT 24
120#define PM_MSI_INT_INTB_MASK 0x02000000u
121#define PM_MSI_INT_INTB_SHIFT 25
122#define PM_MSI_INT_INTC_MASK 0x04000000u
123#define PM_MSI_INT_INTC_SHIFT 26
124#define PM_MSI_INT_INTD_MASK 0x08000000u
125#define PM_MSI_INT_INTD_SHIFT 27
126#define PM_MSI_INT_INTX_MASK 0x0f000000u
127#define PM_MSI_INT_INTX_SHIFT 24
128#define PM_MSI_INT_MSI_MASK 0x10000000u
129#define PM_MSI_INT_MSI_SHIFT 28
130#define PM_MSI_INT_AER_EVT_MASK 0x20000000u
131#define PM_MSI_INT_AER_EVT_SHIFT 29
132#define PM_MSI_INT_EVENTS_MASK 0x40000000u
133#define PM_MSI_INT_EVENTS_SHIFT 30
134#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
135#define PM_MSI_INT_SYS_ERR_SHIFT 31
136#define NUM_LOCAL_EVENTS 15
137#define ISTATUS_LOCAL 0x184
138#define IMASK_HOST 0x188
139#define ISTATUS_HOST 0x18c
140#define MSI_ADDR 0x190
141#define ISTATUS_MSI 0x194
142
143
144#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
145#define ATR0_PCIE_ATR_SIZE 0x25
146#define ATR0_PCIE_ATR_SIZE_SHIFT 1
147#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
148#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
149#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
150#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
151
152
153#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
154#define ATR_SIZE_SHIFT 1
155#define ATR_IMPL_ENABLE 1
156#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
157#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
158#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
159#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
160#define PCIE_TX_RX_INTERFACE 0x00000000u
161#define PCIE_CONFIG_INTERFACE 0x00000001u
162
163#define ATR_ENTRY_SIZE 32
164
165#define EVENT_PCIE_L2_EXIT 0
166#define EVENT_PCIE_HOTRST_EXIT 1
167#define EVENT_PCIE_DLUP_EXIT 2
168#define EVENT_SEC_TX_RAM_SEC_ERR 3
169#define EVENT_SEC_RX_RAM_SEC_ERR 4
170#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5
171#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6
172#define EVENT_DED_TX_RAM_DED_ERR 7
173#define EVENT_DED_RX_RAM_DED_ERR 8
174#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9
175#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10
176#define EVENT_LOCAL_DMA_END_ENGINE_0 11
177#define EVENT_LOCAL_DMA_END_ENGINE_1 12
178#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
179#define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
180#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15
181#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16
182#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17
183#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18
184#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19
185#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20
186#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21
187#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22
188#define EVENT_LOCAL_PM_MSI_INT_INTX 23
189#define EVENT_LOCAL_PM_MSI_INT_MSI 24
190#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25
191#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26
192#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27
193#define NUM_EVENTS 28
194
195#define PCIE_EVENT_CAUSE(x, s) \
196 [EVENT_PCIE_ ## x] = { __stringify(x), s }
197
198#define SEC_ERROR_CAUSE(x, s) \
199 [EVENT_SEC_ ## x] = { __stringify(x), s }
200
201#define DED_ERROR_CAUSE(x, s) \
202 [EVENT_DED_ ## x] = { __stringify(x), s }
203
204#define LOCAL_EVENT_CAUSE(x, s) \
205 [EVENT_LOCAL_ ## x] = { __stringify(x), s }
206
207#define PCIE_EVENT(x) \
208 .base = MC_PCIE_CTRL_ADDR, \
209 .offset = PCIE_EVENT_INT, \
210 .mask_offset = PCIE_EVENT_INT, \
211 .mask_high = 1, \
212 .mask = PCIE_EVENT_INT_ ## x ## _INT, \
213 .enb_mask = PCIE_EVENT_INT_ENB_MASK
214
215#define SEC_EVENT(x) \
216 .base = MC_PCIE_CTRL_ADDR, \
217 .offset = SEC_ERROR_INT, \
218 .mask_offset = SEC_ERROR_INT_MASK, \
219 .mask = SEC_ERROR_INT_ ## x ## _INT, \
220 .mask_high = 1, \
221 .enb_mask = 0
222
223#define DED_EVENT(x) \
224 .base = MC_PCIE_CTRL_ADDR, \
225 .offset = DED_ERROR_INT, \
226 .mask_offset = DED_ERROR_INT_MASK, \
227 .mask_high = 1, \
228 .mask = DED_ERROR_INT_ ## x ## _INT, \
229 .enb_mask = 0
230
231#define LOCAL_EVENT(x) \
232 .base = MC_PCIE_BRIDGE_ADDR, \
233 .offset = ISTATUS_LOCAL, \
234 .mask_offset = IMASK_LOCAL, \
235 .mask_high = 0, \
236 .mask = x ## _MASK, \
237 .enb_mask = 0
238
239#define PCIE_EVENT_TO_EVENT_MAP(x) \
240 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x }
241
242#define SEC_ERROR_TO_EVENT_MAP(x) \
243 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x }
244
245#define DED_ERROR_TO_EVENT_MAP(x) \
246 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x }
247
248#define LOCAL_STATUS_TO_EVENT_MAP(x) \
249 { x ## _MASK, EVENT_LOCAL_ ## x }
250
251struct event_map {
252 u32 reg_mask;
253 u32 event_bit;
254};
255
256struct mc_msi {
257 struct mutex lock;
258 struct irq_domain *msi_domain;
259 struct irq_domain *dev_domain;
260 u32 num_vectors;
261 u64 vector_phy;
262 DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);
263};
264
265struct mc_port {
266 void __iomem *axi_base_addr;
267 struct device *dev;
268 struct irq_domain *intx_domain;
269 struct irq_domain *event_domain;
270 raw_spinlock_t lock;
271 struct mc_msi msi;
272};
273
274struct cause {
275 const char *sym;
276 const char *str;
277};
278
279static const struct cause event_cause[NUM_EVENTS] = {
280 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"),
281 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"),
282 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"),
283 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"),
284 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"),
285 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"),
286 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"),
287 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"),
288 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"),
289 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"),
290 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"),
291 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
292 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
293 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
294 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
295 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
296 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
297 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
298 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
299 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"),
300 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"),
301 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"),
302};
303
304static struct event_map pcie_event_to_event[] = {
305 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT),
306 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT),
307 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT),
308};
309
310static struct event_map sec_error_to_event[] = {
311 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR),
312 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR),
313 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR),
314 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR),
315};
316
317static struct event_map ded_error_to_event[] = {
318 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR),
319 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR),
320 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR),
321 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR),
322};
323
324static struct event_map local_status_to_event[] = {
325 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0),
326 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1),
327 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0),
328 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1),
329 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR),
330 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR),
331 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR),
332 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL),
333 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR),
334 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR),
335 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR),
336 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL),
337 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX),
338 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI),
339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT),
340 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS),
341 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR),
342};
343
344static struct {
345 u32 base;
346 u32 offset;
347 u32 mask;
348 u32 shift;
349 u32 enb_mask;
350 u32 mask_high;
351 u32 mask_offset;
352} event_descs[] = {
353 { PCIE_EVENT(L2_EXIT) },
354 { PCIE_EVENT(HOTRST_EXIT) },
355 { PCIE_EVENT(DLUP_EXIT) },
356 { SEC_EVENT(TX_RAM_SEC_ERR) },
357 { SEC_EVENT(RX_RAM_SEC_ERR) },
358 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) },
359 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) },
360 { DED_EVENT(TX_RAM_DED_ERR) },
361 { DED_EVENT(RX_RAM_DED_ERR) },
362 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) },
363 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) },
364 { LOCAL_EVENT(DMA_END_ENGINE_0) },
365 { LOCAL_EVENT(DMA_END_ENGINE_1) },
366 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) },
367 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) },
368 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) },
369 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) },
370 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) },
371 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) },
372 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) },
373 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) },
374 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) },
375 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) },
376 { LOCAL_EVENT(PM_MSI_INT_INTX) },
377 { LOCAL_EVENT(PM_MSI_INT_MSI) },
378 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) },
379 { LOCAL_EVENT(PM_MSI_INT_EVENTS) },
380 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) },
381};
382
383static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
384
385static void mc_pcie_enable_msi(struct mc_port *port, void __iomem *base)
386{
387 struct mc_msi *msi = &port->msi;
388 u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;
389 u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);
390
391 msg_ctrl |= PCI_MSI_FLAGS_ENABLE;
392 msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;
393 msg_ctrl |= MC_MSI_MAX_Q_AVAIL;
394 msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
395 msg_ctrl |= MC_MSI_Q_SIZE;
396 msg_ctrl |= PCI_MSI_FLAGS_64BIT;
397
398 writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
399
400 writel_relaxed(lower_32_bits(msi->vector_phy),
401 base + cap_offset + PCI_MSI_ADDRESS_LO);
402 writel_relaxed(upper_32_bits(msi->vector_phy),
403 base + cap_offset + PCI_MSI_ADDRESS_HI);
404}
405
406static void mc_handle_msi(struct irq_desc *desc)
407{
408 struct mc_port *port = irq_desc_get_handler_data(desc);
409 struct device *dev = port->dev;
410 struct mc_msi *msi = &port->msi;
411 void __iomem *bridge_base_addr =
412 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
413 unsigned long status;
414 u32 bit;
415 int ret;
416
417 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
418 if (status & PM_MSI_INT_MSI_MASK) {
419 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
420 for_each_set_bit(bit, &status, msi->num_vectors) {
421 ret = generic_handle_domain_irq(msi->dev_domain, bit);
422 if (ret)
423 dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
424 bit);
425 }
426 }
427}
428
429static void mc_msi_bottom_irq_ack(struct irq_data *data)
430{
431 struct mc_port *port = irq_data_get_irq_chip_data(data);
432 void __iomem *bridge_base_addr =
433 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
434 u32 bitpos = data->hwirq;
435 unsigned long status;
436
437 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
438 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
439 if (!status)
440 writel_relaxed(BIT(PM_MSI_INT_MSI_SHIFT),
441 bridge_base_addr + ISTATUS_LOCAL);
442}
443
444static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
445{
446 struct mc_port *port = irq_data_get_irq_chip_data(data);
447 phys_addr_t addr = port->msi.vector_phy;
448
449 msg->address_lo = lower_32_bits(addr);
450 msg->address_hi = upper_32_bits(addr);
451 msg->data = data->hwirq;
452
453 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n",
454 (int)data->hwirq, msg->address_hi, msg->address_lo);
455}
456
457static int mc_msi_set_affinity(struct irq_data *irq_data,
458 const struct cpumask *mask, bool force)
459{
460 return -EINVAL;
461}
462
463static struct irq_chip mc_msi_bottom_irq_chip = {
464 .name = "Microchip MSI",
465 .irq_ack = mc_msi_bottom_irq_ack,
466 .irq_compose_msi_msg = mc_compose_msi_msg,
467 .irq_set_affinity = mc_msi_set_affinity,
468};
469
470static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
471 unsigned int nr_irqs, void *args)
472{
473 struct mc_port *port = domain->host_data;
474 struct mc_msi *msi = &port->msi;
475 void __iomem *bridge_base_addr =
476 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
477 unsigned long bit;
478 u32 val;
479
480 mutex_lock(&msi->lock);
481 bit = find_first_zero_bit(msi->used, msi->num_vectors);
482 if (bit >= msi->num_vectors) {
483 mutex_unlock(&msi->lock);
484 return -ENOSPC;
485 }
486
487 set_bit(bit, msi->used);
488
489 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,
490 domain->host_data, handle_edge_irq, NULL, NULL);
491
492
493 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
494 val |= PM_MSI_INT_MSI_MASK;
495 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
496
497 mutex_unlock(&msi->lock);
498
499 return 0;
500}
501
502static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq,
503 unsigned int nr_irqs)
504{
505 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
506 struct mc_port *port = irq_data_get_irq_chip_data(d);
507 struct mc_msi *msi = &port->msi;
508
509 mutex_lock(&msi->lock);
510
511 if (test_bit(d->hwirq, msi->used))
512 __clear_bit(d->hwirq, msi->used);
513 else
514 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq);
515
516 mutex_unlock(&msi->lock);
517}
518
519static const struct irq_domain_ops msi_domain_ops = {
520 .alloc = mc_irq_msi_domain_alloc,
521 .free = mc_irq_msi_domain_free,
522};
523
524static struct irq_chip mc_msi_irq_chip = {
525 .name = "Microchip PCIe MSI",
526 .irq_ack = irq_chip_ack_parent,
527 .irq_mask = pci_msi_mask_irq,
528 .irq_unmask = pci_msi_unmask_irq,
529};
530
531static struct msi_domain_info mc_msi_domain_info = {
532 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
533 MSI_FLAG_PCI_MSIX),
534 .chip = &mc_msi_irq_chip,
535};
536
537static int mc_allocate_msi_domains(struct mc_port *port)
538{
539 struct device *dev = port->dev;
540 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
541 struct mc_msi *msi = &port->msi;
542
543 mutex_init(&port->msi.lock);
544
545 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors,
546 &msi_domain_ops, port);
547 if (!msi->dev_domain) {
548 dev_err(dev, "failed to create IRQ domain\n");
549 return -ENOMEM;
550 }
551
552 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info,
553 msi->dev_domain);
554 if (!msi->msi_domain) {
555 dev_err(dev, "failed to create MSI domain\n");
556 irq_domain_remove(msi->dev_domain);
557 return -ENOMEM;
558 }
559
560 return 0;
561}
562
563static void mc_handle_intx(struct irq_desc *desc)
564{
565 struct mc_port *port = irq_desc_get_handler_data(desc);
566 struct device *dev = port->dev;
567 void __iomem *bridge_base_addr =
568 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
569 unsigned long status;
570 u32 bit;
571 int ret;
572
573 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
574 if (status & PM_MSI_INT_INTX_MASK) {
575 status &= PM_MSI_INT_INTX_MASK;
576 status >>= PM_MSI_INT_INTX_SHIFT;
577 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
578 ret = generic_handle_domain_irq(port->intx_domain, bit);
579 if (ret)
580 dev_err_ratelimited(dev, "bad INTx IRQ %d\n",
581 bit);
582 }
583 }
584}
585
586static void mc_ack_intx_irq(struct irq_data *data)
587{
588 struct mc_port *port = irq_data_get_irq_chip_data(data);
589 void __iomem *bridge_base_addr =
590 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
591 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
592
593 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
594}
595
596static void mc_mask_intx_irq(struct irq_data *data)
597{
598 struct mc_port *port = irq_data_get_irq_chip_data(data);
599 void __iomem *bridge_base_addr =
600 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
601 unsigned long flags;
602 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
603 u32 val;
604
605 raw_spin_lock_irqsave(&port->lock, flags);
606 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
607 val &= ~mask;
608 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
609 raw_spin_unlock_irqrestore(&port->lock, flags);
610}
611
612static void mc_unmask_intx_irq(struct irq_data *data)
613{
614 struct mc_port *port = irq_data_get_irq_chip_data(data);
615 void __iomem *bridge_base_addr =
616 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
617 unsigned long flags;
618 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
619 u32 val;
620
621 raw_spin_lock_irqsave(&port->lock, flags);
622 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
623 val |= mask;
624 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
625 raw_spin_unlock_irqrestore(&port->lock, flags);
626}
627
628static struct irq_chip mc_intx_irq_chip = {
629 .name = "Microchip PCIe INTx",
630 .irq_ack = mc_ack_intx_irq,
631 .irq_mask = mc_mask_intx_irq,
632 .irq_unmask = mc_unmask_intx_irq,
633};
634
635static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
636 irq_hw_number_t hwirq)
637{
638 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq);
639 irq_set_chip_data(irq, domain->host_data);
640
641 return 0;
642}
643
644static const struct irq_domain_ops intx_domain_ops = {
645 .map = mc_pcie_intx_map,
646};
647
648static inline u32 reg_to_event(u32 reg, struct event_map field)
649{
650 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
651}
652
653static u32 pcie_events(void __iomem *addr)
654{
655 u32 reg = readl_relaxed(addr);
656 u32 val = 0;
657 int i;
658
659 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++)
660 val |= reg_to_event(reg, pcie_event_to_event[i]);
661
662 return val;
663}
664
665static u32 sec_errors(void __iomem *addr)
666{
667 u32 reg = readl_relaxed(addr);
668 u32 val = 0;
669 int i;
670
671 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++)
672 val |= reg_to_event(reg, sec_error_to_event[i]);
673
674 return val;
675}
676
677static u32 ded_errors(void __iomem *addr)
678{
679 u32 reg = readl_relaxed(addr);
680 u32 val = 0;
681 int i;
682
683 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++)
684 val |= reg_to_event(reg, ded_error_to_event[i]);
685
686 return val;
687}
688
689static u32 local_events(void __iomem *addr)
690{
691 u32 reg = readl_relaxed(addr);
692 u32 val = 0;
693 int i;
694
695 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++)
696 val |= reg_to_event(reg, local_status_to_event[i]);
697
698 return val;
699}
700
701static u32 get_events(struct mc_port *port)
702{
703 void __iomem *bridge_base_addr =
704 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
705 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
706 u32 events = 0;
707
708 events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);
709 events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);
710 events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);
711 events |= local_events(bridge_base_addr + ISTATUS_LOCAL);
712
713 return events;
714}
715
716static irqreturn_t mc_event_handler(int irq, void *dev_id)
717{
718 struct mc_port *port = dev_id;
719 struct device *dev = port->dev;
720 struct irq_data *data;
721
722 data = irq_domain_get_irq_data(port->event_domain, irq);
723
724 if (event_cause[data->hwirq].str)
725 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);
726 else
727 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);
728
729 return IRQ_HANDLED;
730}
731
732static void mc_handle_event(struct irq_desc *desc)
733{
734 struct mc_port *port = irq_desc_get_handler_data(desc);
735 unsigned long events;
736 u32 bit;
737 struct irq_chip *chip = irq_desc_get_chip(desc);
738
739 chained_irq_enter(chip, desc);
740
741 events = get_events(port);
742
743 for_each_set_bit(bit, &events, NUM_EVENTS)
744 generic_handle_domain_irq(port->event_domain, bit);
745
746 chained_irq_exit(chip, desc);
747}
748
749static void mc_ack_event_irq(struct irq_data *data)
750{
751 struct mc_port *port = irq_data_get_irq_chip_data(data);
752 u32 event = data->hwirq;
753 void __iomem *addr;
754 u32 mask;
755
756 addr = port->axi_base_addr + event_descs[event].base +
757 event_descs[event].offset;
758 mask = event_descs[event].mask;
759 mask |= event_descs[event].enb_mask;
760
761 writel_relaxed(mask, addr);
762}
763
764static void mc_mask_event_irq(struct irq_data *data)
765{
766 struct mc_port *port = irq_data_get_irq_chip_data(data);
767 u32 event = data->hwirq;
768 void __iomem *addr;
769 u32 mask;
770 u32 val;
771
772 addr = port->axi_base_addr + event_descs[event].base +
773 event_descs[event].mask_offset;
774 mask = event_descs[event].mask;
775 if (event_descs[event].enb_mask) {
776 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
777 mask &= PCIE_EVENT_INT_ENB_MASK;
778 }
779
780 if (!event_descs[event].mask_high)
781 mask = ~mask;
782
783 raw_spin_lock(&port->lock);
784 val = readl_relaxed(addr);
785 if (event_descs[event].mask_high)
786 val |= mask;
787 else
788 val &= mask;
789
790 writel_relaxed(val, addr);
791 raw_spin_unlock(&port->lock);
792}
793
794static void mc_unmask_event_irq(struct irq_data *data)
795{
796 struct mc_port *port = irq_data_get_irq_chip_data(data);
797 u32 event = data->hwirq;
798 void __iomem *addr;
799 u32 mask;
800 u32 val;
801
802 addr = port->axi_base_addr + event_descs[event].base +
803 event_descs[event].mask_offset;
804 mask = event_descs[event].mask;
805
806 if (event_descs[event].enb_mask)
807 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
808
809 if (event_descs[event].mask_high)
810 mask = ~mask;
811
812 if (event_descs[event].enb_mask)
813 mask &= PCIE_EVENT_INT_ENB_MASK;
814
815 raw_spin_lock(&port->lock);
816 val = readl_relaxed(addr);
817 if (event_descs[event].mask_high)
818 val &= mask;
819 else
820 val |= mask;
821 writel_relaxed(val, addr);
822 raw_spin_unlock(&port->lock);
823}
824
825static struct irq_chip mc_event_irq_chip = {
826 .name = "Microchip PCIe EVENT",
827 .irq_ack = mc_ack_event_irq,
828 .irq_mask = mc_mask_event_irq,
829 .irq_unmask = mc_unmask_event_irq,
830};
831
832static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq,
833 irq_hw_number_t hwirq)
834{
835 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
836 irq_set_chip_data(irq, domain->host_data);
837
838 return 0;
839}
840
841static const struct irq_domain_ops event_domain_ops = {
842 .map = mc_pcie_event_map,
843};
844
845static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id)
846{
847 struct clk *clk;
848 int ret;
849
850 clk = devm_clk_get_optional(dev, id);
851 if (IS_ERR(clk))
852 return clk;
853 if (!clk)
854 return clk;
855
856 ret = clk_prepare_enable(clk);
857 if (ret)
858 return ERR_PTR(ret);
859
860 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare,
861 clk);
862
863 return clk;
864}
865
866static int mc_pcie_init_clks(struct device *dev)
867{
868 int i;
869 struct clk *fic;
870
871
872
873
874
875 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) {
876 fic = mc_pcie_init_clk(dev, poss_clks[i]);
877 if (IS_ERR(fic))
878 return PTR_ERR(fic);
879 }
880
881 return 0;
882}
883
884static int mc_pcie_init_irq_domains(struct mc_port *port)
885{
886 struct device *dev = port->dev;
887 struct device_node *node = dev->of_node;
888 struct device_node *pcie_intc_node;
889
890
891 pcie_intc_node = of_get_next_child(node, NULL);
892 if (!pcie_intc_node) {
893 dev_err(dev, "failed to find PCIe Intc node\n");
894 return -EINVAL;
895 }
896
897 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS,
898 &event_domain_ops, port);
899 if (!port->event_domain) {
900 dev_err(dev, "failed to get event domain\n");
901 return -ENOMEM;
902 }
903
904 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS);
905
906 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
907 &intx_domain_ops, port);
908 if (!port->intx_domain) {
909 dev_err(dev, "failed to get an INTx IRQ domain\n");
910 return -ENOMEM;
911 }
912
913 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
914
915 of_node_put(pcie_intc_node);
916 raw_spin_lock_init(&port->lock);
917
918 return mc_allocate_msi_domains(port);
919}
920
921static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
922 phys_addr_t axi_addr, phys_addr_t pci_addr,
923 size_t size)
924{
925 u32 atr_sz = ilog2(size) - 1;
926 u32 val;
927
928 if (index == 0)
929 val = PCIE_CONFIG_INTERFACE;
930 else
931 val = PCIE_TX_RX_INTERFACE;
932
933 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
934 ATR0_AXI4_SLV0_TRSL_PARAM);
935
936 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
937 ATR_IMPL_ENABLE;
938 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
939 ATR0_AXI4_SLV0_SRCADDR_PARAM);
940
941 val = upper_32_bits(axi_addr);
942 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
943 ATR0_AXI4_SLV0_SRC_ADDR);
944
945 val = lower_32_bits(pci_addr);
946 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
947 ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
948
949 val = upper_32_bits(pci_addr);
950 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
951 ATR0_AXI4_SLV0_TRSL_ADDR_UDW);
952
953 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
954 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
955 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
956 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
957}
958
959static int mc_pcie_setup_windows(struct platform_device *pdev,
960 struct mc_port *port)
961{
962 void __iomem *bridge_base_addr =
963 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
964 struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
965 struct resource_entry *entry;
966 u64 pci_addr;
967 u32 index = 1;
968
969 resource_list_for_each_entry(entry, &bridge->windows) {
970 if (resource_type(entry->res) == IORESOURCE_MEM) {
971 pci_addr = entry->res->start - entry->offset;
972 mc_pcie_setup_window(bridge_base_addr, index,
973 entry->res->start, pci_addr,
974 resource_size(entry->res));
975 index++;
976 }
977 }
978
979 return 0;
980}
981
982static int mc_platform_init(struct pci_config_window *cfg)
983{
984 struct device *dev = cfg->parent;
985 struct platform_device *pdev = to_platform_device(dev);
986 struct mc_port *port;
987 void __iomem *bridge_base_addr;
988 void __iomem *ctrl_base_addr;
989 int ret;
990 int irq;
991 int i, intx_irq, msi_irq, event_irq;
992 u32 val;
993 int err;
994
995 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
996 if (!port)
997 return -ENOMEM;
998 port->dev = dev;
999
1000 ret = mc_pcie_init_clks(dev);
1001 if (ret) {
1002 dev_err(dev, "failed to get clock resources, error %d\n", ret);
1003 return -ENODEV;
1004 }
1005
1006 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
1007 if (IS_ERR(port->axi_base_addr))
1008 return PTR_ERR(port->axi_base_addr);
1009
1010 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
1011 ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
1012
1013 port->msi.vector_phy = MSI_ADDR;
1014 port->msi.num_vectors = MC_NUM_MSI_IRQS;
1015 ret = mc_pcie_init_irq_domains(port);
1016 if (ret) {
1017 dev_err(dev, "failed creating IRQ domains\n");
1018 return ret;
1019 }
1020
1021 irq = platform_get_irq(pdev, 0);
1022 if (irq < 0)
1023 return -ENODEV;
1024
1025 for (i = 0; i < NUM_EVENTS; i++) {
1026 event_irq = irq_create_mapping(port->event_domain, i);
1027 if (!event_irq) {
1028 dev_err(dev, "failed to map hwirq %d\n", i);
1029 return -ENXIO;
1030 }
1031
1032 err = devm_request_irq(dev, event_irq, mc_event_handler,
1033 0, event_cause[i].sym, port);
1034 if (err) {
1035 dev_err(dev, "failed to request IRQ %d\n", event_irq);
1036 return err;
1037 }
1038 }
1039
1040 intx_irq = irq_create_mapping(port->event_domain,
1041 EVENT_LOCAL_PM_MSI_INT_INTX);
1042 if (!intx_irq) {
1043 dev_err(dev, "failed to map INTx interrupt\n");
1044 return -ENXIO;
1045 }
1046
1047
1048 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port);
1049
1050 msi_irq = irq_create_mapping(port->event_domain,
1051 EVENT_LOCAL_PM_MSI_INT_MSI);
1052 if (!msi_irq)
1053 return -ENXIO;
1054
1055
1056 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port);
1057
1058
1059 irq_set_chained_handler_and_data(irq, mc_handle_event, port);
1060
1061
1062 mc_pcie_enable_msi(port, cfg->win);
1063
1064 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
1065 val |= PM_MSI_INT_INTX_MASK;
1066 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
1067
1068 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
1069
1070 val = PCIE_EVENT_INT_L2_EXIT_INT |
1071 PCIE_EVENT_INT_HOTRST_EXIT_INT |
1072 PCIE_EVENT_INT_DLUP_EXIT_INT;
1073 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
1074
1075 val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT |
1076 SEC_ERROR_INT_RX_RAM_SEC_ERR_INT |
1077 SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT |
1078 SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
1079 writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
1080 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
1081 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
1082
1083 val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
1084 DED_ERROR_INT_RX_RAM_DED_ERR_INT |
1085 DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |
1086 DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
1087 writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
1088 writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
1089 writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
1090
1091 writel_relaxed(0, bridge_base_addr + IMASK_HOST);
1092 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
1093
1094
1095 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
1096 cfg->res.start, resource_size(&cfg->res));
1097
1098 return mc_pcie_setup_windows(pdev, port);
1099}
1100
1101static const struct pci_ecam_ops mc_ecam_ops = {
1102 .init = mc_platform_init,
1103 .pci_ops = {
1104 .map_bus = pci_ecam_map_bus,
1105 .read = pci_generic_config_read,
1106 .write = pci_generic_config_write,
1107 }
1108};
1109
1110static const struct of_device_id mc_pcie_of_match[] = {
1111 {
1112 .compatible = "microchip,pcie-host-1.0",
1113 .data = &mc_ecam_ops,
1114 },
1115 {},
1116};
1117
1118MODULE_DEVICE_TABLE(of, mc_pcie_of_match)
1119
1120static struct platform_driver mc_pcie_driver = {
1121 .probe = pci_host_common_probe,
1122 .driver = {
1123 .name = "microchip-pcie",
1124 .of_match_table = mc_pcie_of_match,
1125 .suppress_bind_attrs = true,
1126 },
1127};
1128
1129builtin_platform_driver(mc_pcie_driver);
1130MODULE_LICENSE("GPL");
1131MODULE_DESCRIPTION("Microchip PCIe host controller driver");
1132MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
1133