LXR linux/drivers/pci/pci-bridge-emul.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2018 Marvell
   4 *
   5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
   6 *
   7 * This file helps PCI controller drivers implement a fake root port
   8 * PCI bridge when the HW doesn't provide such a root port PCI
   9 * bridge.
  10 *
  11 * It emulates a PCI bridge by providing a fake PCI configuration
  12 * space (and optionally a PCIe capability configuration space) in
  13 * memory. By default the read/write operations simply read and update
  14 * this fake configuration space in memory. However, PCI controller
  15 * drivers can provide through the 'struct pci_sw_bridge_ops'
  16 * structure a set of operations to override or complement this
  17 * default behavior.
  18 */
  19
  20#include <linux/pci.h>
  21#include "pci-bridge-emul.h"
  22
  23#define PCI_BRIDGE_CONF_END     PCI_STD_HEADER_SIZEOF
  24#define PCI_CAP_PCIE_SIZEOF     (PCI_EXP_SLTSTA2 + 2)
  25#define PCI_CAP_PCIE_START      PCI_BRIDGE_CONF_END
  26#define PCI_CAP_PCIE_END        (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
  27
  28/**
  29 * struct pci_bridge_reg_behavior - register bits behaviors
  30 * @ro:         Read-Only bits
  31 * @rw:         Read-Write bits
  32 * @w1c:        Write-1-to-Clear bits
  33 *
  34 * Reads and Writes will be filtered by specified behavior. All other bits not
  35 * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
  36 * "Reserved register fields must be read only and must return 0 (all 0's for
  37 * multi-bit fields) when read".
  38 */
  39struct pci_bridge_reg_behavior {
  40        /* Read-only bits */
  41        u32 ro;
  42
  43        /* Read-write bits */
  44        u32 rw;
  45
  46        /* Write-1-to-clear bits */
  47        u32 w1c;
  48};
  49
  50static const
  51struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
  52        [PCI_VENDOR_ID / 4] = { .ro = ~0 },
  53        [PCI_COMMAND / 4] = {
  54                .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  55                       PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
  56                       PCI_COMMAND_SERR),
  57                .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
  58                        PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
  59                        PCI_COMMAND_FAST_BACK) |
  60                       (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
  61                        PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
  62                .w1c = PCI_STATUS_ERROR_BITS << 16,
  63        },
  64        [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
  65
  66        /*
  67         * Cache Line Size register: implement as read-only, we do not
  68         * pretend implementing "Memory Write and Invalidate"
  69         * transactions"
  70         *
  71         * Latency Timer Register: implemented as read-only, as "A
  72         * bridge that is not capable of a burst transfer of more than
  73         * two data phases on its primary interface is permitted to
  74         * hardwire the Latency Timer to a value of 16 or less"
  75         *
  76         * Header Type: always read-only
  77         *
  78         * BIST register: implemented as read-only, as "A bridge that
  79         * does not support BIST must implement this register as a
  80         * read-only register that returns 0 when read"
  81         */
  82        [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
  83
  84        /*
  85         * Base Address registers not used must be implemented as
  86         * read-only registers that return 0 when read.
  87         */
  88        [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
  89        [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
  90
  91        [PCI_PRIMARY_BUS / 4] = {
  92                /* Primary, secondary and subordinate bus are RW */
  93                .rw = GENMASK(24, 0),
  94                /* Secondary latency is read-only */
  95                .ro = GENMASK(31, 24),
  96        },
  97
  98        [PCI_IO_BASE / 4] = {
  99                /* The high four bits of I/O base/limit are RW */
 100                .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
 101
 102                /* The low four bits of I/O base/limit are RO */
 103                .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
 104                         PCI_STATUS_DEVSEL_MASK) << 16) |
 105                       GENMASK(11, 8) | GENMASK(3, 0)),
 106
 107                .w1c = PCI_STATUS_ERROR_BITS << 16,
 108        },
 109
 110        [PCI_MEMORY_BASE / 4] = {
 111                /* The high 12-bits of mem base/limit are RW */
 112                .rw = GENMASK(31, 20) | GENMASK(15, 4),
 113
 114                /* The low four bits of mem base/limit are RO */
 115                .ro = GENMASK(19, 16) | GENMASK(3, 0),
 116        },
 117
 118        [PCI_PREF_MEMORY_BASE / 4] = {
 119                /* The high 12-bits of pref mem base/limit are RW */
 120                .rw = GENMASK(31, 20) | GENMASK(15, 4),
 121
 122                /* The low four bits of pref mem base/limit are RO */
 123                .ro = GENMASK(19, 16) | GENMASK(3, 0),
 124        },
 125
 126        [PCI_PREF_BASE_UPPER32 / 4] = {
 127                .rw = ~0,
 128        },
 129
 130        [PCI_PREF_LIMIT_UPPER32 / 4] = {
 131                .rw = ~0,
 132        },
 133
 134        [PCI_IO_BASE_UPPER16 / 4] = {
 135                .rw = ~0,
 136        },
 137
 138        [PCI_CAPABILITY_LIST / 4] = {
 139                .ro = GENMASK(7, 0),
 140        },
 141
 142        [PCI_ROM_ADDRESS1 / 4] = {
 143                .rw = GENMASK(31, 11) | BIT(0),
 144        },
 145
 146        /*
 147         * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
 148         * are RO, and bridge control (31:16) are a mix of RW, RO,
 149         * reserved and W1C bits
 150         */
 151        [PCI_INTERRUPT_LINE / 4] = {
 152                /* Interrupt line is RW */
 153                .rw = (GENMASK(7, 0) |
 154                       ((PCI_BRIDGE_CTL_PARITY |
 155                         PCI_BRIDGE_CTL_SERR |
 156                         PCI_BRIDGE_CTL_ISA |
 157                         PCI_BRIDGE_CTL_VGA |
 158                         PCI_BRIDGE_CTL_MASTER_ABORT |
 159                         PCI_BRIDGE_CTL_BUS_RESET |
 160                         BIT(8) | BIT(9) | BIT(11)) << 16)),
 161
 162                /* Interrupt pin is RO */
 163                .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
 164
 165                .w1c = BIT(10) << 16,
 166        },
 167};
 168
 169static const
 170struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
 171        [PCI_CAP_LIST_ID / 4] = {
 172                /*
 173                 * Capability ID, Next Capability Pointer and
 174                 * Capabilities register are all read-only.
 175                 */
 176                .ro = ~0,
 177        },
 178
 179        [PCI_EXP_DEVCAP / 4] = {
 180                .ro = ~0,
 181        },
 182
 183        [PCI_EXP_DEVCTL / 4] = {
 184                /* Device control register is RW */
 185                .rw = GENMASK(15, 0),
 186
 187                /*
 188                 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
 189                 * the rest is reserved
 190                 */
 191                .w1c = (BIT(6) | GENMASK(3, 0)) << 16,
 192                .ro = GENMASK(5, 4) << 16,
 193        },
 194
 195        [PCI_EXP_LNKCAP / 4] = {
 196                /* All bits are RO, except bit 23 which is reserved */
 197                .ro = lower_32_bits(~BIT(23)),
 198        },
 199
 200        [PCI_EXP_LNKCTL / 4] = {
 201                /*
 202                 * Link control has bits [15:14], [11:3] and [1:0] RW, the
 203                 * rest is reserved.
 204                 *
 205                 * Link status has bits [13:0] RO, and bits [15:14]
 206                 * W1C.
 207                 */
 208                .rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
 209                .ro = GENMASK(13, 0) << 16,
 210                .w1c = GENMASK(15, 14) << 16,
 211        },
 212
 213        [PCI_EXP_SLTCAP / 4] = {
 214                .ro = ~0,
 215        },
 216
 217        [PCI_EXP_SLTCTL / 4] = {
 218                /*
 219                 * Slot control has bits [14:0] RW, the rest is
 220                 * reserved.
 221                 *
 222                 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
 223                 * rest is reserved.
 224                 */
 225                .rw = GENMASK(14, 0),
 226                .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 227                        PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 228                        PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
 229                .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
 230                       PCI_EXP_SLTSTA_EIS) << 16,
 231        },
 232
 233        [PCI_EXP_RTCTL / 4] = {
 234                /*
 235                 * Root control has bits [4:0] RW, the rest is
 236                 * reserved.
 237                 *
 238                 * Root capabilities has bit 0 RO, the rest is reserved.
 239                 */
 240                .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 241                       PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
 242                       PCI_EXP_RTCTL_CRSSVE),
 243                .ro = PCI_EXP_RTCAP_CRSVIS << 16,
 244        },
 245
 246        [PCI_EXP_RTSTA / 4] = {
 247                /*
 248                 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
 249                 * is reserved.
 250                 */
 251                .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
 252                .w1c = PCI_EXP_RTSTA_PME,
 253        },
 254};
 255
 256/*
 257 * Initialize a pci_bridge_emul structure to represent a fake PCI
 258 * bridge configuration space. The caller needs to have initialized
 259 * the PCI configuration space with whatever values make sense
 260 * (typically at least vendor, device, revision), the ->ops pointer,
 261 * and optionally ->data and ->has_pcie.
 262 */
 263int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
 264                         unsigned int flags)
 265{
 266        BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
 267
 268        bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
 269        bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
 270        bridge->conf.cache_line_size = 0x10;
 271        bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
 272        bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
 273                                            sizeof(pci_regs_behavior),
 274                                            GFP_KERNEL);
 275        if (!bridge->pci_regs_behavior)
 276                return -ENOMEM;
 277
 278        if (bridge->has_pcie) {
 279                bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
 280                bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
 281                /* Set PCIe v2, root port, slot support */
 282                bridge->pcie_conf.cap =
 283                        cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
 284                                    PCI_EXP_FLAGS_SLOT);
 285                bridge->pcie_cap_regs_behavior =
 286                        kmemdup(pcie_cap_regs_behavior,
 287                                sizeof(pcie_cap_regs_behavior),
 288                                GFP_KERNEL);
 289                if (!bridge->pcie_cap_regs_behavior) {
 290                        kfree(bridge->pci_regs_behavior);
 291                        return -ENOMEM;
 292                }
 293        }
 294
 295        if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
 296                bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
 297                bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
 298        }
 299
 300        return 0;
 301}
 302EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
 303
 304/*
 305 * Cleanup a pci_bridge_emul structure that was previously initialized
 306 * using pci_bridge_emul_init().
 307 */
 308void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
 309{
 310        if (bridge->has_pcie)
 311                kfree(bridge->pcie_cap_regs_behavior);
 312        kfree(bridge->pci_regs_behavior);
 313}
 314EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
 315
 316/*
 317 * Should be called by the PCI controller driver when reading the PCI
 318 * configuration space of the fake bridge. It will call back the
 319 * ->ops->read_base or ->ops->read_pcie operations.
 320 */
 321int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
 322                              int size, u32 *value)
 323{
 324        int ret;
 325        int reg = where & ~3;
 326        pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
 327                                                 int reg, u32 *value);
 328        __le32 *cfgspace;
 329        const struct pci_bridge_reg_behavior *behavior;
 330
 331        if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
 332                *value = 0;
 333                return PCIBIOS_SUCCESSFUL;
 334        }
 335
 336        if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
 337                *value = 0;
 338                return PCIBIOS_SUCCESSFUL;
 339        }
 340
 341        if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
 342                reg -= PCI_CAP_PCIE_START;
 343                read_op = bridge->ops->read_pcie;
 344                cfgspace = (__le32 *) &bridge->pcie_conf;
 345                behavior = bridge->pcie_cap_regs_behavior;
 346        } else {
 347                read_op = bridge->ops->read_base;
 348                cfgspace = (__le32 *) &bridge->conf;
 349                behavior = bridge->pci_regs_behavior;
 350        }
 351
 352        if (read_op)
 353                ret = read_op(bridge, reg, value);
 354        else
 355                ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
 356
 357        if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
 358                *value = le32_to_cpu(cfgspace[reg / 4]);
 359
 360        /*
 361         * Make sure we never return any reserved bit with a value
 362         * different from 0.
 363         */
 364        *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
 365                  behavior[reg / 4].w1c;
 366
 367        if (size == 1)
 368                *value = (*value >> (8 * (where & 3))) & 0xff;
 369        else if (size == 2)
 370                *value = (*value >> (8 * (where & 3))) & 0xffff;
 371        else if (size != 4)
 372                return PCIBIOS_BAD_REGISTER_NUMBER;
 373
 374        return PCIBIOS_SUCCESSFUL;
 375}
 376EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
 377
 378/*
 379 * Should be called by the PCI controller driver when writing the PCI
 380 * configuration space of the fake bridge. It will call back the
 381 * ->ops->write_base or ->ops->write_pcie operations.
 382 */
 383int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
 384                               int size, u32 value)
 385{
 386        int reg = where & ~3;
 387        int mask, ret, old, new, shift;
 388        void (*write_op)(struct pci_bridge_emul *bridge, int reg,
 389                         u32 old, u32 new, u32 mask);
 390        __le32 *cfgspace;
 391        const struct pci_bridge_reg_behavior *behavior;
 392
 393        if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
 394                return PCIBIOS_SUCCESSFUL;
 395
 396        if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
 397                return PCIBIOS_SUCCESSFUL;
 398
 399        shift = (where & 0x3) * 8;
 400
 401        if (size == 4)
 402                mask = 0xffffffff;
 403        else if (size == 2)
 404                mask = 0xffff << shift;
 405        else if (size == 1)
 406                mask = 0xff << shift;
 407        else
 408                return PCIBIOS_BAD_REGISTER_NUMBER;
 409
 410        ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
 411        if (ret != PCIBIOS_SUCCESSFUL)
 412                return ret;
 413
 414        if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
 415                reg -= PCI_CAP_PCIE_START;
 416                write_op = bridge->ops->write_pcie;
 417                cfgspace = (__le32 *) &bridge->pcie_conf;
 418                behavior = bridge->pcie_cap_regs_behavior;
 419        } else {
 420                write_op = bridge->ops->write_base;
 421                cfgspace = (__le32 *) &bridge->conf;
 422                behavior = bridge->pci_regs_behavior;
 423        }
 424
 425        /* Keep all bits, except the RW bits */
 426        new = old & (~mask | ~behavior[reg / 4].rw);
 427
 428        /* Update the value of the RW bits */
 429        new |= (value << shift) & (behavior[reg / 4].rw & mask);
 430
 431        /* Clear the W1C bits */
 432        new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
 433
 434        cfgspace[reg / 4] = cpu_to_le32(new);
 435
 436        if (write_op)
 437                write_op(bridge, reg, old, new, mask);
 438
 439        return PCIBIOS_SUCCESSFUL;
 440}
 441EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);
 442