1
2
3
4
5
6
7
8
9#include <linux/clk.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/phy/phy.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16
17#define GRF_SOC_CON12 0x0274
18
19#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
20#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
21
22#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
23#define GRF_EDP_PHY_SIDDQ_ON 0
24#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
25
26struct rockchip_dp_phy {
27 struct device *dev;
28 struct regmap *grf;
29 struct clk *phy_24m;
30};
31
32static int rockchip_set_phy_state(struct phy *phy, bool enable)
33{
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
35 int ret;
36
37 if (enable) {
38 ret = regmap_write(dp->grf, GRF_SOC_CON12,
39 GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
40 GRF_EDP_PHY_SIDDQ_ON);
41 if (ret < 0) {
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
43 return ret;
44 }
45
46 ret = clk_prepare_enable(dp->phy_24m);
47 } else {
48 clk_disable_unprepare(dp->phy_24m);
49
50 ret = regmap_write(dp->grf, GRF_SOC_CON12,
51 GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
52 GRF_EDP_PHY_SIDDQ_OFF);
53 }
54
55 return ret;
56}
57
58static int rockchip_dp_phy_power_on(struct phy *phy)
59{
60 return rockchip_set_phy_state(phy, true);
61}
62
63static int rockchip_dp_phy_power_off(struct phy *phy)
64{
65 return rockchip_set_phy_state(phy, false);
66}
67
68static const struct phy_ops rockchip_dp_phy_ops = {
69 .power_on = rockchip_dp_phy_power_on,
70 .power_off = rockchip_dp_phy_power_off,
71 .owner = THIS_MODULE,
72};
73
74static int rockchip_dp_phy_probe(struct platform_device *pdev)
75{
76 struct device *dev = &pdev->dev;
77 struct device_node *np = dev->of_node;
78 struct phy_provider *phy_provider;
79 struct rockchip_dp_phy *dp;
80 struct phy *phy;
81 int ret;
82
83 if (!np)
84 return -ENODEV;
85
86 if (!dev->parent || !dev->parent->of_node)
87 return -ENODEV;
88
89 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
90 if (!dp)
91 return -ENOMEM;
92
93 dp->dev = dev;
94
95 dp->phy_24m = devm_clk_get(dev, "24m");
96 if (IS_ERR(dp->phy_24m)) {
97 dev_err(dev, "cannot get clock 24m\n");
98 return PTR_ERR(dp->phy_24m);
99 }
100
101 ret = clk_set_rate(dp->phy_24m, 24000000);
102 if (ret < 0) {
103 dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
104 return ret;
105 }
106
107 dp->grf = syscon_node_to_regmap(dev->parent->of_node);
108 if (IS_ERR(dp->grf)) {
109 dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
110 return PTR_ERR(dp->grf);
111 }
112
113 ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
114 GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
115 if (ret != 0) {
116 dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
117 return ret;
118 }
119
120 phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
121 if (IS_ERR(phy)) {
122 dev_err(dev, "failed to create phy\n");
123 return PTR_ERR(phy);
124 }
125 phy_set_drvdata(phy, dp);
126
127 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
128
129 return PTR_ERR_OR_ZERO(phy_provider);
130}
131
132static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
133 { .compatible = "rockchip,rk3288-dp-phy" },
134 {}
135};
136
137MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
138
139static struct platform_driver rockchip_dp_phy_driver = {
140 .probe = rockchip_dp_phy_probe,
141 .driver = {
142 .name = "rockchip-dp-phy",
143 .of_match_table = rockchip_dp_phy_dt_ids,
144 },
145};
146
147module_platform_driver(rockchip_dp_phy_driver);
148
149MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
150MODULE_DESCRIPTION("Rockchip DP PHY driver");
151MODULE_LICENSE("GPL v2");
152
