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9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-ti.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/gpio.h>
15#include <linux/gpio/consumer.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/mux/consumer.h>
19#include <linux/of_address.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/reset-controller.h>
25
26#define WIZ_SERDES_CTRL 0x404
27#define WIZ_SERDES_TOP_CTRL 0x408
28#define WIZ_SERDES_RST 0x40c
29#define WIZ_SERDES_TYPEC 0x410
30#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
31#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
32
33#define WIZ_MAX_INPUT_CLOCKS 4
34
35#define WIZ_MAX_OUTPUT_CLOCKS 32
36
37#define WIZ_MAX_LANES 4
38#define WIZ_MUX_NUM_CLOCKS 3
39#define WIZ_DIV_NUM_CLOCKS_16G 2
40#define WIZ_DIV_NUM_CLOCKS_10G 1
41
42#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
43
44enum wiz_lane_standard_mode {
45 LANE_MODE_GEN1,
46 LANE_MODE_GEN2,
47 LANE_MODE_GEN3,
48 LANE_MODE_GEN4,
49};
50
51enum wiz_refclk_mux_sel {
52 PLL0_REFCLK,
53 PLL1_REFCLK,
54 REFCLK_DIG,
55};
56
57enum wiz_refclk_div_sel {
58 CMN_REFCLK_DIG_DIV,
59 CMN_REFCLK1_DIG_DIV,
60};
61
62enum wiz_clock_input {
63 WIZ_CORE_REFCLK,
64 WIZ_EXT_REFCLK,
65 WIZ_CORE_REFCLK1,
66 WIZ_EXT_REFCLK1,
67};
68
69static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
70static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
71static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
72static const struct reg_field pll1_refclk_mux_sel =
73 REG_FIELD(WIZ_SERDES_RST, 29, 29);
74static const struct reg_field pll0_refclk_mux_sel =
75 REG_FIELD(WIZ_SERDES_RST, 28, 28);
76static const struct reg_field refclk_dig_sel_16g =
77 REG_FIELD(WIZ_SERDES_RST, 24, 25);
78static const struct reg_field refclk_dig_sel_10g =
79 REG_FIELD(WIZ_SERDES_RST, 24, 24);
80static const struct reg_field pma_cmn_refclk_int_mode =
81 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
82static const struct reg_field pma_cmn_refclk_mode =
83 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
84static const struct reg_field pma_cmn_refclk_dig_div =
85 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
86static const struct reg_field pma_cmn_refclk1_dig_div =
87 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
88static const char * const output_clk_names[] = {
89 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
90 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
91 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
92 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
93};
94
95static const struct reg_field p_enable[WIZ_MAX_LANES] = {
96 REG_FIELD(WIZ_LANECTL(0), 30, 31),
97 REG_FIELD(WIZ_LANECTL(1), 30, 31),
98 REG_FIELD(WIZ_LANECTL(2), 30, 31),
99 REG_FIELD(WIZ_LANECTL(3), 30, 31),
100};
101
102enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
103
104static const struct reg_field p_align[WIZ_MAX_LANES] = {
105 REG_FIELD(WIZ_LANECTL(0), 29, 29),
106 REG_FIELD(WIZ_LANECTL(1), 29, 29),
107 REG_FIELD(WIZ_LANECTL(2), 29, 29),
108 REG_FIELD(WIZ_LANECTL(3), 29, 29),
109};
110
111static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
112 REG_FIELD(WIZ_LANECTL(0), 28, 28),
113 REG_FIELD(WIZ_LANECTL(1), 28, 28),
114 REG_FIELD(WIZ_LANECTL(2), 28, 28),
115 REG_FIELD(WIZ_LANECTL(3), 28, 28),
116};
117
118static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
119 REG_FIELD(WIZ_LANECTL(0), 24, 25),
120 REG_FIELD(WIZ_LANECTL(1), 24, 25),
121 REG_FIELD(WIZ_LANECTL(2), 24, 25),
122 REG_FIELD(WIZ_LANECTL(3), 24, 25),
123};
124
125static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
126 REG_FIELD(WIZ_LANECTL(0), 22, 23),
127 REG_FIELD(WIZ_LANECTL(1), 22, 23),
128 REG_FIELD(WIZ_LANECTL(2), 22, 23),
129 REG_FIELD(WIZ_LANECTL(3), 22, 23),
130};
131
132static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
133 REG_FIELD(WIZ_LANEDIV(0), 16, 22),
134 REG_FIELD(WIZ_LANEDIV(1), 16, 22),
135 REG_FIELD(WIZ_LANEDIV(2), 16, 22),
136 REG_FIELD(WIZ_LANEDIV(3), 16, 22),
137};
138
139static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
140 REG_FIELD(WIZ_LANEDIV(0), 0, 8),
141 REG_FIELD(WIZ_LANEDIV(1), 0, 8),
142 REG_FIELD(WIZ_LANEDIV(2), 0, 8),
143 REG_FIELD(WIZ_LANEDIV(3), 0, 8),
144};
145
146static const struct reg_field typec_ln10_swap =
147 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
148
149struct wiz_clk_mux {
150 struct clk_hw hw;
151 struct regmap_field *field;
152 const u32 *table;
153 struct clk_init_data clk_data;
154};
155
156#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
157
158struct wiz_clk_divider {
159 struct clk_hw hw;
160 struct regmap_field *field;
161 const struct clk_div_table *table;
162 struct clk_init_data clk_data;
163};
164
165#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
166
167struct wiz_clk_mux_sel {
168 u32 table[WIZ_MAX_INPUT_CLOCKS];
169 const char *node_name;
170 u32 num_parents;
171 u32 parents[WIZ_MAX_INPUT_CLOCKS];
172};
173
174struct wiz_clk_div_sel {
175 const struct clk_div_table *table;
176 const char *node_name;
177};
178
179struct wiz_phy_en_refclk {
180 struct clk_hw hw;
181 struct regmap_field *phy_en_refclk;
182 struct clk_init_data clk_data;
183};
184
185#define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
186
187static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
188 {
189
190
191
192
193 .table = { 1, 0 },
194 .node_name = "pll0-refclk",
195 },
196 {
197 .table = { 1, 0 },
198 .node_name = "pll1-refclk",
199 },
200 {
201 .table = { 1, 3, 0, 2 },
202 .node_name = "refclk-dig",
203 },
204};
205
206static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
207 {
208
209
210
211
212 .num_parents = 2,
213 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
214 .table = { 1, 0 },
215 .node_name = "pll0-refclk",
216 },
217 {
218 .num_parents = 2,
219 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
220 .table = { 1, 0 },
221 .node_name = "pll1-refclk",
222 },
223 {
224 .num_parents = 2,
225 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
226 .table = { 1, 0 },
227 .node_name = "refclk-dig",
228 },
229};
230
231static const struct clk_div_table clk_div_table[] = {
232 { .val = 0, .div = 1, },
233 { .val = 1, .div = 2, },
234 { .val = 2, .div = 4, },
235 { .val = 3, .div = 8, },
236};
237
238static const struct wiz_clk_div_sel clk_div_sel[] = {
239 {
240 .table = clk_div_table,
241 .node_name = "cmn-refclk-dig-div",
242 },
243 {
244 .table = clk_div_table,
245 .node_name = "cmn-refclk1-dig-div",
246 },
247};
248
249enum wiz_type {
250 J721E_WIZ_16G,
251 J721E_WIZ_10G,
252 AM64_WIZ_10G,
253};
254
255#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100
256#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
257
258struct wiz {
259 struct regmap *regmap;
260 enum wiz_type type;
261 const struct wiz_clk_mux_sel *clk_mux_sel;
262 const struct wiz_clk_div_sel *clk_div_sel;
263 unsigned int clk_div_sel_num;
264 struct regmap_field *por_en;
265 struct regmap_field *phy_reset_n;
266 struct regmap_field *phy_en_refclk;
267 struct regmap_field *p_enable[WIZ_MAX_LANES];
268 struct regmap_field *p_align[WIZ_MAX_LANES];
269 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
270 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
271 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
272 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
273 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
274 struct regmap_field *pma_cmn_refclk_int_mode;
275 struct regmap_field *pma_cmn_refclk_mode;
276 struct regmap_field *pma_cmn_refclk_dig_div;
277 struct regmap_field *pma_cmn_refclk1_dig_div;
278 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
279 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
280 struct regmap_field *typec_ln10_swap;
281
282 struct device *dev;
283 u32 num_lanes;
284 struct platform_device *serdes_pdev;
285 struct reset_controller_dev wiz_phy_reset_dev;
286 struct gpio_desc *gpio_typec_dir;
287 int typec_dir_delay;
288 u32 lane_phy_type[WIZ_MAX_LANES];
289 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
290 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
291 struct clk_onecell_data clk_data;
292};
293
294static int wiz_reset(struct wiz *wiz)
295{
296 int ret;
297
298 ret = regmap_field_write(wiz->por_en, 0x1);
299 if (ret)
300 return ret;
301
302 mdelay(1);
303
304 ret = regmap_field_write(wiz->por_en, 0x0);
305 if (ret)
306 return ret;
307
308 return 0;
309}
310
311static int wiz_p_mac_div_sel(struct wiz *wiz)
312{
313 u32 num_lanes = wiz->num_lanes;
314 int ret;
315 int i;
316
317 for (i = 0; i < num_lanes; i++) {
318 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
319 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
320 if (ret)
321 return ret;
322
323 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
324 if (ret)
325 return ret;
326 }
327 }
328
329 return 0;
330}
331
332static int wiz_mode_select(struct wiz *wiz)
333{
334 u32 num_lanes = wiz->num_lanes;
335 enum wiz_lane_standard_mode mode;
336 int ret;
337 int i;
338
339 for (i = 0; i < num_lanes; i++) {
340 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
341 mode = LANE_MODE_GEN1;
342 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
343 mode = LANE_MODE_GEN2;
344 else
345 continue;
346
347 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
348 if (ret)
349 return ret;
350 }
351
352 return 0;
353}
354
355static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
356{
357 u32 num_lanes = wiz->num_lanes;
358 int i;
359 int ret;
360
361 for (i = 0; i < num_lanes; i++) {
362 ret = regmap_field_write(wiz->p_align[i], enable);
363 if (ret)
364 return ret;
365
366 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
367 if (ret)
368 return ret;
369 }
370
371 return 0;
372}
373
374static int wiz_init(struct wiz *wiz)
375{
376 struct device *dev = wiz->dev;
377 int ret;
378
379 ret = wiz_reset(wiz);
380 if (ret) {
381 dev_err(dev, "WIZ reset failed\n");
382 return ret;
383 }
384
385 ret = wiz_mode_select(wiz);
386 if (ret) {
387 dev_err(dev, "WIZ mode select failed\n");
388 return ret;
389 }
390
391 ret = wiz_p_mac_div_sel(wiz);
392 if (ret) {
393 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
394 return ret;
395 }
396
397 ret = wiz_init_raw_interface(wiz, true);
398 if (ret) {
399 dev_err(dev, "WIZ interface initialization failed\n");
400 return ret;
401 }
402
403 return 0;
404}
405
406static int wiz_regfield_init(struct wiz *wiz)
407{
408 struct regmap *regmap = wiz->regmap;
409 int num_lanes = wiz->num_lanes;
410 struct device *dev = wiz->dev;
411 int i;
412
413 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
414 if (IS_ERR(wiz->por_en)) {
415 dev_err(dev, "POR_EN reg field init failed\n");
416 return PTR_ERR(wiz->por_en);
417 }
418
419 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
420 phy_reset_n);
421 if (IS_ERR(wiz->phy_reset_n)) {
422 dev_err(dev, "PHY_RESET_N reg field init failed\n");
423 return PTR_ERR(wiz->phy_reset_n);
424 }
425
426 wiz->pma_cmn_refclk_int_mode =
427 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
428 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
429 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
430 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
431 }
432
433 wiz->pma_cmn_refclk_mode =
434 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
435 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
436 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
437 return PTR_ERR(wiz->pma_cmn_refclk_mode);
438 }
439
440 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
441 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
442 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
443 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
444 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
445 }
446
447 if (wiz->type == J721E_WIZ_16G) {
448 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
449 devm_regmap_field_alloc(dev, regmap,
450 pma_cmn_refclk1_dig_div);
451 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
452 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
453 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
454 }
455 }
456
457 wiz->mux_sel_field[PLL0_REFCLK] =
458 devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
459 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
460 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
461 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
462 }
463
464 wiz->mux_sel_field[PLL1_REFCLK] =
465 devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
466 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
467 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
468 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
469 }
470
471 if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
472 wiz->mux_sel_field[REFCLK_DIG] =
473 devm_regmap_field_alloc(dev, regmap,
474 refclk_dig_sel_10g);
475 else
476 wiz->mux_sel_field[REFCLK_DIG] =
477 devm_regmap_field_alloc(dev, regmap,
478 refclk_dig_sel_16g);
479
480 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
481 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
482 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
483 }
484
485 for (i = 0; i < num_lanes; i++) {
486 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
487 p_enable[i]);
488 if (IS_ERR(wiz->p_enable[i])) {
489 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
490 return PTR_ERR(wiz->p_enable[i]);
491 }
492
493 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
494 p_align[i]);
495 if (IS_ERR(wiz->p_align[i])) {
496 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
497 return PTR_ERR(wiz->p_align[i]);
498 }
499
500 wiz->p_raw_auto_start[i] =
501 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
502 if (IS_ERR(wiz->p_raw_auto_start[i])) {
503 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
504 i);
505 return PTR_ERR(wiz->p_raw_auto_start[i]);
506 }
507
508 wiz->p_standard_mode[i] =
509 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
510 if (IS_ERR(wiz->p_standard_mode[i])) {
511 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
512 i);
513 return PTR_ERR(wiz->p_standard_mode[i]);
514 }
515
516 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
517 if (IS_ERR(wiz->p0_fullrt_div[i])) {
518 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
519 return PTR_ERR(wiz->p0_fullrt_div[i]);
520 }
521
522 wiz->p_mac_div_sel0[i] =
523 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
524 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
525 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
526 i);
527 return PTR_ERR(wiz->p_mac_div_sel0[i]);
528 }
529
530 wiz->p_mac_div_sel1[i] =
531 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
532 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
533 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
534 i);
535 return PTR_ERR(wiz->p_mac_div_sel1[i]);
536 }
537 }
538
539 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
540 typec_ln10_swap);
541 if (IS_ERR(wiz->typec_ln10_swap)) {
542 dev_err(dev, "LN10_SWAP reg field init failed\n");
543 return PTR_ERR(wiz->typec_ln10_swap);
544 }
545
546 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
547 if (IS_ERR(wiz->phy_en_refclk)) {
548 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
549 return PTR_ERR(wiz->phy_en_refclk);
550 }
551
552 return 0;
553}
554
555static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
556{
557 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
558 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
559
560 regmap_field_write(phy_en_refclk, 1);
561
562 return 0;
563}
564
565static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
566{
567 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
568 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
569
570 regmap_field_write(phy_en_refclk, 0);
571}
572
573static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
574{
575 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
576 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
577 int val;
578
579 regmap_field_read(phy_en_refclk, &val);
580
581 return !!val;
582}
583
584static const struct clk_ops wiz_phy_en_refclk_ops = {
585 .enable = wiz_phy_en_refclk_enable,
586 .disable = wiz_phy_en_refclk_disable,
587 .is_enabled = wiz_phy_en_refclk_is_enabled,
588};
589
590static int wiz_phy_en_refclk_register(struct wiz *wiz)
591{
592 struct wiz_phy_en_refclk *wiz_phy_en_refclk;
593 struct device *dev = wiz->dev;
594 struct clk_init_data *init;
595 struct clk *clk;
596
597 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
598 if (!wiz_phy_en_refclk)
599 return -ENOMEM;
600
601 init = &wiz_phy_en_refclk->clk_data;
602
603 init->ops = &wiz_phy_en_refclk_ops;
604 init->flags = 0;
605 init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK];
606
607 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
608 wiz_phy_en_refclk->hw.init = init;
609
610 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
611 if (IS_ERR(clk))
612 return PTR_ERR(clk);
613
614 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
615
616 return 0;
617}
618
619static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
620{
621 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
622 struct regmap_field *field = mux->field;
623 unsigned int val;
624
625 regmap_field_read(field, &val);
626 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
627}
628
629static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
630{
631 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
632 struct regmap_field *field = mux->field;
633 int val;
634
635 val = mux->table[index];
636 return regmap_field_write(field, val);
637}
638
639static const struct clk_ops wiz_clk_mux_ops = {
640 .set_parent = wiz_clk_mux_set_parent,
641 .get_parent = wiz_clk_mux_get_parent,
642};
643
644static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
645 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
646{
647 struct device *dev = wiz->dev;
648 struct clk_init_data *init;
649 const char **parent_names;
650 unsigned int num_parents;
651 struct wiz_clk_mux *mux;
652 char clk_name[100];
653 struct clk *clk;
654 int ret = 0, i;
655
656 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
657 if (!mux)
658 return -ENOMEM;
659
660 num_parents = mux_sel->num_parents;
661
662 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
663 if (!parent_names)
664 return -ENOMEM;
665
666 for (i = 0; i < num_parents; i++) {
667 clk = wiz->input_clks[mux_sel->parents[i]];
668 if (IS_ERR_OR_NULL(clk)) {
669 dev_err(dev, "Failed to get parent clk for %s\n",
670 output_clk_names[clk_index]);
671 ret = -EINVAL;
672 goto err;
673 }
674 parent_names[i] = __clk_get_name(clk);
675 }
676
677 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
678
679 init = &mux->clk_data;
680
681 init->ops = &wiz_clk_mux_ops;
682 init->flags = CLK_SET_RATE_NO_REPARENT;
683 init->parent_names = parent_names;
684 init->num_parents = num_parents;
685 init->name = clk_name;
686
687 mux->field = field;
688 mux->table = mux_sel->table;
689 mux->hw.init = init;
690
691 clk = devm_clk_register(dev, &mux->hw);
692 if (IS_ERR(clk)) {
693 ret = PTR_ERR(clk);
694 goto err;
695 }
696
697 wiz->output_clks[clk_index] = clk;
698
699err:
700 kfree(parent_names);
701
702 return ret;
703}
704
705static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
706 struct regmap_field *field, const u32 *table)
707{
708 struct device *dev = wiz->dev;
709 struct clk_init_data *init;
710 const char **parent_names;
711 unsigned int num_parents;
712 struct wiz_clk_mux *mux;
713 char clk_name[100];
714 struct clk *clk;
715 int ret;
716
717 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
718 if (!mux)
719 return -ENOMEM;
720
721 num_parents = of_clk_get_parent_count(node);
722 if (num_parents < 2) {
723 dev_err(dev, "SERDES clock must have parents\n");
724 return -EINVAL;
725 }
726
727 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
728 GFP_KERNEL);
729 if (!parent_names)
730 return -ENOMEM;
731
732 of_clk_parent_fill(node, parent_names, num_parents);
733
734 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
735 node->name);
736
737 init = &mux->clk_data;
738
739 init->ops = &wiz_clk_mux_ops;
740 init->flags = CLK_SET_RATE_NO_REPARENT;
741 init->parent_names = parent_names;
742 init->num_parents = num_parents;
743 init->name = clk_name;
744
745 mux->field = field;
746 mux->table = table;
747 mux->hw.init = init;
748
749 clk = devm_clk_register(dev, &mux->hw);
750 if (IS_ERR(clk))
751 return PTR_ERR(clk);
752
753 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
754 if (ret)
755 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
756
757 return ret;
758}
759
760static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
761 unsigned long parent_rate)
762{
763 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
764 struct regmap_field *field = div->field;
765 int val;
766
767 regmap_field_read(field, &val);
768
769 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
770}
771
772static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
773 unsigned long *prate)
774{
775 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
776
777 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
778}
779
780static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
781 unsigned long parent_rate)
782{
783 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
784 struct regmap_field *field = div->field;
785 int val;
786
787 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
788 if (val < 0)
789 return val;
790
791 return regmap_field_write(field, val);
792}
793
794static const struct clk_ops wiz_clk_div_ops = {
795 .recalc_rate = wiz_clk_div_recalc_rate,
796 .round_rate = wiz_clk_div_round_rate,
797 .set_rate = wiz_clk_div_set_rate,
798};
799
800static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
801 struct regmap_field *field,
802 const struct clk_div_table *table)
803{
804 struct device *dev = wiz->dev;
805 struct wiz_clk_divider *div;
806 struct clk_init_data *init;
807 const char **parent_names;
808 char clk_name[100];
809 struct clk *clk;
810 int ret;
811
812 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
813 if (!div)
814 return -ENOMEM;
815
816 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
817 node->name);
818
819 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
820 if (!parent_names)
821 return -ENOMEM;
822
823 of_clk_parent_fill(node, parent_names, 1);
824
825 init = &div->clk_data;
826
827 init->ops = &wiz_clk_div_ops;
828 init->flags = 0;
829 init->parent_names = parent_names;
830 init->num_parents = 1;
831 init->name = clk_name;
832
833 div->field = field;
834 div->table = table;
835 div->hw.init = init;
836
837 clk = devm_clk_register(dev, &div->hw);
838 if (IS_ERR(clk))
839 return PTR_ERR(clk);
840
841 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
842 if (ret)
843 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
844
845 return ret;
846}
847
848static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
849{
850 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
851 struct device *dev = wiz->dev;
852 struct device_node *clk_node;
853 int i;
854
855 if (wiz->type == AM64_WIZ_10G) {
856 of_clk_del_provider(dev->of_node);
857 return;
858 }
859
860 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
861 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
862 of_clk_del_provider(clk_node);
863 of_node_put(clk_node);
864 }
865
866 for (i = 0; i < wiz->clk_div_sel_num; i++) {
867 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
868 of_clk_del_provider(clk_node);
869 of_node_put(clk_node);
870 }
871
872 of_clk_del_provider(wiz->dev->of_node);
873}
874
875static int wiz_clock_register(struct wiz *wiz)
876{
877 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
878 struct device *dev = wiz->dev;
879 struct device_node *node = dev->of_node;
880 int clk_index;
881 int ret;
882 int i;
883
884 if (wiz->type != AM64_WIZ_10G)
885 return 0;
886
887 clk_index = TI_WIZ_PLL0_REFCLK;
888 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
889 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
890 if (ret) {
891 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
892 return ret;
893 }
894 }
895
896 ret = wiz_phy_en_refclk_register(wiz);
897 if (ret) {
898 dev_err(dev, "Failed to add phy-en-refclk\n");
899 return ret;
900 }
901
902 wiz->clk_data.clks = wiz->output_clks;
903 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
904 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
905 if (ret)
906 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
907
908 return ret;
909}
910
911static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
912{
913 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
914 struct device *dev = wiz->dev;
915 struct device_node *clk_node;
916 const char *node_name;
917 unsigned long rate;
918 struct clk *clk;
919 int ret;
920 int i;
921
922 clk = devm_clk_get(dev, "core_ref_clk");
923 if (IS_ERR(clk)) {
924 dev_err(dev, "core_ref_clk clock not found\n");
925 ret = PTR_ERR(clk);
926 return ret;
927 }
928 wiz->input_clks[WIZ_CORE_REFCLK] = clk;
929
930 rate = clk_get_rate(clk);
931 if (rate >= 100000000)
932 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
933 else
934 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
935
936 clk = devm_clk_get(dev, "ext_ref_clk");
937 if (IS_ERR(clk)) {
938 dev_err(dev, "ext_ref_clk clock not found\n");
939 ret = PTR_ERR(clk);
940 return ret;
941 }
942 wiz->input_clks[WIZ_EXT_REFCLK] = clk;
943
944 rate = clk_get_rate(clk);
945 if (rate >= 100000000)
946 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
947 else
948 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
949
950 if (wiz->type == AM64_WIZ_10G) {
951 ret = wiz_clock_register(wiz);
952 if (ret)
953 dev_err(dev, "Failed to register wiz clocks\n");
954 return ret;
955 }
956
957 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
958 node_name = clk_mux_sel[i].node_name;
959 clk_node = of_get_child_by_name(node, node_name);
960 if (!clk_node) {
961 dev_err(dev, "Unable to get %s node\n", node_name);
962 ret = -EINVAL;
963 goto err;
964 }
965
966 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
967 clk_mux_sel[i].table);
968 if (ret) {
969 dev_err(dev, "Failed to register %s clock\n",
970 node_name);
971 of_node_put(clk_node);
972 goto err;
973 }
974
975 of_node_put(clk_node);
976 }
977
978 for (i = 0; i < wiz->clk_div_sel_num; i++) {
979 node_name = clk_div_sel[i].node_name;
980 clk_node = of_get_child_by_name(node, node_name);
981 if (!clk_node) {
982 dev_err(dev, "Unable to get %s node\n", node_name);
983 ret = -EINVAL;
984 goto err;
985 }
986
987 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
988 clk_div_sel[i].table);
989 if (ret) {
990 dev_err(dev, "Failed to register %s clock\n",
991 node_name);
992 of_node_put(clk_node);
993 goto err;
994 }
995
996 of_node_put(clk_node);
997 }
998
999 return 0;
1000err:
1001 wiz_clock_cleanup(wiz, node);
1002
1003 return ret;
1004}
1005
1006static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1007 unsigned long id)
1008{
1009 struct device *dev = rcdev->dev;
1010 struct wiz *wiz = dev_get_drvdata(dev);
1011 int ret = 0;
1012
1013 if (id == 0) {
1014 ret = regmap_field_write(wiz->phy_reset_n, false);
1015 return ret;
1016 }
1017
1018 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1019 return ret;
1020}
1021
1022static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1023{
1024 if (wiz->type != AM64_WIZ_10G)
1025 return 0;
1026
1027 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1028 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1029
1030 return 0;
1031}
1032
1033static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1034 unsigned long id)
1035{
1036 struct device *dev = rcdev->dev;
1037 struct wiz *wiz = dev_get_drvdata(dev);
1038 int ret;
1039
1040
1041 if (id == 0 && wiz->gpio_typec_dir) {
1042 if (wiz->typec_dir_delay)
1043 msleep_interruptible(wiz->typec_dir_delay);
1044
1045 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1046 regmap_field_write(wiz->typec_ln10_swap, 1);
1047 else
1048 regmap_field_write(wiz->typec_ln10_swap, 0);
1049 }
1050
1051 if (id == 0) {
1052 ret = regmap_field_write(wiz->phy_reset_n, true);
1053 return ret;
1054 }
1055
1056 ret = wiz_phy_fullrt_div(wiz, id - 1);
1057 if (ret)
1058 return ret;
1059
1060 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1061 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1062 else
1063 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1064
1065 return ret;
1066}
1067
1068static const struct reset_control_ops wiz_phy_reset_ops = {
1069 .assert = wiz_phy_reset_assert,
1070 .deassert = wiz_phy_reset_deassert,
1071};
1072
1073static const struct regmap_config wiz_regmap_config = {
1074 .reg_bits = 32,
1075 .val_bits = 32,
1076 .reg_stride = 4,
1077 .fast_io = true,
1078};
1079
1080static const struct of_device_id wiz_id_table[] = {
1081 {
1082 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
1083 },
1084 {
1085 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
1086 },
1087 {
1088 .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
1089 },
1090 {}
1091};
1092MODULE_DEVICE_TABLE(of, wiz_id_table);
1093
1094static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1095{
1096 struct device_node *serdes, *subnode;
1097
1098 serdes = of_get_child_by_name(dev->of_node, "serdes");
1099 if (!serdes) {
1100 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1101 return -EINVAL;
1102 }
1103
1104 for_each_child_of_node(serdes, subnode) {
1105 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1106 int ret, i;
1107
1108 if (!(of_node_name_eq(subnode, "phy") ||
1109 of_node_name_eq(subnode, "link")))
1110 continue;
1111
1112 ret = of_property_read_u32(subnode, "reg", ®);
1113 if (ret) {
1114 of_node_put(subnode);
1115 dev_err(dev,
1116 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
1117 __func__, subnode->name, ret);
1118 return ret;
1119 }
1120 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1121 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1122
1123 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1124 reg, reg + num_lanes - 1, phy_type);
1125
1126 for (i = reg; i < reg + num_lanes; i++)
1127 wiz->lane_phy_type[i] = phy_type;
1128 }
1129
1130 return 0;
1131}
1132
1133static int wiz_probe(struct platform_device *pdev)
1134{
1135 struct reset_controller_dev *phy_reset_dev;
1136 struct device *dev = &pdev->dev;
1137 struct device_node *node = dev->of_node;
1138 struct platform_device *serdes_pdev;
1139 bool already_configured = false;
1140 struct device_node *child_node;
1141 struct regmap *regmap;
1142 struct resource res;
1143 void __iomem *base;
1144 struct wiz *wiz;
1145 int ret, val, i;
1146 u32 num_lanes;
1147
1148 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1149 if (!wiz)
1150 return -ENOMEM;
1151
1152 wiz->type = (enum wiz_type)of_device_get_match_data(dev);
1153
1154 child_node = of_get_child_by_name(node, "serdes");
1155 if (!child_node) {
1156 dev_err(dev, "Failed to get SERDES child DT node\n");
1157 return -ENODEV;
1158 }
1159
1160 ret = of_address_to_resource(child_node, 0, &res);
1161 if (ret) {
1162 dev_err(dev, "Failed to get memory resource\n");
1163 goto err_addr_to_resource;
1164 }
1165
1166 base = devm_ioremap(dev, res.start, resource_size(&res));
1167 if (!base) {
1168 ret = -ENOMEM;
1169 goto err_addr_to_resource;
1170 }
1171
1172 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1173 if (IS_ERR(regmap)) {
1174 dev_err(dev, "Failed to initialize regmap\n");
1175 ret = PTR_ERR(regmap);
1176 goto err_addr_to_resource;
1177 }
1178
1179 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1180 if (ret) {
1181 dev_err(dev, "Failed to read num-lanes property\n");
1182 goto err_addr_to_resource;
1183 }
1184
1185 if (num_lanes > WIZ_MAX_LANES) {
1186 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1187 ret = -ENODEV;
1188 goto err_addr_to_resource;
1189 }
1190
1191 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1192 GPIOD_IN);
1193 if (IS_ERR(wiz->gpio_typec_dir)) {
1194 ret = PTR_ERR(wiz->gpio_typec_dir);
1195 if (ret != -EPROBE_DEFER)
1196 dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1197 ret);
1198 goto err_addr_to_resource;
1199 }
1200
1201 if (wiz->gpio_typec_dir) {
1202 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1203 &wiz->typec_dir_delay);
1204 if (ret && ret != -EINVAL) {
1205 dev_err(dev, "Invalid typec-dir-debounce property\n");
1206 goto err_addr_to_resource;
1207 }
1208
1209
1210 if (ret == -EINVAL)
1211 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1212
1213 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1214 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1215 ret = -EINVAL;
1216 dev_err(dev, "Invalid typec-dir-debounce property\n");
1217 goto err_addr_to_resource;
1218 }
1219 }
1220
1221 ret = wiz_get_lane_phy_types(dev, wiz);
1222 if (ret)
1223 return ret;
1224
1225 wiz->dev = dev;
1226 wiz->regmap = regmap;
1227 wiz->num_lanes = num_lanes;
1228 if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
1229 wiz->clk_mux_sel = clk_mux_sel_10g;
1230 else
1231 wiz->clk_mux_sel = clk_mux_sel_16g;
1232
1233 wiz->clk_div_sel = clk_div_sel;
1234
1235 if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
1236 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
1237 else
1238 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
1239
1240 platform_set_drvdata(pdev, wiz);
1241
1242 ret = wiz_regfield_init(wiz);
1243 if (ret) {
1244 dev_err(dev, "Failed to initialize regfields\n");
1245 goto err_addr_to_resource;
1246 }
1247
1248 phy_reset_dev = &wiz->wiz_phy_reset_dev;
1249 phy_reset_dev->dev = dev;
1250 phy_reset_dev->ops = &wiz_phy_reset_ops,
1251 phy_reset_dev->owner = THIS_MODULE,
1252 phy_reset_dev->of_node = node;
1253
1254 phy_reset_dev->nr_resets = num_lanes + 1;
1255
1256 ret = devm_reset_controller_register(dev, phy_reset_dev);
1257 if (ret < 0) {
1258 dev_warn(dev, "Failed to register reset controller\n");
1259 goto err_addr_to_resource;
1260 }
1261
1262 pm_runtime_enable(dev);
1263 ret = pm_runtime_get_sync(dev);
1264 if (ret < 0) {
1265 dev_err(dev, "pm_runtime_get_sync failed\n");
1266 goto err_get_sync;
1267 }
1268
1269 ret = wiz_clock_init(wiz, node);
1270 if (ret < 0) {
1271 dev_warn(dev, "Failed to initialize clocks\n");
1272 goto err_get_sync;
1273 }
1274
1275 for (i = 0; i < wiz->num_lanes; i++) {
1276 regmap_field_read(wiz->p_enable[i], &val);
1277 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1278 already_configured = true;
1279 break;
1280 }
1281 }
1282
1283 if (!already_configured) {
1284 ret = wiz_init(wiz);
1285 if (ret) {
1286 dev_err(dev, "WIZ initialization failed\n");
1287 goto err_wiz_init;
1288 }
1289 }
1290
1291 serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1292 if (!serdes_pdev) {
1293 dev_WARN(dev, "Unable to create SERDES platform device\n");
1294 ret = -ENOMEM;
1295 goto err_wiz_init;
1296 }
1297 wiz->serdes_pdev = serdes_pdev;
1298
1299 of_node_put(child_node);
1300 return 0;
1301
1302err_wiz_init:
1303 wiz_clock_cleanup(wiz, node);
1304
1305err_get_sync:
1306 pm_runtime_put(dev);
1307 pm_runtime_disable(dev);
1308
1309err_addr_to_resource:
1310 of_node_put(child_node);
1311
1312 return ret;
1313}
1314
1315static int wiz_remove(struct platform_device *pdev)
1316{
1317 struct device *dev = &pdev->dev;
1318 struct device_node *node = dev->of_node;
1319 struct platform_device *serdes_pdev;
1320 struct wiz *wiz;
1321
1322 wiz = dev_get_drvdata(dev);
1323 serdes_pdev = wiz->serdes_pdev;
1324
1325 of_platform_device_destroy(&serdes_pdev->dev, NULL);
1326 wiz_clock_cleanup(wiz, node);
1327 pm_runtime_put(dev);
1328 pm_runtime_disable(dev);
1329
1330 return 0;
1331}
1332
1333static struct platform_driver wiz_driver = {
1334 .probe = wiz_probe,
1335 .remove = wiz_remove,
1336 .driver = {
1337 .name = "wiz",
1338 .of_match_table = wiz_id_table,
1339 },
1340};
1341module_platform_driver(wiz_driver);
1342
1343MODULE_AUTHOR("Texas Instruments Inc.");
1344MODULE_DESCRIPTION("TI J721E WIZ driver");
1345MODULE_LICENSE("GPL v2");
1346
