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9#include <linux/bits.h>
10#include <linux/gpio/driver.h>
11#include <linux/kernel.h>
12#include <linux/of.h>
13#include <linux/pinctrl/pinmux.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16
17#include "../pinctrl-utils.h"
18
19#include "pinctrl-bcm63xx.h"
20
21#define BCM63268_NUM_GPIOS 52
22#define BCM63268_NUM_LEDS 24
23
24#define BCM63268_LED_REG 0x10
25#define BCM63268_MODE_REG 0x18
26#define BCM63268_CTRL_REG 0x1c
27#define BCM63268_BASEMODE_REG 0x38
28#define BCM63268_BASEMODE_NAND BIT(2)
29#define BCM63268_BASEMODE_GPIO35 BIT(4)
30#define BCM63268_BASEMODE_DECTPD BIT(5)
31#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6)
32#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7)
33#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8)
34#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9)
35
36enum bcm63268_pinctrl_reg {
37 BCM63268_LEDCTRL,
38 BCM63268_MODE,
39 BCM63268_CTRL,
40 BCM63268_BASEMODE,
41};
42
43struct bcm63268_pingroup {
44 const char *name;
45 const unsigned * const pins;
46 const unsigned num_pins;
47};
48
49struct bcm63268_function {
50 const char *name;
51 const char * const *groups;
52 const unsigned num_groups;
53
54 enum bcm63268_pinctrl_reg reg;
55 uint32_t mask;
56};
57
58#define BCM63268_PIN(a, b, basemode) \
59 { \
60 .number = a, \
61 .name = b, \
62 .drv_data = (void *)(basemode) \
63 }
64
65static const struct pinctrl_pin_desc bcm63268_pins[] = {
66 PINCTRL_PIN(0, "gpio0"),
67 PINCTRL_PIN(1, "gpio1"),
68 BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
69 BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
70 BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
71 BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
72 BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
73 BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
74 BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
75 BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
76 BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
77 BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
78 BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
79 BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
80 PINCTRL_PIN(14, "gpio14"),
81 PINCTRL_PIN(15, "gpio15"),
82 PINCTRL_PIN(16, "gpio16"),
83 PINCTRL_PIN(17, "gpio17"),
84 PINCTRL_PIN(18, "gpio18"),
85 PINCTRL_PIN(19, "gpio19"),
86 PINCTRL_PIN(20, "gpio20"),
87 PINCTRL_PIN(21, "gpio21"),
88 PINCTRL_PIN(22, "gpio22"),
89 PINCTRL_PIN(23, "gpio23"),
90 BCM63268_PIN(24, "gpio24",
91 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
92 BCM63268_PIN(25, "gpio25",
93 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
94 BCM63268_PIN(26, "gpio26",
95 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
96 BCM63268_PIN(27, "gpio27",
97 BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
98 BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
99 BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
100 BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
101 BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
102 PINCTRL_PIN(32, "gpio32"),
103 PINCTRL_PIN(33, "gpio33"),
104 PINCTRL_PIN(34, "gpio34"),
105 PINCTRL_PIN(35, "gpio35"),
106 PINCTRL_PIN(36, "gpio36"),
107 PINCTRL_PIN(37, "gpio37"),
108 PINCTRL_PIN(38, "gpio38"),
109 PINCTRL_PIN(39, "gpio39"),
110 PINCTRL_PIN(40, "gpio40"),
111 PINCTRL_PIN(41, "gpio41"),
112 PINCTRL_PIN(42, "gpio42"),
113 PINCTRL_PIN(43, "gpio43"),
114 PINCTRL_PIN(44, "gpio44"),
115 PINCTRL_PIN(45, "gpio45"),
116 PINCTRL_PIN(46, "gpio46"),
117 PINCTRL_PIN(47, "gpio47"),
118 PINCTRL_PIN(48, "gpio48"),
119 PINCTRL_PIN(49, "gpio49"),
120 PINCTRL_PIN(50, "gpio50"),
121 PINCTRL_PIN(51, "gpio51"),
122};
123
124static unsigned gpio0_pins[] = { 0 };
125static unsigned gpio1_pins[] = { 1 };
126static unsigned gpio2_pins[] = { 2 };
127static unsigned gpio3_pins[] = { 3 };
128static unsigned gpio4_pins[] = { 4 };
129static unsigned gpio5_pins[] = { 5 };
130static unsigned gpio6_pins[] = { 6 };
131static unsigned gpio7_pins[] = { 7 };
132static unsigned gpio8_pins[] = { 8 };
133static unsigned gpio9_pins[] = { 9 };
134static unsigned gpio10_pins[] = { 10 };
135static unsigned gpio11_pins[] = { 11 };
136static unsigned gpio12_pins[] = { 12 };
137static unsigned gpio13_pins[] = { 13 };
138static unsigned gpio14_pins[] = { 14 };
139static unsigned gpio15_pins[] = { 15 };
140static unsigned gpio16_pins[] = { 16 };
141static unsigned gpio17_pins[] = { 17 };
142static unsigned gpio18_pins[] = { 18 };
143static unsigned gpio19_pins[] = { 19 };
144static unsigned gpio20_pins[] = { 20 };
145static unsigned gpio21_pins[] = { 21 };
146static unsigned gpio22_pins[] = { 22 };
147static unsigned gpio23_pins[] = { 23 };
148static unsigned gpio24_pins[] = { 24 };
149static unsigned gpio25_pins[] = { 25 };
150static unsigned gpio26_pins[] = { 26 };
151static unsigned gpio27_pins[] = { 27 };
152static unsigned gpio28_pins[] = { 28 };
153static unsigned gpio29_pins[] = { 29 };
154static unsigned gpio30_pins[] = { 30 };
155static unsigned gpio31_pins[] = { 31 };
156static unsigned gpio32_pins[] = { 32 };
157static unsigned gpio33_pins[] = { 33 };
158static unsigned gpio34_pins[] = { 34 };
159static unsigned gpio35_pins[] = { 35 };
160static unsigned gpio36_pins[] = { 36 };
161static unsigned gpio37_pins[] = { 37 };
162static unsigned gpio38_pins[] = { 38 };
163static unsigned gpio39_pins[] = { 39 };
164static unsigned gpio40_pins[] = { 40 };
165static unsigned gpio41_pins[] = { 41 };
166static unsigned gpio42_pins[] = { 42 };
167static unsigned gpio43_pins[] = { 43 };
168static unsigned gpio44_pins[] = { 44 };
169static unsigned gpio45_pins[] = { 45 };
170static unsigned gpio46_pins[] = { 46 };
171static unsigned gpio47_pins[] = { 47 };
172static unsigned gpio48_pins[] = { 48 };
173static unsigned gpio49_pins[] = { 49 };
174static unsigned gpio50_pins[] = { 50 };
175static unsigned gpio51_pins[] = { 51 };
176
177static unsigned nand_grp_pins[] = {
178 2, 3, 4, 5, 6, 7, 24,
179 25, 26, 27, 28, 29, 30, 31,
180};
181
182static unsigned dectpd_grp_pins[] = { 8, 9 };
183static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
184static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
185static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
186static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
187
188#define BCM63268_GROUP(n) \
189 { \
190 .name = #n, \
191 .pins = n##_pins, \
192 .num_pins = ARRAY_SIZE(n##_pins), \
193 }
194
195static struct bcm63268_pingroup bcm63268_groups[] = {
196 BCM63268_GROUP(gpio0),
197 BCM63268_GROUP(gpio1),
198 BCM63268_GROUP(gpio2),
199 BCM63268_GROUP(gpio3),
200 BCM63268_GROUP(gpio4),
201 BCM63268_GROUP(gpio5),
202 BCM63268_GROUP(gpio6),
203 BCM63268_GROUP(gpio7),
204 BCM63268_GROUP(gpio8),
205 BCM63268_GROUP(gpio9),
206 BCM63268_GROUP(gpio10),
207 BCM63268_GROUP(gpio11),
208 BCM63268_GROUP(gpio12),
209 BCM63268_GROUP(gpio13),
210 BCM63268_GROUP(gpio14),
211 BCM63268_GROUP(gpio15),
212 BCM63268_GROUP(gpio16),
213 BCM63268_GROUP(gpio17),
214 BCM63268_GROUP(gpio18),
215 BCM63268_GROUP(gpio19),
216 BCM63268_GROUP(gpio20),
217 BCM63268_GROUP(gpio21),
218 BCM63268_GROUP(gpio22),
219 BCM63268_GROUP(gpio23),
220 BCM63268_GROUP(gpio24),
221 BCM63268_GROUP(gpio25),
222 BCM63268_GROUP(gpio26),
223 BCM63268_GROUP(gpio27),
224 BCM63268_GROUP(gpio28),
225 BCM63268_GROUP(gpio29),
226 BCM63268_GROUP(gpio30),
227 BCM63268_GROUP(gpio31),
228 BCM63268_GROUP(gpio32),
229 BCM63268_GROUP(gpio33),
230 BCM63268_GROUP(gpio34),
231 BCM63268_GROUP(gpio35),
232 BCM63268_GROUP(gpio36),
233 BCM63268_GROUP(gpio37),
234 BCM63268_GROUP(gpio38),
235 BCM63268_GROUP(gpio39),
236 BCM63268_GROUP(gpio40),
237 BCM63268_GROUP(gpio41),
238 BCM63268_GROUP(gpio42),
239 BCM63268_GROUP(gpio43),
240 BCM63268_GROUP(gpio44),
241 BCM63268_GROUP(gpio45),
242 BCM63268_GROUP(gpio46),
243 BCM63268_GROUP(gpio47),
244 BCM63268_GROUP(gpio48),
245 BCM63268_GROUP(gpio49),
246 BCM63268_GROUP(gpio50),
247 BCM63268_GROUP(gpio51),
248
249
250 BCM63268_GROUP(nand_grp),
251 BCM63268_GROUP(dectpd_grp),
252 BCM63268_GROUP(vdsl_phy0_grp),
253 BCM63268_GROUP(vdsl_phy1_grp),
254 BCM63268_GROUP(vdsl_phy2_grp),
255 BCM63268_GROUP(vdsl_phy3_grp),
256};
257
258static const char * const led_groups[] = {
259 "gpio0",
260 "gpio1",
261 "gpio2",
262 "gpio3",
263 "gpio4",
264 "gpio5",
265 "gpio6",
266 "gpio7",
267 "gpio8",
268 "gpio9",
269 "gpio10",
270 "gpio11",
271 "gpio12",
272 "gpio13",
273 "gpio14",
274 "gpio15",
275 "gpio16",
276 "gpio17",
277 "gpio18",
278 "gpio19",
279 "gpio20",
280 "gpio21",
281 "gpio22",
282 "gpio23",
283};
284
285static const char * const serial_led_clk_groups[] = {
286 "gpio0",
287};
288
289static const char * const serial_led_data_groups[] = {
290 "gpio1",
291};
292
293static const char * const hsspi_cs4_groups[] = {
294 "gpio16",
295};
296
297static const char * const hsspi_cs5_groups[] = {
298 "gpio17",
299};
300
301static const char * const hsspi_cs6_groups[] = {
302 "gpio8",
303};
304
305static const char * const hsspi_cs7_groups[] = {
306 "gpio9",
307};
308
309static const char * const uart1_scts_groups[] = {
310 "gpio10",
311 "gpio24",
312};
313
314static const char * const uart1_srts_groups[] = {
315 "gpio11",
316 "gpio25",
317};
318
319static const char * const uart1_sdin_groups[] = {
320 "gpio12",
321 "gpio26",
322};
323
324static const char * const uart1_sdout_groups[] = {
325 "gpio13",
326 "gpio27",
327};
328
329static const char * const ntr_pulse_in_groups[] = {
330 "gpio14",
331 "gpio28",
332};
333
334static const char * const dsl_ntr_pulse_out_groups[] = {
335 "gpio15",
336 "gpio29",
337};
338
339static const char * const adsl_spi_miso_groups[] = {
340 "gpio18",
341};
342
343static const char * const adsl_spi_mosi_groups[] = {
344 "gpio19",
345};
346
347static const char * const vreg_clk_groups[] = {
348 "gpio22",
349};
350
351static const char * const pcie_clkreq_b_groups[] = {
352 "gpio23",
353};
354
355static const char * const switch_led_clk_groups[] = {
356 "gpio30",
357};
358
359static const char * const switch_led_data_groups[] = {
360 "gpio31",
361};
362
363static const char * const wifi_groups[] = {
364 "gpio32",
365 "gpio33",
366 "gpio34",
367 "gpio35",
368 "gpio36",
369 "gpio37",
370 "gpio38",
371 "gpio39",
372 "gpio40",
373 "gpio41",
374 "gpio42",
375 "gpio43",
376 "gpio44",
377 "gpio45",
378 "gpio46",
379 "gpio47",
380 "gpio48",
381 "gpio49",
382 "gpio50",
383 "gpio51",
384};
385
386static const char * const nand_groups[] = {
387 "nand_grp",
388};
389
390static const char * const dectpd_groups[] = {
391 "dectpd_grp",
392};
393
394static const char * const vdsl_phy_override_0_groups[] = {
395 "vdsl_phy_override_0_grp",
396};
397
398static const char * const vdsl_phy_override_1_groups[] = {
399 "vdsl_phy_override_1_grp",
400};
401
402static const char * const vdsl_phy_override_2_groups[] = {
403 "vdsl_phy_override_2_grp",
404};
405
406static const char * const vdsl_phy_override_3_groups[] = {
407 "vdsl_phy_override_3_grp",
408};
409
410#define BCM63268_LED_FUN(n) \
411 { \
412 .name = #n, \
413 .groups = n##_groups, \
414 .num_groups = ARRAY_SIZE(n##_groups), \
415 .reg = BCM63268_LEDCTRL, \
416 }
417
418#define BCM63268_MODE_FUN(n) \
419 { \
420 .name = #n, \
421 .groups = n##_groups, \
422 .num_groups = ARRAY_SIZE(n##_groups), \
423 .reg = BCM63268_MODE, \
424 }
425
426#define BCM63268_CTRL_FUN(n) \
427 { \
428 .name = #n, \
429 .groups = n##_groups, \
430 .num_groups = ARRAY_SIZE(n##_groups), \
431 .reg = BCM63268_CTRL, \
432 }
433
434#define BCM63268_BASEMODE_FUN(n, val) \
435 { \
436 .name = #n, \
437 .groups = n##_groups, \
438 .num_groups = ARRAY_SIZE(n##_groups), \
439 .reg = BCM63268_BASEMODE, \
440 .mask = val, \
441 }
442
443static const struct bcm63268_function bcm63268_funcs[] = {
444 BCM63268_LED_FUN(led),
445 BCM63268_MODE_FUN(serial_led_clk),
446 BCM63268_MODE_FUN(serial_led_data),
447 BCM63268_MODE_FUN(hsspi_cs6),
448 BCM63268_MODE_FUN(hsspi_cs7),
449 BCM63268_MODE_FUN(uart1_scts),
450 BCM63268_MODE_FUN(uart1_srts),
451 BCM63268_MODE_FUN(uart1_sdin),
452 BCM63268_MODE_FUN(uart1_sdout),
453 BCM63268_MODE_FUN(ntr_pulse_in),
454 BCM63268_MODE_FUN(dsl_ntr_pulse_out),
455 BCM63268_MODE_FUN(hsspi_cs4),
456 BCM63268_MODE_FUN(hsspi_cs5),
457 BCM63268_MODE_FUN(adsl_spi_miso),
458 BCM63268_MODE_FUN(adsl_spi_mosi),
459 BCM63268_MODE_FUN(vreg_clk),
460 BCM63268_MODE_FUN(pcie_clkreq_b),
461 BCM63268_MODE_FUN(switch_led_clk),
462 BCM63268_MODE_FUN(switch_led_data),
463 BCM63268_CTRL_FUN(wifi),
464 BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
465 BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
466 BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
467 BCM63268_BASEMODE_VDSL_PHY_0),
468 BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
469 BCM63268_BASEMODE_VDSL_PHY_1),
470 BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
471 BCM63268_BASEMODE_VDSL_PHY_2),
472 BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
473 BCM63268_BASEMODE_VDSL_PHY_3),
474};
475
476static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
477{
478 return ARRAY_SIZE(bcm63268_groups);
479}
480
481static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
482 unsigned group)
483{
484 return bcm63268_groups[group].name;
485}
486
487static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
488 unsigned group,
489 const unsigned **pins,
490 unsigned *num_pins)
491{
492 *pins = bcm63268_groups[group].pins;
493 *num_pins = bcm63268_groups[group].num_pins;
494
495 return 0;
496}
497
498static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
499{
500 return ARRAY_SIZE(bcm63268_funcs);
501}
502
503static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
504 unsigned selector)
505{
506 return bcm63268_funcs[selector].name;
507}
508
509static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
510 unsigned selector,
511 const char * const **groups,
512 unsigned * const num_groups)
513{
514 *groups = bcm63268_funcs[selector].groups;
515 *num_groups = bcm63268_funcs[selector].num_groups;
516
517 return 0;
518}
519
520static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
521{
522 const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
523 unsigned int basemode = (unsigned long) desc->drv_data;
524 unsigned int mask = BIT(bcm63xx_bank_pin(pin));
525
526 if (basemode)
527 regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
528 0);
529
530 if (pin < BCM63XX_BANK_GPIOS) {
531
532 regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
533
534
535 if (pin < BCM63268_NUM_LEDS)
536 regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
537 0);
538 } else if (pin < BCM63268_NUM_GPIOS) {
539
540 regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
541 }
542}
543
544static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
545 unsigned selector, unsigned group)
546{
547 struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
548 const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
549 const struct bcm63268_function *f = &bcm63268_funcs[selector];
550 unsigned i;
551 unsigned int reg;
552 unsigned int val, mask;
553
554 for (i = 0; i < pg->num_pins; i++)
555 bcm63268_set_gpio(pc, pg->pins[i]);
556
557 switch (f->reg) {
558 case BCM63268_LEDCTRL:
559 reg = BCM63268_LED_REG;
560 mask = BIT(pg->pins[0]);
561 val = BIT(pg->pins[0]);
562 break;
563 case BCM63268_MODE:
564 reg = BCM63268_MODE_REG;
565 mask = BIT(pg->pins[0]);
566 val = BIT(pg->pins[0]);
567 break;
568 case BCM63268_CTRL:
569 reg = BCM63268_CTRL_REG;
570 mask = BIT(pg->pins[0]);
571 val = 0;
572 break;
573 case BCM63268_BASEMODE:
574 reg = BCM63268_BASEMODE_REG;
575 mask = f->mask;
576 val = f->mask;
577 break;
578 default:
579 WARN_ON(1);
580 return -EINVAL;
581 }
582
583 regmap_update_bits(pc->regs, reg, mask, val);
584
585 return 0;
586}
587
588static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
589 struct pinctrl_gpio_range *range,
590 unsigned offset)
591{
592 struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
593
594
595 bcm63268_set_gpio(pc, offset);
596
597 return 0;
598}
599
600static const struct pinctrl_ops bcm63268_pctl_ops = {
601 .dt_free_map = pinctrl_utils_free_map,
602 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
603 .get_group_name = bcm63268_pinctrl_get_group_name,
604 .get_group_pins = bcm63268_pinctrl_get_group_pins,
605 .get_groups_count = bcm63268_pinctrl_get_group_count,
606};
607
608static const struct pinmux_ops bcm63268_pmx_ops = {
609 .get_function_groups = bcm63268_pinctrl_get_groups,
610 .get_function_name = bcm63268_pinctrl_get_func_name,
611 .get_functions_count = bcm63268_pinctrl_get_func_count,
612 .gpio_request_enable = bcm63268_gpio_request_enable,
613 .set_mux = bcm63268_pinctrl_set_mux,
614 .strict = true,
615};
616
617static const struct bcm63xx_pinctrl_soc bcm63268_soc = {
618 .ngpios = BCM63268_NUM_GPIOS,
619 .npins = ARRAY_SIZE(bcm63268_pins),
620 .pctl_ops = &bcm63268_pctl_ops,
621 .pins = bcm63268_pins,
622 .pmx_ops = &bcm63268_pmx_ops,
623};
624
625static int bcm63268_pinctrl_probe(struct platform_device *pdev)
626{
627 return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);
628}
629
630static const struct of_device_id bcm63268_pinctrl_match[] = {
631 { .compatible = "brcm,bcm63268-pinctrl", },
632 { }
633};
634
635static struct platform_driver bcm63268_pinctrl_driver = {
636 .probe = bcm63268_pinctrl_probe,
637 .driver = {
638 .name = "bcm63268-pinctrl",
639 .of_match_table = bcm63268_pinctrl_match,
640 },
641};
642
643builtin_platform_driver(bcm63268_pinctrl_driver);
644
