LXR linux/drivers/pinctrl/pinctrl-rockchip.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
   4 *
   5 * Copyright (c) 2013 MundoReader S.L.
   6 * Author: Heiko Stuebner <heiko@sntech.de>
   7 *
   8 * With some ideas taken from pinctrl-samsung:
   9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10 *              http://www.samsung.com
  11 * Copyright (c) 2012 Linaro Ltd
  12 *              https://www.linaro.org
  13 *
  14 * and pinctrl-at91:
  15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16 */
  17
  18#ifndef _PINCTRL_ROCKCHIP_H
  19#define _PINCTRL_ROCKCHIP_H
  20
  21enum rockchip_pinctrl_type {
  22        PX30,
  23        RV1108,
  24        RK2928,
  25        RK3066B,
  26        RK3128,
  27        RK3188,
  28        RK3288,
  29        RK3308,
  30        RK3368,
  31        RK3399,
  32        RK3568,
  33};
  34
  35/**
  36 * struct rockchip_gpio_regs
  37 * @port_dr: data register
  38 * @port_ddr: data direction register
  39 * @int_en: interrupt enable
  40 * @int_mask: interrupt mask
  41 * @int_type: interrupt trigger type, such as high, low, edge trriger type.
  42 * @int_polarity: interrupt polarity enable register
  43 * @int_bothedge: interrupt bothedge enable register
  44 * @int_status: interrupt status register
  45 * @int_rawstatus: int_status = int_rawstatus & int_mask
  46 * @debounce: enable debounce for interrupt signal
  47 * @dbclk_div_en: enable divider for debounce clock
  48 * @dbclk_div_con: setting for divider of debounce clock
  49 * @port_eoi: end of interrupt of the port
  50 * @ext_port: port data from external
  51 * @version_id: controller version register
  52 */
  53struct rockchip_gpio_regs {
  54        u32 port_dr;
  55        u32 port_ddr;
  56        u32 int_en;
  57        u32 int_mask;
  58        u32 int_type;
  59        u32 int_polarity;
  60        u32 int_bothedge;
  61        u32 int_status;
  62        u32 int_rawstatus;
  63        u32 debounce;
  64        u32 dbclk_div_en;
  65        u32 dbclk_div_con;
  66        u32 port_eoi;
  67        u32 ext_port;
  68        u32 version_id;
  69};
  70
  71/**
  72 * struct rockchip_iomux
  73 * @type: iomux variant using IOMUX_* constants
  74 * @offset: if initialized to -1 it will be autocalculated, by specifying
  75 *          an initial offset value the relevant source offset can be reset
  76 *          to a new value for autocalculating the following iomux registers.
  77 */
  78struct rockchip_iomux {
  79        int type;
  80        int offset;
  81};
  82
  83/*
  84 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  85 */
  86enum rockchip_pin_drv_type {
  87        DRV_TYPE_IO_DEFAULT = 0,
  88        DRV_TYPE_IO_1V8_OR_3V0,
  89        DRV_TYPE_IO_1V8_ONLY,
  90        DRV_TYPE_IO_1V8_3V0_AUTO,
  91        DRV_TYPE_IO_3V3_ONLY,
  92        DRV_TYPE_MAX
  93};
  94
  95/*
  96 * enum type index corresponding to rockchip_pull_list arrays index.
  97 */
  98enum rockchip_pin_pull_type {
  99        PULL_TYPE_IO_DEFAULT = 0,
 100        PULL_TYPE_IO_1V8_ONLY,
 101        PULL_TYPE_MAX
 102};
 103
 104/**
 105 * struct rockchip_drv
 106 * @drv_type: drive strength variant using rockchip_perpin_drv_type
 107 * @offset: if initialized to -1 it will be autocalculated, by specifying
 108 *          an initial offset value the relevant source offset can be reset
 109 *          to a new value for autocalculating the following drive strength
 110 *          registers. if used chips own cal_drv func instead to calculate
 111 *          registers offset, the variant could be ignored.
 112 */
 113struct rockchip_drv {
 114        enum rockchip_pin_drv_type      drv_type;
 115        int                             offset;
 116};
 117
 118/**
 119 * struct rockchip_pin_bank
 120 * @dev: the pinctrl device bind to the bank
 121 * @reg_base: register base of the gpio bank
 122 * @regmap_pull: optional separate register for additional pull settings
 123 * @clk: clock of the gpio bank
 124 * @db_clk: clock of the gpio debounce
 125 * @irq: interrupt of the gpio bank
 126 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 127 * @pin_base: first pin number
 128 * @nr_pins: number of pins in this bank
 129 * @name: name of the bank
 130 * @bank_num: number of the bank, to account for holes
 131 * @iomux: array describing the 4 iomux sources of the bank
 132 * @drv: array describing the 4 drive strength sources of the bank
 133 * @pull_type: array describing the 4 pull type sources of the bank
 134 * @valid: is all necessary information present
 135 * @of_node: dt node of this bank
 136 * @drvdata: common pinctrl basedata
 137 * @domain: irqdomain of the gpio bank
 138 * @gpio_chip: gpiolib chip
 139 * @grange: gpio range
 140 * @slock: spinlock for the gpio bank
 141 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 142 * @recalced_mask: bit mask to indicate a need to recalulate the mask
 143 * @route_mask: bits describing the routing pins of per bank
 144 * @deferred_output: gpio output settings to be done after gpio bank probed
 145 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
 146 */
 147struct rockchip_pin_bank {
 148        struct device                   *dev;
 149        void __iomem                    *reg_base;
 150        struct regmap                   *regmap_pull;
 151        struct clk                      *clk;
 152        struct clk                      *db_clk;
 153        int                             irq;
 154        u32                             saved_masks;
 155        u32                             pin_base;
 156        u8                              nr_pins;
 157        char                            *name;
 158        u8                              bank_num;
 159        struct rockchip_iomux           iomux[4];
 160        struct rockchip_drv             drv[4];
 161        enum rockchip_pin_pull_type     pull_type[4];
 162        bool                            valid;
 163        struct device_node              *of_node;
 164        struct rockchip_pinctrl         *drvdata;
 165        struct irq_domain               *domain;
 166        struct gpio_chip                gpio_chip;
 167        struct pinctrl_gpio_range       grange;
 168        raw_spinlock_t                  slock;
 169        const struct rockchip_gpio_regs *gpio_regs;
 170        u32                             gpio_type;
 171        u32                             toggle_edge_mode;
 172        u32                             recalced_mask;
 173        u32                             route_mask;
 174        struct list_head                deferred_output;
 175        struct mutex                    deferred_lock;
 176};
 177
 178/**
 179 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 180 * @num: bank number.
 181 * @pin: pin number.
 182 * @bit: index at register.
 183 * @reg: register offset.
 184 * @mask: mask bit
 185 */
 186struct rockchip_mux_recalced_data {
 187        u8 num;
 188        u8 pin;
 189        u32 reg;
 190        u8 bit;
 191        u8 mask;
 192};
 193
 194enum rockchip_mux_route_location {
 195        ROCKCHIP_ROUTE_SAME = 0,
 196        ROCKCHIP_ROUTE_PMU,
 197        ROCKCHIP_ROUTE_GRF,
 198};
 199
 200/**
 201 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 202 * @bank_num: bank number.
 203 * @pin: index at register or used to calc index.
 204 * @func: the min pin.
 205 * @route_location: the mux route location (same, pmu, grf).
 206 * @route_offset: the max pin.
 207 * @route_val: the register offset.
 208 */
 209struct rockchip_mux_route_data {
 210        u8 bank_num;
 211        u8 pin;
 212        u8 func;
 213        enum rockchip_mux_route_location route_location;
 214        u32 route_offset;
 215        u32 route_val;
 216};
 217
 218struct rockchip_pin_ctrl {
 219        struct rockchip_pin_bank        *pin_banks;
 220        u32                             nr_banks;
 221        u32                             nr_pins;
 222        char                            *label;
 223        enum rockchip_pinctrl_type      type;
 224        int                             grf_mux_offset;
 225        int                             pmu_mux_offset;
 226        int                             grf_drv_offset;
 227        int                             pmu_drv_offset;
 228        struct rockchip_mux_recalced_data *iomux_recalced;
 229        u32                             niomux_recalced;
 230        struct rockchip_mux_route_data *iomux_routes;
 231        u32                             niomux_routes;
 232
 233        void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 234                                    int pin_num, struct regmap **regmap,
 235                                    int *reg, u8 *bit);
 236        void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 237                                    int pin_num, struct regmap **regmap,
 238                                    int *reg, u8 *bit);
 239        int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 240                                    int pin_num, struct regmap **regmap,
 241                                    int *reg, u8 *bit);
 242};
 243
 244struct rockchip_pin_config {
 245        unsigned int            func;
 246        unsigned long           *configs;
 247        unsigned int            nconfigs;
 248};
 249
 250struct rockchip_pin_output_deferred {
 251        struct list_head head;
 252        unsigned int pin;
 253        u32 arg;
 254};
 255
 256/**
 257 * struct rockchip_pin_group: represent group of pins of a pinmux function.
 258 * @name: name of the pin group, used to lookup the group.
 259 * @pins: the pins included in this group.
 260 * @npins: number of pins included in this group.
 261 * @data: local pin configuration
 262 */
 263struct rockchip_pin_group {
 264        const char                      *name;
 265        unsigned int                    npins;
 266        unsigned int                    *pins;
 267        struct rockchip_pin_config      *data;
 268};
 269
 270/**
 271 * struct rockchip_pmx_func: represent a pin function.
 272 * @name: name of the pin function, used to lookup the function.
 273 * @groups: one or more names of pin groups that provide this function.
 274 * @ngroups: number of groups included in @groups.
 275 */
 276struct rockchip_pmx_func {
 277        const char              *name;
 278        const char              **groups;
 279        u8                      ngroups;
 280};
 281
 282struct rockchip_pinctrl {
 283        struct regmap                   *regmap_base;
 284        int                             reg_size;
 285        struct regmap                   *regmap_pull;
 286        struct regmap                   *regmap_pmu;
 287        struct device                   *dev;
 288        struct rockchip_pin_ctrl        *ctrl;
 289        struct pinctrl_desc             pctl;
 290        struct pinctrl_dev              *pctl_dev;
 291        struct rockchip_pin_group       *groups;
 292        unsigned int                    ngroups;
 293        struct rockchip_pmx_func        *functions;
 294        unsigned int                    nfunctions;
 295};
 296
 297#endif
 298