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6
7
8#include <linux/errno.h>
9#include <linux/kernel.h>
10
11#include "sh_pfc.h"
12
13#define CPU_ALL_GP(fn, sfx) \
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
30 PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
31 PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
32 PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
33 PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
34 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
36 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
37 PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38 PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
39 PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
40 PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
41 PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
42 PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
43 PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
44 PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
45 PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
46 PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
47 PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
48 PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
49 PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
50 PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
51 PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
52 PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
53 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
54
55#define CPU_ALL_NOGP(fn) \
56 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
57 PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP), \
58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
59 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
60 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
61 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
62 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
63 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
64
65enum {
66 PINMUX_RESERVED = 0,
67
68 PINMUX_DATA_BEGIN,
69 GP_ALL(DATA),
70 PINMUX_DATA_END,
71
72 PINMUX_FUNCTION_BEGIN,
73 GP_ALL(FN),
74
75
76 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
77 FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
78 FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
79 FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
80 FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
81 FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
82
83
84 FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
85 FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
86 FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
87 FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
88 FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
89
90
91 FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
92 FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
93 FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
94 FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
95 FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
96 FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
97 FN_IP7_31_28, FN_IP8_3_0,
98
99
100 FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
101 FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
102 FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
103 FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
104
105
106 FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
107 FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
108 FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
109 FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
110 FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
111 FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
112
113
114 FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
115 FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
116 FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
117 FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
118 FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
119 FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
120 FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
121
122
123 FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
124 FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
125 FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
126 FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
127 FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
128 FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
129 FN_SD0_CD, FN_CAN0_RX_A,
130 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
131
132
133 FN_MMC0_D4, FN_SD1_CD,
134 FN_MMC0_D5, FN_SD1_WP,
135 FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
136 FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
137 FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
138 FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
139 FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
140 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
141
142
143 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
144 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
145 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
146 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
147 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
148 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
149 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
150 FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
151
152
153 FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
154 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
155 FN_QSPI0_SPCLK, FN_WE0_N,
156 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
157 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
158 FN_QSPI0_IO2, FN_CS0_N,
159 FN_QSPI0_IO3, FN_RD_N,
160 FN_QSPI0_SSL, FN_WE1_N,
161
162
163 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
164 FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
165 FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
166 FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
167 FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
168 FN_DU0_DR4, FN_RX1_D, FN_A4,
169 FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
170 FN_DU0_DR6, FN_RX2_C, FN_A6,
171
172
173 FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
174 FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
175 FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
176 FN_DU0_DG2, FN_RX4_D, FN_A10,
177 FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
178 FN_DU0_DG4, FN_HRX0_A, FN_A12,
179 FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
180 FN_DU0_DG6, FN_HRX1_C, FN_A14,
181
182
183 FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
184 FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
185 FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
186 FN_DU0_DB2, FN_HCTS0_N, FN_A18,
187 FN_DU0_DB3, FN_HRTS0_N, FN_A19,
188 FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
189 FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
190 FN_DU0_DB6, FN_A22,
191
192
193 FN_DU0_DB7, FN_A23,
194 FN_DU0_DOTCLKIN, FN_A24,
195 FN_DU0_DOTCLKOUT0, FN_A25,
196 FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
197 FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
198 FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
199 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
200 FN_DU0_DISP, FN_CAN1_RX_C,
201
202
203 FN_DU0_CDE, FN_CAN1_TX_C,
204 FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
205 FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
206 FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
207 FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
208 FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
209 FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
210 FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
211
212
213 FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
214 FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
215 FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
216 FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
217 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
218 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
219 FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
220 FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
221
222
223 FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
224 FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
225 FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
226 FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
227 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
228 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
229 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
230 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
231
232
233 FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
234 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
235 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
236 FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
237 FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
238 FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
239 FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
240 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
241
242
243 FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
244 FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
245 FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
246 FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
247 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
248 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
249 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
250 FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
251
252
253 FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
254 FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
255 FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
256 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
257 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
258 FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
259 FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
260 FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
261
262
263 FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
264 FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
265 FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
266 FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
267 FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
268 FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
269 FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
270 FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
271
272
273 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
274 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
275 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
276 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
277 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
278 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
279 FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
280 FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
281
282
283 FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
284 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
285 FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
286 FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
287 FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
288 FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
289 FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
290 FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
291
292
293 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
294 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
295 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
296 FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
297 FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
298 FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
299 FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
300
301
302 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
303 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
304 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
305 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
306 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
307 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
308 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
309 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
310 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
311 FN_SEL_AVB_0, FN_SEL_AVB_1,
312
313
314 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
315 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
316 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
317 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
318 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
319 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
320 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
321 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
322 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
323 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
324 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
325 FN_SEL_RCN_0, FN_SEL_RCN_1,
326 FN_SEL_TMU2_0, FN_SEL_TMU2_1,
327 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
328 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
329 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
330
331
332 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
333 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
334 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
335 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
336 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
337 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
338 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
339 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
340 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
341 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
342 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
343 PINMUX_FUNCTION_END,
344
345 PINMUX_MARK_BEGIN,
346
347 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
348 CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
349 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
350 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
351 MMC0_D7_MARK,
352
353
354 SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
355 SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
356 SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
357 SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
358 SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
359 SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
360 SD0_CD_MARK, CAN0_RX_A_MARK,
361 SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
362
363
364 MMC0_D4_MARK, SD1_CD_MARK,
365 MMC0_D5_MARK, SD1_WP_MARK,
366 D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
367 D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
368 D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
369 D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
370 D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
371 D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
372
373
374 D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
375 D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
376 D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
377 D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
378 D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
379 D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
380 D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
381 D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
382
383
384 D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
385 D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
386 QSPI0_SPCLK_MARK, WE0_N_MARK,
387 QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
388 QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
389 QSPI0_IO2_MARK, CS0_N_MARK,
390 QSPI0_IO3_MARK, RD_N_MARK,
391 QSPI0_SSL_MARK, WE1_N_MARK,
392
393
394 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
395 DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
396 DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
397 DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
398 DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
399 DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
400 DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
401 DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
402
403
404 DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
405 DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
406 DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
407 DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
408 DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
409 DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
410 DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
411 DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
412
413
414 DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
415 DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
416 DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
417 DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
418 DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
419 DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
420 DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
421 DU0_DB6_MARK, A22_MARK,
422
423
424 DU0_DB7_MARK, A23_MARK,
425 DU0_DOTCLKIN_MARK, A24_MARK,
426 DU0_DOTCLKOUT0_MARK, A25_MARK,
427 DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
428 DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
429 DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
430 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
431 DU0_DISP_MARK, CAN1_RX_C_MARK,
432
433
434 DU0_CDE_MARK, CAN1_TX_C_MARK,
435 VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
436 VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
437 VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
438 VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
439 VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
440 VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
441 VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
442
443
444 VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
445 VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
446 VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
447 VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
448 VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
449 VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
450 VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
451 VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
452
453
454 VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
455 VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
456 AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
457 AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
458 AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
459 SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
460 SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
461 SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
462
463
464 SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
465 MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
466 MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
467 MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
468 MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
469 MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
470 MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
471 HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
472
473
474 HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
475 HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
476 HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
477 SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
478 SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
479 SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
480 SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
481 SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
482
483
484 SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
485 SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
486 SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
487 RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
488 TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
489 SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
490 SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
491 SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
492
493
494 SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
495 SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
496 SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
497 SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
498 SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
499 SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
500 SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
501 SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
502
503
504 SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
505 SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
506 SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
507 SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
508 SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
509 SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
510 SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
511 SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
512
513
514 SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
515 SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
516 SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
517 SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
518 SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
519 SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
520 SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
521 SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
522
523
524 SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
525 SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
526 SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
527 AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
528 AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
529 AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
530 AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
531
532 PINMUX_MARK_END,
533};
534
535static const u16 pinmux_data[] = {
536 PINMUX_DATA_GP_ALL(),
537
538 PINMUX_SINGLE(USB0_PWEN),
539 PINMUX_SINGLE(USB0_OVC),
540 PINMUX_SINGLE(USB1_PWEN),
541 PINMUX_SINGLE(USB1_OVC),
542 PINMUX_SINGLE(CLKOUT),
543 PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
544 PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
545 PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
546 PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
547 PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
548 PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
549 PINMUX_SINGLE(MMC0_D6),
550 PINMUX_SINGLE(MMC0_D7),
551
552
553 PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
554 PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
555 PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
556 PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
557 PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
558 PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
559 PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
560 PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
561 PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
562 PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
563 PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
564 PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
565 PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
566 PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
567 PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
568 PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
569 PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
570 PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
571 PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
572 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
573 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
574 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
575 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
576
577
578 PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
579 PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
580 PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
581 PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
582 PINMUX_IPSR_GPSR(IP1_11_8, D0),
583 PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
584 PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
585 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
586 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
587 PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
588 PINMUX_IPSR_GPSR(IP1_15_12, D1),
589 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
590 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
591 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
592 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
593 PINMUX_IPSR_GPSR(IP1_19_16, D2),
594 PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
595 PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
596 PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
597 PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
598 PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
599 PINMUX_IPSR_GPSR(IP1_23_20, D3),
600 PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
601 PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
602 PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
603 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
604 PINMUX_IPSR_GPSR(IP1_27_24, D4),
605 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
606 PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
607 PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
608 PINMUX_IPSR_GPSR(IP1_31_28, D5),
609 PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
610 PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
611 PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
612 PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
613
614
615 PINMUX_IPSR_GPSR(IP2_3_0, D6),
616 PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
617 PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
618 PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
619 PINMUX_IPSR_GPSR(IP2_7_4, D7),
620 PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
621 PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
622 PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
623 PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
624 PINMUX_IPSR_GPSR(IP2_11_8, D8),
625 PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
626 PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
627 PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
628 PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
629 PINMUX_IPSR_GPSR(IP2_15_12, D9),
630 PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
631 PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
632 PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
633 PINMUX_IPSR_GPSR(IP2_19_16, D10),
634 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
635 PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
636 PINMUX_IPSR_GPSR(IP2_23_20, D11),
637 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
638 PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
639 PINMUX_IPSR_GPSR(IP2_27_24, D12),
640 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
641 PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
642 PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
643 PINMUX_IPSR_GPSR(IP2_31_28, D13),
644 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
645 PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
646
647
648 PINMUX_IPSR_GPSR(IP3_3_0, D14),
649 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
650 PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
651 PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
652 PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
653 PINMUX_IPSR_GPSR(IP3_7_4, D15),
654 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
655 PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
656 PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
657 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
658 PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
659 PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
660 PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
661 PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
662 PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
663 PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
664 PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
665 PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
666 PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
667 PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
668 PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
669 PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
670 PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
671
672
673 PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
674 PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
675 PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
676 PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
677 PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
678 PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
679 PINMUX_IPSR_GPSR(IP4_7_4, A0),
680 PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
681 PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
682 PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
683 PINMUX_IPSR_GPSR(IP4_11_8, A1),
684 PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
685 PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
686 PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
687 PINMUX_IPSR_GPSR(IP4_15_12, A2),
688 PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
689 PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
690 PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
691 PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
692 PINMUX_IPSR_GPSR(IP4_19_16, A3),
693 PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
694 PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
695 PINMUX_IPSR_GPSR(IP4_23_20, A4),
696 PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
697 PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
698 PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
699 PINMUX_IPSR_GPSR(IP4_27_24, A5),
700 PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
701 PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
702 PINMUX_IPSR_GPSR(IP4_31_28, A6),
703
704
705 PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
706 PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
707 PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
708 PINMUX_IPSR_GPSR(IP5_3_0, A7),
709 PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
710 PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
711 PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
712 PINMUX_IPSR_GPSR(IP5_7_4, A8),
713 PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
714 PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
715 PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
716 PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
717 PINMUX_IPSR_GPSR(IP5_11_8, A9),
718 PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
719 PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
720 PINMUX_IPSR_GPSR(IP5_15_12, A10),
721 PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
722 PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
723 PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
724 PINMUX_IPSR_GPSR(IP5_19_16, A11),
725 PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
726 PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
727 PINMUX_IPSR_GPSR(IP5_23_20, A12),
728 PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
729 PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
730 PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
731 PINMUX_IPSR_GPSR(IP5_27_24, A13),
732 PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
733 PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
734 PINMUX_IPSR_GPSR(IP5_31_28, A14),
735
736
737 PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
738 PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
739 PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
740 PINMUX_IPSR_GPSR(IP6_3_0, A15),
741 PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
742 PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
743 PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
744 PINMUX_IPSR_GPSR(IP6_7_4, A16),
745 PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
746 PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
747 PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
748 PINMUX_IPSR_GPSR(IP6_11_8, A17),
749 PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
750 PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
751 PINMUX_IPSR_GPSR(IP6_15_12, A18),
752 PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
753 PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
754 PINMUX_IPSR_GPSR(IP6_19_16, A19),
755 PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
756 PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
757 PINMUX_IPSR_GPSR(IP6_23_20, A20),
758 PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
759 PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
760 PINMUX_IPSR_GPSR(IP6_27_24, A21),
761 PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
762 PINMUX_IPSR_GPSR(IP6_31_28, A22),
763
764
765 PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
766 PINMUX_IPSR_GPSR(IP7_3_0, A23),
767 PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
768 PINMUX_IPSR_GPSR(IP7_7_4, A24),
769 PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
770 PINMUX_IPSR_GPSR(IP7_11_8, A25),
771 PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
772 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
773 PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
774 PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
775 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
776 PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
777 PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
778 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
779 PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
780 PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
781 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
782 PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
783 PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
784 PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
785
786
787 PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
788 PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
789 PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
790 PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
791 PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
792 PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
793 PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
794 PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
795 PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
796 PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
797 PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
798 PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
799 PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
800 PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
801 PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
802 PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
803 PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
804 PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
805 PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
806 PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
807 PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
808 PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
809 PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
810
811
812 PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
813 PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
814 PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
815 PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
816 PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
817 PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
818 PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
819 PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
820 PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
821 PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
822 PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
823 PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
824 PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
825 PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
826 PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
827 PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
828 PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
829 PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
830 PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
831 PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
832 PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
833 PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
834 PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
835 PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
836 PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
837 PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
838 PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
839 PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
840 PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
841 PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
842
843
844 PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
845 PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
846 PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
847 PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
848 PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
849 PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
850 PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
851 PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
852 PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
853 PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
854 PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
855 PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
856 PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
857 PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
858 PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
859 PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
860 PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
861 PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
862 PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
863 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
864 PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
865 PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
866 PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
867 PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
868 PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
869 PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
870 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
871 PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
872 PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
873 PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
874 PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
875 PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
876 PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
877 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
878 PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
879 PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
880 PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
881 PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
882 PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
883 PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
884 PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
885
886
887 PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
888 PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
889 PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
890 PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
891 PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
892 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
893 PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
894 PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
895 PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
896 PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
897 PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
898 PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
899 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
900 PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
901 PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
902 PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
903 PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
904 PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
905 PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
906 PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
907 PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
908 PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
909 PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
910 PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
911 PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
912 PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
913 PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
914 PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
915 PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
916 PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
917 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
918 PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
919 PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
920 PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
921 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
922 PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
923 PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
924 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
925 PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
926 PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
927 PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
928 PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
929
930
931 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
932 PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
933 PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
934 PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
935 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
936 PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
937 PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
938 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
939 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
940 PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
941 PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
942 PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
943 PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
944 PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
945 PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
946 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
947 PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
948 PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
949 PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
950 PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
951 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
952 PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
953 PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
954 PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
955 PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
956 PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
957 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
958 PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
959 PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
960 PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
961 PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
962 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
963 PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
964 PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
965 PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
966 PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
967
968
969 PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
970 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
971 PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
972 PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
973 PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
974 PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
975 PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
976 PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
977 PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
978 PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
979 PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
980 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
981 PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
982 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
983 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
984 PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
985 PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
986 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
987 PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
988 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
989 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
990 PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
991 PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
992 PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
993 PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
994 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
995 PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
996 PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
997 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
998 PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
999 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1000 PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
1001 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
1002 PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
1003 PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
1004
1005
1006 PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
1007 PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
1008 PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
1009 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
1010 PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
1011 PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
1012 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
1013 PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1014 PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
1015 PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
1016 PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
1017 PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
1018 PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
1019 PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
1020 PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
1021 PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
1022 PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
1023 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
1024 PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
1025 PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
1026 PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
1027 PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
1028 PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
1029 PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
1030 PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
1031
1032
1033 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
1034 PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
1035 PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
1036 PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
1037 PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
1038 PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
1039 PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
1040 PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
1041 PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
1042 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1043 PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
1044 PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
1045 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
1046 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
1047 PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
1048 PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
1049 PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
1050 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
1051 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
1052 PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
1053 PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
1054 PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
1055 PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
1056 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
1057 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
1058 PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
1059 PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
1060 PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
1061 PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
1062 PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
1063 PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
1064 PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
1065 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
1066 PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
1067 PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
1068
1069
1070 PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
1071 PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
1072 PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
1073 PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
1074 PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
1075 PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
1076 PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
1077 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
1078 PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
1079 PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
1080 PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
1081 PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
1082 PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
1083 PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
1084 PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
1085 PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
1086 PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
1087 PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
1088 PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
1089 PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
1090 PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
1091 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
1092 PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
1093 PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
1094 PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
1095 PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
1096 PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
1097 PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
1098 PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
1099 PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
1100 PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
1101 PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
1102 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
1103 PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
1104 PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
1105
1106
1107 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
1108 PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
1109 PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
1110 PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
1111 PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
1112 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
1113 PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
1114 PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
1115 PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
1116 PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
1117 PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
1118 PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
1119 PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
1120 PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
1121 PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
1122 PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
1123 PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
1124 PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
1125 PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
1126 PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
1127 PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
1128 PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
1129 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
1130 PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
1131 PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
1132};
1133
1134
1135
1136
1137enum {
1138 GP_ASSIGN_LAST(),
1139 NOGP_ALL(),
1140};
1141
1142static const struct sh_pfc_pin pinmux_pins[] = {
1143 PINMUX_GPIO_GP_ALL(),
1144 PINMUX_NOGP_ALL(),
1145};
1146
1147
1148static const unsigned int avb_col_pins[] = {
1149 RCAR_GP_PIN(5, 18),
1150};
1151static const unsigned int avb_col_mux[] = {
1152 AVB_COL_MARK,
1153};
1154static const unsigned int avb_crs_pins[] = {
1155 RCAR_GP_PIN(5, 17),
1156};
1157static const unsigned int avb_crs_mux[] = {
1158 AVB_CRS_MARK,
1159};
1160static const unsigned int avb_link_pins[] = {
1161 RCAR_GP_PIN(5, 14),
1162};
1163static const unsigned int avb_link_mux[] = {
1164 AVB_LINK_MARK,
1165};
1166static const unsigned int avb_magic_pins[] = {
1167 RCAR_GP_PIN(5, 15),
1168};
1169static const unsigned int avb_magic_mux[] = {
1170 AVB_MAGIC_MARK,
1171};
1172static const unsigned int avb_phy_int_pins[] = {
1173 RCAR_GP_PIN(5, 16),
1174};
1175static const unsigned int avb_phy_int_mux[] = {
1176 AVB_PHY_INT_MARK,
1177};
1178static const unsigned int avb_mdio_pins[] = {
1179 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1180};
1181static const unsigned int avb_mdio_mux[] = {
1182 AVB_MDC_MARK, AVB_MDIO_MARK,
1183};
1184static const unsigned int avb_mii_tx_rx_pins[] = {
1185 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1186 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
1187
1188 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1189 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
1190 RCAR_GP_PIN(3, 10),
1191};
1192static const unsigned int avb_mii_tx_rx_mux[] = {
1193 AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1194 AVB_TXD3_MARK, AVB_TX_EN_MARK,
1195
1196 AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1197 AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1198};
1199static const unsigned int avb_mii_tx_er_pins[] = {
1200 RCAR_GP_PIN(5, 23),
1201};
1202static const unsigned int avb_mii_tx_er_mux[] = {
1203 AVB_TX_ER_MARK,
1204};
1205static const unsigned int avb_gmii_tx_rx_pins[] = {
1206 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1207 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1208 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
1209 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
1210 RCAR_GP_PIN(5, 23),
1211
1212 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1213 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1214 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1215 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
1216};
1217static const unsigned int avb_gmii_tx_rx_mux[] = {
1218 AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
1219 AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
1220 AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
1221 AVB_TX_ER_MARK,
1222
1223 AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1224 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
1225 AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1226};
1227static const unsigned int avb_avtp_match_a_pins[] = {
1228 RCAR_GP_PIN(1, 15),
1229};
1230static const unsigned int avb_avtp_match_a_mux[] = {
1231 AVB_AVTP_MATCH_A_MARK,
1232};
1233static const unsigned int avb_avtp_capture_a_pins[] = {
1234 RCAR_GP_PIN(1, 14),
1235};
1236static const unsigned int avb_avtp_capture_a_mux[] = {
1237 AVB_AVTP_CAPTURE_A_MARK,
1238};
1239static const unsigned int avb_avtp_match_b_pins[] = {
1240 RCAR_GP_PIN(5, 20),
1241};
1242static const unsigned int avb_avtp_match_b_mux[] = {
1243 AVB_AVTP_MATCH_B_MARK,
1244};
1245static const unsigned int avb_avtp_capture_b_pins[] = {
1246 RCAR_GP_PIN(5, 19),
1247};
1248static const unsigned int avb_avtp_capture_b_mux[] = {
1249 AVB_AVTP_CAPTURE_B_MARK,
1250};
1251
1252static const unsigned int du0_rgb666_pins[] = {
1253
1254 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1255 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1256 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1257 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1258 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1259 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1260};
1261static const unsigned int du0_rgb666_mux[] = {
1262 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1263 DU0_DR3_MARK, DU0_DR2_MARK,
1264 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1265 DU0_DG3_MARK, DU0_DG2_MARK,
1266 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1267 DU0_DB3_MARK, DU0_DB2_MARK,
1268};
1269static const unsigned int du0_rgb888_pins[] = {
1270
1271 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1272 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1273 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1274 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1275 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1276 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1277 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1278 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1279 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1280};
1281static const unsigned int du0_rgb888_mux[] = {
1282 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1283 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1284 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1285 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1286 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1287 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1288};
1289static const unsigned int du0_clk0_out_pins[] = {
1290
1291 RCAR_GP_PIN(2, 25),
1292};
1293static const unsigned int du0_clk0_out_mux[] = {
1294 DU0_DOTCLKOUT0_MARK
1295};
1296static const unsigned int du0_clk1_out_pins[] = {
1297
1298 RCAR_GP_PIN(2, 26),
1299};
1300static const unsigned int du0_clk1_out_mux[] = {
1301 DU0_DOTCLKOUT1_MARK
1302};
1303static const unsigned int du0_clk_in_pins[] = {
1304
1305 RCAR_GP_PIN(2, 24),
1306};
1307static const unsigned int du0_clk_in_mux[] = {
1308 DU0_DOTCLKIN_MARK
1309};
1310static const unsigned int du0_sync_pins[] = {
1311
1312 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1313};
1314static const unsigned int du0_sync_mux[] = {
1315 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1316};
1317static const unsigned int du0_oddf_pins[] = {
1318
1319 RCAR_GP_PIN(2, 29),
1320};
1321static const unsigned int du0_oddf_mux[] = {
1322 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1323};
1324static const unsigned int du0_cde_pins[] = {
1325
1326 RCAR_GP_PIN(2, 31),
1327};
1328static const unsigned int du0_cde_mux[] = {
1329 DU0_CDE_MARK,
1330};
1331static const unsigned int du0_disp_pins[] = {
1332
1333 RCAR_GP_PIN(2, 30),
1334};
1335static const unsigned int du0_disp_mux[] = {
1336 DU0_DISP_MARK
1337};
1338static const unsigned int du1_rgb666_pins[] = {
1339
1340 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1341 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1342 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1343 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1344 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1345 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1346};
1347static const unsigned int du1_rgb666_mux[] = {
1348 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1349 DU1_DR3_MARK, DU1_DR2_MARK,
1350 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1351 DU1_DG3_MARK, DU1_DG2_MARK,
1352 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1353 DU1_DB3_MARK, DU1_DB2_MARK,
1354};
1355static const unsigned int du1_rgb888_pins[] = {
1356
1357 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1358 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1359 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1360 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1361 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1362 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1363 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1364 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1365 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1366};
1367static const unsigned int du1_rgb888_mux[] = {
1368 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1369 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1370 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1371 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1372 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1373 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1374};
1375static const unsigned int du1_clk0_out_pins[] = {
1376
1377 RCAR_GP_PIN(5, 2),
1378};
1379static const unsigned int du1_clk0_out_mux[] = {
1380 DU1_DOTCLKOUT0_MARK
1381};
1382static const unsigned int du1_clk1_out_pins[] = {
1383
1384 RCAR_GP_PIN(5, 0),
1385};
1386static const unsigned int du1_clk1_out_mux[] = {
1387 DU1_DOTCLKOUT1_MARK
1388};
1389static const unsigned int du1_clk_in_pins[] = {
1390
1391 RCAR_GP_PIN(5, 1),
1392};
1393static const unsigned int du1_clk_in_mux[] = {
1394 DU1_DOTCLKIN_MARK
1395};
1396static const unsigned int du1_sync_pins[] = {
1397
1398 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1399};
1400static const unsigned int du1_sync_mux[] = {
1401 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1402};
1403static const unsigned int du1_oddf_pins[] = {
1404
1405 RCAR_GP_PIN(5, 3),
1406};
1407static const unsigned int du1_oddf_mux[] = {
1408 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1409};
1410static const unsigned int du1_cde_pins[] = {
1411
1412 RCAR_GP_PIN(5, 7),
1413};
1414static const unsigned int du1_cde_mux[] = {
1415 DU1_CDE_MARK
1416};
1417static const unsigned int du1_disp_pins[] = {
1418
1419 RCAR_GP_PIN(5, 6),
1420};
1421static const unsigned int du1_disp_mux[] = {
1422 DU1_DISP_MARK
1423};
1424
1425static const unsigned int i2c0_a_pins[] = {
1426
1427 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1428};
1429static const unsigned int i2c0_a_mux[] = {
1430 SCL0_A_MARK, SDA0_A_MARK,
1431};
1432static const unsigned int i2c0_b_pins[] = {
1433
1434 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1435};
1436static const unsigned int i2c0_b_mux[] = {
1437 SCL0_B_MARK, SDA0_B_MARK,
1438};
1439static const unsigned int i2c0_c_pins[] = {
1440
1441 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1442};
1443static const unsigned int i2c0_c_mux[] = {
1444 SCL0_C_MARK, SDA0_C_MARK,
1445};
1446static const unsigned int i2c0_d_pins[] = {
1447
1448 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1449};
1450static const unsigned int i2c0_d_mux[] = {
1451 SCL0_D_MARK, SDA0_D_MARK,
1452};
1453static const unsigned int i2c0_e_pins[] = {
1454
1455 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1456};
1457static const unsigned int i2c0_e_mux[] = {
1458 SCL0_E_MARK, SDA0_E_MARK,
1459};
1460
1461static const unsigned int i2c1_a_pins[] = {
1462
1463 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1464};
1465static const unsigned int i2c1_a_mux[] = {
1466 SCL1_A_MARK, SDA1_A_MARK,
1467};
1468static const unsigned int i2c1_b_pins[] = {
1469
1470 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
1471};
1472static const unsigned int i2c1_b_mux[] = {
1473 SCL1_B_MARK, SDA1_B_MARK,
1474};
1475static const unsigned int i2c1_c_pins[] = {
1476
1477 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1478};
1479static const unsigned int i2c1_c_mux[] = {
1480 SCL1_C_MARK, SDA1_C_MARK,
1481};
1482static const unsigned int i2c1_d_pins[] = {
1483
1484 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1485};
1486static const unsigned int i2c1_d_mux[] = {
1487 SCL1_D_MARK, SDA1_D_MARK,
1488};
1489static const unsigned int i2c1_e_pins[] = {
1490
1491 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1492};
1493static const unsigned int i2c1_e_mux[] = {
1494 SCL1_E_MARK, SDA1_E_MARK,
1495};
1496
1497static const unsigned int i2c2_a_pins[] = {
1498
1499 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1500};
1501static const unsigned int i2c2_a_mux[] = {
1502 SCL2_A_MARK, SDA2_A_MARK,
1503};
1504static const unsigned int i2c2_b_pins[] = {
1505
1506 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1507};
1508static const unsigned int i2c2_b_mux[] = {
1509 SCL2_B_MARK, SDA2_B_MARK,
1510};
1511static const unsigned int i2c2_c_pins[] = {
1512
1513 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1514};
1515static const unsigned int i2c2_c_mux[] = {
1516 SCL2_C_MARK, SDA2_C_MARK,
1517};
1518static const unsigned int i2c2_d_pins[] = {
1519
1520 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1521};
1522static const unsigned int i2c2_d_mux[] = {
1523 SCL2_D_MARK, SDA2_D_MARK,
1524};
1525
1526static const unsigned int i2c3_a_pins[] = {
1527
1528 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1529};
1530static const unsigned int i2c3_a_mux[] = {
1531 SCL3_A_MARK, SDA3_A_MARK,
1532};
1533static const unsigned int i2c3_b_pins[] = {
1534
1535 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1536};
1537static const unsigned int i2c3_b_mux[] = {
1538 SCL3_B_MARK, SDA3_B_MARK,
1539};
1540static const unsigned int i2c3_c_pins[] = {
1541
1542 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1543};
1544static const unsigned int i2c3_c_mux[] = {
1545 SCL3_C_MARK, SDA3_C_MARK,
1546};
1547static const unsigned int i2c3_d_pins[] = {
1548
1549 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1550};
1551static const unsigned int i2c3_d_mux[] = {
1552 SCL3_D_MARK, SDA3_D_MARK,
1553};
1554static const unsigned int i2c3_e_pins[] = {
1555
1556 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1557};
1558static const unsigned int i2c3_e_mux[] = {
1559 SCL3_E_MARK, SDA3_E_MARK,
1560};
1561
1562static const unsigned int i2c4_a_pins[] = {
1563
1564 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1565};
1566static const unsigned int i2c4_a_mux[] = {
1567 SCL4_A_MARK, SDA4_A_MARK,
1568};
1569static const unsigned int i2c4_b_pins[] = {
1570
1571 RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
1572};
1573static const unsigned int i2c4_b_mux[] = {
1574 SCL4_B_MARK, SDA4_B_MARK,
1575};
1576static const unsigned int i2c4_c_pins[] = {
1577
1578 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1579};
1580static const unsigned int i2c4_c_mux[] = {
1581 SCL4_C_MARK, SDA4_C_MARK,
1582};
1583static const unsigned int i2c4_d_pins[] = {
1584
1585 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1586};
1587static const unsigned int i2c4_d_mux[] = {
1588 SCL4_D_MARK, SDA4_D_MARK,
1589};
1590static const unsigned int i2c4_e_pins[] = {
1591
1592 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
1593};
1594static const unsigned int i2c4_e_mux[] = {
1595 SCL4_E_MARK, SDA4_E_MARK,
1596};
1597
1598static const unsigned int mmc_data1_pins[] = {
1599
1600 RCAR_GP_PIN(0, 15),
1601};
1602static const unsigned int mmc_data1_mux[] = {
1603 MMC0_D0_SDHI1_D0_MARK,
1604};
1605static const unsigned int mmc_data4_pins[] = {
1606
1607 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1608 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1609};
1610static const unsigned int mmc_data4_mux[] = {
1611 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1612 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1613};
1614static const unsigned int mmc_data8_pins[] = {
1615
1616 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1617 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1618 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
1619 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
1620};
1621static const unsigned int mmc_data8_mux[] = {
1622 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1623 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1624 MMC0_D4_MARK, MMC0_D5_MARK,
1625 MMC0_D6_MARK, MMC0_D7_MARK,
1626};
1627static const unsigned int mmc_ctrl_pins[] = {
1628
1629 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1630};
1631static const unsigned int mmc_ctrl_mux[] = {
1632 MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1633};
1634
1635static const unsigned int qspi0_ctrl_pins[] = {
1636
1637 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
1638};
1639static const unsigned int qspi0_ctrl_mux[] = {
1640 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1641};
1642static const unsigned int qspi0_data2_pins[] = {
1643
1644 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
1645};
1646static const unsigned int qspi0_data2_mux[] = {
1647 QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1648};
1649static const unsigned int qspi0_data4_pins[] = {
1650
1651 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1652 RCAR_GP_PIN(1, 20),
1653};
1654static const unsigned int qspi0_data4_mux[] = {
1655 QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1656 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1657};
1658static const unsigned int qspi1_ctrl_pins[] = {
1659
1660 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1661};
1662static const unsigned int qspi1_ctrl_mux[] = {
1663 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1664};
1665static const unsigned int qspi1_data2_pins[] = {
1666
1667 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1668};
1669static const unsigned int qspi1_data2_mux[] = {
1670 QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1671};
1672static const unsigned int qspi1_data4_pins[] = {
1673
1674 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1675 RCAR_GP_PIN(4, 8),
1676};
1677static const unsigned int qspi1_data4_mux[] = {
1678 QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1679 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1680};
1681
1682static const unsigned int scif0_data_a_pins[] = {
1683
1684 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1685};
1686static const unsigned int scif0_data_a_mux[] = {
1687 RX0_A_MARK, TX0_A_MARK,
1688};
1689static const unsigned int scif0_data_b_pins[] = {
1690
1691 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1692};
1693static const unsigned int scif0_data_b_mux[] = {
1694 RX0_B_MARK, TX0_B_MARK,
1695};
1696static const unsigned int scif0_data_c_pins[] = {
1697
1698 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1699};
1700static const unsigned int scif0_data_c_mux[] = {
1701 RX0_C_MARK, TX0_C_MARK,
1702};
1703static const unsigned int scif0_data_d_pins[] = {
1704
1705 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1706};
1707static const unsigned int scif0_data_d_mux[] = {
1708 RX0_D_MARK, TX0_D_MARK,
1709};
1710
1711static const unsigned int scif1_data_a_pins[] = {
1712
1713 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1714};
1715static const unsigned int scif1_data_a_mux[] = {
1716 RX1_A_MARK, TX1_A_MARK,
1717};
1718static const unsigned int scif1_clk_a_pins[] = {
1719
1720 RCAR_GP_PIN(4, 15),
1721};
1722static const unsigned int scif1_clk_a_mux[] = {
1723 SCIF1_SCK_A_MARK,
1724};
1725static const unsigned int scif1_data_b_pins[] = {
1726
1727 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1728};
1729static const unsigned int scif1_data_b_mux[] = {
1730 RX1_B_MARK, TX1_B_MARK,
1731};
1732static const unsigned int scif1_clk_b_pins[] = {
1733
1734 RCAR_GP_PIN(5, 18),
1735};
1736static const unsigned int scif1_clk_b_mux[] = {
1737 SCIF1_SCK_B_MARK,
1738};
1739static const unsigned int scif1_data_c_pins[] = {
1740
1741 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1742};
1743static const unsigned int scif1_data_c_mux[] = {
1744 RX1_C_MARK, TX1_C_MARK,
1745};
1746static const unsigned int scif1_clk_c_pins[] = {
1747
1748 RCAR_GP_PIN(1, 7),
1749};
1750static const unsigned int scif1_clk_c_mux[] = {
1751 SCIF1_SCK_C_MARK,
1752};
1753static const unsigned int scif1_data_d_pins[] = {
1754
1755 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1756};
1757static const unsigned int scif1_data_d_mux[] = {
1758 RX1_D_MARK, TX1_D_MARK,
1759};
1760
1761static const unsigned int scif2_data_a_pins[] = {
1762
1763 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1764};
1765static const unsigned int scif2_data_a_mux[] = {
1766 RX2_A_MARK, TX2_A_MARK,
1767};
1768static const unsigned int scif2_clk_a_pins[] = {
1769
1770 RCAR_GP_PIN(4, 20),
1771};
1772static const unsigned int scif2_clk_a_mux[] = {
1773 SCIF2_SCK_A_MARK,
1774};
1775static const unsigned int scif2_data_b_pins[] = {
1776
1777 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1778};
1779static const unsigned int scif2_data_b_mux[] = {
1780 RX2_B_MARK, TX2_B_MARK,
1781};
1782static const unsigned int scif2_clk_b_pins[] = {
1783
1784 RCAR_GP_PIN(5, 27),
1785};
1786static const unsigned int scif2_clk_b_mux[] = {
1787 SCIF2_SCK_B_MARK,
1788};
1789static const unsigned int scif2_data_c_pins[] = {
1790
1791 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1792};
1793static const unsigned int scif2_data_c_mux[] = {
1794 RX2_C_MARK, TX2_C_MARK,
1795};
1796
1797static const unsigned int scif3_data_a_pins[] = {
1798
1799 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1800};
1801static const unsigned int scif3_data_a_mux[] = {
1802 RX3_A_MARK, TX3_A_MARK,
1803};
1804static const unsigned int scif3_clk_pins[] = {
1805
1806 RCAR_GP_PIN(4, 21),
1807};
1808static const unsigned int scif3_clk_mux[] = {
1809 SCIF3_SCK_MARK,
1810};
1811static const unsigned int scif3_data_b_pins[] = {
1812
1813 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1814};
1815static const unsigned int scif3_data_b_mux[] = {
1816 RX3_B_MARK, TX3_B_MARK,
1817};
1818static const unsigned int scif3_data_c_pins[] = {
1819
1820 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1821};
1822static const unsigned int scif3_data_c_mux[] = {
1823 RX3_C_MARK, TX3_C_MARK,
1824};
1825
1826static const unsigned int scif4_data_a_pins[] = {
1827
1828 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1829};
1830static const unsigned int scif4_data_a_mux[] = {
1831 RX4_A_MARK, TX4_A_MARK,
1832};
1833static const unsigned int scif4_data_b_pins[] = {
1834
1835 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1836};
1837static const unsigned int scif4_data_b_mux[] = {
1838 RX4_B_MARK, TX4_B_MARK,
1839};
1840static const unsigned int scif4_data_c_pins[] = {
1841
1842 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
1843};
1844static const unsigned int scif4_data_c_mux[] = {
1845 RX4_C_MARK, TX4_C_MARK,
1846};
1847static const unsigned int scif4_data_d_pins[] = {
1848
1849 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1850};
1851static const unsigned int scif4_data_d_mux[] = {
1852 RX4_D_MARK, TX4_D_MARK,
1853};
1854static const unsigned int scif4_data_e_pins[] = {
1855
1856 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1857};
1858static const unsigned int scif4_data_e_mux[] = {
1859 RX4_E_MARK, TX4_E_MARK,
1860};
1861
1862static const unsigned int scif5_data_a_pins[] = {
1863
1864 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1865};
1866static const unsigned int scif5_data_a_mux[] = {
1867 RX5_A_MARK, TX5_A_MARK,
1868};
1869static const unsigned int scif5_data_b_pins[] = {
1870
1871 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1872};
1873static const unsigned int scif5_data_b_mux[] = {
1874 RX5_B_MARK, TX5_B_MARK,
1875};
1876static const unsigned int scif5_data_c_pins[] = {
1877
1878 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1879};
1880static const unsigned int scif5_data_c_mux[] = {
1881 RX5_C_MARK, TX5_C_MARK,
1882};
1883static const unsigned int scif5_data_d_pins[] = {
1884
1885 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1886};
1887static const unsigned int scif5_data_d_mux[] = {
1888 RX5_D_MARK, TX5_D_MARK,
1889};
1890static const unsigned int scif5_data_e_pins[] = {
1891
1892 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1893};
1894static const unsigned int scif5_data_e_mux[] = {
1895 RX5_E_MARK, TX5_E_MARK,
1896};
1897static const unsigned int scif5_data_f_pins[] = {
1898
1899 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1900};
1901static const unsigned int scif5_data_f_mux[] = {
1902 RX5_F_MARK, TX5_F_MARK,
1903};
1904
1905static const unsigned int scif_clk_a_pins[] = {
1906
1907 RCAR_GP_PIN(1, 22),
1908};
1909static const unsigned int scif_clk_a_mux[] = {
1910 SCIF_CLK_A_MARK,
1911};
1912static const unsigned int scif_clk_b_pins[] = {
1913
1914 RCAR_GP_PIN(3, 29),
1915};
1916static const unsigned int scif_clk_b_mux[] = {
1917 SCIF_CLK_B_MARK,
1918};
1919
1920static const unsigned int sdhi0_data1_pins[] = {
1921
1922 RCAR_GP_PIN(0, 7),
1923};
1924static const unsigned int sdhi0_data1_mux[] = {
1925 SD0_DAT0_MARK,
1926};
1927static const unsigned int sdhi0_data4_pins[] = {
1928
1929 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1930 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1931};
1932static const unsigned int sdhi0_data4_mux[] = {
1933 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1934};
1935static const unsigned int sdhi0_ctrl_pins[] = {
1936
1937 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1938};
1939static const unsigned int sdhi0_ctrl_mux[] = {
1940 SD0_CLK_MARK, SD0_CMD_MARK,
1941};
1942static const unsigned int sdhi0_cd_pins[] = {
1943
1944 RCAR_GP_PIN(0, 11),
1945};
1946static const unsigned int sdhi0_cd_mux[] = {
1947 SD0_CD_MARK,
1948};
1949static const unsigned int sdhi0_wp_pins[] = {
1950
1951 RCAR_GP_PIN(0, 12),
1952};
1953static const unsigned int sdhi0_wp_mux[] = {
1954 SD0_WP_MARK,
1955};
1956
1957static const unsigned int sdhi1_data1_pins[] = {
1958
1959 RCAR_GP_PIN(0, 15),
1960};
1961static const unsigned int sdhi1_data1_mux[] = {
1962 MMC0_D0_SDHI1_D0_MARK,
1963};
1964static const unsigned int sdhi1_data4_pins[] = {
1965
1966 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1967 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1968};
1969static const unsigned int sdhi1_data4_mux[] = {
1970 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1971 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1972};
1973static const unsigned int sdhi1_ctrl_pins[] = {
1974
1975 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1976};
1977static const unsigned int sdhi1_ctrl_mux[] = {
1978 MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1979};
1980static const unsigned int sdhi1_cd_pins[] = {
1981
1982 RCAR_GP_PIN(0, 19),
1983};
1984static const unsigned int sdhi1_cd_mux[] = {
1985 SD1_CD_MARK,
1986};
1987static const unsigned int sdhi1_wp_pins[] = {
1988
1989 RCAR_GP_PIN(0, 20),
1990};
1991static const unsigned int sdhi1_wp_mux[] = {
1992 SD1_WP_MARK,
1993};
1994
1995static const unsigned int sdhi2_data1_pins[] = {
1996
1997 RCAR_GP_PIN(4, 16),
1998};
1999static const unsigned int sdhi2_data1_mux[] = {
2000 SD2_DAT0_MARK,
2001};
2002static const unsigned int sdhi2_data4_pins[] = {
2003
2004 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2005 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
2006};
2007static const unsigned int sdhi2_data4_mux[] = {
2008 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2009};
2010static const unsigned int sdhi2_ctrl_pins[] = {
2011
2012 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2013};
2014static const unsigned int sdhi2_ctrl_mux[] = {
2015 SD2_CLK_MARK, SD2_CMD_MARK,
2016};
2017static const unsigned int sdhi2_cd_pins[] = {
2018
2019 RCAR_GP_PIN(4, 20),
2020};
2021static const unsigned int sdhi2_cd_mux[] = {
2022 SD2_CD_MARK,
2023};
2024static const unsigned int sdhi2_wp_pins[] = {
2025
2026 RCAR_GP_PIN(4, 21),
2027};
2028static const unsigned int sdhi2_wp_mux[] = {
2029 SD2_WP_MARK,
2030};
2031
2032static const unsigned int usb0_pins[] = {
2033 RCAR_GP_PIN(0, 0),
2034 RCAR_GP_PIN(0, 1),
2035};
2036static const unsigned int usb0_mux[] = {
2037 USB0_PWEN_MARK,
2038 USB0_OVC_MARK,
2039};
2040
2041static const unsigned int usb1_pins[] = {
2042 RCAR_GP_PIN(0, 2),
2043 RCAR_GP_PIN(0, 3),
2044};
2045static const unsigned int usb1_mux[] = {
2046 USB1_PWEN_MARK,
2047 USB1_OVC_MARK,
2048};
2049
2050static const union vin_data vin0_data_pins = {
2051 .data24 = {
2052
2053 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2054 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2055 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2056 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2057
2058 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2059 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2060 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2061 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2062
2063 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2064 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2065 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2066 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2067 },
2068};
2069static const union vin_data vin0_data_mux = {
2070 .data24 = {
2071
2072 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2073 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2074 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2075 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2076
2077 VI0_G0_MARK, VI0_G1_MARK,
2078 VI0_G2_MARK, VI0_G3_MARK,
2079 VI0_G4_MARK, VI0_G5_MARK,
2080 VI0_G6_MARK, VI0_G7_MARK,
2081
2082 VI0_R0_MARK, VI0_R1_MARK,
2083 VI0_R2_MARK, VI0_R3_MARK,
2084 VI0_R4_MARK, VI0_R5_MARK,
2085 VI0_R6_MARK, VI0_R7_MARK,
2086 },
2087};
2088static const unsigned int vin0_data18_pins[] = {
2089
2090 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2091 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2092 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2093
2094 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2095 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2096 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2097
2098 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2099 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2100 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2101};
2102static const unsigned int vin0_data18_mux[] = {
2103
2104 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2105 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2106 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2107
2108 VI0_G2_MARK, VI0_G3_MARK,
2109 VI0_G4_MARK, VI0_G5_MARK,
2110 VI0_G6_MARK, VI0_G7_MARK,
2111
2112 VI0_R2_MARK, VI0_R3_MARK,
2113 VI0_R4_MARK, VI0_R5_MARK,
2114 VI0_R6_MARK, VI0_R7_MARK,
2115};
2116static const unsigned int vin0_sync_pins[] = {
2117 RCAR_GP_PIN(5, 30),
2118 RCAR_GP_PIN(5, 31),
2119};
2120static const unsigned int vin0_sync_mux[] = {
2121 VI0_HSYNC_N_MARK,
2122 VI0_VSYNC_N_MARK,
2123};
2124static const unsigned int vin0_field_pins[] = {
2125 RCAR_GP_PIN(5, 29),
2126};
2127static const unsigned int vin0_field_mux[] = {
2128 VI0_FIELD_MARK,
2129};
2130static const unsigned int vin0_clkenb_pins[] = {
2131 RCAR_GP_PIN(5, 28),
2132};
2133static const unsigned int vin0_clkenb_mux[] = {
2134 VI0_CLKENB_MARK,
2135};
2136static const unsigned int vin0_clk_pins[] = {
2137 RCAR_GP_PIN(5, 18),
2138};
2139static const unsigned int vin0_clk_mux[] = {
2140 VI0_CLK_MARK,
2141};
2142
2143static const union vin_data vin1_data_pins = {
2144 .data12 = {
2145 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2146 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2147 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2148 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2149 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2150 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2151 },
2152};
2153static const union vin_data vin1_data_mux = {
2154 .data12 = {
2155 VI1_DATA0_MARK, VI1_DATA1_MARK,
2156 VI1_DATA2_MARK, VI1_DATA3_MARK,
2157 VI1_DATA4_MARK, VI1_DATA5_MARK,
2158 VI1_DATA6_MARK, VI1_DATA7_MARK,
2159 VI1_DATA8_MARK, VI1_DATA9_MARK,
2160 VI1_DATA10_MARK, VI1_DATA11_MARK,
2161 },
2162};
2163static const unsigned int vin1_sync_pins[] = {
2164 RCAR_GP_PIN(3, 11),
2165 RCAR_GP_PIN(3, 12),
2166};
2167static const unsigned int vin1_sync_mux[] = {
2168 VI1_HSYNC_N_MARK,
2169 VI1_VSYNC_N_MARK,
2170};
2171static const unsigned int vin1_field_pins[] = {
2172 RCAR_GP_PIN(3, 10),
2173};
2174static const unsigned int vin1_field_mux[] = {
2175 VI1_FIELD_MARK,
2176};
2177static const unsigned int vin1_clkenb_pins[] = {
2178 RCAR_GP_PIN(3, 9),
2179};
2180static const unsigned int vin1_clkenb_mux[] = {
2181 VI1_CLKENB_MARK,
2182};
2183static const unsigned int vin1_clk_pins[] = {
2184 RCAR_GP_PIN(3, 0),
2185};
2186static const unsigned int vin1_clk_mux[] = {
2187 VI1_CLK_MARK,
2188};
2189
2190static const struct sh_pfc_pin_group pinmux_groups[] = {
2191 SH_PFC_PIN_GROUP(avb_col),
2192 SH_PFC_PIN_GROUP(avb_crs),
2193 SH_PFC_PIN_GROUP(avb_link),
2194 SH_PFC_PIN_GROUP(avb_magic),
2195 SH_PFC_PIN_GROUP(avb_phy_int),
2196 SH_PFC_PIN_GROUP(avb_mdio),
2197 SH_PFC_PIN_GROUP(avb_mii_tx_rx),
2198 SH_PFC_PIN_GROUP(avb_mii_tx_er),
2199 SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
2200 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2201 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2202 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2203 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2204 SH_PFC_PIN_GROUP(du0_rgb666),
2205 SH_PFC_PIN_GROUP(du0_rgb888),
2206 SH_PFC_PIN_GROUP(du0_clk0_out),
2207 SH_PFC_PIN_GROUP(du0_clk1_out),
2208 SH_PFC_PIN_GROUP(du0_clk_in),
2209 SH_PFC_PIN_GROUP(du0_sync),
2210 SH_PFC_PIN_GROUP(du0_oddf),
2211 SH_PFC_PIN_GROUP(du0_cde),
2212 SH_PFC_PIN_GROUP(du0_disp),
2213 SH_PFC_PIN_GROUP(du1_rgb666),
2214 SH_PFC_PIN_GROUP(du1_rgb888),
2215 SH_PFC_PIN_GROUP(du1_clk0_out),
2216 SH_PFC_PIN_GROUP(du1_clk1_out),
2217 SH_PFC_PIN_GROUP(du1_clk_in),
2218 SH_PFC_PIN_GROUP(du1_sync),
2219 SH_PFC_PIN_GROUP(du1_oddf),
2220 SH_PFC_PIN_GROUP(du1_cde),
2221 SH_PFC_PIN_GROUP(du1_disp),
2222 SH_PFC_PIN_GROUP(i2c0_a),
2223 SH_PFC_PIN_GROUP(i2c0_b),
2224 SH_PFC_PIN_GROUP(i2c0_c),
2225 SH_PFC_PIN_GROUP(i2c0_d),
2226 SH_PFC_PIN_GROUP(i2c0_e),
2227 SH_PFC_PIN_GROUP(i2c1_a),
2228 SH_PFC_PIN_GROUP(i2c1_b),
2229 SH_PFC_PIN_GROUP(i2c1_c),
2230 SH_PFC_PIN_GROUP(i2c1_d),
2231 SH_PFC_PIN_GROUP(i2c1_e),
2232 SH_PFC_PIN_GROUP(i2c2_a),
2233 SH_PFC_PIN_GROUP(i2c2_b),
2234 SH_PFC_PIN_GROUP(i2c2_c),
2235 SH_PFC_PIN_GROUP(i2c2_d),
2236 SH_PFC_PIN_GROUP(i2c3_a),
2237 SH_PFC_PIN_GROUP(i2c3_b),
2238 SH_PFC_PIN_GROUP(i2c3_c),
2239 SH_PFC_PIN_GROUP(i2c3_d),
2240 SH_PFC_PIN_GROUP(i2c3_e),
2241 SH_PFC_PIN_GROUP(i2c4_a),
2242 SH_PFC_PIN_GROUP(i2c4_b),
2243 SH_PFC_PIN_GROUP(i2c4_c),
2244 SH_PFC_PIN_GROUP(i2c4_d),
2245 SH_PFC_PIN_GROUP(i2c4_e),
2246 SH_PFC_PIN_GROUP(mmc_data1),
2247 SH_PFC_PIN_GROUP(mmc_data4),
2248 SH_PFC_PIN_GROUP(mmc_data8),
2249 SH_PFC_PIN_GROUP(mmc_ctrl),
2250 SH_PFC_PIN_GROUP(qspi0_ctrl),
2251 SH_PFC_PIN_GROUP(qspi0_data2),
2252 SH_PFC_PIN_GROUP(qspi0_data4),
2253 SH_PFC_PIN_GROUP(qspi1_ctrl),
2254 SH_PFC_PIN_GROUP(qspi1_data2),
2255 SH_PFC_PIN_GROUP(qspi1_data4),
2256 SH_PFC_PIN_GROUP(scif0_data_a),
2257 SH_PFC_PIN_GROUP(scif0_data_b),
2258 SH_PFC_PIN_GROUP(scif0_data_c),
2259 SH_PFC_PIN_GROUP(scif0_data_d),
2260 SH_PFC_PIN_GROUP(scif1_data_a),
2261 SH_PFC_PIN_GROUP(scif1_clk_a),
2262 SH_PFC_PIN_GROUP(scif1_data_b),
2263 SH_PFC_PIN_GROUP(scif1_clk_b),
2264 SH_PFC_PIN_GROUP(scif1_data_c),
2265 SH_PFC_PIN_GROUP(scif1_clk_c),
2266 SH_PFC_PIN_GROUP(scif1_data_d),
2267 SH_PFC_PIN_GROUP(scif2_data_a),
2268 SH_PFC_PIN_GROUP(scif2_clk_a),
2269 SH_PFC_PIN_GROUP(scif2_data_b),
2270 SH_PFC_PIN_GROUP(scif2_clk_b),
2271 SH_PFC_PIN_GROUP(scif2_data_c),
2272 SH_PFC_PIN_GROUP(scif3_data_a),
2273 SH_PFC_PIN_GROUP(scif3_clk),
2274 SH_PFC_PIN_GROUP(scif3_data_b),
2275 SH_PFC_PIN_GROUP(scif3_data_c),
2276 SH_PFC_PIN_GROUP(scif4_data_a),
2277 SH_PFC_PIN_GROUP(scif4_data_b),
2278 SH_PFC_PIN_GROUP(scif4_data_c),
2279 SH_PFC_PIN_GROUP(scif4_data_d),
2280 SH_PFC_PIN_GROUP(scif4_data_e),
2281 SH_PFC_PIN_GROUP(scif5_data_a),
2282 SH_PFC_PIN_GROUP(scif5_data_b),
2283 SH_PFC_PIN_GROUP(scif5_data_c),
2284 SH_PFC_PIN_GROUP(scif5_data_d),
2285 SH_PFC_PIN_GROUP(scif5_data_e),
2286 SH_PFC_PIN_GROUP(scif5_data_f),
2287 SH_PFC_PIN_GROUP(scif_clk_a),
2288 SH_PFC_PIN_GROUP(scif_clk_b),
2289 SH_PFC_PIN_GROUP(sdhi0_data1),
2290 SH_PFC_PIN_GROUP(sdhi0_data4),
2291 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2292 SH_PFC_PIN_GROUP(sdhi0_cd),
2293 SH_PFC_PIN_GROUP(sdhi0_wp),
2294 SH_PFC_PIN_GROUP(sdhi1_data1),
2295 SH_PFC_PIN_GROUP(sdhi1_data4),
2296 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2297 SH_PFC_PIN_GROUP(sdhi1_cd),
2298 SH_PFC_PIN_GROUP(sdhi1_wp),
2299 SH_PFC_PIN_GROUP(sdhi2_data1),
2300 SH_PFC_PIN_GROUP(sdhi2_data4),
2301 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2302 SH_PFC_PIN_GROUP(sdhi2_cd),
2303 SH_PFC_PIN_GROUP(sdhi2_wp),
2304 SH_PFC_PIN_GROUP(usb0),
2305 SH_PFC_PIN_GROUP(usb1),
2306 VIN_DATA_PIN_GROUP(vin0_data, 24),
2307 VIN_DATA_PIN_GROUP(vin0_data, 20),
2308 SH_PFC_PIN_GROUP(vin0_data18),
2309 VIN_DATA_PIN_GROUP(vin0_data, 16),
2310 VIN_DATA_PIN_GROUP(vin0_data, 12),
2311 VIN_DATA_PIN_GROUP(vin0_data, 10),
2312 VIN_DATA_PIN_GROUP(vin0_data, 8),
2313 SH_PFC_PIN_GROUP(vin0_sync),
2314 SH_PFC_PIN_GROUP(vin0_field),
2315 SH_PFC_PIN_GROUP(vin0_clkenb),
2316 SH_PFC_PIN_GROUP(vin0_clk),
2317 VIN_DATA_PIN_GROUP(vin1_data, 12),
2318 VIN_DATA_PIN_GROUP(vin1_data, 10),
2319 VIN_DATA_PIN_GROUP(vin1_data, 8),
2320 SH_PFC_PIN_GROUP(vin1_sync),
2321 SH_PFC_PIN_GROUP(vin1_field),
2322 SH_PFC_PIN_GROUP(vin1_clkenb),
2323 SH_PFC_PIN_GROUP(vin1_clk),
2324};
2325
2326static const char * const avb_groups[] = {
2327 "avb_col",
2328 "avb_crs",
2329 "avb_link",
2330 "avb_magic",
2331 "avb_phy_int",
2332 "avb_mdio",
2333 "avb_mii_tx_rx",
2334 "avb_mii_tx_er",
2335 "avb_gmii_tx_rx",
2336 "avb_avtp_match_a",
2337 "avb_avtp_capture_a",
2338 "avb_avtp_match_b",
2339 "avb_avtp_capture_b",
2340};
2341
2342static const char * const du0_groups[] = {
2343 "du0_rgb666",
2344 "du0_rgb888",
2345 "du0_clk0_out",
2346 "du0_clk1_out",
2347 "du0_clk_in",
2348 "du0_sync",
2349 "du0_oddf",
2350 "du0_cde",
2351 "du0_disp",
2352};
2353
2354static const char * const du1_groups[] = {
2355 "du1_rgb666",
2356 "du1_rgb888",
2357 "du1_clk0_out",
2358 "du1_clk1_out",
2359 "du1_clk_in",
2360 "du1_sync",
2361 "du1_oddf",
2362 "du1_cde",
2363 "du1_disp",
2364};
2365
2366static const char * const i2c0_groups[] = {
2367 "i2c0_a",
2368 "i2c0_b",
2369 "i2c0_c",
2370 "i2c0_d",
2371 "i2c0_e",
2372};
2373
2374static const char * const i2c1_groups[] = {
2375 "i2c1_a",
2376 "i2c1_b",
2377 "i2c1_c",
2378 "i2c1_d",
2379 "i2c1_e",
2380};
2381
2382static const char * const i2c2_groups[] = {
2383 "i2c2_a",
2384 "i2c2_b",
2385 "i2c2_c",
2386 "i2c2_d",
2387};
2388
2389static const char * const i2c3_groups[] = {
2390 "i2c3_a",
2391 "i2c3_b",
2392 "i2c3_c",
2393 "i2c3_d",
2394 "i2c3_e",
2395};
2396
2397static const char * const i2c4_groups[] = {
2398 "i2c4_a",
2399 "i2c4_b",
2400 "i2c4_c",
2401 "i2c4_d",
2402 "i2c4_e",
2403};
2404
2405static const char * const mmc_groups[] = {
2406 "mmc_data1",
2407 "mmc_data4",
2408 "mmc_data8",
2409 "mmc_ctrl",
2410};
2411
2412static const char * const qspi0_groups[] = {
2413 "qspi0_ctrl",
2414 "qspi0_data2",
2415 "qspi0_data4",
2416};
2417
2418static const char * const qspi1_groups[] = {
2419 "qspi1_ctrl",
2420 "qspi1_data2",
2421 "qspi1_data4",
2422};
2423
2424static const char * const scif0_groups[] = {
2425 "scif0_data_a",
2426 "scif0_data_b",
2427 "scif0_data_c",
2428 "scif0_data_d",
2429};
2430
2431static const char * const scif1_groups[] = {
2432 "scif1_data_a",
2433 "scif1_clk_a",
2434 "scif1_data_b",
2435 "scif1_clk_b",
2436 "scif1_data_c",
2437 "scif1_clk_c",
2438 "scif1_data_d",
2439};
2440
2441static const char * const scif2_groups[] = {
2442 "scif2_data_a",
2443 "scif2_clk_a",
2444 "scif2_data_b",
2445 "scif2_clk_b",
2446 "scif2_data_c",
2447};
2448
2449static const char * const scif3_groups[] = {
2450 "scif3_data_a",
2451 "scif3_clk",
2452 "scif3_data_b",
2453 "scif3_data_c",
2454};
2455
2456static const char * const scif4_groups[] = {
2457 "scif4_data_a",
2458 "scif4_data_b",
2459 "scif4_data_c",
2460 "scif4_data_d",
2461 "scif4_data_e",
2462};
2463
2464static const char * const scif5_groups[] = {
2465 "scif5_data_a",
2466 "scif5_data_b",
2467 "scif5_data_c",
2468 "scif5_data_d",
2469 "scif5_data_e",
2470 "scif5_data_f",
2471};
2472
2473static const char * const scif_clk_groups[] = {
2474 "scif_clk_a",
2475 "scif_clk_b",
2476};
2477
2478static const char * const sdhi0_groups[] = {
2479 "sdhi0_data1",
2480 "sdhi0_data4",
2481 "sdhi0_ctrl",
2482 "sdhi0_cd",
2483 "sdhi0_wp",
2484};
2485
2486static const char * const sdhi1_groups[] = {
2487 "sdhi1_data1",
2488 "sdhi1_data4",
2489 "sdhi1_ctrl",
2490 "sdhi1_cd",
2491 "sdhi1_wp",
2492};
2493
2494static const char * const sdhi2_groups[] = {
2495 "sdhi2_data1",
2496 "sdhi2_data4",
2497 "sdhi2_ctrl",
2498 "sdhi2_cd",
2499 "sdhi2_wp",
2500};
2501
2502static const char * const usb0_groups[] = {
2503 "usb0",
2504};
2505
2506static const char * const usb1_groups[] = {
2507 "usb1",
2508};
2509
2510static const char * const vin0_groups[] = {
2511 "vin0_data24",
2512 "vin0_data20",
2513 "vin0_data18",
2514 "vin0_data16",
2515 "vin0_data12",
2516 "vin0_data10",
2517 "vin0_data8",
2518 "vin0_sync",
2519 "vin0_field",
2520 "vin0_clkenb",
2521 "vin0_clk",
2522};
2523
2524static const char * const vin1_groups[] = {
2525 "vin1_data12",
2526 "vin1_data10",
2527 "vin1_data8",
2528 "vin1_sync",
2529 "vin1_field",
2530 "vin1_clkenb",
2531 "vin1_clk",
2532};
2533
2534static const struct sh_pfc_function pinmux_functions[] = {
2535 SH_PFC_FUNCTION(avb),
2536 SH_PFC_FUNCTION(du0),
2537 SH_PFC_FUNCTION(du1),
2538 SH_PFC_FUNCTION(i2c0),
2539 SH_PFC_FUNCTION(i2c1),
2540 SH_PFC_FUNCTION(i2c2),
2541 SH_PFC_FUNCTION(i2c3),
2542 SH_PFC_FUNCTION(i2c4),
2543 SH_PFC_FUNCTION(mmc),
2544 SH_PFC_FUNCTION(qspi0),
2545 SH_PFC_FUNCTION(qspi1),
2546 SH_PFC_FUNCTION(scif0),
2547 SH_PFC_FUNCTION(scif1),
2548 SH_PFC_FUNCTION(scif2),
2549 SH_PFC_FUNCTION(scif3),
2550 SH_PFC_FUNCTION(scif4),
2551 SH_PFC_FUNCTION(scif5),
2552 SH_PFC_FUNCTION(scif_clk),
2553 SH_PFC_FUNCTION(sdhi0),
2554 SH_PFC_FUNCTION(sdhi1),
2555 SH_PFC_FUNCTION(sdhi2),
2556 SH_PFC_FUNCTION(usb0),
2557 SH_PFC_FUNCTION(usb1),
2558 SH_PFC_FUNCTION(vin0),
2559 SH_PFC_FUNCTION(vin1),
2560};
2561
2562static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2563 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2564 0, 0,
2565 0, 0,
2566 0, 0,
2567 0, 0,
2568 0, 0,
2569 0, 0,
2570 0, 0,
2571 0, 0,
2572 0, 0,
2573 GP_0_22_FN, FN_MMC0_D7,
2574 GP_0_21_FN, FN_MMC0_D6,
2575 GP_0_20_FN, FN_IP1_7_4,
2576 GP_0_19_FN, FN_IP1_3_0,
2577 GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
2578 GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
2579 GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
2580 GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
2581 GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
2582 GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
2583 GP_0_12_FN, FN_IP0_31_28,
2584 GP_0_11_FN, FN_IP0_27_24,
2585 GP_0_10_FN, FN_IP0_23_20,
2586 GP_0_9_FN, FN_IP0_19_16,
2587 GP_0_8_FN, FN_IP0_15_12,
2588 GP_0_7_FN, FN_IP0_11_8,
2589 GP_0_6_FN, FN_IP0_7_4,
2590 GP_0_5_FN, FN_IP0_3_0,
2591 GP_0_4_FN, FN_CLKOUT,
2592 GP_0_3_FN, FN_USB1_OVC,
2593 GP_0_2_FN, FN_USB1_PWEN,
2594 GP_0_1_FN, FN_USB0_OVC,
2595 GP_0_0_FN, FN_USB0_PWEN, ))
2596 },
2597 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2598 0, 0,
2599 0, 0,
2600 0, 0,
2601 0, 0,
2602 0, 0,
2603 0, 0,
2604 0, 0,
2605 0, 0,
2606 0, 0,
2607 GP_1_22_FN, FN_IP4_3_0,
2608 GP_1_21_FN, FN_IP3_31_28,
2609 GP_1_20_FN, FN_IP3_27_24,
2610 GP_1_19_FN, FN_IP3_23_20,
2611 GP_1_18_FN, FN_IP3_19_16,
2612 GP_1_17_FN, FN_IP3_15_12,
2613 GP_1_16_FN, FN_IP3_11_8,
2614 GP_1_15_FN, FN_IP3_7_4,
2615 GP_1_14_FN, FN_IP3_3_0,
2616 GP_1_13_FN, FN_IP2_31_28,
2617 GP_1_12_FN, FN_IP2_27_24,
2618 GP_1_11_FN, FN_IP2_23_20,
2619 GP_1_10_FN, FN_IP2_19_16,
2620 GP_1_9_FN, FN_IP2_15_12,
2621 GP_1_8_FN, FN_IP2_11_8,
2622 GP_1_7_FN, FN_IP2_7_4,
2623 GP_1_6_FN, FN_IP2_3_0,
2624 GP_1_5_FN, FN_IP1_31_28,
2625 GP_1_4_FN, FN_IP1_27_24,
2626 GP_1_3_FN, FN_IP1_23_20,
2627 GP_1_2_FN, FN_IP1_19_16,
2628 GP_1_1_FN, FN_IP1_15_12,
2629 GP_1_0_FN, FN_IP1_11_8, ))
2630 },
2631 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2632 GP_2_31_FN, FN_IP8_3_0,
2633 GP_2_30_FN, FN_IP7_31_28,
2634 GP_2_29_FN, FN_IP7_27_24,
2635 GP_2_28_FN, FN_IP7_23_20,
2636 GP_2_27_FN, FN_IP7_19_16,
2637 GP_2_26_FN, FN_IP7_15_12,
2638 GP_2_25_FN, FN_IP7_11_8,
2639 GP_2_24_FN, FN_IP7_7_4,
2640 GP_2_23_FN, FN_IP7_3_0,
2641 GP_2_22_FN, FN_IP6_31_28,
2642 GP_2_21_FN, FN_IP6_27_24,
2643 GP_2_20_FN, FN_IP6_23_20,
2644 GP_2_19_FN, FN_IP6_19_16,
2645 GP_2_18_FN, FN_IP6_15_12,
2646 GP_2_17_FN, FN_IP6_11_8,
2647 GP_2_16_FN, FN_IP6_7_4,
2648 GP_2_15_FN, FN_IP6_3_0,
2649 GP_2_14_FN, FN_IP5_31_28,
2650 GP_2_13_FN, FN_IP5_27_24,
2651 GP_2_12_FN, FN_IP5_23_20,
2652 GP_2_11_FN, FN_IP5_19_16,
2653 GP_2_10_FN, FN_IP5_15_12,
2654 GP_2_9_FN, FN_IP5_11_8,
2655 GP_2_8_FN, FN_IP5_7_4,
2656 GP_2_7_FN, FN_IP5_3_0,
2657 GP_2_6_FN, FN_IP4_31_28,
2658 GP_2_5_FN, FN_IP4_27_24,
2659 GP_2_4_FN, FN_IP4_23_20,
2660 GP_2_3_FN, FN_IP4_19_16,
2661 GP_2_2_FN, FN_IP4_15_12,
2662 GP_2_1_FN, FN_IP4_11_8,
2663 GP_2_0_FN, FN_IP4_7_4, ))
2664 },
2665 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2666 0, 0,
2667 0, 0,
2668 GP_3_29_FN, FN_IP10_19_16,
2669 GP_3_28_FN, FN_IP10_15_12,
2670 GP_3_27_FN, FN_IP10_11_8,
2671 0, 0,
2672 0, 0,
2673 0, 0,
2674 0, 0,
2675 0, 0,
2676 0, 0,
2677 0, 0,
2678 0, 0,
2679 0, 0,
2680 0, 0,
2681 GP_3_16_FN, FN_IP10_7_4,
2682 GP_3_15_FN, FN_IP10_3_0,
2683 GP_3_14_FN, FN_IP9_31_28,
2684 GP_3_13_FN, FN_IP9_27_24,
2685 GP_3_12_FN, FN_IP9_23_20,
2686 GP_3_11_FN, FN_IP9_19_16,
2687 GP_3_10_FN, FN_IP9_15_12,
2688 GP_3_9_FN, FN_IP9_11_8,
2689 GP_3_8_FN, FN_IP9_7_4,
2690 GP_3_7_FN, FN_IP9_3_0,
2691 GP_3_6_FN, FN_IP8_31_28,
2692 GP_3_5_FN, FN_IP8_27_24,
2693 GP_3_4_FN, FN_IP8_23_20,
2694 GP_3_3_FN, FN_IP8_19_16,
2695 GP_3_2_FN, FN_IP8_15_12,
2696 GP_3_1_FN, FN_IP8_11_8,
2697 GP_3_0_FN, FN_IP8_7_4, ))
2698 },
2699 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2700 0, 0,
2701 0, 0,
2702 0, 0,
2703 0, 0,
2704 0, 0,
2705 0, 0,
2706 GP_4_25_FN, FN_IP13_27_24,
2707 GP_4_24_FN, FN_IP13_23_20,
2708 GP_4_23_FN, FN_IP13_19_16,
2709 GP_4_22_FN, FN_IP13_15_12,
2710 GP_4_21_FN, FN_IP13_11_8,
2711 GP_4_20_FN, FN_IP13_7_4,
2712 GP_4_19_FN, FN_IP13_3_0,
2713 GP_4_18_FN, FN_IP12_31_28,
2714 GP_4_17_FN, FN_IP12_27_24,
2715 GP_4_16_FN, FN_IP12_23_20,
2716 GP_4_15_FN, FN_IP12_19_16,
2717 GP_4_14_FN, FN_IP12_15_12,
2718 GP_4_13_FN, FN_IP12_11_8,
2719 GP_4_12_FN, FN_IP12_7_4,
2720 GP_4_11_FN, FN_IP12_3_0,
2721 GP_4_10_FN, FN_IP11_31_28,
2722 GP_4_9_FN, FN_IP11_27_24,
2723 GP_4_8_FN, FN_IP11_23_20,
2724 GP_4_7_FN, FN_IP11_19_16,
2725 GP_4_6_FN, FN_IP11_15_12,
2726 GP_4_5_FN, FN_IP11_11_8,
2727 GP_4_4_FN, FN_IP11_7_4,
2728 GP_4_3_FN, FN_IP11_3_0,
2729 GP_4_2_FN, FN_IP10_31_28,
2730 GP_4_1_FN, FN_IP10_27_24,
2731 GP_4_0_FN, FN_IP10_23_20, ))
2732 },
2733 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2734 GP_5_31_FN, FN_IP17_27_24,
2735 GP_5_30_FN, FN_IP17_23_20,
2736 GP_5_29_FN, FN_IP17_19_16,
2737 GP_5_28_FN, FN_IP17_15_12,
2738 GP_5_27_FN, FN_IP17_11_8,
2739 GP_5_26_FN, FN_IP17_7_4,
2740 GP_5_25_FN, FN_IP17_3_0,
2741 GP_5_24_FN, FN_IP16_31_28,
2742 GP_5_23_FN, FN_IP16_27_24,
2743 GP_5_22_FN, FN_IP16_23_20,
2744 GP_5_21_FN, FN_IP16_19_16,
2745 GP_5_20_FN, FN_IP16_15_12,
2746 GP_5_19_FN, FN_IP16_11_8,
2747 GP_5_18_FN, FN_IP16_7_4,
2748 GP_5_17_FN, FN_IP16_3_0,
2749 GP_5_16_FN, FN_IP15_31_28,
2750 GP_5_15_FN, FN_IP15_27_24,
2751 GP_5_14_FN, FN_IP15_23_20,
2752 GP_5_13_FN, FN_IP15_19_16,
2753 GP_5_12_FN, FN_IP15_15_12,
2754 GP_5_11_FN, FN_IP15_11_8,
2755 GP_5_10_FN, FN_IP15_7_4,
2756 GP_5_9_FN, FN_IP15_3_0,
2757 GP_5_8_FN, FN_IP14_31_28,
2758 GP_5_7_FN, FN_IP14_27_24,
2759 GP_5_6_FN, FN_IP14_23_20,
2760 GP_5_5_FN, FN_IP14_19_16,
2761 GP_5_4_FN, FN_IP14_15_12,
2762 GP_5_3_FN, FN_IP14_11_8,
2763 GP_5_2_FN, FN_IP14_7_4,
2764 GP_5_1_FN, FN_IP14_3_0,
2765 GP_5_0_FN, FN_IP13_31_28, ))
2766 },
2767 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2768 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2769 GROUP(
2770
2771 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2772 0, 0, 0, 0, 0, 0, 0, 0,
2773
2774 FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
2775 0, 0, 0, 0, 0, 0, 0, 0,
2776
2777 FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
2778 0, 0, 0, 0, 0, 0, 0, 0,
2779
2780 FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782
2783 FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785
2786 FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
2787 0, 0, 0, 0, 0, 0, 0, 0,
2788
2789 FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
2790 0, 0, 0, 0, 0, 0, 0, 0,
2791
2792 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2793 0, 0, 0, 0, 0, 0, 0, 0, ))
2794 },
2795 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2796 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2797 GROUP(
2798
2799 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2800 0, 0, 0, 0, 0, 0, 0, 0,
2801
2802 FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
2803 0, 0, 0, 0, 0, 0, 0, 0,
2804
2805 FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
2806 FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2807
2808 FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
2809 FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2810
2811 FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
2812 FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2813
2814 FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
2815 FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2816
2817 FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
2818 0, 0, 0, 0, 0, 0, 0, 0,
2819
2820 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2821 0, 0, 0, 0, 0, 0, 0, 0, ))
2822 },
2823 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2824 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2825 GROUP(
2826
2827 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2828 0, 0, 0, 0, 0, 0, 0,
2829
2830 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
2831 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2832
2833 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
2834 0, 0, 0, 0, 0, 0, 0,
2835
2836 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
2837 0, 0, 0, 0, 0, 0, 0,
2838
2839 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
2840 0, 0, 0, 0, 0, 0, 0, 0, 0,
2841
2842 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
2843 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2844
2845 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
2846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2847
2848 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2849 0, 0, 0, 0, 0, 0, 0, 0, ))
2850 },
2851 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2852 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2853 GROUP(
2854
2855 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2856 0, 0,
2857
2858 FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2859 0, 0,
2860
2861 FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2862 0, 0,
2863
2864 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2865 0, 0, 0, 0,
2866
2867 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2868 0, 0, 0,
2869
2870 FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2871 0, 0,
2872
2873 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
2874 FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2875
2876 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2877 0, FN_AVB_AVTP_CAPTURE_A,
2878 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2879 },
2880 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2881 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2882 GROUP(
2883
2884 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2885 0, 0, 0, 0, 0, 0, 0, 0,
2886
2887 FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
2888 0, 0, 0, 0, 0, 0, 0, 0,
2889
2890 FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
2891 0, 0, 0, 0, 0,
2892
2893 FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
2894 FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2895
2896 FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
2897 0, 0, 0, 0, 0, 0, 0, 0,
2898
2899 FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
2900 0, 0, 0, 0, 0, 0, 0, 0,
2901
2902 FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
2903 0, 0, 0, 0, 0, 0, 0, 0,
2904
2905 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2906 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2907 },
2908 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2909 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2910 GROUP(
2911
2912 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
2913 0, 0, 0, 0, 0, 0,
2914
2915 FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
2916 0, 0, 0, 0, 0, 0, 0, 0, 0,
2917
2918 FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
2919 0, 0, 0, 0, 0, 0,
2920
2921 FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
2922 0, 0, 0, 0, 0, 0, 0, 0,
2923
2924 FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
2925 0, 0, 0, 0, 0, 0,
2926
2927 FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
2928 FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2929
2930 FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
2931 0, 0, 0, 0, 0, 0, 0, 0,
2932
2933 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2934 0, 0, 0, 0, 0, 0, 0, 0, ))
2935 },
2936 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2937 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2938 GROUP(
2939
2940 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2941 0, 0, 0, 0, 0, 0, 0,
2942
2943 FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
2944 FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2945
2946 FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
2947 FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2948
2949 FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
2950 0, 0, 0, 0, 0, 0,
2951
2952 FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
2953 0, 0, 0, 0, 0, 0,
2954
2955 FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
2956 0, 0, 0, 0, 0, 0, 0, 0, 0,
2957
2958 FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
2959 0, 0, 0, 0, 0, 0, 0, 0, 0,
2960
2961 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
2962 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2963 },
2964 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2965 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2966 GROUP(
2967
2968 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2969 0, 0, 0, 0, 0,
2970
2971 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
2972 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2973
2974 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
2975 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2976
2977 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
2978 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2979
2980 FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
2981 FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2982
2983 FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
2984 0, 0, 0, 0, 0,
2985
2986 FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
2987 0, 0, 0, 0, 0, 0,
2988
2989 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2990 0, 0, 0, 0, 0, 0, 0, ))
2991 },
2992 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
2993 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2994 GROUP(
2995
2996 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2997 0, 0, 0, 0, 0, 0,
2998
2999 FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
3000 0, 0, 0, 0, 0, 0,
3001
3002 FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
3003 0, 0, 0, 0, 0, 0,
3004
3005 FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
3006 0, 0, 0, 0, 0, 0,
3007
3008 FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
3009 0, 0, 0, 0, 0, 0,
3010
3011 FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
3012 0, 0, 0, 0, 0, 0, 0,
3013
3014 FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
3015 0, 0, 0, 0, 0, 0, 0,
3016
3017 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
3018 0, 0, 0, 0, ))
3019 },
3020 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
3021 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3022 GROUP(
3023
3024 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
3025 0, 0, 0, 0, 0,
3026
3027 FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
3028 0, 0, 0, 0, 0,
3029
3030 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
3031 FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3032
3033 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
3034 FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3035
3036 FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
3037 0, 0, 0, 0, 0, 0, 0, 0, 0,
3038
3039 FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
3040 0, 0, 0, 0, 0, 0, 0, 0, 0,
3041
3042 FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
3043 0, 0, 0, 0, 0, 0,
3044
3045 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
3046 0, 0, 0, 0, 0, 0, ))
3047 },
3048 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3049 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3050 GROUP(
3051
3052 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
3053 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
3054
3055 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
3056 FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3057
3058 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
3059 FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3060
3061 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
3062 FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
3063 0, 0,
3064
3065 FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
3066 FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3067
3068 FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
3069 FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3070
3071 FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
3072 0, 0, 0, 0, 0, 0, 0,
3073
3074 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
3075 0, 0, 0, 0, 0, 0, 0, ))
3076 },
3077 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3078 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3079 GROUP(
3080
3081 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
3082 0, 0, 0, 0, 0, 0, 0, 0, 0,
3083
3084 FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
3085 FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3086
3087 FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
3088 FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3089
3090 FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
3091 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
3092 0, 0, 0, 0,
3093
3094 FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
3095 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
3096 0, 0, 0, 0, 0, 0, 0, 0,
3097
3098 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
3099 FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
3100 0, 0, 0, 0, 0, 0, 0, 0,
3101
3102 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
3103 FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
3104 0, 0, 0, 0, 0, 0, 0, 0,
3105
3106 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
3107 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
3108 },
3109 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3110 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3111 GROUP(
3112
3113 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
3114 0, 0, 0, 0, 0, 0, 0, 0, 0,
3115
3116 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
3117 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3118
3119 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
3120 FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3121
3122 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
3123 FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3124
3125 FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
3126 0, 0, 0, 0, 0, 0, 0, 0,
3127
3128 FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
3129 0, 0, 0, 0, 0, 0, 0, 0,
3130
3131 FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
3132 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3133
3134 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3135 0, 0, 0, 0, 0, 0, ))
3136 },
3137 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3138 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3139 GROUP(
3140
3141 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3142 0, 0, 0, 0, 0,
3143
3144 FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3145 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3146
3147 FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3148 FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3149
3150 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
3151 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3152
3153 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
3154 FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
3155 0, 0,
3156
3157 FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
3158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3159
3160 FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
3161 0, 0, 0, 0, 0, 0, 0, 0, 0,
3162
3163 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3164 0, 0, 0, 0, 0, 0, 0, 0, ))
3165 },
3166 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3167 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3168 GROUP(
3169
3170 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3171 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3172
3173 FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
3174 0, 0, 0, 0, 0,
3175
3176 FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
3177 0, 0, 0, 0, 0, 0,
3178
3179 FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
3180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3181
3182 FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
3183 0, 0, 0, 0, 0, 0, 0, 0, 0,
3184
3185 FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
3186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3187
3188 FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
3189 0, 0, 0, 0, 0, 0, 0, 0, 0,
3190
3191 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3192 0, 0, 0, 0, 0, 0, ))
3193 },
3194 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3195 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3196 GROUP(
3197
3198 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3199 0, 0, 0, 0, 0, 0,
3200
3201 FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
3202 0, 0, 0, 0, 0, 0,
3203
3204 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
3205 FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3206
3207 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
3208 FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3209
3210 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
3211 FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3212
3213 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
3214 FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3215
3216 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
3217 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218
3219 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3220 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3221 },
3222 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3223 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3224 GROUP(
3225
3226 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3227 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3228
3229 FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
3230 FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3231
3232 FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
3233 FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3234
3235 FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
3236 0, 0, 0, 0, 0, 0, 0, 0, 0,
3237
3238 FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
3239 FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
3240 0, 0, 0,
3241
3242 FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
3243 FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3244
3245 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
3246 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3247
3248 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3249 0, 0, 0, 0, 0, 0, ))
3250 },
3251 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3252 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3253 GROUP(
3254
3255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3256
3257 FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
3258 FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3259
3260 FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
3261 FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3262
3263 FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
3264 FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3265
3266 FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
3267 FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3268
3269 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
3270 FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3271
3272 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
3273 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3274
3275 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3276 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3277 },
3278 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3279 GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
3280 3, 3, 1, 2, 3, 3, 1),
3281 GROUP(
3282
3283 0, 0,
3284
3285 0, 0,
3286
3287 0, 0,
3288
3289 0, 0,
3290
3291 0, 0,
3292
3293 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
3294
3295 0, 0,
3296
3297 0, 0,
3298
3299 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
3300 FN_SEL_CANCLK_3,
3301
3302 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
3303
3304 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3305
3306 0, 0,
3307
3308 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
3309 FN_SEL_I2C04_4, 0, 0, 0,
3310
3311 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
3312 FN_SEL_I2C03_4, 0, 0, 0,
3313
3314 0, 0,
3315
3316 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
3317
3318 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
3319 FN_SEL_I2C01_4, 0, 0, 0,
3320
3321 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
3322 FN_SEL_I2C00_4, 0, 0, 0,
3323
3324 FN_SEL_AVB_0, FN_SEL_AVB_1, ))
3325 },
3326 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3327 GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
3328 1, 1, 2, 1, 1, 2, 2, 1),
3329 GROUP(
3330
3331 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3332
3333 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3334 FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
3335
3336 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3337 FN_SEL_SCIF4_4, 0, 0, 0,
3338
3339 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
3340
3341 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3342
3343 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
3344
3345 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3346
3347 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3348
3349 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
3350
3351 0, 0,
3352
3353 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
3354
3355 0, 0,
3356
3357 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
3358
3359 FN_SEL_RCN_0, FN_SEL_RCN_1,
3360
3361 0, 0, 0, 0,
3362
3363 FN_SEL_TMU2_0, FN_SEL_TMU2_1,
3364
3365 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3366
3367 0, 0, 0, 0,
3368
3369 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3370
3371 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
3372 },
3373 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3374 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3375 2, 2, 2, 2, 2, 2, 2, 2, 2),
3376 GROUP(
3377
3378 0, 0,
3379
3380 0, 0,
3381
3382 0, 0,
3383
3384 0, 0,
3385
3386 0, 0,
3387
3388 0, 0,
3389
3390 0, 0,
3391
3392 0, 0,
3393
3394 0, 0,
3395
3396 0, 0,
3397
3398 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
3399
3400 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
3401
3402 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
3403
3404 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
3405
3406 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
3407
3408 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
3409
3410 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
3411
3412 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
3413
3414 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
3415
3416 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
3417
3418 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3419 },
3420 { },
3421};
3422
3423static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
3424 u32 *pocctrl)
3425{
3426 int bit = -EINVAL;
3427
3428 *pocctrl = 0xe60600b0;
3429
3430 if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
3431 bit = 0;
3432
3433 if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
3434 bit = 2;
3435
3436 if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
3437 bit = 1;
3438
3439 return bit;
3440}
3441
3442static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3443 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
3444
3445 [ 0] = RCAR_GP_PIN(1, 0),
3446 [ 1] = RCAR_GP_PIN(0, 22),
3447 [ 2] = RCAR_GP_PIN(0, 21),
3448 [ 3] = RCAR_GP_PIN(0, 20),
3449 [ 4] = RCAR_GP_PIN(0, 19),
3450 [ 5] = RCAR_GP_PIN(0, 18),
3451 [ 6] = RCAR_GP_PIN(0, 17),
3452 [ 7] = RCAR_GP_PIN(0, 16),
3453 [ 8] = RCAR_GP_PIN(0, 15),
3454 [ 9] = RCAR_GP_PIN(0, 14),
3455 [10] = RCAR_GP_PIN(0, 13),
3456 [11] = RCAR_GP_PIN(0, 12),
3457 [12] = RCAR_GP_PIN(0, 11),
3458 [13] = RCAR_GP_PIN(0, 10),
3459 [14] = RCAR_GP_PIN(0, 9),
3460 [15] = RCAR_GP_PIN(0, 8),
3461 [16] = RCAR_GP_PIN(0, 7),
3462 [17] = RCAR_GP_PIN(0, 6),
3463 [18] = RCAR_GP_PIN(0, 5),
3464 [19] = RCAR_GP_PIN(0, 4),
3465 [20] = PIN_NMI,
3466 [21] = RCAR_GP_PIN(0, 3),
3467 [22] = RCAR_GP_PIN(0, 2),
3468 [23] = RCAR_GP_PIN(0, 1),
3469 [24] = RCAR_GP_PIN(0, 0),
3470 [25] = SH_PFC_PIN_NONE,
3471 [26] = PIN_TDO,
3472 [27] = PIN_TDI,
3473 [28] = PIN_TMS,
3474 [29] = PIN_TCK,
3475 [30] = PIN_TRST_N,
3476 [31] = PIN_PRESETOUT_N,
3477 } },
3478 { PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
3479
3480 [ 0] = SH_PFC_PIN_NONE,
3481 [ 1] = SH_PFC_PIN_NONE,
3482 [ 2] = SH_PFC_PIN_NONE,
3483 [ 3] = SH_PFC_PIN_NONE,
3484 [ 4] = SH_PFC_PIN_NONE,
3485 [ 5] = SH_PFC_PIN_NONE,
3486 [ 6] = SH_PFC_PIN_NONE,
3487 [ 7] = SH_PFC_PIN_NONE,
3488 [ 8] = SH_PFC_PIN_NONE,
3489 [ 9] = SH_PFC_PIN_NONE,
3490 [10] = SH_PFC_PIN_NONE,
3491 [11] = SH_PFC_PIN_NONE,
3492 [12] = SH_PFC_PIN_NONE,
3493 [13] = SH_PFC_PIN_NONE,
3494 [14] = SH_PFC_PIN_NONE,
3495 [15] = SH_PFC_PIN_NONE,
3496 [16] = SH_PFC_PIN_NONE,
3497 [17] = SH_PFC_PIN_NONE,
3498 [18] = SH_PFC_PIN_NONE,
3499 [19] = SH_PFC_PIN_NONE,
3500 [20] = SH_PFC_PIN_NONE,
3501 [21] = SH_PFC_PIN_NONE,
3502 [22] = SH_PFC_PIN_NONE,
3503 [23] = SH_PFC_PIN_NONE,
3504 [24] = SH_PFC_PIN_NONE,
3505 [25] = PIN_ASEBRK_N_ACK,
3506 [26] = SH_PFC_PIN_NONE,
3507 [27] = SH_PFC_PIN_NONE,
3508 [28] = SH_PFC_PIN_NONE,
3509 [29] = SH_PFC_PIN_NONE,
3510 [30] = SH_PFC_PIN_NONE,
3511 [31] = SH_PFC_PIN_NONE,
3512 } },
3513 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
3514 [ 0] = RCAR_GP_PIN(2, 9),
3515 [ 1] = RCAR_GP_PIN(2, 8),
3516 [ 2] = RCAR_GP_PIN(2, 7),
3517 [ 3] = RCAR_GP_PIN(2, 6),
3518 [ 4] = RCAR_GP_PIN(2, 5),
3519 [ 5] = RCAR_GP_PIN(2, 4),
3520 [ 6] = RCAR_GP_PIN(2, 3),
3521 [ 7] = RCAR_GP_PIN(2, 2),
3522 [ 8] = RCAR_GP_PIN(2, 1),
3523 [ 9] = RCAR_GP_PIN(2, 0),
3524 [10] = RCAR_GP_PIN(1, 22),
3525 [11] = RCAR_GP_PIN(1, 21),
3526 [12] = RCAR_GP_PIN(1, 20),
3527 [13] = RCAR_GP_PIN(1, 19),
3528 [14] = RCAR_GP_PIN(1, 18),
3529 [15] = RCAR_GP_PIN(1, 17),
3530 [16] = RCAR_GP_PIN(1, 16),
3531 [17] = RCAR_GP_PIN(1, 15),
3532 [18] = RCAR_GP_PIN(1, 14),
3533 [19] = RCAR_GP_PIN(1, 13),
3534 [20] = RCAR_GP_PIN(1, 12),
3535 [21] = RCAR_GP_PIN(1, 11),
3536 [22] = RCAR_GP_PIN(1, 10),
3537 [23] = RCAR_GP_PIN(1, 9),
3538 [24] = RCAR_GP_PIN(1, 8),
3539 [25] = RCAR_GP_PIN(1, 7),
3540 [26] = RCAR_GP_PIN(1, 6),
3541 [27] = RCAR_GP_PIN(1, 5),
3542 [28] = RCAR_GP_PIN(1, 4),
3543 [29] = RCAR_GP_PIN(1, 3),
3544 [30] = RCAR_GP_PIN(1, 2),
3545 [31] = RCAR_GP_PIN(1, 1),
3546 } },
3547 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
3548 [ 0] = RCAR_GP_PIN(3, 9),
3549 [ 1] = RCAR_GP_PIN(3, 8),
3550 [ 2] = RCAR_GP_PIN(3, 7),
3551 [ 3] = RCAR_GP_PIN(3, 6),
3552 [ 4] = RCAR_GP_PIN(3, 5),
3553 [ 5] = RCAR_GP_PIN(3, 4),
3554 [ 6] = RCAR_GP_PIN(3, 3),
3555 [ 7] = RCAR_GP_PIN(3, 2),
3556 [ 8] = RCAR_GP_PIN(3, 1),
3557 [ 9] = RCAR_GP_PIN(3, 0),
3558 [10] = RCAR_GP_PIN(2, 31),
3559 [11] = RCAR_GP_PIN(2, 30),
3560 [12] = RCAR_GP_PIN(2, 29),
3561 [13] = RCAR_GP_PIN(2, 28),
3562 [14] = RCAR_GP_PIN(2, 27),
3563 [15] = RCAR_GP_PIN(2, 26),
3564 [16] = RCAR_GP_PIN(2, 25),
3565 [17] = RCAR_GP_PIN(2, 24),
3566 [18] = RCAR_GP_PIN(2, 23),
3567 [19] = RCAR_GP_PIN(2, 22),
3568 [20] = RCAR_GP_PIN(2, 21),
3569 [21] = RCAR_GP_PIN(2, 20),
3570 [22] = RCAR_GP_PIN(2, 19),
3571 [23] = RCAR_GP_PIN(2, 18),
3572 [24] = RCAR_GP_PIN(2, 17),
3573 [25] = RCAR_GP_PIN(2, 16),
3574 [26] = RCAR_GP_PIN(2, 15),
3575 [27] = RCAR_GP_PIN(2, 14),
3576 [28] = RCAR_GP_PIN(2, 13),
3577 [29] = RCAR_GP_PIN(2, 12),
3578 [30] = RCAR_GP_PIN(2, 11),
3579 [31] = RCAR_GP_PIN(2, 10),
3580 } },
3581 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
3582 [ 0] = RCAR_GP_PIN(4, 21),
3583 [ 1] = RCAR_GP_PIN(4, 20),
3584 [ 2] = RCAR_GP_PIN(4, 19),
3585 [ 3] = RCAR_GP_PIN(4, 18),
3586 [ 4] = RCAR_GP_PIN(4, 17),
3587 [ 5] = RCAR_GP_PIN(4, 16),
3588 [ 6] = RCAR_GP_PIN(4, 15),
3589 [ 7] = RCAR_GP_PIN(4, 14),
3590 [ 8] = RCAR_GP_PIN(4, 13),
3591 [ 9] = RCAR_GP_PIN(4, 12),
3592 [10] = RCAR_GP_PIN(4, 11),
3593 [11] = RCAR_GP_PIN(4, 10),
3594 [12] = RCAR_GP_PIN(4, 9),
3595 [13] = RCAR_GP_PIN(4, 8),
3596 [14] = RCAR_GP_PIN(4, 7),
3597 [15] = RCAR_GP_PIN(4, 6),
3598 [16] = RCAR_GP_PIN(4, 5),
3599 [17] = RCAR_GP_PIN(4, 4),
3600 [18] = RCAR_GP_PIN(4, 3),
3601 [19] = RCAR_GP_PIN(4, 2),
3602 [20] = RCAR_GP_PIN(4, 1),
3603 [21] = RCAR_GP_PIN(4, 0),
3604 [22] = RCAR_GP_PIN(3, 29),
3605 [23] = RCAR_GP_PIN(3, 28),
3606 [24] = RCAR_GP_PIN(3, 27),
3607 [25] = RCAR_GP_PIN(3, 16),
3608 [26] = RCAR_GP_PIN(3, 15),
3609 [27] = RCAR_GP_PIN(3, 14),
3610 [28] = RCAR_GP_PIN(3, 13),
3611 [29] = RCAR_GP_PIN(3, 12),
3612 [30] = RCAR_GP_PIN(3, 11),
3613 [31] = RCAR_GP_PIN(3, 10),
3614 } },
3615 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
3616 [ 0] = RCAR_GP_PIN(5, 27),
3617 [ 1] = RCAR_GP_PIN(5, 26),
3618 [ 2] = RCAR_GP_PIN(5, 25),
3619 [ 3] = RCAR_GP_PIN(5, 24),
3620 [ 4] = RCAR_GP_PIN(5, 23),
3621 [ 5] = RCAR_GP_PIN(5, 22),
3622 [ 6] = RCAR_GP_PIN(5, 21),
3623 [ 7] = RCAR_GP_PIN(5, 20),
3624 [ 8] = RCAR_GP_PIN(5, 19),
3625 [ 9] = RCAR_GP_PIN(5, 18),
3626 [10] = RCAR_GP_PIN(5, 17),
3627 [11] = RCAR_GP_PIN(5, 16),
3628 [12] = RCAR_GP_PIN(5, 15),
3629 [13] = RCAR_GP_PIN(5, 14),
3630 [14] = RCAR_GP_PIN(5, 13),
3631 [15] = RCAR_GP_PIN(5, 12),
3632 [16] = RCAR_GP_PIN(5, 11),
3633 [17] = RCAR_GP_PIN(5, 10),
3634 [18] = RCAR_GP_PIN(5, 9),
3635 [19] = RCAR_GP_PIN(5, 8),
3636 [20] = RCAR_GP_PIN(5, 7),
3637 [21] = RCAR_GP_PIN(5, 6),
3638 [22] = RCAR_GP_PIN(5, 5),
3639 [23] = RCAR_GP_PIN(5, 4),
3640 [24] = RCAR_GP_PIN(5, 3),
3641 [25] = RCAR_GP_PIN(5, 2),
3642 [26] = RCAR_GP_PIN(5, 1),
3643 [27] = RCAR_GP_PIN(5, 0),
3644 [28] = RCAR_GP_PIN(4, 25),
3645 [29] = RCAR_GP_PIN(4, 24),
3646 [30] = RCAR_GP_PIN(4, 23),
3647 [31] = RCAR_GP_PIN(4, 22),
3648 } },
3649 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
3650 [ 0] = SH_PFC_PIN_NONE,
3651 [ 1] = SH_PFC_PIN_NONE,
3652 [ 2] = SH_PFC_PIN_NONE,
3653 [ 3] = SH_PFC_PIN_NONE,
3654 [ 4] = SH_PFC_PIN_NONE,
3655 [ 5] = SH_PFC_PIN_NONE,
3656 [ 6] = SH_PFC_PIN_NONE,
3657 [ 7] = SH_PFC_PIN_NONE,
3658 [ 8] = SH_PFC_PIN_NONE,
3659 [ 9] = SH_PFC_PIN_NONE,
3660 [10] = SH_PFC_PIN_NONE,
3661 [11] = SH_PFC_PIN_NONE,
3662 [12] = SH_PFC_PIN_NONE,
3663 [13] = SH_PFC_PIN_NONE,
3664 [14] = SH_PFC_PIN_NONE,
3665 [15] = SH_PFC_PIN_NONE,
3666 [16] = SH_PFC_PIN_NONE,
3667 [17] = SH_PFC_PIN_NONE,
3668 [18] = SH_PFC_PIN_NONE,
3669 [19] = SH_PFC_PIN_NONE,
3670 [20] = SH_PFC_PIN_NONE,
3671 [21] = SH_PFC_PIN_NONE,
3672 [22] = SH_PFC_PIN_NONE,
3673 [23] = SH_PFC_PIN_NONE,
3674 [24] = SH_PFC_PIN_NONE,
3675 [25] = SH_PFC_PIN_NONE,
3676 [26] = SH_PFC_PIN_NONE,
3677 [27] = SH_PFC_PIN_NONE,
3678 [28] = RCAR_GP_PIN(5, 31),
3679 [29] = RCAR_GP_PIN(5, 30),
3680 [30] = RCAR_GP_PIN(5, 29),
3681 [31] = RCAR_GP_PIN(5, 28),
3682 } },
3683 { }
3684};
3685
3686static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
3687 .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
3688 .get_bias = rcar_pinmux_get_bias,
3689 .set_bias = rcar_pinmux_set_bias,
3690};
3691
3692#ifdef CONFIG_PINCTRL_PFC_R8A77470
3693const struct sh_pfc_soc_info r8a77470_pinmux_info = {
3694 .name = "r8a77470_pfc",
3695 .ops = &r8a77470_pinmux_ops,
3696 .unlock_reg = 0xe6060000,
3697
3698 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3699
3700 .pins = pinmux_pins,
3701 .nr_pins = ARRAY_SIZE(pinmux_pins),
3702 .groups = pinmux_groups,
3703 .nr_groups = ARRAY_SIZE(pinmux_groups),
3704 .functions = pinmux_functions,
3705 .nr_functions = ARRAY_SIZE(pinmux_functions),
3706
3707 .cfg_regs = pinmux_config_regs,
3708 .bias_regs = pinmux_bias_regs,
3709
3710 .pinmux_data = pinmux_data,
3711 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3712};
3713#endif
3714
