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14#include <linux/errno.h>
15#include <linux/kernel.h>
16
17#include "sh_pfc.h"
18
19#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
20
21#define CPU_ALL_GP(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34
35#define CPU_ALL_NOGP(fn) \
36 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
55 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
71 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
75 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
77 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
78 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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84
85
86#define GPSR0_15 F_(D15, IP7_11_8)
87#define GPSR0_14 F_(D14, IP7_7_4)
88#define GPSR0_13 F_(D13, IP7_3_0)
89#define GPSR0_12 F_(D12, IP6_31_28)
90#define GPSR0_11 F_(D11, IP6_27_24)
91#define GPSR0_10 F_(D10, IP6_23_20)
92#define GPSR0_9 F_(D9, IP6_19_16)
93#define GPSR0_8 F_(D8, IP6_15_12)
94#define GPSR0_7 F_(D7, IP6_11_8)
95#define GPSR0_6 F_(D6, IP6_7_4)
96#define GPSR0_5 F_(D5, IP6_3_0)
97#define GPSR0_4 F_(D4, IP5_31_28)
98#define GPSR0_3 F_(D3, IP5_27_24)
99#define GPSR0_2 F_(D2, IP5_23_20)
100#define GPSR0_1 F_(D1, IP5_19_16)
101#define GPSR0_0 F_(D0, IP5_15_12)
102
103
104#define GPSR1_28 FM(CLKOUT)
105#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106#define GPSR1_26 F_(WE1_N, IP5_7_4)
107#define GPSR1_25 F_(WE0_N, IP5_3_0)
108#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109#define GPSR1_23 F_(RD_N, IP4_27_24)
110#define GPSR1_22 F_(BS_N, IP4_23_20)
111#define GPSR1_21 F_(CS1_N, IP4_19_16)
112#define GPSR1_20 F_(CS0_N, IP4_15_12)
113#define GPSR1_19 F_(A19, IP4_11_8)
114#define GPSR1_18 F_(A18, IP4_7_4)
115#define GPSR1_17 F_(A17, IP4_3_0)
116#define GPSR1_16 F_(A16, IP3_31_28)
117#define GPSR1_15 F_(A15, IP3_27_24)
118#define GPSR1_14 F_(A14, IP3_23_20)
119#define GPSR1_13 F_(A13, IP3_19_16)
120#define GPSR1_12 F_(A12, IP3_15_12)
121#define GPSR1_11 F_(A11, IP3_11_8)
122#define GPSR1_10 F_(A10, IP3_7_4)
123#define GPSR1_9 F_(A9, IP3_3_0)
124#define GPSR1_8 F_(A8, IP2_31_28)
125#define GPSR1_7 F_(A7, IP2_27_24)
126#define GPSR1_6 F_(A6, IP2_23_20)
127#define GPSR1_5 F_(A5, IP2_19_16)
128#define GPSR1_4 F_(A4, IP2_15_12)
129#define GPSR1_3 F_(A3, IP2_11_8)
130#define GPSR1_2 F_(A2, IP2_7_4)
131#define GPSR1_1 F_(A1, IP2_3_0)
132#define GPSR1_0 F_(A0, IP1_31_28)
133
134
135#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141#define GPSR2_8 F_(PWM2_A, IP1_27_24)
142#define GPSR2_7 F_(PWM1_A, IP1_23_20)
143#define GPSR2_6 F_(PWM0, IP1_19_16)
144#define GPSR2_5 F_(IRQ5, IP1_15_12)
145#define GPSR2_4 F_(IRQ4, IP1_11_8)
146#define GPSR2_3 F_(IRQ3, IP1_7_4)
147#define GPSR2_2 F_(IRQ2, IP1_3_0)
148#define GPSR2_1 F_(IRQ1, IP0_31_28)
149#define GPSR2_0 F_(IRQ0, IP0_27_24)
150
151
152#define GPSR3_15 F_(SD1_WP, IP11_23_20)
153#define GPSR3_14 F_(SD1_CD, IP11_19_16)
154#define GPSR3_13 F_(SD0_WP, IP11_15_12)
155#define GPSR3_12 F_(SD0_CD, IP11_11_8)
156#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
168
169
170#define GPSR4_17 F_(SD3_DS, IP11_7_4)
171#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181#define GPSR4_6 F_(SD2_DS, IP9_27_24)
182#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
188
189
190#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193#define GPSR5_22 FM(MSIOF0_RXD)
194#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195#define GPSR5_20 FM(MSIOF0_TXD)
196#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198#define GPSR5_17 FM(MSIOF0_SCK)
199#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201#define GPSR5_14 F_(HTX0, IP13_19_16)
202#define GPSR5_13 F_(HRX0, IP13_15_12)
203#define GPSR5_12 F_(HSCK0, IP13_11_8)
204#define GPSR5_11 F_(RX2_A, IP13_7_4)
205#define GPSR5_10 F_(TX2_A, IP13_3_0)
206#define GPSR5_9 F_(SCK2, IP12_31_28)
207#define GPSR5_8 F_(RTS1_N, IP12_27_24)
208#define GPSR5_7 F_(CTS1_N, IP12_23_20)
209#define GPSR5_6 F_(TX1_A, IP12_19_16)
210#define GPSR5_5 F_(RX1_A, IP12_15_12)
211#define GPSR5_4 F_(RTS0_N, IP12_11_8)
212#define GPSR5_3 F_(CTS0_N, IP12_7_4)
213#define GPSR5_2 F_(TX0, IP12_3_0)
214#define GPSR5_1 F_(RX0, IP11_31_28)
215#define GPSR5_0 F_(SCK0, IP11_27_24)
216
217
218#define GPSR6_31 F_(GP6_31, IP18_7_4)
219#define GPSR6_30 F_(GP6_30, IP18_3_0)
220#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236#define GPSR6_13 FM(SSI_SDATA5)
237#define GPSR6_12 FM(SSI_WS5)
238#define GPSR6_11 FM(SSI_SCK5)
239#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
250
251
252#define GPSR7_3 FM(GP7_03)
253#define GPSR7_2 FM(GP7_02)
254#define GPSR7_1 FM(AVS2)
255#define GPSR7_0 FM(AVS1)
256
257
258
259#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286
287
288#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318
319#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353
354
355#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383
384
385#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
412
413#define PINMUX_GPSR \
414\
415 GPSR6_31 \
416 GPSR6_30 \
417 GPSR6_29 \
418 GPSR1_28 GPSR6_28 \
419 GPSR1_27 GPSR6_27 \
420 GPSR1_26 GPSR6_26 \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
447
448#define PINMUX_IPSR \
449\
450FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
458\
459FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
467\
468FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
476\
477FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
485\
486FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
494
495
496#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
514
515
516#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
538
539
540#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
553
554#define PINMUX_MOD_SELS \
555\
556MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
557 MOD_SEL2_30 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559MOD_SEL0_28_27 MOD_SEL2_28_27 \
560MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562MOD_SEL0_23 MOD_SEL1_23_22_21 \
563MOD_SEL0_22 MOD_SEL2_22 \
564MOD_SEL0_21 MOD_SEL2_21 \
565MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
568 MOD_SEL2_17 \
569MOD_SEL0_16 MOD_SEL1_16 \
570 MOD_SEL1_15_14 \
571MOD_SEL0_14_13 \
572 MOD_SEL1_13 \
573MOD_SEL0_12 MOD_SEL1_12 \
574MOD_SEL0_11 MOD_SEL1_11 \
575MOD_SEL0_10 MOD_SEL1_10 \
576MOD_SEL0_9_8 MOD_SEL1_9 \
577MOD_SEL0_7_6 \
578 MOD_SEL1_6 \
579MOD_SEL0_5 MOD_SEL1_5 \
580MOD_SEL0_4_3 MOD_SEL1_4 \
581 MOD_SEL1_3 \
582 MOD_SEL1_2 \
583 MOD_SEL1_1 \
584 MOD_SEL1_0 MOD_SEL2_0
585
586
587
588
589
590#define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
599 FM(PRESETOUT) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
602
603#define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
605
606enum {
607 PINMUX_RESERVED = 0,
608
609 PINMUX_DATA_BEGIN,
610 GP_ALL(DATA),
611 PINMUX_DATA_END,
612
613#define F_(x, y)
614#define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
616 GP_ALL(FN),
617 PINMUX_GPSR
618 PINMUX_IPSR
619 PINMUX_MOD_SELS
620 PINMUX_FUNCTION_END,
621#undef F_
622#undef FM
623
624#define F_(x, y)
625#define FM(x) x##_MARK,
626 PINMUX_MARK_BEGIN,
627 PINMUX_GPSR
628 PINMUX_IPSR
629 PINMUX_MOD_SELS
630 PINMUX_STATIC
631 PINMUX_PHYS
632 PINMUX_MARK_END,
633#undef F_
634#undef FM
635};
636
637static const u16 pinmux_data[] = {
638 PINMUX_DATA_GP_ALL(),
639
640 PINMUX_SINGLE(AVS1),
641 PINMUX_SINGLE(AVS2),
642 PINMUX_SINGLE(CLKOUT),
643 PINMUX_SINGLE(GP7_03),
644 PINMUX_SINGLE(GP7_02),
645 PINMUX_SINGLE(MSIOF0_RXD),
646 PINMUX_SINGLE(MSIOF0_SCK),
647 PINMUX_SINGLE(MSIOF0_TXD),
648 PINMUX_SINGLE(SSI_SCK5),
649 PINMUX_SINGLE(SSI_SDATA5),
650 PINMUX_SINGLE(SSI_WS5),
651
652
653 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
655
656 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
659
660 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
663
664 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
667
668 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
671 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
672
673 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
676 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
677
678 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
679 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
680 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
681 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
685
686 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
687 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
688 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
689 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
693
694
695 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
696 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
697 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
698 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
699 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
701
702 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
703 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
704 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
705 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
706 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
707 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
708
709 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
710 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
711 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
712 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
713 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
714 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
715
716 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
717 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
718 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
719 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
720 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
722
723 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
724 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
725 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
726 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
727
728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
732 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
733
734 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
737 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
738
739 PINMUX_IPSR_GPSR(IP1_31_28, A0),
740 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
741 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
742 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
743 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
744 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
745
746
747 PINMUX_IPSR_GPSR(IP2_3_0, A1),
748 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
749 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
750 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
751 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
752 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
753
754 PINMUX_IPSR_GPSR(IP2_7_4, A2),
755 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
756 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
757 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
758 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
759 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
760
761 PINMUX_IPSR_GPSR(IP2_11_8, A3),
762 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
763 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
764 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
765 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
766 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
767
768 PINMUX_IPSR_GPSR(IP2_15_12, A4),
769 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
770 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
771 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
772 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
773 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
774
775 PINMUX_IPSR_GPSR(IP2_19_16, A5),
776 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
777 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
778 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
779 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
780 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
781 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
782
783 PINMUX_IPSR_GPSR(IP2_23_20, A6),
784 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
785 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
786 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
787 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
788 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
789 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
790
791 PINMUX_IPSR_GPSR(IP2_27_24, A7),
792 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
793 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
794 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
795 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
796 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
797 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
798
799 PINMUX_IPSR_GPSR(IP2_31_28, A8),
800 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
801 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
802 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
803 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
804 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
805 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
806
807
808 PINMUX_IPSR_GPSR(IP3_3_0, A9),
809 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
810 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
811 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
812
813 PINMUX_IPSR_GPSR(IP3_7_4, A10),
814 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
817
818 PINMUX_IPSR_GPSR(IP3_11_8, A11),
819 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
820 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
821 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
822 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
823 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
824 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
825 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
826 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
827
828 PINMUX_IPSR_GPSR(IP3_15_12, A12),
829 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
830 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
831 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
832 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
833 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
834
835 PINMUX_IPSR_GPSR(IP3_19_16, A13),
836 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
837 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
838 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
839 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
840 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
841
842 PINMUX_IPSR_GPSR(IP3_23_20, A14),
843 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
844 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
845 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
846 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
847 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
848
849 PINMUX_IPSR_GPSR(IP3_27_24, A15),
850 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
851 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
852 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
853 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
854 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
855
856 PINMUX_IPSR_GPSR(IP3_31_28, A16),
857 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
858 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
859 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
860
861
862 PINMUX_IPSR_GPSR(IP4_3_0, A17),
863 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
864 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
865 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
866
867 PINMUX_IPSR_GPSR(IP4_7_4, A18),
868 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
869 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
870 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
871
872 PINMUX_IPSR_GPSR(IP4_11_8, A19),
873 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
874 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
875 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
876
877 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
878 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
879
880 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
881 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
882 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
883
884 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
885 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
886 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
887 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
888 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
889 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
890 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
891 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
892
893 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
894 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
895 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
896 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
897 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
899
900 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
901 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
902 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
903 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
904 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
906
907
908 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
909 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
910 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
911 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
912 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
913 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
914 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
915
916 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
917 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
918 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
919 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
920 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
921 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
922 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
923 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
924
925 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
926 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
927 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
928 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
929
930 PINMUX_IPSR_GPSR(IP5_15_12, D0),
931 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
933 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
934 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
935
936 PINMUX_IPSR_GPSR(IP5_19_16, D1),
937 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
939 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
940 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
941
942 PINMUX_IPSR_GPSR(IP5_23_20, D2),
943 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
944 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
945 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
946
947 PINMUX_IPSR_GPSR(IP5_27_24, D3),
948 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
951
952 PINMUX_IPSR_GPSR(IP5_31_28, D4),
953 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
954 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
955 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
956
957
958 PINMUX_IPSR_GPSR(IP6_3_0, D5),
959 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
960 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
961 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
962
963 PINMUX_IPSR_GPSR(IP6_7_4, D6),
964 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
965 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
966 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
967
968 PINMUX_IPSR_GPSR(IP6_11_8, D7),
969 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
970 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
971 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
972
973 PINMUX_IPSR_GPSR(IP6_15_12, D8),
974 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
975 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
976 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
977 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
979
980 PINMUX_IPSR_GPSR(IP6_19_16, D9),
981 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
982 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
983 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
985
986 PINMUX_IPSR_GPSR(IP6_23_20, D10),
987 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
988 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
989 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
990 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
991 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
992 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
993
994 PINMUX_IPSR_GPSR(IP6_27_24, D11),
995 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
996 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
997 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
998 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
999 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1000 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1001
1002 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1003 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1004 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1005 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1006 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1007 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1008
1009
1010 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1011 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1012 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1013 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1014 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1015 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1016
1017 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1018 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1019 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1020 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1021 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1022 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1023 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1024
1025 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1026 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1027 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1028 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1029 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1030 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1031 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1032
1033 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1034 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1035 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1036
1037 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1038 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1039 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1040
1041 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1042 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1043 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1044 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1045
1046 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1047 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1048 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1049 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1050
1051
1052 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1053 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1054 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1055 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1056
1057 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1058 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1059 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1060 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1061
1062 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1063 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1064 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1065
1066 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1067 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1068 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1069 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1070 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1071
1072 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1073 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1074 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1075 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1076 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1077 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1078
1079 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1080 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1081 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1082 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1083 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1084 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1085
1086 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1087 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1088 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1089 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1090 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1091 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1092
1093 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1094 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1095 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1096 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1097 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1098 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1099
1100
1101 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1102 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1103
1104 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1105 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1106
1107 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1108 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1109
1110 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1111 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1112
1113 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1114 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1115
1116 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1117 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1118
1119 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1120 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1121
1122 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1123 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1124
1125
1126 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1127 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1128
1129 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1130 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1131
1132 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1133 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1134
1135 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1136 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1137
1138 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1139 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1140
1141 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1142 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1143 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1144
1145 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1146 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1147 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1148
1149 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1151 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1152
1153
1154 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1156 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1157
1158 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1159 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1160
1161 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1162 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1163 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1164 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1165
1166 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1167 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1168 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1169
1170 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1171 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1173 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1174
1175 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1176 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1178 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1179
1180 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1181 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1182 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1183 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1184 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1185 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1187 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1188 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1189 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1190
1191 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1192 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1193 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1194 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1196
1197
1198 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1199 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1200 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1201 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1202 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1203
1204 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1205 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1206 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1207 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1208 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1209 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1210 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1211 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1212
1213 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1214 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1215 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1216 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1217 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1218 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1219 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1220 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1221
1222 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1223 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1225 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1226 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1227
1228 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1229 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1231 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1232 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1233
1234 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1235 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1236 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1237 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1238 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1239 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1240 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1241
1242 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1243 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1244 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1245 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1246 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1247 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1248 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1249
1250 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1251 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1252 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1253 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1254 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1256 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1257
1258
1259 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1260 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1261 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1262 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1263 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1264 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1265
1266 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1267 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1268 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1269 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1270 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1271 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1272
1273 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1274 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1275 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1276 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1277 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1278 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1280 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1281
1282 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1283 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1285 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1286 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1288
1289 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1290 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1291 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1292 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1293 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1294 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1295
1296 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1297 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1298 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1299 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1300 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1301 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1302 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1303 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1304
1305 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1306 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1307 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1308 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1309 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1310 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1311 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1312
1313 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1314 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1315 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1316 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1317
1318
1319 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1320 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1321 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1322 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1323 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1324 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1325 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1326 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1327
1328 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1329 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1330 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1331 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1332 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1333 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1334 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1335 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1336
1337 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1338 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1339 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1340
1341 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1342 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1343 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1344 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1345
1346 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1347 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1348 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1349
1350 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1351 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1352
1353 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1354 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1355
1356 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1357 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1358
1359
1360 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1361
1362 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1364
1365 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1366 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1367 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1368
1369 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1370 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1371 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1372 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1373
1374 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1375 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1376 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1377 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1378 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1381
1382 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1383 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1384 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1389
1390 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1391 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1392 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1397
1398 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1399 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1400 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1401 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1402 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1405
1406
1407 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1408 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1409
1410 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1411 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1412
1413 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1414 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1415
1416 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1417 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1418 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1419 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1420 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1421 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1423
1424 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1425 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1426 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1427 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1428 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1431
1432 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1433 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1434 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1435 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1436 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1437 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1440
1441 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1442 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1443 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1444 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1445 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1446 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1448
1449 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1450 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1451 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1452 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1453 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1454 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1455 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1456 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1457
1458
1459 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1460
1461 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1462 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1463 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1464 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1465 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1466
1467 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1468 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1469 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1472 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1474
1475 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1476 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1477 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1478 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1479 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1480 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1481
1482 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1483 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1484 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1485 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1488 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1490 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1491
1492 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1493 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1494 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1495 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1498 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1499 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1500 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1501
1502 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1503 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1504 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1505 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1506 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1508 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1509 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1510 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1511 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1512 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1513
1514 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1515 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1516 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1517 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1518 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1520 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1521 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1522 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1523
1524
1525 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1526 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1527 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1528 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1529 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1530 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1531 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1532 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1534
1535 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1536 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1537 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1538 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1539 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1540 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1541 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1542 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1544
1545
1546
1547
1548
1549
1550
1551
1552#define FM(x) PINMUX_DATA(x##_MARK, 0),
1553 PINMUX_STATIC
1554#undef FM
1555};
1556
1557
1558
1559
1560enum {
1561 GP_ASSIGN_LAST(),
1562 NOGP_ALL(),
1563};
1564
1565static const struct sh_pfc_pin pinmux_pins[] = {
1566 PINMUX_GPIO_GP_ALL(),
1567 PINMUX_NOGP_ALL(),
1568};
1569
1570
1571static const unsigned int audio_clk_a_a_pins[] = {
1572
1573 RCAR_GP_PIN(6, 22),
1574};
1575static const unsigned int audio_clk_a_a_mux[] = {
1576 AUDIO_CLKA_A_MARK,
1577};
1578static const unsigned int audio_clk_a_b_pins[] = {
1579
1580 RCAR_GP_PIN(5, 4),
1581};
1582static const unsigned int audio_clk_a_b_mux[] = {
1583 AUDIO_CLKA_B_MARK,
1584};
1585static const unsigned int audio_clk_a_c_pins[] = {
1586
1587 RCAR_GP_PIN(5, 19),
1588};
1589static const unsigned int audio_clk_a_c_mux[] = {
1590 AUDIO_CLKA_C_MARK,
1591};
1592static const unsigned int audio_clk_b_a_pins[] = {
1593
1594 RCAR_GP_PIN(5, 12),
1595};
1596static const unsigned int audio_clk_b_a_mux[] = {
1597 AUDIO_CLKB_A_MARK,
1598};
1599static const unsigned int audio_clk_b_b_pins[] = {
1600
1601 RCAR_GP_PIN(6, 23),
1602};
1603static const unsigned int audio_clk_b_b_mux[] = {
1604 AUDIO_CLKB_B_MARK,
1605};
1606static const unsigned int audio_clk_c_a_pins[] = {
1607
1608 RCAR_GP_PIN(5, 21),
1609};
1610static const unsigned int audio_clk_c_a_mux[] = {
1611 AUDIO_CLKC_A_MARK,
1612};
1613static const unsigned int audio_clk_c_b_pins[] = {
1614
1615 RCAR_GP_PIN(5, 0),
1616};
1617static const unsigned int audio_clk_c_b_mux[] = {
1618 AUDIO_CLKC_B_MARK,
1619};
1620static const unsigned int audio_clkout_a_pins[] = {
1621
1622 RCAR_GP_PIN(5, 18),
1623};
1624static const unsigned int audio_clkout_a_mux[] = {
1625 AUDIO_CLKOUT_A_MARK,
1626};
1627static const unsigned int audio_clkout_b_pins[] = {
1628
1629 RCAR_GP_PIN(6, 28),
1630};
1631static const unsigned int audio_clkout_b_mux[] = {
1632 AUDIO_CLKOUT_B_MARK,
1633};
1634static const unsigned int audio_clkout_c_pins[] = {
1635
1636 RCAR_GP_PIN(5, 3),
1637};
1638static const unsigned int audio_clkout_c_mux[] = {
1639 AUDIO_CLKOUT_C_MARK,
1640};
1641static const unsigned int audio_clkout_d_pins[] = {
1642
1643 RCAR_GP_PIN(5, 21),
1644};
1645static const unsigned int audio_clkout_d_mux[] = {
1646 AUDIO_CLKOUT_D_MARK,
1647};
1648static const unsigned int audio_clkout1_a_pins[] = {
1649
1650 RCAR_GP_PIN(5, 15),
1651};
1652static const unsigned int audio_clkout1_a_mux[] = {
1653 AUDIO_CLKOUT1_A_MARK,
1654};
1655static const unsigned int audio_clkout1_b_pins[] = {
1656
1657 RCAR_GP_PIN(6, 29),
1658};
1659static const unsigned int audio_clkout1_b_mux[] = {
1660 AUDIO_CLKOUT1_B_MARK,
1661};
1662static const unsigned int audio_clkout2_a_pins[] = {
1663
1664 RCAR_GP_PIN(5, 16),
1665};
1666static const unsigned int audio_clkout2_a_mux[] = {
1667 AUDIO_CLKOUT2_A_MARK,
1668};
1669static const unsigned int audio_clkout2_b_pins[] = {
1670
1671 RCAR_GP_PIN(6, 30),
1672};
1673static const unsigned int audio_clkout2_b_mux[] = {
1674 AUDIO_CLKOUT2_B_MARK,
1675};
1676
1677static const unsigned int audio_clkout3_a_pins[] = {
1678
1679 RCAR_GP_PIN(5, 19),
1680};
1681static const unsigned int audio_clkout3_a_mux[] = {
1682 AUDIO_CLKOUT3_A_MARK,
1683};
1684static const unsigned int audio_clkout3_b_pins[] = {
1685
1686 RCAR_GP_PIN(6, 31),
1687};
1688static const unsigned int audio_clkout3_b_mux[] = {
1689 AUDIO_CLKOUT3_B_MARK,
1690};
1691
1692
1693static const unsigned int avb_link_pins[] = {
1694
1695 RCAR_GP_PIN(2, 12),
1696};
1697static const unsigned int avb_link_mux[] = {
1698 AVB_LINK_MARK,
1699};
1700static const unsigned int avb_magic_pins[] = {
1701
1702 RCAR_GP_PIN(2, 10),
1703};
1704static const unsigned int avb_magic_mux[] = {
1705 AVB_MAGIC_MARK,
1706};
1707static const unsigned int avb_phy_int_pins[] = {
1708
1709 RCAR_GP_PIN(2, 11),
1710};
1711static const unsigned int avb_phy_int_mux[] = {
1712 AVB_PHY_INT_MARK,
1713};
1714static const unsigned int avb_mdio_pins[] = {
1715
1716 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1717};
1718static const unsigned int avb_mdio_mux[] = {
1719 AVB_MDC_MARK, AVB_MDIO_MARK,
1720};
1721static const unsigned int avb_mii_pins[] = {
1722
1723
1724
1725
1726
1727
1728
1729 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1730 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1731 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1733 PIN_AVB_TXCREFCLK,
1734};
1735static const unsigned int avb_mii_mux[] = {
1736 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1737 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1738 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1739 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1740 AVB_TXCREFCLK_MARK,
1741};
1742static const unsigned int avb_avtp_pps_pins[] = {
1743
1744 RCAR_GP_PIN(2, 6),
1745};
1746static const unsigned int avb_avtp_pps_mux[] = {
1747 AVB_AVTP_PPS_MARK,
1748};
1749static const unsigned int avb_avtp_match_a_pins[] = {
1750
1751 RCAR_GP_PIN(2, 13),
1752};
1753static const unsigned int avb_avtp_match_a_mux[] = {
1754 AVB_AVTP_MATCH_A_MARK,
1755};
1756static const unsigned int avb_avtp_capture_a_pins[] = {
1757
1758 RCAR_GP_PIN(2, 14),
1759};
1760static const unsigned int avb_avtp_capture_a_mux[] = {
1761 AVB_AVTP_CAPTURE_A_MARK,
1762};
1763static const unsigned int avb_avtp_match_b_pins[] = {
1764
1765 RCAR_GP_PIN(1, 8),
1766};
1767static const unsigned int avb_avtp_match_b_mux[] = {
1768 AVB_AVTP_MATCH_B_MARK,
1769};
1770static const unsigned int avb_avtp_capture_b_pins[] = {
1771
1772 RCAR_GP_PIN(1, 11),
1773};
1774static const unsigned int avb_avtp_capture_b_mux[] = {
1775 AVB_AVTP_CAPTURE_B_MARK,
1776};
1777
1778
1779static const unsigned int can0_data_a_pins[] = {
1780
1781 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1782};
1783static const unsigned int can0_data_a_mux[] = {
1784 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1785};
1786static const unsigned int can0_data_b_pins[] = {
1787
1788 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1789};
1790static const unsigned int can0_data_b_mux[] = {
1791 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1792};
1793static const unsigned int can1_data_pins[] = {
1794
1795 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1796};
1797static const unsigned int can1_data_mux[] = {
1798 CAN1_TX_MARK, CAN1_RX_MARK,
1799};
1800
1801
1802static const unsigned int can_clk_pins[] = {
1803
1804 RCAR_GP_PIN(1, 25),
1805};
1806static const unsigned int can_clk_mux[] = {
1807 CAN_CLK_MARK,
1808};
1809
1810
1811static const unsigned int canfd0_data_a_pins[] = {
1812
1813 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1814};
1815static const unsigned int canfd0_data_a_mux[] = {
1816 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1817};
1818static const unsigned int canfd0_data_b_pins[] = {
1819
1820 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1821};
1822static const unsigned int canfd0_data_b_mux[] = {
1823 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1824};
1825static const unsigned int canfd1_data_pins[] = {
1826
1827 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1828};
1829static const unsigned int canfd1_data_mux[] = {
1830 CANFD1_TX_MARK, CANFD1_RX_MARK,
1831};
1832
1833#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1834
1835static const unsigned int drif0_ctrl_a_pins[] = {
1836
1837 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838};
1839static const unsigned int drif0_ctrl_a_mux[] = {
1840 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1841};
1842static const unsigned int drif0_data0_a_pins[] = {
1843
1844 RCAR_GP_PIN(6, 10),
1845};
1846static const unsigned int drif0_data0_a_mux[] = {
1847 RIF0_D0_A_MARK,
1848};
1849static const unsigned int drif0_data1_a_pins[] = {
1850
1851 RCAR_GP_PIN(6, 7),
1852};
1853static const unsigned int drif0_data1_a_mux[] = {
1854 RIF0_D1_A_MARK,
1855};
1856static const unsigned int drif0_ctrl_b_pins[] = {
1857
1858 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1859};
1860static const unsigned int drif0_ctrl_b_mux[] = {
1861 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1862};
1863static const unsigned int drif0_data0_b_pins[] = {
1864
1865 RCAR_GP_PIN(5, 1),
1866};
1867static const unsigned int drif0_data0_b_mux[] = {
1868 RIF0_D0_B_MARK,
1869};
1870static const unsigned int drif0_data1_b_pins[] = {
1871
1872 RCAR_GP_PIN(5, 2),
1873};
1874static const unsigned int drif0_data1_b_mux[] = {
1875 RIF0_D1_B_MARK,
1876};
1877static const unsigned int drif0_ctrl_c_pins[] = {
1878
1879 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1880};
1881static const unsigned int drif0_ctrl_c_mux[] = {
1882 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1883};
1884static const unsigned int drif0_data0_c_pins[] = {
1885
1886 RCAR_GP_PIN(5, 13),
1887};
1888static const unsigned int drif0_data0_c_mux[] = {
1889 RIF0_D0_C_MARK,
1890};
1891static const unsigned int drif0_data1_c_pins[] = {
1892
1893 RCAR_GP_PIN(5, 14),
1894};
1895static const unsigned int drif0_data1_c_mux[] = {
1896 RIF0_D1_C_MARK,
1897};
1898
1899static const unsigned int drif1_ctrl_a_pins[] = {
1900
1901 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1902};
1903static const unsigned int drif1_ctrl_a_mux[] = {
1904 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1905};
1906static const unsigned int drif1_data0_a_pins[] = {
1907
1908 RCAR_GP_PIN(6, 19),
1909};
1910static const unsigned int drif1_data0_a_mux[] = {
1911 RIF1_D0_A_MARK,
1912};
1913static const unsigned int drif1_data1_a_pins[] = {
1914
1915 RCAR_GP_PIN(6, 20),
1916};
1917static const unsigned int drif1_data1_a_mux[] = {
1918 RIF1_D1_A_MARK,
1919};
1920static const unsigned int drif1_ctrl_b_pins[] = {
1921
1922 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1923};
1924static const unsigned int drif1_ctrl_b_mux[] = {
1925 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1926};
1927static const unsigned int drif1_data0_b_pins[] = {
1928
1929 RCAR_GP_PIN(5, 7),
1930};
1931static const unsigned int drif1_data0_b_mux[] = {
1932 RIF1_D0_B_MARK,
1933};
1934static const unsigned int drif1_data1_b_pins[] = {
1935
1936 RCAR_GP_PIN(5, 8),
1937};
1938static const unsigned int drif1_data1_b_mux[] = {
1939 RIF1_D1_B_MARK,
1940};
1941static const unsigned int drif1_ctrl_c_pins[] = {
1942
1943 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1944};
1945static const unsigned int drif1_ctrl_c_mux[] = {
1946 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1947};
1948static const unsigned int drif1_data0_c_pins[] = {
1949
1950 RCAR_GP_PIN(5, 6),
1951};
1952static const unsigned int drif1_data0_c_mux[] = {
1953 RIF1_D0_C_MARK,
1954};
1955static const unsigned int drif1_data1_c_pins[] = {
1956
1957 RCAR_GP_PIN(5, 10),
1958};
1959static const unsigned int drif1_data1_c_mux[] = {
1960 RIF1_D1_C_MARK,
1961};
1962
1963static const unsigned int drif2_ctrl_a_pins[] = {
1964
1965 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1966};
1967static const unsigned int drif2_ctrl_a_mux[] = {
1968 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1969};
1970static const unsigned int drif2_data0_a_pins[] = {
1971
1972 RCAR_GP_PIN(6, 7),
1973};
1974static const unsigned int drif2_data0_a_mux[] = {
1975 RIF2_D0_A_MARK,
1976};
1977static const unsigned int drif2_data1_a_pins[] = {
1978
1979 RCAR_GP_PIN(6, 10),
1980};
1981static const unsigned int drif2_data1_a_mux[] = {
1982 RIF2_D1_A_MARK,
1983};
1984static const unsigned int drif2_ctrl_b_pins[] = {
1985
1986 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1987};
1988static const unsigned int drif2_ctrl_b_mux[] = {
1989 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1990};
1991static const unsigned int drif2_data0_b_pins[] = {
1992
1993 RCAR_GP_PIN(6, 30),
1994};
1995static const unsigned int drif2_data0_b_mux[] = {
1996 RIF2_D0_B_MARK,
1997};
1998static const unsigned int drif2_data1_b_pins[] = {
1999
2000 RCAR_GP_PIN(6, 31),
2001};
2002static const unsigned int drif2_data1_b_mux[] = {
2003 RIF2_D1_B_MARK,
2004};
2005
2006static const unsigned int drif3_ctrl_a_pins[] = {
2007
2008 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2009};
2010static const unsigned int drif3_ctrl_a_mux[] = {
2011 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2012};
2013static const unsigned int drif3_data0_a_pins[] = {
2014
2015 RCAR_GP_PIN(6, 19),
2016};
2017static const unsigned int drif3_data0_a_mux[] = {
2018 RIF3_D0_A_MARK,
2019};
2020static const unsigned int drif3_data1_a_pins[] = {
2021
2022 RCAR_GP_PIN(6, 20),
2023};
2024static const unsigned int drif3_data1_a_mux[] = {
2025 RIF3_D1_A_MARK,
2026};
2027static const unsigned int drif3_ctrl_b_pins[] = {
2028
2029 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2030};
2031static const unsigned int drif3_ctrl_b_mux[] = {
2032 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2033};
2034static const unsigned int drif3_data0_b_pins[] = {
2035
2036 RCAR_GP_PIN(6, 28),
2037};
2038static const unsigned int drif3_data0_b_mux[] = {
2039 RIF3_D0_B_MARK,
2040};
2041static const unsigned int drif3_data1_b_pins[] = {
2042
2043 RCAR_GP_PIN(6, 29),
2044};
2045static const unsigned int drif3_data1_b_mux[] = {
2046 RIF3_D1_B_MARK,
2047};
2048#endif
2049
2050
2051static const unsigned int du_rgb666_pins[] = {
2052
2053 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2055 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2056 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2057 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2058 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2059};
2060static const unsigned int du_rgb666_mux[] = {
2061 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2062 DU_DR3_MARK, DU_DR2_MARK,
2063 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2064 DU_DG3_MARK, DU_DG2_MARK,
2065 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2066 DU_DB3_MARK, DU_DB2_MARK,
2067};
2068static const unsigned int du_rgb888_pins[] = {
2069
2070 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2073 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2074 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2075 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2076 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2077 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2078 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2079};
2080static const unsigned int du_rgb888_mux[] = {
2081 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2082 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2083 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2084 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2085 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2086 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2087};
2088static const unsigned int du_clk_out_0_pins[] = {
2089
2090 RCAR_GP_PIN(1, 27),
2091};
2092static const unsigned int du_clk_out_0_mux[] = {
2093 DU_DOTCLKOUT0_MARK
2094};
2095static const unsigned int du_clk_out_1_pins[] = {
2096
2097 RCAR_GP_PIN(2, 3),
2098};
2099static const unsigned int du_clk_out_1_mux[] = {
2100 DU_DOTCLKOUT1_MARK
2101};
2102static const unsigned int du_sync_pins[] = {
2103
2104 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2105};
2106static const unsigned int du_sync_mux[] = {
2107 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108};
2109static const unsigned int du_oddf_pins[] = {
2110
2111 RCAR_GP_PIN(2, 2),
2112};
2113static const unsigned int du_oddf_mux[] = {
2114 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115};
2116static const unsigned int du_cde_pins[] = {
2117
2118 RCAR_GP_PIN(2, 0),
2119};
2120static const unsigned int du_cde_mux[] = {
2121 DU_CDE_MARK,
2122};
2123static const unsigned int du_disp_pins[] = {
2124
2125 RCAR_GP_PIN(2, 1),
2126};
2127static const unsigned int du_disp_mux[] = {
2128 DU_DISP_MARK,
2129};
2130
2131
2132static const unsigned int hscif0_data_pins[] = {
2133
2134 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2135};
2136static const unsigned int hscif0_data_mux[] = {
2137 HRX0_MARK, HTX0_MARK,
2138};
2139static const unsigned int hscif0_clk_pins[] = {
2140
2141 RCAR_GP_PIN(5, 12),
2142};
2143static const unsigned int hscif0_clk_mux[] = {
2144 HSCK0_MARK,
2145};
2146static const unsigned int hscif0_ctrl_pins[] = {
2147
2148 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2149};
2150static const unsigned int hscif0_ctrl_mux[] = {
2151 HRTS0_N_MARK, HCTS0_N_MARK,
2152};
2153
2154static const unsigned int hscif1_data_a_pins[] = {
2155
2156 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2157};
2158static const unsigned int hscif1_data_a_mux[] = {
2159 HRX1_A_MARK, HTX1_A_MARK,
2160};
2161static const unsigned int hscif1_clk_a_pins[] = {
2162
2163 RCAR_GP_PIN(6, 21),
2164};
2165static const unsigned int hscif1_clk_a_mux[] = {
2166 HSCK1_A_MARK,
2167};
2168static const unsigned int hscif1_ctrl_a_pins[] = {
2169
2170 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2171};
2172static const unsigned int hscif1_ctrl_a_mux[] = {
2173 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2174};
2175
2176static const unsigned int hscif1_data_b_pins[] = {
2177
2178 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2179};
2180static const unsigned int hscif1_data_b_mux[] = {
2181 HRX1_B_MARK, HTX1_B_MARK,
2182};
2183static const unsigned int hscif1_clk_b_pins[] = {
2184
2185 RCAR_GP_PIN(5, 0),
2186};
2187static const unsigned int hscif1_clk_b_mux[] = {
2188 HSCK1_B_MARK,
2189};
2190static const unsigned int hscif1_ctrl_b_pins[] = {
2191
2192 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2193};
2194static const unsigned int hscif1_ctrl_b_mux[] = {
2195 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2196};
2197
2198static const unsigned int hscif2_data_a_pins[] = {
2199
2200 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2201};
2202static const unsigned int hscif2_data_a_mux[] = {
2203 HRX2_A_MARK, HTX2_A_MARK,
2204};
2205static const unsigned int hscif2_clk_a_pins[] = {
2206
2207 RCAR_GP_PIN(6, 10),
2208};
2209static const unsigned int hscif2_clk_a_mux[] = {
2210 HSCK2_A_MARK,
2211};
2212static const unsigned int hscif2_ctrl_a_pins[] = {
2213
2214 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2215};
2216static const unsigned int hscif2_ctrl_a_mux[] = {
2217 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2218};
2219
2220static const unsigned int hscif2_data_b_pins[] = {
2221
2222 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2223};
2224static const unsigned int hscif2_data_b_mux[] = {
2225 HRX2_B_MARK, HTX2_B_MARK,
2226};
2227static const unsigned int hscif2_clk_b_pins[] = {
2228
2229 RCAR_GP_PIN(6, 21),
2230};
2231static const unsigned int hscif2_clk_b_mux[] = {
2232 HSCK2_B_MARK,
2233};
2234static const unsigned int hscif2_ctrl_b_pins[] = {
2235
2236 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2237};
2238static const unsigned int hscif2_ctrl_b_mux[] = {
2239 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2240};
2241
2242static const unsigned int hscif2_data_c_pins[] = {
2243
2244 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2245};
2246static const unsigned int hscif2_data_c_mux[] = {
2247 HRX2_C_MARK, HTX2_C_MARK,
2248};
2249static const unsigned int hscif2_clk_c_pins[] = {
2250
2251 RCAR_GP_PIN(6, 24),
2252};
2253static const unsigned int hscif2_clk_c_mux[] = {
2254 HSCK2_C_MARK,
2255};
2256static const unsigned int hscif2_ctrl_c_pins[] = {
2257
2258 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2259};
2260static const unsigned int hscif2_ctrl_c_mux[] = {
2261 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2262};
2263
2264static const unsigned int hscif3_data_a_pins[] = {
2265
2266 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2267};
2268static const unsigned int hscif3_data_a_mux[] = {
2269 HRX3_A_MARK, HTX3_A_MARK,
2270};
2271static const unsigned int hscif3_clk_pins[] = {
2272
2273 RCAR_GP_PIN(1, 22),
2274};
2275static const unsigned int hscif3_clk_mux[] = {
2276 HSCK3_MARK,
2277};
2278static const unsigned int hscif3_ctrl_pins[] = {
2279
2280 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2281};
2282static const unsigned int hscif3_ctrl_mux[] = {
2283 HRTS3_N_MARK, HCTS3_N_MARK,
2284};
2285
2286static const unsigned int hscif3_data_b_pins[] = {
2287
2288 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2289};
2290static const unsigned int hscif3_data_b_mux[] = {
2291 HRX3_B_MARK, HTX3_B_MARK,
2292};
2293static const unsigned int hscif3_data_c_pins[] = {
2294
2295 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2296};
2297static const unsigned int hscif3_data_c_mux[] = {
2298 HRX3_C_MARK, HTX3_C_MARK,
2299};
2300static const unsigned int hscif3_data_d_pins[] = {
2301
2302 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2303};
2304static const unsigned int hscif3_data_d_mux[] = {
2305 HRX3_D_MARK, HTX3_D_MARK,
2306};
2307
2308static const unsigned int hscif4_data_a_pins[] = {
2309
2310 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2311};
2312static const unsigned int hscif4_data_a_mux[] = {
2313 HRX4_A_MARK, HTX4_A_MARK,
2314};
2315static const unsigned int hscif4_clk_pins[] = {
2316
2317 RCAR_GP_PIN(1, 11),
2318};
2319static const unsigned int hscif4_clk_mux[] = {
2320 HSCK4_MARK,
2321};
2322static const unsigned int hscif4_ctrl_pins[] = {
2323
2324 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2325};
2326static const unsigned int hscif4_ctrl_mux[] = {
2327 HRTS4_N_MARK, HCTS4_N_MARK,
2328};
2329
2330static const unsigned int hscif4_data_b_pins[] = {
2331
2332 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2333};
2334static const unsigned int hscif4_data_b_mux[] = {
2335 HRX4_B_MARK, HTX4_B_MARK,
2336};
2337
2338
2339static const unsigned int i2c0_pins[] = {
2340
2341 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2342};
2343
2344static const unsigned int i2c0_mux[] = {
2345 SCL0_MARK, SDA0_MARK,
2346};
2347
2348static const unsigned int i2c1_a_pins[] = {
2349
2350 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2351};
2352static const unsigned int i2c1_a_mux[] = {
2353 SDA1_A_MARK, SCL1_A_MARK,
2354};
2355static const unsigned int i2c1_b_pins[] = {
2356
2357 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2358};
2359static const unsigned int i2c1_b_mux[] = {
2360 SDA1_B_MARK, SCL1_B_MARK,
2361};
2362static const unsigned int i2c2_a_pins[] = {
2363
2364 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2365};
2366static const unsigned int i2c2_a_mux[] = {
2367 SDA2_A_MARK, SCL2_A_MARK,
2368};
2369static const unsigned int i2c2_b_pins[] = {
2370
2371 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2372};
2373static const unsigned int i2c2_b_mux[] = {
2374 SDA2_B_MARK, SCL2_B_MARK,
2375};
2376
2377static const unsigned int i2c3_pins[] = {
2378
2379 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2380};
2381
2382static const unsigned int i2c3_mux[] = {
2383 SCL3_MARK, SDA3_MARK,
2384};
2385
2386static const unsigned int i2c5_pins[] = {
2387
2388 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2389};
2390
2391static const unsigned int i2c5_mux[] = {
2392 SCL5_MARK, SDA5_MARK,
2393};
2394
2395static const unsigned int i2c6_a_pins[] = {
2396
2397 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2398};
2399static const unsigned int i2c6_a_mux[] = {
2400 SDA6_A_MARK, SCL6_A_MARK,
2401};
2402static const unsigned int i2c6_b_pins[] = {
2403
2404 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2405};
2406static const unsigned int i2c6_b_mux[] = {
2407 SDA6_B_MARK, SCL6_B_MARK,
2408};
2409static const unsigned int i2c6_c_pins[] = {
2410
2411 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2412};
2413static const unsigned int i2c6_c_mux[] = {
2414 SDA6_C_MARK, SCL6_C_MARK,
2415};
2416
2417
2418static const unsigned int intc_ex_irq0_pins[] = {
2419
2420 RCAR_GP_PIN(2, 0),
2421};
2422static const unsigned int intc_ex_irq0_mux[] = {
2423 IRQ0_MARK,
2424};
2425static const unsigned int intc_ex_irq1_pins[] = {
2426
2427 RCAR_GP_PIN(2, 1),
2428};
2429static const unsigned int intc_ex_irq1_mux[] = {
2430 IRQ1_MARK,
2431};
2432static const unsigned int intc_ex_irq2_pins[] = {
2433
2434 RCAR_GP_PIN(2, 2),
2435};
2436static const unsigned int intc_ex_irq2_mux[] = {
2437 IRQ2_MARK,
2438};
2439static const unsigned int intc_ex_irq3_pins[] = {
2440
2441 RCAR_GP_PIN(2, 3),
2442};
2443static const unsigned int intc_ex_irq3_mux[] = {
2444 IRQ3_MARK,
2445};
2446static const unsigned int intc_ex_irq4_pins[] = {
2447
2448 RCAR_GP_PIN(2, 4),
2449};
2450static const unsigned int intc_ex_irq4_mux[] = {
2451 IRQ4_MARK,
2452};
2453static const unsigned int intc_ex_irq5_pins[] = {
2454
2455 RCAR_GP_PIN(2, 5),
2456};
2457static const unsigned int intc_ex_irq5_mux[] = {
2458 IRQ5_MARK,
2459};
2460
2461
2462static const unsigned int msiof0_clk_pins[] = {
2463
2464 RCAR_GP_PIN(5, 17),
2465};
2466static const unsigned int msiof0_clk_mux[] = {
2467 MSIOF0_SCK_MARK,
2468};
2469static const unsigned int msiof0_sync_pins[] = {
2470
2471 RCAR_GP_PIN(5, 18),
2472};
2473static const unsigned int msiof0_sync_mux[] = {
2474 MSIOF0_SYNC_MARK,
2475};
2476static const unsigned int msiof0_ss1_pins[] = {
2477
2478 RCAR_GP_PIN(5, 19),
2479};
2480static const unsigned int msiof0_ss1_mux[] = {
2481 MSIOF0_SS1_MARK,
2482};
2483static const unsigned int msiof0_ss2_pins[] = {
2484
2485 RCAR_GP_PIN(5, 21),
2486};
2487static const unsigned int msiof0_ss2_mux[] = {
2488 MSIOF0_SS2_MARK,
2489};
2490static const unsigned int msiof0_txd_pins[] = {
2491
2492 RCAR_GP_PIN(5, 20),
2493};
2494static const unsigned int msiof0_txd_mux[] = {
2495 MSIOF0_TXD_MARK,
2496};
2497static const unsigned int msiof0_rxd_pins[] = {
2498
2499 RCAR_GP_PIN(5, 22),
2500};
2501static const unsigned int msiof0_rxd_mux[] = {
2502 MSIOF0_RXD_MARK,
2503};
2504
2505static const unsigned int msiof1_clk_a_pins[] = {
2506
2507 RCAR_GP_PIN(6, 8),
2508};
2509static const unsigned int msiof1_clk_a_mux[] = {
2510 MSIOF1_SCK_A_MARK,
2511};
2512static const unsigned int msiof1_sync_a_pins[] = {
2513
2514 RCAR_GP_PIN(6, 9),
2515};
2516static const unsigned int msiof1_sync_a_mux[] = {
2517 MSIOF1_SYNC_A_MARK,
2518};
2519static const unsigned int msiof1_ss1_a_pins[] = {
2520
2521 RCAR_GP_PIN(6, 5),
2522};
2523static const unsigned int msiof1_ss1_a_mux[] = {
2524 MSIOF1_SS1_A_MARK,
2525};
2526static const unsigned int msiof1_ss2_a_pins[] = {
2527
2528 RCAR_GP_PIN(6, 6),
2529};
2530static const unsigned int msiof1_ss2_a_mux[] = {
2531 MSIOF1_SS2_A_MARK,
2532};
2533static const unsigned int msiof1_txd_a_pins[] = {
2534
2535 RCAR_GP_PIN(6, 7),
2536};
2537static const unsigned int msiof1_txd_a_mux[] = {
2538 MSIOF1_TXD_A_MARK,
2539};
2540static const unsigned int msiof1_rxd_a_pins[] = {
2541
2542 RCAR_GP_PIN(6, 10),
2543};
2544static const unsigned int msiof1_rxd_a_mux[] = {
2545 MSIOF1_RXD_A_MARK,
2546};
2547static const unsigned int msiof1_clk_b_pins[] = {
2548
2549 RCAR_GP_PIN(5, 9),
2550};
2551static const unsigned int msiof1_clk_b_mux[] = {
2552 MSIOF1_SCK_B_MARK,
2553};
2554static const unsigned int msiof1_sync_b_pins[] = {
2555
2556 RCAR_GP_PIN(5, 3),
2557};
2558static const unsigned int msiof1_sync_b_mux[] = {
2559 MSIOF1_SYNC_B_MARK,
2560};
2561static const unsigned int msiof1_ss1_b_pins[] = {
2562
2563 RCAR_GP_PIN(5, 4),
2564};
2565static const unsigned int msiof1_ss1_b_mux[] = {
2566 MSIOF1_SS1_B_MARK,
2567};
2568static const unsigned int msiof1_ss2_b_pins[] = {
2569
2570 RCAR_GP_PIN(5, 0),
2571};
2572static const unsigned int msiof1_ss2_b_mux[] = {
2573 MSIOF1_SS2_B_MARK,
2574};
2575static const unsigned int msiof1_txd_b_pins[] = {
2576
2577 RCAR_GP_PIN(5, 8),
2578};
2579static const unsigned int msiof1_txd_b_mux[] = {
2580 MSIOF1_TXD_B_MARK,
2581};
2582static const unsigned int msiof1_rxd_b_pins[] = {
2583
2584 RCAR_GP_PIN(5, 7),
2585};
2586static const unsigned int msiof1_rxd_b_mux[] = {
2587 MSIOF1_RXD_B_MARK,
2588};
2589static const unsigned int msiof1_clk_c_pins[] = {
2590
2591 RCAR_GP_PIN(6, 17),
2592};
2593static const unsigned int msiof1_clk_c_mux[] = {
2594 MSIOF1_SCK_C_MARK,
2595};
2596static const unsigned int msiof1_sync_c_pins[] = {
2597
2598 RCAR_GP_PIN(6, 18),
2599};
2600static const unsigned int msiof1_sync_c_mux[] = {
2601 MSIOF1_SYNC_C_MARK,
2602};
2603static const unsigned int msiof1_ss1_c_pins[] = {
2604
2605 RCAR_GP_PIN(6, 21),
2606};
2607static const unsigned int msiof1_ss1_c_mux[] = {
2608 MSIOF1_SS1_C_MARK,
2609};
2610static const unsigned int msiof1_ss2_c_pins[] = {
2611
2612 RCAR_GP_PIN(6, 27),
2613};
2614static const unsigned int msiof1_ss2_c_mux[] = {
2615 MSIOF1_SS2_C_MARK,
2616};
2617static const unsigned int msiof1_txd_c_pins[] = {
2618
2619 RCAR_GP_PIN(6, 20),
2620};
2621static const unsigned int msiof1_txd_c_mux[] = {
2622 MSIOF1_TXD_C_MARK,
2623};
2624static const unsigned int msiof1_rxd_c_pins[] = {
2625
2626 RCAR_GP_PIN(6, 19),
2627};
2628static const unsigned int msiof1_rxd_c_mux[] = {
2629 MSIOF1_RXD_C_MARK,
2630};
2631static const unsigned int msiof1_clk_d_pins[] = {
2632
2633 RCAR_GP_PIN(5, 12),
2634};
2635static const unsigned int msiof1_clk_d_mux[] = {
2636 MSIOF1_SCK_D_MARK,
2637};
2638static const unsigned int msiof1_sync_d_pins[] = {
2639
2640 RCAR_GP_PIN(5, 15),
2641};
2642static const unsigned int msiof1_sync_d_mux[] = {
2643 MSIOF1_SYNC_D_MARK,
2644};
2645static const unsigned int msiof1_ss1_d_pins[] = {
2646
2647 RCAR_GP_PIN(5, 16),
2648};
2649static const unsigned int msiof1_ss1_d_mux[] = {
2650 MSIOF1_SS1_D_MARK,
2651};
2652static const unsigned int msiof1_ss2_d_pins[] = {
2653
2654 RCAR_GP_PIN(5, 21),
2655};
2656static const unsigned int msiof1_ss2_d_mux[] = {
2657 MSIOF1_SS2_D_MARK,
2658};
2659static const unsigned int msiof1_txd_d_pins[] = {
2660
2661 RCAR_GP_PIN(5, 14),
2662};
2663static const unsigned int msiof1_txd_d_mux[] = {
2664 MSIOF1_TXD_D_MARK,
2665};
2666static const unsigned int msiof1_rxd_d_pins[] = {
2667
2668 RCAR_GP_PIN(5, 13),
2669};
2670static const unsigned int msiof1_rxd_d_mux[] = {
2671 MSIOF1_RXD_D_MARK,
2672};
2673static const unsigned int msiof1_clk_e_pins[] = {
2674
2675 RCAR_GP_PIN(3, 0),
2676};
2677static const unsigned int msiof1_clk_e_mux[] = {
2678 MSIOF1_SCK_E_MARK,
2679};
2680static const unsigned int msiof1_sync_e_pins[] = {
2681
2682 RCAR_GP_PIN(3, 1),
2683};
2684static const unsigned int msiof1_sync_e_mux[] = {
2685 MSIOF1_SYNC_E_MARK,
2686};
2687static const unsigned int msiof1_ss1_e_pins[] = {
2688
2689 RCAR_GP_PIN(3, 4),
2690};
2691static const unsigned int msiof1_ss1_e_mux[] = {
2692 MSIOF1_SS1_E_MARK,
2693};
2694static const unsigned int msiof1_ss2_e_pins[] = {
2695
2696 RCAR_GP_PIN(3, 5),
2697};
2698static const unsigned int msiof1_ss2_e_mux[] = {
2699 MSIOF1_SS2_E_MARK,
2700};
2701static const unsigned int msiof1_txd_e_pins[] = {
2702
2703 RCAR_GP_PIN(3, 3),
2704};
2705static const unsigned int msiof1_txd_e_mux[] = {
2706 MSIOF1_TXD_E_MARK,
2707};
2708static const unsigned int msiof1_rxd_e_pins[] = {
2709
2710 RCAR_GP_PIN(3, 2),
2711};
2712static const unsigned int msiof1_rxd_e_mux[] = {
2713 MSIOF1_RXD_E_MARK,
2714};
2715static const unsigned int msiof1_clk_f_pins[] = {
2716
2717 RCAR_GP_PIN(5, 23),
2718};
2719static const unsigned int msiof1_clk_f_mux[] = {
2720 MSIOF1_SCK_F_MARK,
2721};
2722static const unsigned int msiof1_sync_f_pins[] = {
2723
2724 RCAR_GP_PIN(5, 24),
2725};
2726static const unsigned int msiof1_sync_f_mux[] = {
2727 MSIOF1_SYNC_F_MARK,
2728};
2729static const unsigned int msiof1_ss1_f_pins[] = {
2730
2731 RCAR_GP_PIN(6, 1),
2732};
2733static const unsigned int msiof1_ss1_f_mux[] = {
2734 MSIOF1_SS1_F_MARK,
2735};
2736static const unsigned int msiof1_ss2_f_pins[] = {
2737
2738 RCAR_GP_PIN(6, 2),
2739};
2740static const unsigned int msiof1_ss2_f_mux[] = {
2741 MSIOF1_SS2_F_MARK,
2742};
2743static const unsigned int msiof1_txd_f_pins[] = {
2744
2745 RCAR_GP_PIN(6, 0),
2746};
2747static const unsigned int msiof1_txd_f_mux[] = {
2748 MSIOF1_TXD_F_MARK,
2749};
2750static const unsigned int msiof1_rxd_f_pins[] = {
2751
2752 RCAR_GP_PIN(5, 25),
2753};
2754static const unsigned int msiof1_rxd_f_mux[] = {
2755 MSIOF1_RXD_F_MARK,
2756};
2757static const unsigned int msiof1_clk_g_pins[] = {
2758
2759 RCAR_GP_PIN(3, 6),
2760};
2761static const unsigned int msiof1_clk_g_mux[] = {
2762 MSIOF1_SCK_G_MARK,
2763};
2764static const unsigned int msiof1_sync_g_pins[] = {
2765
2766 RCAR_GP_PIN(3, 7),
2767};
2768static const unsigned int msiof1_sync_g_mux[] = {
2769 MSIOF1_SYNC_G_MARK,
2770};
2771static const unsigned int msiof1_ss1_g_pins[] = {
2772
2773 RCAR_GP_PIN(3, 10),
2774};
2775static const unsigned int msiof1_ss1_g_mux[] = {
2776 MSIOF1_SS1_G_MARK,
2777};
2778static const unsigned int msiof1_ss2_g_pins[] = {
2779
2780 RCAR_GP_PIN(3, 11),
2781};
2782static const unsigned int msiof1_ss2_g_mux[] = {
2783 MSIOF1_SS2_G_MARK,
2784};
2785static const unsigned int msiof1_txd_g_pins[] = {
2786
2787 RCAR_GP_PIN(3, 9),
2788};
2789static const unsigned int msiof1_txd_g_mux[] = {
2790 MSIOF1_TXD_G_MARK,
2791};
2792static const unsigned int msiof1_rxd_g_pins[] = {
2793
2794 RCAR_GP_PIN(3, 8),
2795};
2796static const unsigned int msiof1_rxd_g_mux[] = {
2797 MSIOF1_RXD_G_MARK,
2798};
2799
2800static const unsigned int msiof2_clk_a_pins[] = {
2801
2802 RCAR_GP_PIN(1, 9),
2803};
2804static const unsigned int msiof2_clk_a_mux[] = {
2805 MSIOF2_SCK_A_MARK,
2806};
2807static const unsigned int msiof2_sync_a_pins[] = {
2808
2809 RCAR_GP_PIN(1, 8),
2810};
2811static const unsigned int msiof2_sync_a_mux[] = {
2812 MSIOF2_SYNC_A_MARK,
2813};
2814static const unsigned int msiof2_ss1_a_pins[] = {
2815
2816 RCAR_GP_PIN(1, 6),
2817};
2818static const unsigned int msiof2_ss1_a_mux[] = {
2819 MSIOF2_SS1_A_MARK,
2820};
2821static const unsigned int msiof2_ss2_a_pins[] = {
2822
2823 RCAR_GP_PIN(1, 7),
2824};
2825static const unsigned int msiof2_ss2_a_mux[] = {
2826 MSIOF2_SS2_A_MARK,
2827};
2828static const unsigned int msiof2_txd_a_pins[] = {
2829
2830 RCAR_GP_PIN(1, 11),
2831};
2832static const unsigned int msiof2_txd_a_mux[] = {
2833 MSIOF2_TXD_A_MARK,
2834};
2835static const unsigned int msiof2_rxd_a_pins[] = {
2836
2837 RCAR_GP_PIN(1, 10),
2838};
2839static const unsigned int msiof2_rxd_a_mux[] = {
2840 MSIOF2_RXD_A_MARK,
2841};
2842static const unsigned int msiof2_clk_b_pins[] = {
2843
2844 RCAR_GP_PIN(0, 4),
2845};
2846static const unsigned int msiof2_clk_b_mux[] = {
2847 MSIOF2_SCK_B_MARK,
2848};
2849static const unsigned int msiof2_sync_b_pins[] = {
2850
2851 RCAR_GP_PIN(0, 5),
2852};
2853static const unsigned int msiof2_sync_b_mux[] = {
2854 MSIOF2_SYNC_B_MARK,
2855};
2856static const unsigned int msiof2_ss1_b_pins[] = {
2857
2858 RCAR_GP_PIN(0, 0),
2859};
2860static const unsigned int msiof2_ss1_b_mux[] = {
2861 MSIOF2_SS1_B_MARK,
2862};
2863static const unsigned int msiof2_ss2_b_pins[] = {
2864
2865 RCAR_GP_PIN(0, 1),
2866};
2867static const unsigned int msiof2_ss2_b_mux[] = {
2868 MSIOF2_SS2_B_MARK,
2869};
2870static const unsigned int msiof2_txd_b_pins[] = {
2871
2872 RCAR_GP_PIN(0, 7),
2873};
2874static const unsigned int msiof2_txd_b_mux[] = {
2875 MSIOF2_TXD_B_MARK,
2876};
2877static const unsigned int msiof2_rxd_b_pins[] = {
2878
2879 RCAR_GP_PIN(0, 6),
2880};
2881static const unsigned int msiof2_rxd_b_mux[] = {
2882 MSIOF2_RXD_B_MARK,
2883};
2884static const unsigned int msiof2_clk_c_pins[] = {
2885
2886 RCAR_GP_PIN(2, 12),
2887};
2888static const unsigned int msiof2_clk_c_mux[] = {
2889 MSIOF2_SCK_C_MARK,
2890};
2891static const unsigned int msiof2_sync_c_pins[] = {
2892
2893 RCAR_GP_PIN(2, 11),
2894};
2895static const unsigned int msiof2_sync_c_mux[] = {
2896 MSIOF2_SYNC_C_MARK,
2897};
2898static const unsigned int msiof2_ss1_c_pins[] = {
2899
2900 RCAR_GP_PIN(2, 10),
2901};
2902static const unsigned int msiof2_ss1_c_mux[] = {
2903 MSIOF2_SS1_C_MARK,
2904};
2905static const unsigned int msiof2_ss2_c_pins[] = {
2906
2907 RCAR_GP_PIN(2, 9),
2908};
2909static const unsigned int msiof2_ss2_c_mux[] = {
2910 MSIOF2_SS2_C_MARK,
2911};
2912static const unsigned int msiof2_txd_c_pins[] = {
2913
2914 RCAR_GP_PIN(2, 14),
2915};
2916static const unsigned int msiof2_txd_c_mux[] = {
2917 MSIOF2_TXD_C_MARK,
2918};
2919static const unsigned int msiof2_rxd_c_pins[] = {
2920
2921 RCAR_GP_PIN(2, 13),
2922};
2923static const unsigned int msiof2_rxd_c_mux[] = {
2924 MSIOF2_RXD_C_MARK,
2925};
2926static const unsigned int msiof2_clk_d_pins[] = {
2927
2928 RCAR_GP_PIN(0, 8),
2929};
2930static const unsigned int msiof2_clk_d_mux[] = {
2931 MSIOF2_SCK_D_MARK,
2932};
2933static const unsigned int msiof2_sync_d_pins[] = {
2934
2935 RCAR_GP_PIN(0, 9),
2936};
2937static const unsigned int msiof2_sync_d_mux[] = {
2938 MSIOF2_SYNC_D_MARK,
2939};
2940static const unsigned int msiof2_ss1_d_pins[] = {
2941
2942 RCAR_GP_PIN(0, 12),
2943};
2944static const unsigned int msiof2_ss1_d_mux[] = {
2945 MSIOF2_SS1_D_MARK,
2946};
2947static const unsigned int msiof2_ss2_d_pins[] = {
2948
2949 RCAR_GP_PIN(0, 13),
2950};
2951static const unsigned int msiof2_ss2_d_mux[] = {
2952 MSIOF2_SS2_D_MARK,
2953};
2954static const unsigned int msiof2_txd_d_pins[] = {
2955
2956 RCAR_GP_PIN(0, 11),
2957};
2958static const unsigned int msiof2_txd_d_mux[] = {
2959 MSIOF2_TXD_D_MARK,
2960};
2961static const unsigned int msiof2_rxd_d_pins[] = {
2962
2963 RCAR_GP_PIN(0, 10),
2964};
2965static const unsigned int msiof2_rxd_d_mux[] = {
2966 MSIOF2_RXD_D_MARK,
2967};
2968
2969static const unsigned int msiof3_clk_a_pins[] = {
2970
2971 RCAR_GP_PIN(0, 0),
2972};
2973static const unsigned int msiof3_clk_a_mux[] = {
2974 MSIOF3_SCK_A_MARK,
2975};
2976static const unsigned int msiof3_sync_a_pins[] = {
2977
2978 RCAR_GP_PIN(0, 1),
2979};
2980static const unsigned int msiof3_sync_a_mux[] = {
2981 MSIOF3_SYNC_A_MARK,
2982};
2983static const unsigned int msiof3_ss1_a_pins[] = {
2984
2985 RCAR_GP_PIN(0, 14),
2986};
2987static const unsigned int msiof3_ss1_a_mux[] = {
2988 MSIOF3_SS1_A_MARK,
2989};
2990static const unsigned int msiof3_ss2_a_pins[] = {
2991
2992 RCAR_GP_PIN(0, 15),
2993};
2994static const unsigned int msiof3_ss2_a_mux[] = {
2995 MSIOF3_SS2_A_MARK,
2996};
2997static const unsigned int msiof3_txd_a_pins[] = {
2998
2999 RCAR_GP_PIN(0, 3),
3000};
3001static const unsigned int msiof3_txd_a_mux[] = {
3002 MSIOF3_TXD_A_MARK,
3003};
3004static const unsigned int msiof3_rxd_a_pins[] = {
3005
3006 RCAR_GP_PIN(0, 2),
3007};
3008static const unsigned int msiof3_rxd_a_mux[] = {
3009 MSIOF3_RXD_A_MARK,
3010};
3011static const unsigned int msiof3_clk_b_pins[] = {
3012
3013 RCAR_GP_PIN(1, 2),
3014};
3015static const unsigned int msiof3_clk_b_mux[] = {
3016 MSIOF3_SCK_B_MARK,
3017};
3018static const unsigned int msiof3_sync_b_pins[] = {
3019
3020 RCAR_GP_PIN(1, 0),
3021};
3022static const unsigned int msiof3_sync_b_mux[] = {
3023 MSIOF3_SYNC_B_MARK,
3024};
3025static const unsigned int msiof3_ss1_b_pins[] = {
3026
3027 RCAR_GP_PIN(1, 4),
3028};
3029static const unsigned int msiof3_ss1_b_mux[] = {
3030 MSIOF3_SS1_B_MARK,
3031};
3032static const unsigned int msiof3_ss2_b_pins[] = {
3033
3034 RCAR_GP_PIN(1, 5),
3035};
3036static const unsigned int msiof3_ss2_b_mux[] = {
3037 MSIOF3_SS2_B_MARK,
3038};
3039static const unsigned int msiof3_txd_b_pins[] = {
3040
3041 RCAR_GP_PIN(1, 1),
3042};
3043static const unsigned int msiof3_txd_b_mux[] = {
3044 MSIOF3_TXD_B_MARK,
3045};
3046static const unsigned int msiof3_rxd_b_pins[] = {
3047
3048 RCAR_GP_PIN(1, 3),
3049};
3050static const unsigned int msiof3_rxd_b_mux[] = {
3051 MSIOF3_RXD_B_MARK,
3052};
3053static const unsigned int msiof3_clk_c_pins[] = {
3054
3055 RCAR_GP_PIN(1, 12),
3056};
3057static const unsigned int msiof3_clk_c_mux[] = {
3058 MSIOF3_SCK_C_MARK,
3059};
3060static const unsigned int msiof3_sync_c_pins[] = {
3061
3062 RCAR_GP_PIN(1, 13),
3063};
3064static const unsigned int msiof3_sync_c_mux[] = {
3065 MSIOF3_SYNC_C_MARK,
3066};
3067static const unsigned int msiof3_txd_c_pins[] = {
3068
3069 RCAR_GP_PIN(1, 15),
3070};
3071static const unsigned int msiof3_txd_c_mux[] = {
3072 MSIOF3_TXD_C_MARK,
3073};
3074static const unsigned int msiof3_rxd_c_pins[] = {
3075
3076 RCAR_GP_PIN(1, 14),
3077};
3078static const unsigned int msiof3_rxd_c_mux[] = {
3079 MSIOF3_RXD_C_MARK,
3080};
3081static const unsigned int msiof3_clk_d_pins[] = {
3082
3083 RCAR_GP_PIN(1, 22),
3084};
3085static const unsigned int msiof3_clk_d_mux[] = {
3086 MSIOF3_SCK_D_MARK,
3087};
3088static const unsigned int msiof3_sync_d_pins[] = {
3089
3090 RCAR_GP_PIN(1, 23),
3091};
3092static const unsigned int msiof3_sync_d_mux[] = {
3093 MSIOF3_SYNC_D_MARK,
3094};
3095static const unsigned int msiof3_ss1_d_pins[] = {
3096
3097 RCAR_GP_PIN(1, 26),
3098};
3099static const unsigned int msiof3_ss1_d_mux[] = {
3100 MSIOF3_SS1_D_MARK,
3101};
3102static const unsigned int msiof3_txd_d_pins[] = {
3103
3104 RCAR_GP_PIN(1, 25),
3105};
3106static const unsigned int msiof3_txd_d_mux[] = {
3107 MSIOF3_TXD_D_MARK,
3108};
3109static const unsigned int msiof3_rxd_d_pins[] = {
3110
3111 RCAR_GP_PIN(1, 24),
3112};
3113static const unsigned int msiof3_rxd_d_mux[] = {
3114 MSIOF3_RXD_D_MARK,
3115};
3116
3117static const unsigned int msiof3_clk_e_pins[] = {
3118
3119 RCAR_GP_PIN(2, 3),
3120};
3121static const unsigned int msiof3_clk_e_mux[] = {
3122 MSIOF3_SCK_E_MARK,
3123};
3124static const unsigned int msiof3_sync_e_pins[] = {
3125
3126 RCAR_GP_PIN(2, 2),
3127};
3128static const unsigned int msiof3_sync_e_mux[] = {
3129 MSIOF3_SYNC_E_MARK,
3130};
3131static const unsigned int msiof3_ss1_e_pins[] = {
3132
3133 RCAR_GP_PIN(2, 1),
3134};
3135static const unsigned int msiof3_ss1_e_mux[] = {
3136 MSIOF3_SS1_E_MARK,
3137};
3138static const unsigned int msiof3_ss2_e_pins[] = {
3139
3140 RCAR_GP_PIN(2, 0),
3141};
3142static const unsigned int msiof3_ss2_e_mux[] = {
3143 MSIOF3_SS2_E_MARK,
3144};
3145static const unsigned int msiof3_txd_e_pins[] = {
3146
3147 RCAR_GP_PIN(2, 5),
3148};
3149static const unsigned int msiof3_txd_e_mux[] = {
3150 MSIOF3_TXD_E_MARK,
3151};
3152static const unsigned int msiof3_rxd_e_pins[] = {
3153
3154 RCAR_GP_PIN(2, 4),
3155};
3156static const unsigned int msiof3_rxd_e_mux[] = {
3157 MSIOF3_RXD_E_MARK,
3158};
3159
3160
3161static const unsigned int pwm0_pins[] = {
3162
3163 RCAR_GP_PIN(2, 6),
3164};
3165static const unsigned int pwm0_mux[] = {
3166 PWM0_MARK,
3167};
3168
3169static const unsigned int pwm1_a_pins[] = {
3170
3171 RCAR_GP_PIN(2, 7),
3172};
3173static const unsigned int pwm1_a_mux[] = {
3174 PWM1_A_MARK,
3175};
3176static const unsigned int pwm1_b_pins[] = {
3177
3178 RCAR_GP_PIN(1, 8),
3179};
3180static const unsigned int pwm1_b_mux[] = {
3181 PWM1_B_MARK,
3182};
3183
3184static const unsigned int pwm2_a_pins[] = {
3185
3186 RCAR_GP_PIN(2, 8),
3187};
3188static const unsigned int pwm2_a_mux[] = {
3189 PWM2_A_MARK,
3190};
3191static const unsigned int pwm2_b_pins[] = {
3192
3193 RCAR_GP_PIN(1, 11),
3194};
3195static const unsigned int pwm2_b_mux[] = {
3196 PWM2_B_MARK,
3197};
3198
3199static const unsigned int pwm3_a_pins[] = {
3200
3201 RCAR_GP_PIN(1, 0),
3202};
3203static const unsigned int pwm3_a_mux[] = {
3204 PWM3_A_MARK,
3205};
3206static const unsigned int pwm3_b_pins[] = {
3207
3208 RCAR_GP_PIN(2, 2),
3209};
3210static const unsigned int pwm3_b_mux[] = {
3211 PWM3_B_MARK,
3212};
3213
3214static const unsigned int pwm4_a_pins[] = {
3215
3216 RCAR_GP_PIN(1, 1),
3217};
3218static const unsigned int pwm4_a_mux[] = {
3219 PWM4_A_MARK,
3220};
3221static const unsigned int pwm4_b_pins[] = {
3222
3223 RCAR_GP_PIN(2, 3),
3224};
3225static const unsigned int pwm4_b_mux[] = {
3226 PWM4_B_MARK,
3227};
3228
3229static const unsigned int pwm5_a_pins[] = {
3230
3231 RCAR_GP_PIN(1, 2),
3232};
3233static const unsigned int pwm5_a_mux[] = {
3234 PWM5_A_MARK,
3235};
3236static const unsigned int pwm5_b_pins[] = {
3237
3238 RCAR_GP_PIN(2, 4),
3239};
3240static const unsigned int pwm5_b_mux[] = {
3241 PWM5_B_MARK,
3242};
3243
3244static const unsigned int pwm6_a_pins[] = {
3245
3246 RCAR_GP_PIN(1, 3),
3247};
3248static const unsigned int pwm6_a_mux[] = {
3249 PWM6_A_MARK,
3250};
3251static const unsigned int pwm6_b_pins[] = {
3252
3253 RCAR_GP_PIN(2, 5),
3254};
3255static const unsigned int pwm6_b_mux[] = {
3256 PWM6_B_MARK,
3257};
3258
3259
3260static const unsigned int qspi0_ctrl_pins[] = {
3261
3262 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3263};
3264static const unsigned int qspi0_ctrl_mux[] = {
3265 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3266};
3267static const unsigned int qspi0_data2_pins[] = {
3268
3269 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3270};
3271static const unsigned int qspi0_data2_mux[] = {
3272 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3273};
3274static const unsigned int qspi0_data4_pins[] = {
3275
3276 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3277
3278 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3279};
3280static const unsigned int qspi0_data4_mux[] = {
3281 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3282 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3283};
3284
3285static const unsigned int qspi1_ctrl_pins[] = {
3286
3287 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3288};
3289static const unsigned int qspi1_ctrl_mux[] = {
3290 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3291};
3292static const unsigned int qspi1_data2_pins[] = {
3293
3294 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3295};
3296static const unsigned int qspi1_data2_mux[] = {
3297 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3298};
3299static const unsigned int qspi1_data4_pins[] = {
3300
3301 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3302
3303 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3304};
3305static const unsigned int qspi1_data4_mux[] = {
3306 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3307 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3308};
3309
3310
3311static const unsigned int scif0_data_pins[] = {
3312
3313 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3314};
3315static const unsigned int scif0_data_mux[] = {
3316 RX0_MARK, TX0_MARK,
3317};
3318static const unsigned int scif0_clk_pins[] = {
3319
3320 RCAR_GP_PIN(5, 0),
3321};
3322static const unsigned int scif0_clk_mux[] = {
3323 SCK0_MARK,
3324};
3325static const unsigned int scif0_ctrl_pins[] = {
3326
3327 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3328};
3329static const unsigned int scif0_ctrl_mux[] = {
3330 RTS0_N_MARK, CTS0_N_MARK,
3331};
3332
3333static const unsigned int scif1_data_a_pins[] = {
3334
3335 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3336};
3337static const unsigned int scif1_data_a_mux[] = {
3338 RX1_A_MARK, TX1_A_MARK,
3339};
3340static const unsigned int scif1_clk_pins[] = {
3341
3342 RCAR_GP_PIN(6, 21),
3343};
3344static const unsigned int scif1_clk_mux[] = {
3345 SCK1_MARK,
3346};
3347static const unsigned int scif1_ctrl_pins[] = {
3348
3349 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3350};
3351static const unsigned int scif1_ctrl_mux[] = {
3352 RTS1_N_MARK, CTS1_N_MARK,
3353};
3354
3355static const unsigned int scif1_data_b_pins[] = {
3356
3357 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3358};
3359static const unsigned int scif1_data_b_mux[] = {
3360 RX1_B_MARK, TX1_B_MARK,
3361};
3362
3363static const unsigned int scif2_data_a_pins[] = {
3364
3365 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3366};
3367static const unsigned int scif2_data_a_mux[] = {
3368 RX2_A_MARK, TX2_A_MARK,
3369};
3370static const unsigned int scif2_clk_pins[] = {
3371
3372 RCAR_GP_PIN(5, 9),
3373};
3374static const unsigned int scif2_clk_mux[] = {
3375 SCK2_MARK,
3376};
3377static const unsigned int scif2_data_b_pins[] = {
3378
3379 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3380};
3381static const unsigned int scif2_data_b_mux[] = {
3382 RX2_B_MARK, TX2_B_MARK,
3383};
3384
3385static const unsigned int scif3_data_a_pins[] = {
3386
3387 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3388};
3389static const unsigned int scif3_data_a_mux[] = {
3390 RX3_A_MARK, TX3_A_MARK,
3391};
3392static const unsigned int scif3_clk_pins[] = {
3393
3394 RCAR_GP_PIN(1, 22),
3395};
3396static const unsigned int scif3_clk_mux[] = {
3397 SCK3_MARK,
3398};
3399static const unsigned int scif3_ctrl_pins[] = {
3400
3401 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3402};
3403static const unsigned int scif3_ctrl_mux[] = {
3404 RTS3_N_MARK, CTS3_N_MARK,
3405};
3406static const unsigned int scif3_data_b_pins[] = {
3407
3408 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3409};
3410static const unsigned int scif3_data_b_mux[] = {
3411 RX3_B_MARK, TX3_B_MARK,
3412};
3413
3414static const unsigned int scif4_data_a_pins[] = {
3415
3416 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3417};
3418static const unsigned int scif4_data_a_mux[] = {
3419 RX4_A_MARK, TX4_A_MARK,
3420};
3421static const unsigned int scif4_clk_a_pins[] = {
3422
3423 RCAR_GP_PIN(2, 10),
3424};
3425static const unsigned int scif4_clk_a_mux[] = {
3426 SCK4_A_MARK,
3427};
3428static const unsigned int scif4_ctrl_a_pins[] = {
3429
3430 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3431};
3432static const unsigned int scif4_ctrl_a_mux[] = {
3433 RTS4_N_A_MARK, CTS4_N_A_MARK,
3434};
3435static const unsigned int scif4_data_b_pins[] = {
3436
3437 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3438};
3439static const unsigned int scif4_data_b_mux[] = {
3440 RX4_B_MARK, TX4_B_MARK,
3441};
3442static const unsigned int scif4_clk_b_pins[] = {
3443
3444 RCAR_GP_PIN(1, 5),
3445};
3446static const unsigned int scif4_clk_b_mux[] = {
3447 SCK4_B_MARK,
3448};
3449static const unsigned int scif4_ctrl_b_pins[] = {
3450
3451 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3452};
3453static const unsigned int scif4_ctrl_b_mux[] = {
3454 RTS4_N_B_MARK, CTS4_N_B_MARK,
3455};
3456static const unsigned int scif4_data_c_pins[] = {
3457
3458 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3459};
3460static const unsigned int scif4_data_c_mux[] = {
3461 RX4_C_MARK, TX4_C_MARK,
3462};
3463static const unsigned int scif4_clk_c_pins[] = {
3464
3465 RCAR_GP_PIN(0, 8),
3466};
3467static const unsigned int scif4_clk_c_mux[] = {
3468 SCK4_C_MARK,
3469};
3470static const unsigned int scif4_ctrl_c_pins[] = {
3471
3472 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3473};
3474static const unsigned int scif4_ctrl_c_mux[] = {
3475 RTS4_N_C_MARK, CTS4_N_C_MARK,
3476};
3477
3478static const unsigned int scif5_data_a_pins[] = {
3479
3480 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3481};
3482static const unsigned int scif5_data_a_mux[] = {
3483 RX5_A_MARK, TX5_A_MARK,
3484};
3485static const unsigned int scif5_clk_a_pins[] = {
3486
3487 RCAR_GP_PIN(6, 21),
3488};
3489static const unsigned int scif5_clk_a_mux[] = {
3490 SCK5_A_MARK,
3491};
3492
3493static const unsigned int scif5_data_b_pins[] = {
3494
3495 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3496};
3497static const unsigned int scif5_data_b_mux[] = {
3498 RX5_B_MARK, TX5_B_MARK,
3499};
3500static const unsigned int scif5_clk_b_pins[] = {
3501
3502 RCAR_GP_PIN(5, 0),
3503};
3504static const unsigned int scif5_clk_b_mux[] = {
3505 SCK5_B_MARK,
3506};
3507
3508
3509static const unsigned int scif_clk_a_pins[] = {
3510
3511 RCAR_GP_PIN(6, 23),
3512};
3513static const unsigned int scif_clk_a_mux[] = {
3514 SCIF_CLK_A_MARK,
3515};
3516static const unsigned int scif_clk_b_pins[] = {
3517
3518 RCAR_GP_PIN(5, 9),
3519};
3520static const unsigned int scif_clk_b_mux[] = {
3521 SCIF_CLK_B_MARK,
3522};
3523
3524
3525static const unsigned int sdhi0_data1_pins[] = {
3526
3527 RCAR_GP_PIN(3, 2),
3528};
3529static const unsigned int sdhi0_data1_mux[] = {
3530 SD0_DAT0_MARK,
3531};
3532static const unsigned int sdhi0_data4_pins[] = {
3533
3534 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3535 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3536};
3537static const unsigned int sdhi0_data4_mux[] = {
3538 SD0_DAT0_MARK, SD0_DAT1_MARK,
3539 SD0_DAT2_MARK, SD0_DAT3_MARK,
3540};
3541static const unsigned int sdhi0_ctrl_pins[] = {
3542
3543 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3544};
3545static const unsigned int sdhi0_ctrl_mux[] = {
3546 SD0_CLK_MARK, SD0_CMD_MARK,
3547};
3548static const unsigned int sdhi0_cd_pins[] = {
3549
3550 RCAR_GP_PIN(3, 12),
3551};
3552static const unsigned int sdhi0_cd_mux[] = {
3553 SD0_CD_MARK,
3554};
3555static const unsigned int sdhi0_wp_pins[] = {
3556
3557 RCAR_GP_PIN(3, 13),
3558};
3559static const unsigned int sdhi0_wp_mux[] = {
3560 SD0_WP_MARK,
3561};
3562
3563static const unsigned int sdhi1_data1_pins[] = {
3564
3565 RCAR_GP_PIN(3, 8),
3566};
3567static const unsigned int sdhi1_data1_mux[] = {
3568 SD1_DAT0_MARK,
3569};
3570static const unsigned int sdhi1_data4_pins[] = {
3571
3572 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3573 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3574};
3575static const unsigned int sdhi1_data4_mux[] = {
3576 SD1_DAT0_MARK, SD1_DAT1_MARK,
3577 SD1_DAT2_MARK, SD1_DAT3_MARK,
3578};
3579static const unsigned int sdhi1_ctrl_pins[] = {
3580
3581 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3582};
3583static const unsigned int sdhi1_ctrl_mux[] = {
3584 SD1_CLK_MARK, SD1_CMD_MARK,
3585};
3586static const unsigned int sdhi1_cd_pins[] = {
3587
3588 RCAR_GP_PIN(3, 14),
3589};
3590static const unsigned int sdhi1_cd_mux[] = {
3591 SD1_CD_MARK,
3592};
3593static const unsigned int sdhi1_wp_pins[] = {
3594
3595 RCAR_GP_PIN(3, 15),
3596};
3597static const unsigned int sdhi1_wp_mux[] = {
3598 SD1_WP_MARK,
3599};
3600
3601static const unsigned int sdhi2_data1_pins[] = {
3602
3603 RCAR_GP_PIN(4, 2),
3604};
3605static const unsigned int sdhi2_data1_mux[] = {
3606 SD2_DAT0_MARK,
3607};
3608static const unsigned int sdhi2_data4_pins[] = {
3609
3610 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3611 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3612};
3613static const unsigned int sdhi2_data4_mux[] = {
3614 SD2_DAT0_MARK, SD2_DAT1_MARK,
3615 SD2_DAT2_MARK, SD2_DAT3_MARK,
3616};
3617static const unsigned int sdhi2_data8_pins[] = {
3618
3619 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3620 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3621 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3622 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3623};
3624static const unsigned int sdhi2_data8_mux[] = {
3625 SD2_DAT0_MARK, SD2_DAT1_MARK,
3626 SD2_DAT2_MARK, SD2_DAT3_MARK,
3627 SD2_DAT4_MARK, SD2_DAT5_MARK,
3628 SD2_DAT6_MARK, SD2_DAT7_MARK,
3629};
3630static const unsigned int sdhi2_ctrl_pins[] = {
3631
3632 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3633};
3634static const unsigned int sdhi2_ctrl_mux[] = {
3635 SD2_CLK_MARK, SD2_CMD_MARK,
3636};
3637static const unsigned int sdhi2_cd_a_pins[] = {
3638
3639 RCAR_GP_PIN(4, 13),
3640};
3641static const unsigned int sdhi2_cd_a_mux[] = {
3642 SD2_CD_A_MARK,
3643};
3644static const unsigned int sdhi2_cd_b_pins[] = {
3645
3646 RCAR_GP_PIN(5, 10),
3647};
3648static const unsigned int sdhi2_cd_b_mux[] = {
3649 SD2_CD_B_MARK,
3650};
3651static const unsigned int sdhi2_wp_a_pins[] = {
3652
3653 RCAR_GP_PIN(4, 14),
3654};
3655static const unsigned int sdhi2_wp_a_mux[] = {
3656 SD2_WP_A_MARK,
3657};
3658static const unsigned int sdhi2_wp_b_pins[] = {
3659
3660 RCAR_GP_PIN(5, 11),
3661};
3662static const unsigned int sdhi2_wp_b_mux[] = {
3663 SD2_WP_B_MARK,
3664};
3665static const unsigned int sdhi2_ds_pins[] = {
3666
3667 RCAR_GP_PIN(4, 6),
3668};
3669static const unsigned int sdhi2_ds_mux[] = {
3670 SD2_DS_MARK,
3671};
3672
3673static const unsigned int sdhi3_data1_pins[] = {
3674
3675 RCAR_GP_PIN(4, 9),
3676};
3677static const unsigned int sdhi3_data1_mux[] = {
3678 SD3_DAT0_MARK,
3679};
3680static const unsigned int sdhi3_data4_pins[] = {
3681
3682 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3683 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3684};
3685static const unsigned int sdhi3_data4_mux[] = {
3686 SD3_DAT0_MARK, SD3_DAT1_MARK,
3687 SD3_DAT2_MARK, SD3_DAT3_MARK,
3688};
3689static const unsigned int sdhi3_data8_pins[] = {
3690
3691 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3692 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3693 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3694 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3695};
3696static const unsigned int sdhi3_data8_mux[] = {
3697 SD3_DAT0_MARK, SD3_DAT1_MARK,
3698 SD3_DAT2_MARK, SD3_DAT3_MARK,
3699 SD3_DAT4_MARK, SD3_DAT5_MARK,
3700 SD3_DAT6_MARK, SD3_DAT7_MARK,
3701};
3702static const unsigned int sdhi3_ctrl_pins[] = {
3703
3704 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3705};
3706static const unsigned int sdhi3_ctrl_mux[] = {
3707 SD3_CLK_MARK, SD3_CMD_MARK,
3708};
3709static const unsigned int sdhi3_cd_pins[] = {
3710
3711 RCAR_GP_PIN(4, 15),
3712};
3713static const unsigned int sdhi3_cd_mux[] = {
3714 SD3_CD_MARK,
3715};
3716static const unsigned int sdhi3_wp_pins[] = {
3717
3718 RCAR_GP_PIN(4, 16),
3719};
3720static const unsigned int sdhi3_wp_mux[] = {
3721 SD3_WP_MARK,
3722};
3723static const unsigned int sdhi3_ds_pins[] = {
3724
3725 RCAR_GP_PIN(4, 17),
3726};
3727static const unsigned int sdhi3_ds_mux[] = {
3728 SD3_DS_MARK,
3729};
3730
3731
3732static const unsigned int ssi0_data_pins[] = {
3733
3734 RCAR_GP_PIN(6, 2),
3735};
3736static const unsigned int ssi0_data_mux[] = {
3737 SSI_SDATA0_MARK,
3738};
3739static const unsigned int ssi01239_ctrl_pins[] = {
3740
3741 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3742};
3743static const unsigned int ssi01239_ctrl_mux[] = {
3744 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3745};
3746static const unsigned int ssi1_data_a_pins[] = {
3747
3748 RCAR_GP_PIN(6, 3),
3749};
3750static const unsigned int ssi1_data_a_mux[] = {
3751 SSI_SDATA1_A_MARK,
3752};
3753static const unsigned int ssi1_data_b_pins[] = {
3754
3755 RCAR_GP_PIN(5, 12),
3756};
3757static const unsigned int ssi1_data_b_mux[] = {
3758 SSI_SDATA1_B_MARK,
3759};
3760static const unsigned int ssi1_ctrl_a_pins[] = {
3761
3762 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3763};
3764static const unsigned int ssi1_ctrl_a_mux[] = {
3765 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3766};
3767static const unsigned int ssi1_ctrl_b_pins[] = {
3768
3769 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3770};
3771static const unsigned int ssi1_ctrl_b_mux[] = {
3772 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3773};
3774static const unsigned int ssi2_data_a_pins[] = {
3775
3776 RCAR_GP_PIN(6, 4),
3777};
3778static const unsigned int ssi2_data_a_mux[] = {
3779 SSI_SDATA2_A_MARK,
3780};
3781static const unsigned int ssi2_data_b_pins[] = {
3782
3783 RCAR_GP_PIN(5, 13),
3784};
3785static const unsigned int ssi2_data_b_mux[] = {
3786 SSI_SDATA2_B_MARK,
3787};
3788static const unsigned int ssi2_ctrl_a_pins[] = {
3789
3790 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3791};
3792static const unsigned int ssi2_ctrl_a_mux[] = {
3793 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3794};
3795static const unsigned int ssi2_ctrl_b_pins[] = {
3796
3797 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3798};
3799static const unsigned int ssi2_ctrl_b_mux[] = {
3800 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3801};
3802static const unsigned int ssi3_data_pins[] = {
3803
3804 RCAR_GP_PIN(6, 7),
3805};
3806static const unsigned int ssi3_data_mux[] = {
3807 SSI_SDATA3_MARK,
3808};
3809static const unsigned int ssi349_ctrl_pins[] = {
3810
3811 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3812};
3813static const unsigned int ssi349_ctrl_mux[] = {
3814 SSI_SCK349_MARK, SSI_WS349_MARK,
3815};
3816static const unsigned int ssi4_data_pins[] = {
3817
3818 RCAR_GP_PIN(6, 10),
3819};
3820static const unsigned int ssi4_data_mux[] = {
3821 SSI_SDATA4_MARK,
3822};
3823static const unsigned int ssi4_ctrl_pins[] = {
3824
3825 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3826};
3827static const unsigned int ssi4_ctrl_mux[] = {
3828 SSI_SCK4_MARK, SSI_WS4_MARK,
3829};
3830static const unsigned int ssi5_data_pins[] = {
3831
3832 RCAR_GP_PIN(6, 13),
3833};
3834static const unsigned int ssi5_data_mux[] = {
3835 SSI_SDATA5_MARK,
3836};
3837static const unsigned int ssi5_ctrl_pins[] = {
3838
3839 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3840};
3841static const unsigned int ssi5_ctrl_mux[] = {
3842 SSI_SCK5_MARK, SSI_WS5_MARK,
3843};
3844static const unsigned int ssi6_data_pins[] = {
3845
3846 RCAR_GP_PIN(6, 16),
3847};
3848static const unsigned int ssi6_data_mux[] = {
3849 SSI_SDATA6_MARK,
3850};
3851static const unsigned int ssi6_ctrl_pins[] = {
3852
3853 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3854};
3855static const unsigned int ssi6_ctrl_mux[] = {
3856 SSI_SCK6_MARK, SSI_WS6_MARK,
3857};
3858static const unsigned int ssi7_data_pins[] = {
3859
3860 RCAR_GP_PIN(6, 19),
3861};
3862static const unsigned int ssi7_data_mux[] = {
3863 SSI_SDATA7_MARK,
3864};
3865static const unsigned int ssi78_ctrl_pins[] = {
3866
3867 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3868};
3869static const unsigned int ssi78_ctrl_mux[] = {
3870 SSI_SCK78_MARK, SSI_WS78_MARK,
3871};
3872static const unsigned int ssi8_data_pins[] = {
3873
3874 RCAR_GP_PIN(6, 20),
3875};
3876static const unsigned int ssi8_data_mux[] = {
3877 SSI_SDATA8_MARK,
3878};
3879static const unsigned int ssi9_data_a_pins[] = {
3880
3881 RCAR_GP_PIN(6, 21),
3882};
3883static const unsigned int ssi9_data_a_mux[] = {
3884 SSI_SDATA9_A_MARK,
3885};
3886static const unsigned int ssi9_data_b_pins[] = {
3887
3888 RCAR_GP_PIN(5, 14),
3889};
3890static const unsigned int ssi9_data_b_mux[] = {
3891 SSI_SDATA9_B_MARK,
3892};
3893static const unsigned int ssi9_ctrl_a_pins[] = {
3894
3895 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3896};
3897static const unsigned int ssi9_ctrl_a_mux[] = {
3898 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3899};
3900static const unsigned int ssi9_ctrl_b_pins[] = {
3901
3902 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3903};
3904static const unsigned int ssi9_ctrl_b_mux[] = {
3905 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3906};
3907
3908
3909static const unsigned int tmu_tclk1_a_pins[] = {
3910
3911 RCAR_GP_PIN(6, 23),
3912};
3913static const unsigned int tmu_tclk1_a_mux[] = {
3914 TCLK1_A_MARK,
3915};
3916static const unsigned int tmu_tclk1_b_pins[] = {
3917
3918 RCAR_GP_PIN(5, 19),
3919};
3920static const unsigned int tmu_tclk1_b_mux[] = {
3921 TCLK1_B_MARK,
3922};
3923static const unsigned int tmu_tclk2_a_pins[] = {
3924
3925 RCAR_GP_PIN(6, 19),
3926};
3927static const unsigned int tmu_tclk2_a_mux[] = {
3928 TCLK2_A_MARK,
3929};
3930static const unsigned int tmu_tclk2_b_pins[] = {
3931
3932 RCAR_GP_PIN(6, 28),
3933};
3934static const unsigned int tmu_tclk2_b_mux[] = {
3935 TCLK2_B_MARK,
3936};
3937
3938
3939static const unsigned int tpu_to0_pins[] = {
3940
3941 RCAR_GP_PIN(6, 28),
3942};
3943static const unsigned int tpu_to0_mux[] = {
3944 TPU0TO0_MARK,
3945};
3946static const unsigned int tpu_to1_pins[] = {
3947
3948 RCAR_GP_PIN(6, 29),
3949};
3950static const unsigned int tpu_to1_mux[] = {
3951 TPU0TO1_MARK,
3952};
3953static const unsigned int tpu_to2_pins[] = {
3954
3955 RCAR_GP_PIN(6, 30),
3956};
3957static const unsigned int tpu_to2_mux[] = {
3958 TPU0TO2_MARK,
3959};
3960static const unsigned int tpu_to3_pins[] = {
3961
3962 RCAR_GP_PIN(6, 31),
3963};
3964static const unsigned int tpu_to3_mux[] = {
3965 TPU0TO3_MARK,
3966};
3967
3968
3969static const unsigned int usb0_pins[] = {
3970
3971 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3972};
3973static const unsigned int usb0_mux[] = {
3974 USB0_PWEN_MARK, USB0_OVC_MARK,
3975};
3976
3977static const unsigned int usb1_pins[] = {
3978
3979 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3980};
3981static const unsigned int usb1_mux[] = {
3982 USB1_PWEN_MARK, USB1_OVC_MARK,
3983};
3984
3985
3986static const unsigned int usb30_pins[] = {
3987
3988 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3989};
3990static const unsigned int usb30_mux[] = {
3991 USB30_PWEN_MARK, USB30_OVC_MARK,
3992};
3993
3994
3995static const unsigned int vin4_data18_a_pins[] = {
3996 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3997 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3998 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3999 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4000 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4001 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4002 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4003 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4004 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4005};
4006static const unsigned int vin4_data18_a_mux[] = {
4007 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4008 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4009 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4010 VI4_DATA10_MARK, VI4_DATA11_MARK,
4011 VI4_DATA12_MARK, VI4_DATA13_MARK,
4012 VI4_DATA14_MARK, VI4_DATA15_MARK,
4013 VI4_DATA18_MARK, VI4_DATA19_MARK,
4014 VI4_DATA20_MARK, VI4_DATA21_MARK,
4015 VI4_DATA22_MARK, VI4_DATA23_MARK,
4016};
4017static const unsigned int vin4_data18_b_pins[] = {
4018 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4019 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4020 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4021 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4022 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4023 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4024 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4025 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4026 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4027};
4028static const unsigned int vin4_data18_b_mux[] = {
4029 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4030 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4031 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4032 VI4_DATA10_MARK, VI4_DATA11_MARK,
4033 VI4_DATA12_MARK, VI4_DATA13_MARK,
4034 VI4_DATA14_MARK, VI4_DATA15_MARK,
4035 VI4_DATA18_MARK, VI4_DATA19_MARK,
4036 VI4_DATA20_MARK, VI4_DATA21_MARK,
4037 VI4_DATA22_MARK, VI4_DATA23_MARK,
4038};
4039static const union vin_data vin4_data_a_pins = {
4040 .data24 = {
4041 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4042 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4043 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4044 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4045 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4046 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4047 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4048 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4049 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4050 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4051 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4052 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4053 },
4054};
4055static const union vin_data vin4_data_a_mux = {
4056 .data24 = {
4057 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4058 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4059 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4060 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4061 VI4_DATA8_MARK, VI4_DATA9_MARK,
4062 VI4_DATA10_MARK, VI4_DATA11_MARK,
4063 VI4_DATA12_MARK, VI4_DATA13_MARK,
4064 VI4_DATA14_MARK, VI4_DATA15_MARK,
4065 VI4_DATA16_MARK, VI4_DATA17_MARK,
4066 VI4_DATA18_MARK, VI4_DATA19_MARK,
4067 VI4_DATA20_MARK, VI4_DATA21_MARK,
4068 VI4_DATA22_MARK, VI4_DATA23_MARK,
4069 },
4070};
4071static const union vin_data vin4_data_b_pins = {
4072 .data24 = {
4073 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4074 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4075 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4076 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4077 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4078 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4079 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4080 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4081 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4082 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4083 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4084 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4085 },
4086};
4087static const union vin_data vin4_data_b_mux = {
4088 .data24 = {
4089 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4090 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4091 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4092 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4093 VI4_DATA8_MARK, VI4_DATA9_MARK,
4094 VI4_DATA10_MARK, VI4_DATA11_MARK,
4095 VI4_DATA12_MARK, VI4_DATA13_MARK,
4096 VI4_DATA14_MARK, VI4_DATA15_MARK,
4097 VI4_DATA16_MARK, VI4_DATA17_MARK,
4098 VI4_DATA18_MARK, VI4_DATA19_MARK,
4099 VI4_DATA20_MARK, VI4_DATA21_MARK,
4100 VI4_DATA22_MARK, VI4_DATA23_MARK,
4101 },
4102};
4103static const unsigned int vin4_g8_pins[] = {
4104 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4105 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4106 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4107 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4108};
4109static const unsigned int vin4_g8_mux[] = {
4110 VI4_DATA8_MARK, VI4_DATA9_MARK,
4111 VI4_DATA10_MARK, VI4_DATA11_MARK,
4112 VI4_DATA12_MARK, VI4_DATA13_MARK,
4113 VI4_DATA14_MARK, VI4_DATA15_MARK,
4114};
4115static const unsigned int vin4_sync_pins[] = {
4116
4117 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4118};
4119static const unsigned int vin4_sync_mux[] = {
4120 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4121};
4122static const unsigned int vin4_field_pins[] = {
4123
4124 RCAR_GP_PIN(1, 16),
4125};
4126static const unsigned int vin4_field_mux[] = {
4127 VI4_FIELD_MARK,
4128};
4129static const unsigned int vin4_clkenb_pins[] = {
4130
4131 RCAR_GP_PIN(1, 19),
4132};
4133static const unsigned int vin4_clkenb_mux[] = {
4134 VI4_CLKENB_MARK,
4135};
4136static const unsigned int vin4_clk_pins[] = {
4137
4138 RCAR_GP_PIN(1, 27),
4139};
4140static const unsigned int vin4_clk_mux[] = {
4141 VI4_CLK_MARK,
4142};
4143
4144
4145static const union vin_data16 vin5_data_pins = {
4146 .data16 = {
4147 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4148 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4149 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4150 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4151 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4152 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4153 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4154 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4155 },
4156};
4157static const union vin_data16 vin5_data_mux = {
4158 .data16 = {
4159 VI5_DATA0_MARK, VI5_DATA1_MARK,
4160 VI5_DATA2_MARK, VI5_DATA3_MARK,
4161 VI5_DATA4_MARK, VI5_DATA5_MARK,
4162 VI5_DATA6_MARK, VI5_DATA7_MARK,
4163 VI5_DATA8_MARK, VI5_DATA9_MARK,
4164 VI5_DATA10_MARK, VI5_DATA11_MARK,
4165 VI5_DATA12_MARK, VI5_DATA13_MARK,
4166 VI5_DATA14_MARK, VI5_DATA15_MARK,
4167 },
4168};
4169static const unsigned int vin5_high8_pins[] = {
4170 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4171 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4172 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4173 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4174};
4175static const unsigned int vin5_high8_mux[] = {
4176 VI5_DATA8_MARK, VI5_DATA9_MARK,
4177 VI5_DATA10_MARK, VI5_DATA11_MARK,
4178 VI5_DATA12_MARK, VI5_DATA13_MARK,
4179 VI5_DATA14_MARK, VI5_DATA15_MARK,
4180};
4181static const unsigned int vin5_sync_pins[] = {
4182
4183 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4184};
4185static const unsigned int vin5_sync_mux[] = {
4186 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4187};
4188static const unsigned int vin5_field_pins[] = {
4189 RCAR_GP_PIN(1, 11),
4190};
4191static const unsigned int vin5_field_mux[] = {
4192
4193 VI5_FIELD_MARK,
4194};
4195static const unsigned int vin5_clkenb_pins[] = {
4196 RCAR_GP_PIN(1, 20),
4197};
4198static const unsigned int vin5_clkenb_mux[] = {
4199
4200 VI5_CLKENB_MARK,
4201};
4202static const unsigned int vin5_clk_pins[] = {
4203 RCAR_GP_PIN(1, 21),
4204};
4205static const unsigned int vin5_clk_mux[] = {
4206
4207 VI5_CLK_MARK,
4208};
4209
4210static const struct {
4211 struct sh_pfc_pin_group common[324];
4212#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4213 struct sh_pfc_pin_group automotive[30];
4214#endif
4215} pinmux_groups = {
4216 .common = {
4217 SH_PFC_PIN_GROUP(audio_clk_a_a),
4218 SH_PFC_PIN_GROUP(audio_clk_a_b),
4219 SH_PFC_PIN_GROUP(audio_clk_a_c),
4220 SH_PFC_PIN_GROUP(audio_clk_b_a),
4221 SH_PFC_PIN_GROUP(audio_clk_b_b),
4222 SH_PFC_PIN_GROUP(audio_clk_c_a),
4223 SH_PFC_PIN_GROUP(audio_clk_c_b),
4224 SH_PFC_PIN_GROUP(audio_clkout_a),
4225 SH_PFC_PIN_GROUP(audio_clkout_b),
4226 SH_PFC_PIN_GROUP(audio_clkout_c),
4227 SH_PFC_PIN_GROUP(audio_clkout_d),
4228 SH_PFC_PIN_GROUP(audio_clkout1_a),
4229 SH_PFC_PIN_GROUP(audio_clkout1_b),
4230 SH_PFC_PIN_GROUP(audio_clkout2_a),
4231 SH_PFC_PIN_GROUP(audio_clkout2_b),
4232 SH_PFC_PIN_GROUP(audio_clkout3_a),
4233 SH_PFC_PIN_GROUP(audio_clkout3_b),
4234 SH_PFC_PIN_GROUP(avb_link),
4235 SH_PFC_PIN_GROUP(avb_magic),
4236 SH_PFC_PIN_GROUP(avb_phy_int),
4237 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),
4238 SH_PFC_PIN_GROUP(avb_mdio),
4239 SH_PFC_PIN_GROUP(avb_mii),
4240 SH_PFC_PIN_GROUP(avb_avtp_pps),
4241 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4242 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4243 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4244 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4245 SH_PFC_PIN_GROUP(can0_data_a),
4246 SH_PFC_PIN_GROUP(can0_data_b),
4247 SH_PFC_PIN_GROUP(can1_data),
4248 SH_PFC_PIN_GROUP(can_clk),
4249 SH_PFC_PIN_GROUP(canfd0_data_a),
4250 SH_PFC_PIN_GROUP(canfd0_data_b),
4251 SH_PFC_PIN_GROUP(canfd1_data),
4252 SH_PFC_PIN_GROUP(du_rgb666),
4253 SH_PFC_PIN_GROUP(du_rgb888),
4254 SH_PFC_PIN_GROUP(du_clk_out_0),
4255 SH_PFC_PIN_GROUP(du_clk_out_1),
4256 SH_PFC_PIN_GROUP(du_sync),
4257 SH_PFC_PIN_GROUP(du_oddf),
4258 SH_PFC_PIN_GROUP(du_cde),
4259 SH_PFC_PIN_GROUP(du_disp),
4260 SH_PFC_PIN_GROUP(hscif0_data),
4261 SH_PFC_PIN_GROUP(hscif0_clk),
4262 SH_PFC_PIN_GROUP(hscif0_ctrl),
4263 SH_PFC_PIN_GROUP(hscif1_data_a),
4264 SH_PFC_PIN_GROUP(hscif1_clk_a),
4265 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4266 SH_PFC_PIN_GROUP(hscif1_data_b),
4267 SH_PFC_PIN_GROUP(hscif1_clk_b),
4268 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4269 SH_PFC_PIN_GROUP(hscif2_data_a),
4270 SH_PFC_PIN_GROUP(hscif2_clk_a),
4271 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4272 SH_PFC_PIN_GROUP(hscif2_data_b),
4273 SH_PFC_PIN_GROUP(hscif2_clk_b),
4274 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4275 SH_PFC_PIN_GROUP(hscif2_data_c),
4276 SH_PFC_PIN_GROUP(hscif2_clk_c),
4277 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4278 SH_PFC_PIN_GROUP(hscif3_data_a),
4279 SH_PFC_PIN_GROUP(hscif3_clk),
4280 SH_PFC_PIN_GROUP(hscif3_ctrl),
4281 SH_PFC_PIN_GROUP(hscif3_data_b),
4282 SH_PFC_PIN_GROUP(hscif3_data_c),
4283 SH_PFC_PIN_GROUP(hscif3_data_d),
4284 SH_PFC_PIN_GROUP(hscif4_data_a),
4285 SH_PFC_PIN_GROUP(hscif4_clk),
4286 SH_PFC_PIN_GROUP(hscif4_ctrl),
4287 SH_PFC_PIN_GROUP(hscif4_data_b),
4288 SH_PFC_PIN_GROUP(i2c0),
4289 SH_PFC_PIN_GROUP(i2c1_a),
4290 SH_PFC_PIN_GROUP(i2c1_b),
4291 SH_PFC_PIN_GROUP(i2c2_a),
4292 SH_PFC_PIN_GROUP(i2c2_b),
4293 SH_PFC_PIN_GROUP(i2c3),
4294 SH_PFC_PIN_GROUP(i2c5),
4295 SH_PFC_PIN_GROUP(i2c6_a),
4296 SH_PFC_PIN_GROUP(i2c6_b),
4297 SH_PFC_PIN_GROUP(i2c6_c),
4298 SH_PFC_PIN_GROUP(intc_ex_irq0),
4299 SH_PFC_PIN_GROUP(intc_ex_irq1),
4300 SH_PFC_PIN_GROUP(intc_ex_irq2),
4301 SH_PFC_PIN_GROUP(intc_ex_irq3),
4302 SH_PFC_PIN_GROUP(intc_ex_irq4),
4303 SH_PFC_PIN_GROUP(intc_ex_irq5),
4304 SH_PFC_PIN_GROUP(msiof0_clk),
4305 SH_PFC_PIN_GROUP(msiof0_sync),
4306 SH_PFC_PIN_GROUP(msiof0_ss1),
4307 SH_PFC_PIN_GROUP(msiof0_ss2),
4308 SH_PFC_PIN_GROUP(msiof0_txd),
4309 SH_PFC_PIN_GROUP(msiof0_rxd),
4310 SH_PFC_PIN_GROUP(msiof1_clk_a),
4311 SH_PFC_PIN_GROUP(msiof1_sync_a),
4312 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4313 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4314 SH_PFC_PIN_GROUP(msiof1_txd_a),
4315 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4316 SH_PFC_PIN_GROUP(msiof1_clk_b),
4317 SH_PFC_PIN_GROUP(msiof1_sync_b),
4318 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4319 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4320 SH_PFC_PIN_GROUP(msiof1_txd_b),
4321 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4322 SH_PFC_PIN_GROUP(msiof1_clk_c),
4323 SH_PFC_PIN_GROUP(msiof1_sync_c),
4324 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4325 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4326 SH_PFC_PIN_GROUP(msiof1_txd_c),
4327 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4328 SH_PFC_PIN_GROUP(msiof1_clk_d),
4329 SH_PFC_PIN_GROUP(msiof1_sync_d),
4330 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4331 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4332 SH_PFC_PIN_GROUP(msiof1_txd_d),
4333 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4334 SH_PFC_PIN_GROUP(msiof1_clk_e),
4335 SH_PFC_PIN_GROUP(msiof1_sync_e),
4336 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4337 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4338 SH_PFC_PIN_GROUP(msiof1_txd_e),
4339 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4340 SH_PFC_PIN_GROUP(msiof1_clk_f),
4341 SH_PFC_PIN_GROUP(msiof1_sync_f),
4342 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4343 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4344 SH_PFC_PIN_GROUP(msiof1_txd_f),
4345 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4346 SH_PFC_PIN_GROUP(msiof1_clk_g),
4347 SH_PFC_PIN_GROUP(msiof1_sync_g),
4348 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4349 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4350 SH_PFC_PIN_GROUP(msiof1_txd_g),
4351 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4352 SH_PFC_PIN_GROUP(msiof2_clk_a),
4353 SH_PFC_PIN_GROUP(msiof2_sync_a),
4354 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4355 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4356 SH_PFC_PIN_GROUP(msiof2_txd_a),
4357 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4358 SH_PFC_PIN_GROUP(msiof2_clk_b),
4359 SH_PFC_PIN_GROUP(msiof2_sync_b),
4360 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4361 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4362 SH_PFC_PIN_GROUP(msiof2_txd_b),
4363 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4364 SH_PFC_PIN_GROUP(msiof2_clk_c),
4365 SH_PFC_PIN_GROUP(msiof2_sync_c),
4366 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4367 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4368 SH_PFC_PIN_GROUP(msiof2_txd_c),
4369 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4370 SH_PFC_PIN_GROUP(msiof2_clk_d),
4371 SH_PFC_PIN_GROUP(msiof2_sync_d),
4372 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4373 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4374 SH_PFC_PIN_GROUP(msiof2_txd_d),
4375 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4376 SH_PFC_PIN_GROUP(msiof3_clk_a),
4377 SH_PFC_PIN_GROUP(msiof3_sync_a),
4378 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4379 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4380 SH_PFC_PIN_GROUP(msiof3_txd_a),
4381 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4382 SH_PFC_PIN_GROUP(msiof3_clk_b),
4383 SH_PFC_PIN_GROUP(msiof3_sync_b),
4384 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4385 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4386 SH_PFC_PIN_GROUP(msiof3_txd_b),
4387 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4388 SH_PFC_PIN_GROUP(msiof3_clk_c),
4389 SH_PFC_PIN_GROUP(msiof3_sync_c),
4390 SH_PFC_PIN_GROUP(msiof3_txd_c),
4391 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4392 SH_PFC_PIN_GROUP(msiof3_clk_d),
4393 SH_PFC_PIN_GROUP(msiof3_sync_d),
4394 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4395 SH_PFC_PIN_GROUP(msiof3_txd_d),
4396 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4397 SH_PFC_PIN_GROUP(msiof3_clk_e),
4398 SH_PFC_PIN_GROUP(msiof3_sync_e),
4399 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4400 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4401 SH_PFC_PIN_GROUP(msiof3_txd_e),
4402 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4403 SH_PFC_PIN_GROUP(pwm0),
4404 SH_PFC_PIN_GROUP(pwm1_a),
4405 SH_PFC_PIN_GROUP(pwm1_b),
4406 SH_PFC_PIN_GROUP(pwm2_a),
4407 SH_PFC_PIN_GROUP(pwm2_b),
4408 SH_PFC_PIN_GROUP(pwm3_a),
4409 SH_PFC_PIN_GROUP(pwm3_b),
4410 SH_PFC_PIN_GROUP(pwm4_a),
4411 SH_PFC_PIN_GROUP(pwm4_b),
4412 SH_PFC_PIN_GROUP(pwm5_a),
4413 SH_PFC_PIN_GROUP(pwm5_b),
4414 SH_PFC_PIN_GROUP(pwm6_a),
4415 SH_PFC_PIN_GROUP(pwm6_b),
4416 SH_PFC_PIN_GROUP(qspi0_ctrl),
4417 SH_PFC_PIN_GROUP(qspi0_data2),
4418 SH_PFC_PIN_GROUP(qspi0_data4),
4419 SH_PFC_PIN_GROUP(qspi1_ctrl),
4420 SH_PFC_PIN_GROUP(qspi1_data2),
4421 SH_PFC_PIN_GROUP(qspi1_data4),
4422 SH_PFC_PIN_GROUP(scif0_data),
4423 SH_PFC_PIN_GROUP(scif0_clk),
4424 SH_PFC_PIN_GROUP(scif0_ctrl),
4425 SH_PFC_PIN_GROUP(scif1_data_a),
4426 SH_PFC_PIN_GROUP(scif1_clk),
4427 SH_PFC_PIN_GROUP(scif1_ctrl),
4428 SH_PFC_PIN_GROUP(scif1_data_b),
4429 SH_PFC_PIN_GROUP(scif2_data_a),
4430 SH_PFC_PIN_GROUP(scif2_clk),
4431 SH_PFC_PIN_GROUP(scif2_data_b),
4432 SH_PFC_PIN_GROUP(scif3_data_a),
4433 SH_PFC_PIN_GROUP(scif3_clk),
4434 SH_PFC_PIN_GROUP(scif3_ctrl),
4435 SH_PFC_PIN_GROUP(scif3_data_b),
4436 SH_PFC_PIN_GROUP(scif4_data_a),
4437 SH_PFC_PIN_GROUP(scif4_clk_a),
4438 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4439 SH_PFC_PIN_GROUP(scif4_data_b),
4440 SH_PFC_PIN_GROUP(scif4_clk_b),
4441 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4442 SH_PFC_PIN_GROUP(scif4_data_c),
4443 SH_PFC_PIN_GROUP(scif4_clk_c),
4444 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4445 SH_PFC_PIN_GROUP(scif5_data_a),
4446 SH_PFC_PIN_GROUP(scif5_clk_a),
4447 SH_PFC_PIN_GROUP(scif5_data_b),
4448 SH_PFC_PIN_GROUP(scif5_clk_b),
4449 SH_PFC_PIN_GROUP(scif_clk_a),
4450 SH_PFC_PIN_GROUP(scif_clk_b),
4451 SH_PFC_PIN_GROUP(sdhi0_data1),
4452 SH_PFC_PIN_GROUP(sdhi0_data4),
4453 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4454 SH_PFC_PIN_GROUP(sdhi0_cd),
4455 SH_PFC_PIN_GROUP(sdhi0_wp),
4456 SH_PFC_PIN_GROUP(sdhi1_data1),
4457 SH_PFC_PIN_GROUP(sdhi1_data4),
4458 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4459 SH_PFC_PIN_GROUP(sdhi1_cd),
4460 SH_PFC_PIN_GROUP(sdhi1_wp),
4461 SH_PFC_PIN_GROUP(sdhi2_data1),
4462 SH_PFC_PIN_GROUP(sdhi2_data4),
4463 SH_PFC_PIN_GROUP(sdhi2_data8),
4464 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4465 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4466 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4467 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4468 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4469 SH_PFC_PIN_GROUP(sdhi2_ds),
4470 SH_PFC_PIN_GROUP(sdhi3_data1),
4471 SH_PFC_PIN_GROUP(sdhi3_data4),
4472 SH_PFC_PIN_GROUP(sdhi3_data8),
4473 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4474 SH_PFC_PIN_GROUP(sdhi3_cd),
4475 SH_PFC_PIN_GROUP(sdhi3_wp),
4476 SH_PFC_PIN_GROUP(sdhi3_ds),
4477 SH_PFC_PIN_GROUP(ssi0_data),
4478 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4479 SH_PFC_PIN_GROUP(ssi1_data_a),
4480 SH_PFC_PIN_GROUP(ssi1_data_b),
4481 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4482 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4483 SH_PFC_PIN_GROUP(ssi2_data_a),
4484 SH_PFC_PIN_GROUP(ssi2_data_b),
4485 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4486 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4487 SH_PFC_PIN_GROUP(ssi3_data),
4488 SH_PFC_PIN_GROUP(ssi349_ctrl),
4489 SH_PFC_PIN_GROUP(ssi4_data),
4490 SH_PFC_PIN_GROUP(ssi4_ctrl),
4491 SH_PFC_PIN_GROUP(ssi5_data),
4492 SH_PFC_PIN_GROUP(ssi5_ctrl),
4493 SH_PFC_PIN_GROUP(ssi6_data),
4494 SH_PFC_PIN_GROUP(ssi6_ctrl),
4495 SH_PFC_PIN_GROUP(ssi7_data),
4496 SH_PFC_PIN_GROUP(ssi78_ctrl),
4497 SH_PFC_PIN_GROUP(ssi8_data),
4498 SH_PFC_PIN_GROUP(ssi9_data_a),
4499 SH_PFC_PIN_GROUP(ssi9_data_b),
4500 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4501 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4502 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4503 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4504 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4505 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4506 SH_PFC_PIN_GROUP(tpu_to0),
4507 SH_PFC_PIN_GROUP(tpu_to1),
4508 SH_PFC_PIN_GROUP(tpu_to2),
4509 SH_PFC_PIN_GROUP(tpu_to3),
4510 SH_PFC_PIN_GROUP(usb0),
4511 SH_PFC_PIN_GROUP(usb1),
4512 SH_PFC_PIN_GROUP(usb30),
4513 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4514 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4515 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4516 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4517 SH_PFC_PIN_GROUP(vin4_data18_a),
4518 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4519 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4520 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4521 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4522 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4523 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4524 SH_PFC_PIN_GROUP(vin4_data18_b),
4525 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4526 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4527 SH_PFC_PIN_GROUP(vin4_g8),
4528 SH_PFC_PIN_GROUP(vin4_sync),
4529 SH_PFC_PIN_GROUP(vin4_field),
4530 SH_PFC_PIN_GROUP(vin4_clkenb),
4531 SH_PFC_PIN_GROUP(vin4_clk),
4532 VIN_DATA_PIN_GROUP(vin5_data, 8),
4533 VIN_DATA_PIN_GROUP(vin5_data, 10),
4534 VIN_DATA_PIN_GROUP(vin5_data, 12),
4535 VIN_DATA_PIN_GROUP(vin5_data, 16),
4536 SH_PFC_PIN_GROUP(vin5_high8),
4537 SH_PFC_PIN_GROUP(vin5_sync),
4538 SH_PFC_PIN_GROUP(vin5_field),
4539 SH_PFC_PIN_GROUP(vin5_clkenb),
4540 SH_PFC_PIN_GROUP(vin5_clk),
4541 },
4542#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4543 .automotive = {
4544 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4545 SH_PFC_PIN_GROUP(drif0_data0_a),
4546 SH_PFC_PIN_GROUP(drif0_data1_a),
4547 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4548 SH_PFC_PIN_GROUP(drif0_data0_b),
4549 SH_PFC_PIN_GROUP(drif0_data1_b),
4550 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4551 SH_PFC_PIN_GROUP(drif0_data0_c),
4552 SH_PFC_PIN_GROUP(drif0_data1_c),
4553 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4554 SH_PFC_PIN_GROUP(drif1_data0_a),
4555 SH_PFC_PIN_GROUP(drif1_data1_a),
4556 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4557 SH_PFC_PIN_GROUP(drif1_data0_b),
4558 SH_PFC_PIN_GROUP(drif1_data1_b),
4559 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4560 SH_PFC_PIN_GROUP(drif1_data0_c),
4561 SH_PFC_PIN_GROUP(drif1_data1_c),
4562 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4563 SH_PFC_PIN_GROUP(drif2_data0_a),
4564 SH_PFC_PIN_GROUP(drif2_data1_a),
4565 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4566 SH_PFC_PIN_GROUP(drif2_data0_b),
4567 SH_PFC_PIN_GROUP(drif2_data1_b),
4568 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4569 SH_PFC_PIN_GROUP(drif3_data0_a),
4570 SH_PFC_PIN_GROUP(drif3_data1_a),
4571 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4572 SH_PFC_PIN_GROUP(drif3_data0_b),
4573 SH_PFC_PIN_GROUP(drif3_data1_b),
4574 }
4575#endif
4576};
4577
4578static const char * const audio_clk_groups[] = {
4579 "audio_clk_a_a",
4580 "audio_clk_a_b",
4581 "audio_clk_a_c",
4582 "audio_clk_b_a",
4583 "audio_clk_b_b",
4584 "audio_clk_c_a",
4585 "audio_clk_c_b",
4586 "audio_clkout_a",
4587 "audio_clkout_b",
4588 "audio_clkout_c",
4589 "audio_clkout_d",
4590 "audio_clkout1_a",
4591 "audio_clkout1_b",
4592 "audio_clkout2_a",
4593 "audio_clkout2_b",
4594 "audio_clkout3_a",
4595 "audio_clkout3_b",
4596};
4597
4598static const char * const avb_groups[] = {
4599 "avb_link",
4600 "avb_magic",
4601 "avb_phy_int",
4602 "avb_mdc",
4603 "avb_mdio",
4604 "avb_mii",
4605 "avb_avtp_pps",
4606 "avb_avtp_match_a",
4607 "avb_avtp_capture_a",
4608 "avb_avtp_match_b",
4609 "avb_avtp_capture_b",
4610};
4611
4612static const char * const can0_groups[] = {
4613 "can0_data_a",
4614 "can0_data_b",
4615};
4616
4617static const char * const can1_groups[] = {
4618 "can1_data",
4619};
4620
4621static const char * const can_clk_groups[] = {
4622 "can_clk",
4623};
4624
4625static const char * const canfd0_groups[] = {
4626 "canfd0_data_a",
4627 "canfd0_data_b",
4628};
4629
4630static const char * const canfd1_groups[] = {
4631 "canfd1_data",
4632};
4633
4634#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4635static const char * const drif0_groups[] = {
4636 "drif0_ctrl_a",
4637 "drif0_data0_a",
4638 "drif0_data1_a",
4639 "drif0_ctrl_b",
4640 "drif0_data0_b",
4641 "drif0_data1_b",
4642 "drif0_ctrl_c",
4643 "drif0_data0_c",
4644 "drif0_data1_c",
4645};
4646
4647static const char * const drif1_groups[] = {
4648 "drif1_ctrl_a",
4649 "drif1_data0_a",
4650 "drif1_data1_a",
4651 "drif1_ctrl_b",
4652 "drif1_data0_b",
4653 "drif1_data1_b",
4654 "drif1_ctrl_c",
4655 "drif1_data0_c",
4656 "drif1_data1_c",
4657};
4658
4659static const char * const drif2_groups[] = {
4660 "drif2_ctrl_a",
4661 "drif2_data0_a",
4662 "drif2_data1_a",
4663 "drif2_ctrl_b",
4664 "drif2_data0_b",
4665 "drif2_data1_b",
4666};
4667
4668static const char * const drif3_groups[] = {
4669 "drif3_ctrl_a",
4670 "drif3_data0_a",
4671 "drif3_data1_a",
4672 "drif3_ctrl_b",
4673 "drif3_data0_b",
4674 "drif3_data1_b",
4675};
4676#endif
4677
4678static const char * const du_groups[] = {
4679 "du_rgb666",
4680 "du_rgb888",
4681 "du_clk_out_0",
4682 "du_clk_out_1",
4683 "du_sync",
4684 "du_oddf",
4685 "du_cde",
4686 "du_disp",
4687};
4688
4689static const char * const hscif0_groups[] = {
4690 "hscif0_data",
4691 "hscif0_clk",
4692 "hscif0_ctrl",
4693};
4694
4695static const char * const hscif1_groups[] = {
4696 "hscif1_data_a",
4697 "hscif1_clk_a",
4698 "hscif1_ctrl_a",
4699 "hscif1_data_b",
4700 "hscif1_clk_b",
4701 "hscif1_ctrl_b",
4702};
4703
4704static const char * const hscif2_groups[] = {
4705 "hscif2_data_a",
4706 "hscif2_clk_a",
4707 "hscif2_ctrl_a",
4708 "hscif2_data_b",
4709 "hscif2_clk_b",
4710 "hscif2_ctrl_b",
4711 "hscif2_data_c",
4712 "hscif2_clk_c",
4713 "hscif2_ctrl_c",
4714};
4715
4716static const char * const hscif3_groups[] = {
4717 "hscif3_data_a",
4718 "hscif3_clk",
4719 "hscif3_ctrl",
4720 "hscif3_data_b",
4721 "hscif3_data_c",
4722 "hscif3_data_d",
4723};
4724
4725static const char * const hscif4_groups[] = {
4726 "hscif4_data_a",
4727 "hscif4_clk",
4728 "hscif4_ctrl",
4729 "hscif4_data_b",
4730};
4731
4732static const char * const i2c0_groups[] = {
4733 "i2c0",
4734};
4735
4736static const char * const i2c1_groups[] = {
4737 "i2c1_a",
4738 "i2c1_b",
4739};
4740
4741static const char * const i2c2_groups[] = {
4742 "i2c2_a",
4743 "i2c2_b",
4744};
4745
4746static const char * const i2c3_groups[] = {
4747 "i2c3",
4748};
4749
4750static const char * const i2c5_groups[] = {
4751 "i2c5",
4752};
4753
4754static const char * const i2c6_groups[] = {
4755 "i2c6_a",
4756 "i2c6_b",
4757 "i2c6_c",
4758};
4759
4760static const char * const intc_ex_groups[] = {
4761 "intc_ex_irq0",
4762 "intc_ex_irq1",
4763 "intc_ex_irq2",
4764 "intc_ex_irq3",
4765 "intc_ex_irq4",
4766 "intc_ex_irq5",
4767};
4768
4769static const char * const msiof0_groups[] = {
4770 "msiof0_clk",
4771 "msiof0_sync",
4772 "msiof0_ss1",
4773 "msiof0_ss2",
4774 "msiof0_txd",
4775 "msiof0_rxd",
4776};
4777
4778static const char * const msiof1_groups[] = {
4779 "msiof1_clk_a",
4780 "msiof1_sync_a",
4781 "msiof1_ss1_a",
4782 "msiof1_ss2_a",
4783 "msiof1_txd_a",
4784 "msiof1_rxd_a",
4785 "msiof1_clk_b",
4786 "msiof1_sync_b",
4787 "msiof1_ss1_b",
4788 "msiof1_ss2_b",
4789 "msiof1_txd_b",
4790 "msiof1_rxd_b",
4791 "msiof1_clk_c",
4792 "msiof1_sync_c",
4793 "msiof1_ss1_c",
4794 "msiof1_ss2_c",
4795 "msiof1_txd_c",
4796 "msiof1_rxd_c",
4797 "msiof1_clk_d",
4798 "msiof1_sync_d",
4799 "msiof1_ss1_d",
4800 "msiof1_ss2_d",
4801 "msiof1_txd_d",
4802 "msiof1_rxd_d",
4803 "msiof1_clk_e",
4804 "msiof1_sync_e",
4805 "msiof1_ss1_e",
4806 "msiof1_ss2_e",
4807 "msiof1_txd_e",
4808 "msiof1_rxd_e",
4809 "msiof1_clk_f",
4810 "msiof1_sync_f",
4811 "msiof1_ss1_f",
4812 "msiof1_ss2_f",
4813 "msiof1_txd_f",
4814 "msiof1_rxd_f",
4815 "msiof1_clk_g",
4816 "msiof1_sync_g",
4817 "msiof1_ss1_g",
4818 "msiof1_ss2_g",
4819 "msiof1_txd_g",
4820 "msiof1_rxd_g",
4821};
4822
4823static const char * const msiof2_groups[] = {
4824 "msiof2_clk_a",
4825 "msiof2_sync_a",
4826 "msiof2_ss1_a",
4827 "msiof2_ss2_a",
4828 "msiof2_txd_a",
4829 "msiof2_rxd_a",
4830 "msiof2_clk_b",
4831 "msiof2_sync_b",
4832 "msiof2_ss1_b",
4833 "msiof2_ss2_b",
4834 "msiof2_txd_b",
4835 "msiof2_rxd_b",
4836 "msiof2_clk_c",
4837 "msiof2_sync_c",
4838 "msiof2_ss1_c",
4839 "msiof2_ss2_c",
4840 "msiof2_txd_c",
4841 "msiof2_rxd_c",
4842 "msiof2_clk_d",
4843 "msiof2_sync_d",
4844 "msiof2_ss1_d",
4845 "msiof2_ss2_d",
4846 "msiof2_txd_d",
4847 "msiof2_rxd_d",
4848};
4849
4850static const char * const msiof3_groups[] = {
4851 "msiof3_clk_a",
4852 "msiof3_sync_a",
4853 "msiof3_ss1_a",
4854 "msiof3_ss2_a",
4855 "msiof3_txd_a",
4856 "msiof3_rxd_a",
4857 "msiof3_clk_b",
4858 "msiof3_sync_b",
4859 "msiof3_ss1_b",
4860 "msiof3_ss2_b",
4861 "msiof3_txd_b",
4862 "msiof3_rxd_b",
4863 "msiof3_clk_c",
4864 "msiof3_sync_c",
4865 "msiof3_txd_c",
4866 "msiof3_rxd_c",
4867 "msiof3_clk_d",
4868 "msiof3_sync_d",
4869 "msiof3_ss1_d",
4870 "msiof3_txd_d",
4871 "msiof3_rxd_d",
4872 "msiof3_clk_e",
4873 "msiof3_sync_e",
4874 "msiof3_ss1_e",
4875 "msiof3_ss2_e",
4876 "msiof3_txd_e",
4877 "msiof3_rxd_e",
4878};
4879
4880static const char * const pwm0_groups[] = {
4881 "pwm0",
4882};
4883
4884static const char * const pwm1_groups[] = {
4885 "pwm1_a",
4886 "pwm1_b",
4887};
4888
4889static const char * const pwm2_groups[] = {
4890 "pwm2_a",
4891 "pwm2_b",
4892};
4893
4894static const char * const pwm3_groups[] = {
4895 "pwm3_a",
4896 "pwm3_b",
4897};
4898
4899static const char * const pwm4_groups[] = {
4900 "pwm4_a",
4901 "pwm4_b",
4902};
4903
4904static const char * const pwm5_groups[] = {
4905 "pwm5_a",
4906 "pwm5_b",
4907};
4908
4909static const char * const pwm6_groups[] = {
4910 "pwm6_a",
4911 "pwm6_b",
4912};
4913
4914static const char * const qspi0_groups[] = {
4915 "qspi0_ctrl",
4916 "qspi0_data2",
4917 "qspi0_data4",
4918};
4919
4920static const char * const qspi1_groups[] = {
4921 "qspi1_ctrl",
4922 "qspi1_data2",
4923 "qspi1_data4",
4924};
4925
4926static const char * const scif0_groups[] = {
4927 "scif0_data",
4928 "scif0_clk",
4929 "scif0_ctrl",
4930};
4931
4932static const char * const scif1_groups[] = {
4933 "scif1_data_a",
4934 "scif1_clk",
4935 "scif1_ctrl",
4936 "scif1_data_b",
4937};
4938
4939static const char * const scif2_groups[] = {
4940 "scif2_data_a",
4941 "scif2_clk",
4942 "scif2_data_b",
4943};
4944
4945static const char * const scif3_groups[] = {
4946 "scif3_data_a",
4947 "scif3_clk",
4948 "scif3_ctrl",
4949 "scif3_data_b",
4950};
4951
4952static const char * const scif4_groups[] = {
4953 "scif4_data_a",
4954 "scif4_clk_a",
4955 "scif4_ctrl_a",
4956 "scif4_data_b",
4957 "scif4_clk_b",
4958 "scif4_ctrl_b",
4959 "scif4_data_c",
4960 "scif4_clk_c",
4961 "scif4_ctrl_c",
4962};
4963
4964static const char * const scif5_groups[] = {
4965 "scif5_data_a",
4966 "scif5_clk_a",
4967 "scif5_data_b",
4968 "scif5_clk_b",
4969};
4970
4971static const char * const scif_clk_groups[] = {
4972 "scif_clk_a",
4973 "scif_clk_b",
4974};
4975
4976static const char * const sdhi0_groups[] = {
4977 "sdhi0_data1",
4978 "sdhi0_data4",
4979 "sdhi0_ctrl",
4980 "sdhi0_cd",
4981 "sdhi0_wp",
4982};
4983
4984static const char * const sdhi1_groups[] = {
4985 "sdhi1_data1",
4986 "sdhi1_data4",
4987 "sdhi1_ctrl",
4988 "sdhi1_cd",
4989 "sdhi1_wp",
4990};
4991
4992static const char * const sdhi2_groups[] = {
4993 "sdhi2_data1",
4994 "sdhi2_data4",
4995 "sdhi2_data8",
4996 "sdhi2_ctrl",
4997 "sdhi2_cd_a",
4998 "sdhi2_wp_a",
4999 "sdhi2_cd_b",
5000 "sdhi2_wp_b",
5001 "sdhi2_ds",
5002};
5003
5004static const char * const sdhi3_groups[] = {
5005 "sdhi3_data1",
5006 "sdhi3_data4",
5007 "sdhi3_data8",
5008 "sdhi3_ctrl",
5009 "sdhi3_cd",
5010 "sdhi3_wp",
5011 "sdhi3_ds",
5012};
5013
5014static const char * const ssi_groups[] = {
5015 "ssi0_data",
5016 "ssi01239_ctrl",
5017 "ssi1_data_a",
5018 "ssi1_data_b",
5019 "ssi1_ctrl_a",
5020 "ssi1_ctrl_b",
5021 "ssi2_data_a",
5022 "ssi2_data_b",
5023 "ssi2_ctrl_a",
5024 "ssi2_ctrl_b",
5025 "ssi3_data",
5026 "ssi349_ctrl",
5027 "ssi4_data",
5028 "ssi4_ctrl",
5029 "ssi5_data",
5030 "ssi5_ctrl",
5031 "ssi6_data",
5032 "ssi6_ctrl",
5033 "ssi7_data",
5034 "ssi78_ctrl",
5035 "ssi8_data",
5036 "ssi9_data_a",
5037 "ssi9_data_b",
5038 "ssi9_ctrl_a",
5039 "ssi9_ctrl_b",
5040};
5041
5042static const char * const tmu_groups[] = {
5043 "tmu_tclk1_a",
5044 "tmu_tclk1_b",
5045 "tmu_tclk2_a",
5046 "tmu_tclk2_b",
5047};
5048
5049static const char * const tpu_groups[] = {
5050 "tpu_to0",
5051 "tpu_to1",
5052 "tpu_to2",
5053 "tpu_to3",
5054};
5055
5056static const char * const usb0_groups[] = {
5057 "usb0",
5058};
5059
5060static const char * const usb1_groups[] = {
5061 "usb1",
5062};
5063
5064static const char * const usb30_groups[] = {
5065 "usb30",
5066};
5067
5068static const char * const vin4_groups[] = {
5069 "vin4_data8_a",
5070 "vin4_data10_a",
5071 "vin4_data12_a",
5072 "vin4_data16_a",
5073 "vin4_data18_a",
5074 "vin4_data20_a",
5075 "vin4_data24_a",
5076 "vin4_data8_b",
5077 "vin4_data10_b",
5078 "vin4_data12_b",
5079 "vin4_data16_b",
5080 "vin4_data18_b",
5081 "vin4_data20_b",
5082 "vin4_data24_b",
5083 "vin4_g8",
5084 "vin4_sync",
5085 "vin4_field",
5086 "vin4_clkenb",
5087 "vin4_clk",
5088};
5089
5090static const char * const vin5_groups[] = {
5091 "vin5_data8",
5092 "vin5_data10",
5093 "vin5_data12",
5094 "vin5_data16",
5095 "vin5_high8",
5096 "vin5_sync",
5097 "vin5_field",
5098 "vin5_clkenb",
5099 "vin5_clk",
5100};
5101
5102static const struct {
5103 struct sh_pfc_function common[52];
5104#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5105 struct sh_pfc_function automotive[4];
5106#endif
5107} pinmux_functions = {
5108 .common = {
5109 SH_PFC_FUNCTION(audio_clk),
5110 SH_PFC_FUNCTION(avb),
5111 SH_PFC_FUNCTION(can0),
5112 SH_PFC_FUNCTION(can1),
5113 SH_PFC_FUNCTION(can_clk),
5114 SH_PFC_FUNCTION(canfd0),
5115 SH_PFC_FUNCTION(canfd1),
5116 SH_PFC_FUNCTION(du),
5117 SH_PFC_FUNCTION(hscif0),
5118 SH_PFC_FUNCTION(hscif1),
5119 SH_PFC_FUNCTION(hscif2),
5120 SH_PFC_FUNCTION(hscif3),
5121 SH_PFC_FUNCTION(hscif4),
5122 SH_PFC_FUNCTION(i2c0),
5123 SH_PFC_FUNCTION(i2c1),
5124 SH_PFC_FUNCTION(i2c2),
5125 SH_PFC_FUNCTION(i2c3),
5126 SH_PFC_FUNCTION(i2c5),
5127 SH_PFC_FUNCTION(i2c6),
5128 SH_PFC_FUNCTION(intc_ex),
5129 SH_PFC_FUNCTION(msiof0),
5130 SH_PFC_FUNCTION(msiof1),
5131 SH_PFC_FUNCTION(msiof2),
5132 SH_PFC_FUNCTION(msiof3),
5133 SH_PFC_FUNCTION(pwm0),
5134 SH_PFC_FUNCTION(pwm1),
5135 SH_PFC_FUNCTION(pwm2),
5136 SH_PFC_FUNCTION(pwm3),
5137 SH_PFC_FUNCTION(pwm4),
5138 SH_PFC_FUNCTION(pwm5),
5139 SH_PFC_FUNCTION(pwm6),
5140 SH_PFC_FUNCTION(qspi0),
5141 SH_PFC_FUNCTION(qspi1),
5142 SH_PFC_FUNCTION(scif0),
5143 SH_PFC_FUNCTION(scif1),
5144 SH_PFC_FUNCTION(scif2),
5145 SH_PFC_FUNCTION(scif3),
5146 SH_PFC_FUNCTION(scif4),
5147 SH_PFC_FUNCTION(scif5),
5148 SH_PFC_FUNCTION(scif_clk),
5149 SH_PFC_FUNCTION(sdhi0),
5150 SH_PFC_FUNCTION(sdhi1),
5151 SH_PFC_FUNCTION(sdhi2),
5152 SH_PFC_FUNCTION(sdhi3),
5153 SH_PFC_FUNCTION(ssi),
5154 SH_PFC_FUNCTION(tmu),
5155 SH_PFC_FUNCTION(tpu),
5156 SH_PFC_FUNCTION(usb0),
5157 SH_PFC_FUNCTION(usb1),
5158 SH_PFC_FUNCTION(usb30),
5159 SH_PFC_FUNCTION(vin4),
5160 SH_PFC_FUNCTION(vin5),
5161 },
5162#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5163 .automotive = {
5164 SH_PFC_FUNCTION(drif0),
5165 SH_PFC_FUNCTION(drif1),
5166 SH_PFC_FUNCTION(drif2),
5167 SH_PFC_FUNCTION(drif3),
5168 }
5169#endif
5170};
5171
5172static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5173#define F_(x, y) FN_##y
5174#define FM(x) FN_##x
5175 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 0, 0,
5183 0, 0,
5184 0, 0,
5185 0, 0,
5186 0, 0,
5187 0, 0,
5188 0, 0,
5189 0, 0,
5190 0, 0,
5191 0, 0,
5192 GP_0_15_FN, GPSR0_15,
5193 GP_0_14_FN, GPSR0_14,
5194 GP_0_13_FN, GPSR0_13,
5195 GP_0_12_FN, GPSR0_12,
5196 GP_0_11_FN, GPSR0_11,
5197 GP_0_10_FN, GPSR0_10,
5198 GP_0_9_FN, GPSR0_9,
5199 GP_0_8_FN, GPSR0_8,
5200 GP_0_7_FN, GPSR0_7,
5201 GP_0_6_FN, GPSR0_6,
5202 GP_0_5_FN, GPSR0_5,
5203 GP_0_4_FN, GPSR0_4,
5204 GP_0_3_FN, GPSR0_3,
5205 GP_0_2_FN, GPSR0_2,
5206 GP_0_1_FN, GPSR0_1,
5207 GP_0_0_FN, GPSR0_0, ))
5208 },
5209 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5210 0, 0,
5211 0, 0,
5212 0, 0,
5213 GP_1_28_FN, GPSR1_28,
5214 GP_1_27_FN, GPSR1_27,
5215 GP_1_26_FN, GPSR1_26,
5216 GP_1_25_FN, GPSR1_25,
5217 GP_1_24_FN, GPSR1_24,
5218 GP_1_23_FN, GPSR1_23,
5219 GP_1_22_FN, GPSR1_22,
5220 GP_1_21_FN, GPSR1_21,
5221 GP_1_20_FN, GPSR1_20,
5222 GP_1_19_FN, GPSR1_19,
5223 GP_1_18_FN, GPSR1_18,
5224 GP_1_17_FN, GPSR1_17,
5225 GP_1_16_FN, GPSR1_16,
5226 GP_1_15_FN, GPSR1_15,
5227 GP_1_14_FN, GPSR1_14,
5228 GP_1_13_FN, GPSR1_13,
5229 GP_1_12_FN, GPSR1_12,
5230 GP_1_11_FN, GPSR1_11,
5231 GP_1_10_FN, GPSR1_10,
5232 GP_1_9_FN, GPSR1_9,
5233 GP_1_8_FN, GPSR1_8,
5234 GP_1_7_FN, GPSR1_7,
5235 GP_1_6_FN, GPSR1_6,
5236 GP_1_5_FN, GPSR1_5,
5237 GP_1_4_FN, GPSR1_4,
5238 GP_1_3_FN, GPSR1_3,
5239 GP_1_2_FN, GPSR1_2,
5240 GP_1_1_FN, GPSR1_1,
5241 GP_1_0_FN, GPSR1_0, ))
5242 },
5243 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5244 0, 0,
5245 0, 0,
5246 0, 0,
5247 0, 0,
5248 0, 0,
5249 0, 0,
5250 0, 0,
5251 0, 0,
5252 0, 0,
5253 0, 0,
5254 0, 0,
5255 0, 0,
5256 0, 0,
5257 0, 0,
5258 0, 0,
5259 0, 0,
5260 0, 0,
5261 GP_2_14_FN, GPSR2_14,
5262 GP_2_13_FN, GPSR2_13,
5263 GP_2_12_FN, GPSR2_12,
5264 GP_2_11_FN, GPSR2_11,
5265 GP_2_10_FN, GPSR2_10,
5266 GP_2_9_FN, GPSR2_9,
5267 GP_2_8_FN, GPSR2_8,
5268 GP_2_7_FN, GPSR2_7,
5269 GP_2_6_FN, GPSR2_6,
5270 GP_2_5_FN, GPSR2_5,
5271 GP_2_4_FN, GPSR2_4,
5272 GP_2_3_FN, GPSR2_3,
5273 GP_2_2_FN, GPSR2_2,
5274 GP_2_1_FN, GPSR2_1,
5275 GP_2_0_FN, GPSR2_0, ))
5276 },
5277 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 0, 0,
5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 0, 0,
5291 0, 0,
5292 0, 0,
5293 0, 0,
5294 GP_3_15_FN, GPSR3_15,
5295 GP_3_14_FN, GPSR3_14,
5296 GP_3_13_FN, GPSR3_13,
5297 GP_3_12_FN, GPSR3_12,
5298 GP_3_11_FN, GPSR3_11,
5299 GP_3_10_FN, GPSR3_10,
5300 GP_3_9_FN, GPSR3_9,
5301 GP_3_8_FN, GPSR3_8,
5302 GP_3_7_FN, GPSR3_7,
5303 GP_3_6_FN, GPSR3_6,
5304 GP_3_5_FN, GPSR3_5,
5305 GP_3_4_FN, GPSR3_4,
5306 GP_3_3_FN, GPSR3_3,
5307 GP_3_2_FN, GPSR3_2,
5308 GP_3_1_FN, GPSR3_1,
5309 GP_3_0_FN, GPSR3_0, ))
5310 },
5311 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5312 0, 0,
5313 0, 0,
5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 GP_4_17_FN, GPSR4_17,
5327 GP_4_16_FN, GPSR4_16,
5328 GP_4_15_FN, GPSR4_15,
5329 GP_4_14_FN, GPSR4_14,
5330 GP_4_13_FN, GPSR4_13,
5331 GP_4_12_FN, GPSR4_12,
5332 GP_4_11_FN, GPSR4_11,
5333 GP_4_10_FN, GPSR4_10,
5334 GP_4_9_FN, GPSR4_9,
5335 GP_4_8_FN, GPSR4_8,
5336 GP_4_7_FN, GPSR4_7,
5337 GP_4_6_FN, GPSR4_6,
5338 GP_4_5_FN, GPSR4_5,
5339 GP_4_4_FN, GPSR4_4,
5340 GP_4_3_FN, GPSR4_3,
5341 GP_4_2_FN, GPSR4_2,
5342 GP_4_1_FN, GPSR4_1,
5343 GP_4_0_FN, GPSR4_0, ))
5344 },
5345 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5346 0, 0,
5347 0, 0,
5348 0, 0,
5349 0, 0,
5350 0, 0,
5351 0, 0,
5352 GP_5_25_FN, GPSR5_25,
5353 GP_5_24_FN, GPSR5_24,
5354 GP_5_23_FN, GPSR5_23,
5355 GP_5_22_FN, GPSR5_22,
5356 GP_5_21_FN, GPSR5_21,
5357 GP_5_20_FN, GPSR5_20,
5358 GP_5_19_FN, GPSR5_19,
5359 GP_5_18_FN, GPSR5_18,
5360 GP_5_17_FN, GPSR5_17,
5361 GP_5_16_FN, GPSR5_16,
5362 GP_5_15_FN, GPSR5_15,
5363 GP_5_14_FN, GPSR5_14,
5364 GP_5_13_FN, GPSR5_13,
5365 GP_5_12_FN, GPSR5_12,
5366 GP_5_11_FN, GPSR5_11,
5367 GP_5_10_FN, GPSR5_10,
5368 GP_5_9_FN, GPSR5_9,
5369 GP_5_8_FN, GPSR5_8,
5370 GP_5_7_FN, GPSR5_7,
5371 GP_5_6_FN, GPSR5_6,
5372 GP_5_5_FN, GPSR5_5,
5373 GP_5_4_FN, GPSR5_4,
5374 GP_5_3_FN, GPSR5_3,
5375 GP_5_2_FN, GPSR5_2,
5376 GP_5_1_FN, GPSR5_1,
5377 GP_5_0_FN, GPSR5_0, ))
5378 },
5379 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5380 GP_6_31_FN, GPSR6_31,
5381 GP_6_30_FN, GPSR6_30,
5382 GP_6_29_FN, GPSR6_29,
5383 GP_6_28_FN, GPSR6_28,
5384 GP_6_27_FN, GPSR6_27,
5385 GP_6_26_FN, GPSR6_26,
5386 GP_6_25_FN, GPSR6_25,
5387 GP_6_24_FN, GPSR6_24,
5388 GP_6_23_FN, GPSR6_23,
5389 GP_6_22_FN, GPSR6_22,
5390 GP_6_21_FN, GPSR6_21,
5391 GP_6_20_FN, GPSR6_20,
5392 GP_6_19_FN, GPSR6_19,
5393 GP_6_18_FN, GPSR6_18,
5394 GP_6_17_FN, GPSR6_17,
5395 GP_6_16_FN, GPSR6_16,
5396 GP_6_15_FN, GPSR6_15,
5397 GP_6_14_FN, GPSR6_14,
5398 GP_6_13_FN, GPSR6_13,
5399 GP_6_12_FN, GPSR6_12,
5400 GP_6_11_FN, GPSR6_11,
5401 GP_6_10_FN, GPSR6_10,
5402 GP_6_9_FN, GPSR6_9,
5403 GP_6_8_FN, GPSR6_8,
5404 GP_6_7_FN, GPSR6_7,
5405 GP_6_6_FN, GPSR6_6,
5406 GP_6_5_FN, GPSR6_5,
5407 GP_6_4_FN, GPSR6_4,
5408 GP_6_3_FN, GPSR6_3,
5409 GP_6_2_FN, GPSR6_2,
5410 GP_6_1_FN, GPSR6_1,
5411 GP_6_0_FN, GPSR6_0, ))
5412 },
5413 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 0, 0,
5420 0, 0,
5421 0, 0,
5422 0, 0,
5423 0, 0,
5424 0, 0,
5425 0, 0,
5426 0, 0,
5427 0, 0,
5428 0, 0,
5429 0, 0,
5430 0, 0,
5431 0, 0,
5432 0, 0,
5433 0, 0,
5434 0, 0,
5435 0, 0,
5436 0, 0,
5437 0, 0,
5438 0, 0,
5439 0, 0,
5440 0, 0,
5441 0, 0,
5442 GP_7_3_FN, GPSR7_3,
5443 GP_7_2_FN, GPSR7_2,
5444 GP_7_1_FN, GPSR7_1,
5445 GP_7_0_FN, GPSR7_0, ))
5446 },
5447#undef F_
5448#undef FM
5449
5450#define F_(x, y) x,
5451#define FM(x) FN_##x,
5452 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5453 IP0_31_28
5454 IP0_27_24
5455 IP0_23_20
5456 IP0_19_16
5457 IP0_15_12
5458 IP0_11_8
5459 IP0_7_4
5460 IP0_3_0 ))
5461 },
5462 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5463 IP1_31_28
5464 IP1_27_24
5465 IP1_23_20
5466 IP1_19_16
5467 IP1_15_12
5468 IP1_11_8
5469 IP1_7_4
5470 IP1_3_0 ))
5471 },
5472 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5473 IP2_31_28
5474 IP2_27_24
5475 IP2_23_20
5476 IP2_19_16
5477 IP2_15_12
5478 IP2_11_8
5479 IP2_7_4
5480 IP2_3_0 ))
5481 },
5482 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5483 IP3_31_28
5484 IP3_27_24
5485 IP3_23_20
5486 IP3_19_16
5487 IP3_15_12
5488 IP3_11_8
5489 IP3_7_4
5490 IP3_3_0 ))
5491 },
5492 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5493 IP4_31_28
5494 IP4_27_24
5495 IP4_23_20
5496 IP4_19_16
5497 IP4_15_12
5498 IP4_11_8
5499 IP4_7_4
5500 IP4_3_0 ))
5501 },
5502 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5503 IP5_31_28
5504 IP5_27_24
5505 IP5_23_20
5506 IP5_19_16
5507 IP5_15_12
5508 IP5_11_8
5509 IP5_7_4
5510 IP5_3_0 ))
5511 },
5512 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5513 IP6_31_28
5514 IP6_27_24
5515 IP6_23_20
5516 IP6_19_16
5517 IP6_15_12
5518 IP6_11_8
5519 IP6_7_4
5520 IP6_3_0 ))
5521 },
5522 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5523 IP7_31_28
5524 IP7_27_24
5525 IP7_23_20
5526 IP7_19_16
5527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5528 IP7_11_8
5529 IP7_7_4
5530 IP7_3_0 ))
5531 },
5532 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5533 IP8_31_28
5534 IP8_27_24
5535 IP8_23_20
5536 IP8_19_16
5537 IP8_15_12
5538 IP8_11_8
5539 IP8_7_4
5540 IP8_3_0 ))
5541 },
5542 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5543 IP9_31_28
5544 IP9_27_24
5545 IP9_23_20
5546 IP9_19_16
5547 IP9_15_12
5548 IP9_11_8
5549 IP9_7_4
5550 IP9_3_0 ))
5551 },
5552 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5553 IP10_31_28
5554 IP10_27_24
5555 IP10_23_20
5556 IP10_19_16
5557 IP10_15_12
5558 IP10_11_8
5559 IP10_7_4
5560 IP10_3_0 ))
5561 },
5562 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5563 IP11_31_28
5564 IP11_27_24
5565 IP11_23_20
5566 IP11_19_16
5567 IP11_15_12
5568 IP11_11_8
5569 IP11_7_4
5570 IP11_3_0 ))
5571 },
5572 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5573 IP12_31_28
5574 IP12_27_24
5575 IP12_23_20
5576 IP12_19_16
5577 IP12_15_12
5578 IP12_11_8
5579 IP12_7_4
5580 IP12_3_0 ))
5581 },
5582 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5583 IP13_31_28
5584 IP13_27_24
5585 IP13_23_20
5586 IP13_19_16
5587 IP13_15_12
5588 IP13_11_8
5589 IP13_7_4
5590 IP13_3_0 ))
5591 },
5592 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5593 IP14_31_28
5594 IP14_27_24
5595 IP14_23_20
5596 IP14_19_16
5597 IP14_15_12
5598 IP14_11_8
5599 IP14_7_4
5600 IP14_3_0 ))
5601 },
5602 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5603 IP15_31_28
5604 IP15_27_24
5605 IP15_23_20
5606 IP15_19_16
5607 IP15_15_12
5608 IP15_11_8
5609 IP15_7_4
5610 IP15_3_0 ))
5611 },
5612 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5613 IP16_31_28
5614 IP16_27_24
5615 IP16_23_20
5616 IP16_19_16
5617 IP16_15_12
5618 IP16_11_8
5619 IP16_7_4
5620 IP16_3_0 ))
5621 },
5622 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5623 IP17_31_28
5624 IP17_27_24
5625 IP17_23_20
5626 IP17_19_16
5627 IP17_15_12
5628 IP17_11_8
5629 IP17_7_4
5630 IP17_3_0 ))
5631 },
5632 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5639 IP18_7_4
5640 IP18_3_0 ))
5641 },
5642#undef F_
5643#undef FM
5644
5645#define F_(x, y) x,
5646#define FM(x) FN_##x,
5647 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5648 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5649 1, 1, 1, 2, 2, 1, 2, 3),
5650 GROUP(
5651 MOD_SEL0_31_30_29
5652 MOD_SEL0_28_27
5653 MOD_SEL0_26_25_24
5654 MOD_SEL0_23
5655 MOD_SEL0_22
5656 MOD_SEL0_21
5657 MOD_SEL0_20
5658 MOD_SEL0_19
5659 MOD_SEL0_18_17
5660 MOD_SEL0_16
5661 0, 0,
5662 MOD_SEL0_14_13
5663 MOD_SEL0_12
5664 MOD_SEL0_11
5665 MOD_SEL0_10
5666 MOD_SEL0_9_8
5667 MOD_SEL0_7_6
5668 MOD_SEL0_5
5669 MOD_SEL0_4_3
5670
5671 0, 0, 0, 0, 0, 0, 0, 0 ))
5672 },
5673 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5674 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5675 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5676 GROUP(
5677 MOD_SEL1_31_30
5678 MOD_SEL1_29_28_27
5679 MOD_SEL1_26
5680 MOD_SEL1_25_24
5681 MOD_SEL1_23_22_21
5682 MOD_SEL1_20
5683 MOD_SEL1_19
5684 MOD_SEL1_18_17
5685 MOD_SEL1_16
5686 MOD_SEL1_15_14
5687 MOD_SEL1_13
5688 MOD_SEL1_12
5689 MOD_SEL1_11
5690 MOD_SEL1_10
5691 MOD_SEL1_9
5692 0, 0, 0, 0,
5693 MOD_SEL1_6
5694 MOD_SEL1_5
5695 MOD_SEL1_4
5696 MOD_SEL1_3
5697 MOD_SEL1_2
5698 MOD_SEL1_1
5699 MOD_SEL1_0 ))
5700 },
5701 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5702 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5703 1, 4, 4, 4, 3, 1),
5704 GROUP(
5705 MOD_SEL2_31
5706 MOD_SEL2_30
5707 MOD_SEL2_29
5708 MOD_SEL2_28_27
5709 MOD_SEL2_26
5710 MOD_SEL2_25_24_23
5711 MOD_SEL2_22
5712 MOD_SEL2_21
5713 MOD_SEL2_20
5714 MOD_SEL2_19
5715 MOD_SEL2_18
5716 MOD_SEL2_17
5717
5718 0, 0,
5719
5720 0, 0, 0, 0, 0, 0, 0, 0,
5721 0, 0, 0, 0, 0, 0, 0, 0,
5722
5723 0, 0, 0, 0, 0, 0, 0, 0,
5724 0, 0, 0, 0, 0, 0, 0, 0,
5725
5726 0, 0, 0, 0, 0, 0, 0, 0,
5727 0, 0, 0, 0, 0, 0, 0, 0,
5728
5729 0, 0, 0, 0, 0, 0, 0, 0,
5730 MOD_SEL2_0 ))
5731 },
5732 { },
5733};
5734
5735static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5736 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5737 { PIN_QSPI0_SPCLK, 28, 2 },
5738 { PIN_QSPI0_MOSI_IO0, 24, 2 },
5739 { PIN_QSPI0_MISO_IO1, 20, 2 },
5740 { PIN_QSPI0_IO2, 16, 2 },
5741 { PIN_QSPI0_IO3, 12, 2 },
5742 { PIN_QSPI0_SSL, 8, 2 },
5743 { PIN_QSPI1_SPCLK, 4, 2 },
5744 { PIN_QSPI1_MOSI_IO0, 0, 2 },
5745 } },
5746 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5747 { PIN_QSPI1_MISO_IO1, 28, 2 },
5748 { PIN_QSPI1_IO2, 24, 2 },
5749 { PIN_QSPI1_IO3, 20, 2 },
5750 { PIN_QSPI1_SSL, 16, 2 },
5751 { PIN_RPC_INT_N, 12, 2 },
5752 { PIN_RPC_WP_N, 8, 2 },
5753 { PIN_RPC_RESET_N, 4, 2 },
5754 { PIN_AVB_RX_CTL, 0, 3 },
5755 } },
5756 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5757 { PIN_AVB_RXC, 28, 3 },
5758 { PIN_AVB_RD0, 24, 3 },
5759 { PIN_AVB_RD1, 20, 3 },
5760 { PIN_AVB_RD2, 16, 3 },
5761 { PIN_AVB_RD3, 12, 3 },
5762 { PIN_AVB_TX_CTL, 8, 3 },
5763 { PIN_AVB_TXC, 4, 3 },
5764 { PIN_AVB_TD0, 0, 3 },
5765 } },
5766 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5767 { PIN_AVB_TD1, 28, 3 },
5768 { PIN_AVB_TD2, 24, 3 },
5769 { PIN_AVB_TD3, 20, 3 },
5770 { PIN_AVB_TXCREFCLK, 16, 3 },
5771 { PIN_AVB_MDIO, 12, 3 },
5772 { RCAR_GP_PIN(2, 9), 8, 3 },
5773 { RCAR_GP_PIN(2, 10), 4, 3 },
5774 { RCAR_GP_PIN(2, 11), 0, 3 },
5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5777 { RCAR_GP_PIN(2, 12), 28, 3 },
5778 { RCAR_GP_PIN(2, 13), 24, 3 },
5779 { RCAR_GP_PIN(2, 14), 20, 3 },
5780 { RCAR_GP_PIN(2, 0), 16, 3 },
5781 { RCAR_GP_PIN(2, 1), 12, 3 },
5782 { RCAR_GP_PIN(2, 2), 8, 3 },
5783 { RCAR_GP_PIN(2, 3), 4, 3 },
5784 { RCAR_GP_PIN(2, 4), 0, 3 },
5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5787 { RCAR_GP_PIN(2, 5), 28, 3 },
5788 { RCAR_GP_PIN(2, 6), 24, 3 },
5789 { RCAR_GP_PIN(2, 7), 20, 3 },
5790 { RCAR_GP_PIN(2, 8), 16, 3 },
5791 { RCAR_GP_PIN(1, 0), 12, 3 },
5792 { RCAR_GP_PIN(1, 1), 8, 3 },
5793 { RCAR_GP_PIN(1, 2), 4, 3 },
5794 { RCAR_GP_PIN(1, 3), 0, 3 },
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5797 { RCAR_GP_PIN(1, 4), 28, 3 },
5798 { RCAR_GP_PIN(1, 5), 24, 3 },
5799 { RCAR_GP_PIN(1, 6), 20, 3 },
5800 { RCAR_GP_PIN(1, 7), 16, 3 },
5801 { RCAR_GP_PIN(1, 8), 12, 3 },
5802 { RCAR_GP_PIN(1, 9), 8, 3 },
5803 { RCAR_GP_PIN(1, 10), 4, 3 },
5804 { RCAR_GP_PIN(1, 11), 0, 3 },
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5807 { RCAR_GP_PIN(1, 12), 28, 3 },
5808 { RCAR_GP_PIN(1, 13), 24, 3 },
5809 { RCAR_GP_PIN(1, 14), 20, 3 },
5810 { RCAR_GP_PIN(1, 15), 16, 3 },
5811 { RCAR_GP_PIN(1, 16), 12, 3 },
5812 { RCAR_GP_PIN(1, 17), 8, 3 },
5813 { RCAR_GP_PIN(1, 18), 4, 3 },
5814 { RCAR_GP_PIN(1, 19), 0, 3 },
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5817 { RCAR_GP_PIN(1, 28), 28, 3 },
5818 { RCAR_GP_PIN(1, 20), 24, 3 },
5819 { RCAR_GP_PIN(1, 21), 20, 3 },
5820 { RCAR_GP_PIN(1, 22), 16, 3 },
5821 { RCAR_GP_PIN(1, 23), 12, 3 },
5822 { RCAR_GP_PIN(1, 24), 8, 3 },
5823 { RCAR_GP_PIN(1, 25), 4, 3 },
5824 { RCAR_GP_PIN(1, 26), 0, 3 },
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5827 { RCAR_GP_PIN(1, 27), 28, 3 },
5828 { PIN_PRESETOUT_N, 24, 3 },
5829 { RCAR_GP_PIN(0, 0), 20, 3 },
5830 { RCAR_GP_PIN(0, 1), 16, 3 },
5831 { RCAR_GP_PIN(0, 2), 12, 3 },
5832 { RCAR_GP_PIN(0, 3), 8, 3 },
5833 { RCAR_GP_PIN(0, 4), 4, 3 },
5834 { RCAR_GP_PIN(0, 5), 0, 3 },
5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5837 { RCAR_GP_PIN(0, 6), 28, 3 },
5838 { RCAR_GP_PIN(0, 7), 24, 3 },
5839 { RCAR_GP_PIN(0, 8), 20, 3 },
5840 { RCAR_GP_PIN(0, 9), 16, 3 },
5841 { RCAR_GP_PIN(0, 10), 12, 3 },
5842 { RCAR_GP_PIN(0, 11), 8, 3 },
5843 { RCAR_GP_PIN(0, 12), 4, 3 },
5844 { RCAR_GP_PIN(0, 13), 0, 3 },
5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5847 { RCAR_GP_PIN(0, 14), 28, 3 },
5848 { RCAR_GP_PIN(0, 15), 24, 3 },
5849 { RCAR_GP_PIN(7, 0), 20, 3 },
5850 { RCAR_GP_PIN(7, 1), 16, 3 },
5851 { RCAR_GP_PIN(7, 2), 12, 3 },
5852 { RCAR_GP_PIN(7, 3), 8, 3 },
5853 { PIN_DU_DOTCLKIN0, 4, 2 },
5854 { PIN_DU_DOTCLKIN1, 0, 2 },
5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5857 { PIN_DU_DOTCLKIN2, 28, 2 },
5858 { PIN_FSCLKST, 20, 2 },
5859 { PIN_TMS, 4, 2 },
5860 } },
5861 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5862 { PIN_TDO, 28, 2 },
5863 { PIN_ASEBRK, 24, 2 },
5864 { RCAR_GP_PIN(3, 0), 20, 3 },
5865 { RCAR_GP_PIN(3, 1), 16, 3 },
5866 { RCAR_GP_PIN(3, 2), 12, 3 },
5867 { RCAR_GP_PIN(3, 3), 8, 3 },
5868 { RCAR_GP_PIN(3, 4), 4, 3 },
5869 { RCAR_GP_PIN(3, 5), 0, 3 },
5870 } },
5871 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5872 { RCAR_GP_PIN(3, 6), 28, 3 },
5873 { RCAR_GP_PIN(3, 7), 24, 3 },
5874 { RCAR_GP_PIN(3, 8), 20, 3 },
5875 { RCAR_GP_PIN(3, 9), 16, 3 },
5876 { RCAR_GP_PIN(3, 10), 12, 3 },
5877 { RCAR_GP_PIN(3, 11), 8, 3 },
5878 { RCAR_GP_PIN(4, 0), 4, 3 },
5879 { RCAR_GP_PIN(4, 1), 0, 3 },
5880 } },
5881 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5882 { RCAR_GP_PIN(4, 2), 28, 3 },
5883 { RCAR_GP_PIN(4, 3), 24, 3 },
5884 { RCAR_GP_PIN(4, 4), 20, 3 },
5885 { RCAR_GP_PIN(4, 5), 16, 3 },
5886 { RCAR_GP_PIN(4, 6), 12, 3 },
5887 { RCAR_GP_PIN(4, 7), 8, 3 },
5888 { RCAR_GP_PIN(4, 8), 4, 3 },
5889 { RCAR_GP_PIN(4, 9), 0, 3 },
5890 } },
5891 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5892 { RCAR_GP_PIN(4, 10), 28, 3 },
5893 { RCAR_GP_PIN(4, 11), 24, 3 },
5894 { RCAR_GP_PIN(4, 12), 20, 3 },
5895 { RCAR_GP_PIN(4, 13), 16, 3 },
5896 { RCAR_GP_PIN(4, 14), 12, 3 },
5897 { RCAR_GP_PIN(4, 15), 8, 3 },
5898 { RCAR_GP_PIN(4, 16), 4, 3 },
5899 { RCAR_GP_PIN(4, 17), 0, 3 },
5900 } },
5901 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5902 { RCAR_GP_PIN(3, 12), 28, 3 },
5903 { RCAR_GP_PIN(3, 13), 24, 3 },
5904 { RCAR_GP_PIN(3, 14), 20, 3 },
5905 { RCAR_GP_PIN(3, 15), 16, 3 },
5906 { RCAR_GP_PIN(5, 0), 12, 3 },
5907 { RCAR_GP_PIN(5, 1), 8, 3 },
5908 { RCAR_GP_PIN(5, 2), 4, 3 },
5909 { RCAR_GP_PIN(5, 3), 0, 3 },
5910 } },
5911 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5912 { RCAR_GP_PIN(5, 4), 28, 3 },
5913 { RCAR_GP_PIN(5, 5), 24, 3 },
5914 { RCAR_GP_PIN(5, 6), 20, 3 },
5915 { RCAR_GP_PIN(5, 7), 16, 3 },
5916 { RCAR_GP_PIN(5, 8), 12, 3 },
5917 { RCAR_GP_PIN(5, 9), 8, 3 },
5918 { RCAR_GP_PIN(5, 10), 4, 3 },
5919 { RCAR_GP_PIN(5, 11), 0, 3 },
5920 } },
5921 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5922 { RCAR_GP_PIN(5, 12), 28, 3 },
5923 { RCAR_GP_PIN(5, 13), 24, 3 },
5924 { RCAR_GP_PIN(5, 14), 20, 3 },
5925 { RCAR_GP_PIN(5, 15), 16, 3 },
5926 { RCAR_GP_PIN(5, 16), 12, 3 },
5927 { RCAR_GP_PIN(5, 17), 8, 3 },
5928 { RCAR_GP_PIN(5, 18), 4, 3 },
5929 { RCAR_GP_PIN(5, 19), 0, 3 },
5930 } },
5931 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5932 { RCAR_GP_PIN(5, 20), 28, 3 },
5933 { RCAR_GP_PIN(5, 21), 24, 3 },
5934 { RCAR_GP_PIN(5, 22), 20, 3 },
5935 { RCAR_GP_PIN(5, 23), 16, 3 },
5936 { RCAR_GP_PIN(5, 24), 12, 3 },
5937 { RCAR_GP_PIN(5, 25), 8, 3 },
5938 { PIN_MLB_REF, 4, 3 },
5939 { RCAR_GP_PIN(6, 0), 0, 3 },
5940 } },
5941 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5942 { RCAR_GP_PIN(6, 1), 28, 3 },
5943 { RCAR_GP_PIN(6, 2), 24, 3 },
5944 { RCAR_GP_PIN(6, 3), 20, 3 },
5945 { RCAR_GP_PIN(6, 4), 16, 3 },
5946 { RCAR_GP_PIN(6, 5), 12, 3 },
5947 { RCAR_GP_PIN(6, 6), 8, 3 },
5948 { RCAR_GP_PIN(6, 7), 4, 3 },
5949 { RCAR_GP_PIN(6, 8), 0, 3 },
5950 } },
5951 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5952 { RCAR_GP_PIN(6, 9), 28, 3 },
5953 { RCAR_GP_PIN(6, 10), 24, 3 },
5954 { RCAR_GP_PIN(6, 11), 20, 3 },
5955 { RCAR_GP_PIN(6, 12), 16, 3 },
5956 { RCAR_GP_PIN(6, 13), 12, 3 },
5957 { RCAR_GP_PIN(6, 14), 8, 3 },
5958 { RCAR_GP_PIN(6, 15), 4, 3 },
5959 { RCAR_GP_PIN(6, 16), 0, 3 },
5960 } },
5961 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5962 { RCAR_GP_PIN(6, 17), 28, 3 },
5963 { RCAR_GP_PIN(6, 18), 24, 3 },
5964 { RCAR_GP_PIN(6, 19), 20, 3 },
5965 { RCAR_GP_PIN(6, 20), 16, 3 },
5966 { RCAR_GP_PIN(6, 21), 12, 3 },
5967 { RCAR_GP_PIN(6, 22), 8, 3 },
5968 { RCAR_GP_PIN(6, 23), 4, 3 },
5969 { RCAR_GP_PIN(6, 24), 0, 3 },
5970 } },
5971 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5972 { RCAR_GP_PIN(6, 25), 28, 3 },
5973 { RCAR_GP_PIN(6, 26), 24, 3 },
5974 { RCAR_GP_PIN(6, 27), 20, 3 },
5975 { RCAR_GP_PIN(6, 28), 16, 3 },
5976 { RCAR_GP_PIN(6, 29), 12, 3 },
5977 { RCAR_GP_PIN(6, 30), 8, 3 },
5978 { RCAR_GP_PIN(6, 31), 4, 3 },
5979 } },
5980 { },
5981};
5982
5983enum ioctrl_regs {
5984 POCCTRL,
5985 TDSELCTRL,
5986};
5987
5988static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5989 [POCCTRL] = { 0xe6060380, },
5990 [TDSELCTRL] = { 0xe60603c0, },
5991 { },
5992};
5993
5994static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
5995 unsigned int pin, u32 *pocctrl)
5996{
5997 int bit = -EINVAL;
5998
5999 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6000
6001 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6002 bit = pin & 0x1f;
6003
6004 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6005 bit = (pin & 0x1f) + 12;
6006
6007 return bit;
6008}
6009
6010static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6011 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6012 [ 0] = PIN_QSPI0_SPCLK,
6013 [ 1] = PIN_QSPI0_MOSI_IO0,
6014 [ 2] = PIN_QSPI0_MISO_IO1,
6015 [ 3] = PIN_QSPI0_IO2,
6016 [ 4] = PIN_QSPI0_IO3,
6017 [ 5] = PIN_QSPI0_SSL,
6018 [ 6] = PIN_QSPI1_SPCLK,
6019 [ 7] = PIN_QSPI1_MOSI_IO0,
6020 [ 8] = PIN_QSPI1_MISO_IO1,
6021 [ 9] = PIN_QSPI1_IO2,
6022 [10] = PIN_QSPI1_IO3,
6023 [11] = PIN_QSPI1_SSL,
6024 [12] = PIN_RPC_INT_N,
6025 [13] = PIN_RPC_WP_N,
6026 [14] = PIN_RPC_RESET_N,
6027 [15] = PIN_AVB_RX_CTL,
6028 [16] = PIN_AVB_RXC,
6029 [17] = PIN_AVB_RD0,
6030 [18] = PIN_AVB_RD1,
6031 [19] = PIN_AVB_RD2,
6032 [20] = PIN_AVB_RD3,
6033 [21] = PIN_AVB_TX_CTL,
6034 [22] = PIN_AVB_TXC,
6035 [23] = PIN_AVB_TD0,
6036 [24] = PIN_AVB_TD1,
6037 [25] = PIN_AVB_TD2,
6038 [26] = PIN_AVB_TD3,
6039 [27] = PIN_AVB_TXCREFCLK,
6040 [28] = PIN_AVB_MDIO,
6041 [29] = RCAR_GP_PIN(2, 9),
6042 [30] = RCAR_GP_PIN(2, 10),
6043 [31] = RCAR_GP_PIN(2, 11),
6044 } },
6045 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6046 [ 0] = RCAR_GP_PIN(2, 12),
6047 [ 1] = RCAR_GP_PIN(2, 13),
6048 [ 2] = RCAR_GP_PIN(2, 14),
6049 [ 3] = RCAR_GP_PIN(2, 0),
6050 [ 4] = RCAR_GP_PIN(2, 1),
6051 [ 5] = RCAR_GP_PIN(2, 2),
6052 [ 6] = RCAR_GP_PIN(2, 3),
6053 [ 7] = RCAR_GP_PIN(2, 4),
6054 [ 8] = RCAR_GP_PIN(2, 5),
6055 [ 9] = RCAR_GP_PIN(2, 6),
6056 [10] = RCAR_GP_PIN(2, 7),
6057 [11] = RCAR_GP_PIN(2, 8),
6058 [12] = RCAR_GP_PIN(1, 0),
6059 [13] = RCAR_GP_PIN(1, 1),
6060 [14] = RCAR_GP_PIN(1, 2),
6061 [15] = RCAR_GP_PIN(1, 3),
6062 [16] = RCAR_GP_PIN(1, 4),
6063 [17] = RCAR_GP_PIN(1, 5),
6064 [18] = RCAR_GP_PIN(1, 6),
6065 [19] = RCAR_GP_PIN(1, 7),
6066 [20] = RCAR_GP_PIN(1, 8),
6067 [21] = RCAR_GP_PIN(1, 9),
6068 [22] = RCAR_GP_PIN(1, 10),
6069 [23] = RCAR_GP_PIN(1, 11),
6070 [24] = RCAR_GP_PIN(1, 12),
6071 [25] = RCAR_GP_PIN(1, 13),
6072 [26] = RCAR_GP_PIN(1, 14),
6073 [27] = RCAR_GP_PIN(1, 15),
6074 [28] = RCAR_GP_PIN(1, 16),
6075 [29] = RCAR_GP_PIN(1, 17),
6076 [30] = RCAR_GP_PIN(1, 18),
6077 [31] = RCAR_GP_PIN(1, 19),
6078 } },
6079 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6080 [ 0] = RCAR_GP_PIN(1, 28),
6081 [ 1] = RCAR_GP_PIN(1, 20),
6082 [ 2] = RCAR_GP_PIN(1, 21),
6083 [ 3] = RCAR_GP_PIN(1, 22),
6084 [ 4] = RCAR_GP_PIN(1, 23),
6085 [ 5] = RCAR_GP_PIN(1, 24),
6086 [ 6] = RCAR_GP_PIN(1, 25),
6087 [ 7] = RCAR_GP_PIN(1, 26),
6088 [ 8] = RCAR_GP_PIN(1, 27),
6089 [ 9] = PIN_PRESETOUT_N,
6090 [10] = RCAR_GP_PIN(0, 0),
6091 [11] = RCAR_GP_PIN(0, 1),
6092 [12] = RCAR_GP_PIN(0, 2),
6093 [13] = RCAR_GP_PIN(0, 3),
6094 [14] = RCAR_GP_PIN(0, 4),
6095 [15] = RCAR_GP_PIN(0, 5),
6096 [16] = RCAR_GP_PIN(0, 6),
6097 [17] = RCAR_GP_PIN(0, 7),
6098 [18] = RCAR_GP_PIN(0, 8),
6099 [19] = RCAR_GP_PIN(0, 9),
6100 [20] = RCAR_GP_PIN(0, 10),
6101 [21] = RCAR_GP_PIN(0, 11),
6102 [22] = RCAR_GP_PIN(0, 12),
6103 [23] = RCAR_GP_PIN(0, 13),
6104 [24] = RCAR_GP_PIN(0, 14),
6105 [25] = RCAR_GP_PIN(0, 15),
6106 [26] = RCAR_GP_PIN(7, 0),
6107 [27] = RCAR_GP_PIN(7, 1),
6108 [28] = RCAR_GP_PIN(7, 2),
6109 [29] = RCAR_GP_PIN(7, 3),
6110 [30] = PIN_DU_DOTCLKIN0,
6111 [31] = PIN_DU_DOTCLKIN1,
6112 } },
6113 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6114 [ 0] = PIN_DU_DOTCLKIN2,
6115 [ 1] = SH_PFC_PIN_NONE,
6116 [ 2] = PIN_FSCLKST,
6117 [ 3] = PIN_EXTALR,
6118 [ 4] = PIN_TRST_N,
6119 [ 5] = PIN_TCK,
6120 [ 6] = PIN_TMS,
6121 [ 7] = PIN_TDI,
6122 [ 8] = SH_PFC_PIN_NONE,
6123 [ 9] = PIN_ASEBRK,
6124 [10] = RCAR_GP_PIN(3, 0),
6125 [11] = RCAR_GP_PIN(3, 1),
6126 [12] = RCAR_GP_PIN(3, 2),
6127 [13] = RCAR_GP_PIN(3, 3),
6128 [14] = RCAR_GP_PIN(3, 4),
6129 [15] = RCAR_GP_PIN(3, 5),
6130 [16] = RCAR_GP_PIN(3, 6),
6131 [17] = RCAR_GP_PIN(3, 7),
6132 [18] = RCAR_GP_PIN(3, 8),
6133 [19] = RCAR_GP_PIN(3, 9),
6134 [20] = RCAR_GP_PIN(3, 10),
6135 [21] = RCAR_GP_PIN(3, 11),
6136 [22] = RCAR_GP_PIN(4, 0),
6137 [23] = RCAR_GP_PIN(4, 1),
6138 [24] = RCAR_GP_PIN(4, 2),
6139 [25] = RCAR_GP_PIN(4, 3),
6140 [26] = RCAR_GP_PIN(4, 4),
6141 [27] = RCAR_GP_PIN(4, 5),
6142 [28] = RCAR_GP_PIN(4, 6),
6143 [29] = RCAR_GP_PIN(4, 7),
6144 [30] = RCAR_GP_PIN(4, 8),
6145 [31] = RCAR_GP_PIN(4, 9),
6146 } },
6147 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6148 [ 0] = RCAR_GP_PIN(4, 10),
6149 [ 1] = RCAR_GP_PIN(4, 11),
6150 [ 2] = RCAR_GP_PIN(4, 12),
6151 [ 3] = RCAR_GP_PIN(4, 13),
6152 [ 4] = RCAR_GP_PIN(4, 14),
6153 [ 5] = RCAR_GP_PIN(4, 15),
6154 [ 6] = RCAR_GP_PIN(4, 16),
6155 [ 7] = RCAR_GP_PIN(4, 17),
6156 [ 8] = RCAR_GP_PIN(3, 12),
6157 [ 9] = RCAR_GP_PIN(3, 13),
6158 [10] = RCAR_GP_PIN(3, 14),
6159 [11] = RCAR_GP_PIN(3, 15),
6160 [12] = RCAR_GP_PIN(5, 0),
6161 [13] = RCAR_GP_PIN(5, 1),
6162 [14] = RCAR_GP_PIN(5, 2),
6163 [15] = RCAR_GP_PIN(5, 3),
6164 [16] = RCAR_GP_PIN(5, 4),
6165 [17] = RCAR_GP_PIN(5, 5),
6166 [18] = RCAR_GP_PIN(5, 6),
6167 [19] = RCAR_GP_PIN(5, 7),
6168 [20] = RCAR_GP_PIN(5, 8),
6169 [21] = RCAR_GP_PIN(5, 9),
6170 [22] = RCAR_GP_PIN(5, 10),
6171 [23] = RCAR_GP_PIN(5, 11),
6172 [24] = RCAR_GP_PIN(5, 12),
6173 [25] = RCAR_GP_PIN(5, 13),
6174 [26] = RCAR_GP_PIN(5, 14),
6175 [27] = RCAR_GP_PIN(5, 15),
6176 [28] = RCAR_GP_PIN(5, 16),
6177 [29] = RCAR_GP_PIN(5, 17),
6178 [30] = RCAR_GP_PIN(5, 18),
6179 [31] = RCAR_GP_PIN(5, 19),
6180 } },
6181 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6182 [ 0] = RCAR_GP_PIN(5, 20),
6183 [ 1] = RCAR_GP_PIN(5, 21),
6184 [ 2] = RCAR_GP_PIN(5, 22),
6185 [ 3] = RCAR_GP_PIN(5, 23),
6186 [ 4] = RCAR_GP_PIN(5, 24),
6187 [ 5] = RCAR_GP_PIN(5, 25),
6188 [ 6] = PIN_MLB_REF,
6189 [ 7] = RCAR_GP_PIN(6, 0),
6190 [ 8] = RCAR_GP_PIN(6, 1),
6191 [ 9] = RCAR_GP_PIN(6, 2),
6192 [10] = RCAR_GP_PIN(6, 3),
6193 [11] = RCAR_GP_PIN(6, 4),
6194 [12] = RCAR_GP_PIN(6, 5),
6195 [13] = RCAR_GP_PIN(6, 6),
6196 [14] = RCAR_GP_PIN(6, 7),
6197 [15] = RCAR_GP_PIN(6, 8),
6198 [16] = RCAR_GP_PIN(6, 9),
6199 [17] = RCAR_GP_PIN(6, 10),
6200 [18] = RCAR_GP_PIN(6, 11),
6201 [19] = RCAR_GP_PIN(6, 12),
6202 [20] = RCAR_GP_PIN(6, 13),
6203 [21] = RCAR_GP_PIN(6, 14),
6204 [22] = RCAR_GP_PIN(6, 15),
6205 [23] = RCAR_GP_PIN(6, 16),
6206 [24] = RCAR_GP_PIN(6, 17),
6207 [25] = RCAR_GP_PIN(6, 18),
6208 [26] = RCAR_GP_PIN(6, 19),
6209 [27] = RCAR_GP_PIN(6, 20),
6210 [28] = RCAR_GP_PIN(6, 21),
6211 [29] = RCAR_GP_PIN(6, 22),
6212 [30] = RCAR_GP_PIN(6, 23),
6213 [31] = RCAR_GP_PIN(6, 24),
6214 } },
6215 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6216 [ 0] = RCAR_GP_PIN(6, 25),
6217 [ 1] = RCAR_GP_PIN(6, 26),
6218 [ 2] = RCAR_GP_PIN(6, 27),
6219 [ 3] = RCAR_GP_PIN(6, 28),
6220 [ 4] = RCAR_GP_PIN(6, 29),
6221 [ 5] = RCAR_GP_PIN(6, 30),
6222 [ 6] = RCAR_GP_PIN(6, 31),
6223 [ 7] = PIN_PRESET_N,
6224 [ 8] = SH_PFC_PIN_NONE,
6225 [ 9] = SH_PFC_PIN_NONE,
6226 [10] = SH_PFC_PIN_NONE,
6227 [11] = SH_PFC_PIN_NONE,
6228 [12] = SH_PFC_PIN_NONE,
6229 [13] = SH_PFC_PIN_NONE,
6230 [14] = SH_PFC_PIN_NONE,
6231 [15] = SH_PFC_PIN_NONE,
6232 [16] = SH_PFC_PIN_NONE,
6233 [17] = SH_PFC_PIN_NONE,
6234 [18] = SH_PFC_PIN_NONE,
6235 [19] = SH_PFC_PIN_NONE,
6236 [20] = SH_PFC_PIN_NONE,
6237 [21] = SH_PFC_PIN_NONE,
6238 [22] = SH_PFC_PIN_NONE,
6239 [23] = SH_PFC_PIN_NONE,
6240 [24] = SH_PFC_PIN_NONE,
6241 [25] = SH_PFC_PIN_NONE,
6242 [26] = SH_PFC_PIN_NONE,
6243 [27] = SH_PFC_PIN_NONE,
6244 [28] = SH_PFC_PIN_NONE,
6245 [29] = SH_PFC_PIN_NONE,
6246 [30] = SH_PFC_PIN_NONE,
6247 [31] = SH_PFC_PIN_NONE,
6248 } },
6249 { },
6250};
6251
6252static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6253 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6254 .get_bias = rcar_pinmux_get_bias,
6255 .set_bias = rcar_pinmux_set_bias,
6256};
6257
6258#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6259const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6260 .name = "r8a774a1_pfc",
6261 .ops = &r8a7796_pinmux_ops,
6262 .unlock_reg = 0xe6060000,
6263
6264 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6265
6266 .pins = pinmux_pins,
6267 .nr_pins = ARRAY_SIZE(pinmux_pins),
6268 .groups = pinmux_groups.common,
6269 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6270 .functions = pinmux_functions.common,
6271 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6272
6273 .cfg_regs = pinmux_config_regs,
6274 .drive_regs = pinmux_drive_regs,
6275 .bias_regs = pinmux_bias_regs,
6276 .ioctrl_regs = pinmux_ioctrl_regs,
6277
6278 .pinmux_data = pinmux_data,
6279 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6280};
6281#endif
6282
6283#ifdef CONFIG_PINCTRL_PFC_R8A77960
6284const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6285 .name = "r8a77960_pfc",
6286 .ops = &r8a7796_pinmux_ops,
6287 .unlock_reg = 0xe6060000,
6288
6289 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6290
6291 .pins = pinmux_pins,
6292 .nr_pins = ARRAY_SIZE(pinmux_pins),
6293 .groups = pinmux_groups.common,
6294 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6295 ARRAY_SIZE(pinmux_groups.automotive),
6296 .functions = pinmux_functions.common,
6297 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6298 ARRAY_SIZE(pinmux_functions.automotive),
6299
6300 .cfg_regs = pinmux_config_regs,
6301 .drive_regs = pinmux_drive_regs,
6302 .bias_regs = pinmux_bias_regs,
6303 .ioctrl_regs = pinmux_ioctrl_regs,
6304
6305 .pinmux_data = pinmux_data,
6306 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6307};
6308#endif
6309
6310#ifdef CONFIG_PINCTRL_PFC_R8A77961
6311const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6312 .name = "r8a77961_pfc",
6313 .ops = &r8a7796_pinmux_ops,
6314 .unlock_reg = 0xe6060000,
6315
6316 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6317
6318 .pins = pinmux_pins,
6319 .nr_pins = ARRAY_SIZE(pinmux_pins),
6320 .groups = pinmux_groups.common,
6321 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6322 ARRAY_SIZE(pinmux_groups.automotive),
6323 .functions = pinmux_functions.common,
6324 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6325 ARRAY_SIZE(pinmux_functions.automotive),
6326
6327 .cfg_regs = pinmux_config_regs,
6328 .drive_regs = pinmux_drive_regs,
6329 .bias_regs = pinmux_bias_regs,
6330 .ioctrl_regs = pinmux_ioctrl_regs,
6331
6332 .pinmux_data = pinmux_data,
6333 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6334};
6335#endif
6336
