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15#include <linux/errno.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18
19#include "sh_pfc.h"
20
21#define CPU_ALL_GP(fn, sfx) \
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28
29#define CPU_ALL_NOGP(fn) \
30 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
31 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
32 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
35 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
36 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
37 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
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43
44
45#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
46#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
47#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
48#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
49#define GPSR0_17 F_(DU_DB7, IP2_7_4)
50#define GPSR0_16 F_(DU_DB6, IP2_3_0)
51#define GPSR0_15 F_(DU_DB5, IP1_31_28)
52#define GPSR0_14 F_(DU_DB4, IP1_27_24)
53#define GPSR0_13 F_(DU_DB3, IP1_23_20)
54#define GPSR0_12 F_(DU_DB2, IP1_19_16)
55#define GPSR0_11 F_(DU_DG7, IP1_15_12)
56#define GPSR0_10 F_(DU_DG6, IP1_11_8)
57#define GPSR0_9 F_(DU_DG5, IP1_7_4)
58#define GPSR0_8 F_(DU_DG4, IP1_3_0)
59#define GPSR0_7 F_(DU_DG3, IP0_31_28)
60#define GPSR0_6 F_(DU_DG2, IP0_27_24)
61#define GPSR0_5 F_(DU_DR7, IP0_23_20)
62#define GPSR0_4 F_(DU_DR6, IP0_19_16)
63#define GPSR0_3 F_(DU_DR5, IP0_15_12)
64#define GPSR0_2 F_(DU_DR4, IP0_11_8)
65#define GPSR0_1 F_(DU_DR3, IP0_7_4)
66#define GPSR0_0 F_(DU_DR2, IP0_3_0)
67
68
69#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
70#define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
71#define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
72#define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
73#define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
74#define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
75#define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
76#define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
77#define GPSR1_19 FM(AVB0_AVTP_MATCH)
78#define GPSR1_18 FM(AVB0_LINK)
79#define GPSR1_17 FM(AVB0_PHY_INT)
80#define GPSR1_16 FM(AVB0_MAGIC)
81#define GPSR1_15 FM(AVB0_MDC)
82#define GPSR1_14 FM(AVB0_MDIO)
83#define GPSR1_13 FM(AVB0_TXCREFCLK)
84#define GPSR1_12 FM(AVB0_TD3)
85#define GPSR1_11 FM(AVB0_TD2)
86#define GPSR1_10 FM(AVB0_TD1)
87#define GPSR1_9 FM(AVB0_TD0)
88#define GPSR1_8 FM(AVB0_TXC)
89#define GPSR1_7 FM(AVB0_TX_CTL)
90#define GPSR1_6 FM(AVB0_RD3)
91#define GPSR1_5 FM(AVB0_RD2)
92#define GPSR1_4 FM(AVB0_RD1)
93#define GPSR1_3 FM(AVB0_RD0)
94#define GPSR1_2 FM(AVB0_RXC)
95#define GPSR1_1 FM(AVB0_RX_CTL)
96#define GPSR1_0 F_(IRQ0, IP2_27_24)
97
98
99#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
100#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
101#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
102#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
103#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
104#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
105#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
106#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
107#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
108#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
109#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
110#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
111#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
112#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
113#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
114#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
115#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
116
117
118#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
119#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
120#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
121#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
122#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
123#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
124#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
125#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
126#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
127#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
128#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
129#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
130#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
131#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
132#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
133#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
134#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
135
136
137#define GPSR4_5 F_(SDA2, IP7_27_24)
138#define GPSR4_4 F_(SCL2, IP7_23_20)
139#define GPSR4_3 F_(SDA1, IP7_19_16)
140#define GPSR4_2 F_(SCL1, IP7_15_12)
141#define GPSR4_1 F_(SDA0, IP7_11_8)
142#define GPSR4_0 F_(SCL0, IP7_7_4)
143
144
145#define GPSR5_14 FM(RPC_INT_N)
146#define GPSR5_13 FM(RPC_WP_N)
147#define GPSR5_12 FM(RPC_RESET_N)
148#define GPSR5_11 FM(QSPI1_SSL)
149#define GPSR5_10 FM(QSPI1_IO3)
150#define GPSR5_9 FM(QSPI1_IO2)
151#define GPSR5_8 FM(QSPI1_MISO_IO1)
152#define GPSR5_7 FM(QSPI1_MOSI_IO0)
153#define GPSR5_6 FM(QSPI1_SPCLK)
154#define GPSR5_5 FM(QSPI0_SSL)
155#define GPSR5_4 FM(QSPI0_IO3)
156#define GPSR5_3 FM(QSPI0_IO2)
157#define GPSR5_2 FM(QSPI0_MISO_IO1)
158#define GPSR5_1 FM(QSPI0_MOSI_IO0)
159#define GPSR5_0 FM(QSPI0_SPCLK)
160
161
162
163#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235
236#define PINMUX_GPSR \
237\
238 GPSR1_27 \
239 GPSR1_26 \
240 GPSR1_25 \
241 GPSR1_24 \
242 GPSR1_23 \
243 GPSR1_22 \
244GPSR0_21 GPSR1_21 \
245GPSR0_20 GPSR1_20 \
246GPSR0_19 GPSR1_19 \
247GPSR0_18 GPSR1_18 \
248GPSR0_17 GPSR1_17 \
249GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
250GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
251GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
252GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
253GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
254GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
255GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
256GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
257GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
258GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
259GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
260GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
261GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
262GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
263GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
264GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
265GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
266
267#define PINMUX_IPSR \
268\
269FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
270FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
271FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
272FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
273FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
274FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
275FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
276FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
277\
278FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
279FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
280FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
281FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
282FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
283FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
284FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
285FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
286\
287FM(IP8_3_0) IP8_3_0 \
288FM(IP8_7_4) IP8_7_4 \
289FM(IP8_11_8) IP8_11_8 \
290FM(IP8_15_12) IP8_15_12 \
291FM(IP8_19_16) IP8_19_16 \
292FM(IP8_23_20) IP8_23_20 \
293FM(IP8_27_24) IP8_27_24 \
294FM(IP8_31_28) IP8_31_28
295
296
297#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
298#define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
299#define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
300#define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
301#define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
302#define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
303#define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
304#define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
305#define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
306#define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
307#define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
308#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
309
310#define PINMUX_MOD_SELS \
311\
312MOD_SEL0_11 \
313MOD_SEL0_10 \
314MOD_SEL0_9 \
315MOD_SEL0_8 \
316MOD_SEL0_7 \
317MOD_SEL0_6 \
318MOD_SEL0_5 \
319MOD_SEL0_4 \
320MOD_SEL0_3 \
321MOD_SEL0_2 \
322MOD_SEL0_1 \
323MOD_SEL0_0
324
325enum {
326 PINMUX_RESERVED = 0,
327
328 PINMUX_DATA_BEGIN,
329 GP_ALL(DATA),
330 PINMUX_DATA_END,
331
332#define F_(x, y)
333#define FM(x) FN_##x,
334 PINMUX_FUNCTION_BEGIN,
335 GP_ALL(FN),
336 PINMUX_GPSR
337 PINMUX_IPSR
338 PINMUX_MOD_SELS
339 PINMUX_FUNCTION_END,
340#undef F_
341#undef FM
342
343#define F_(x, y)
344#define FM(x) x##_MARK,
345 PINMUX_MARK_BEGIN,
346 PINMUX_GPSR
347 PINMUX_IPSR
348 PINMUX_MOD_SELS
349 PINMUX_MARK_END,
350#undef F_
351#undef FM
352};
353
354static const u16 pinmux_data[] = {
355 PINMUX_DATA_GP_ALL(),
356
357 PINMUX_SINGLE(AVB0_RX_CTL),
358 PINMUX_SINGLE(AVB0_RXC),
359 PINMUX_SINGLE(AVB0_RD0),
360 PINMUX_SINGLE(AVB0_RD1),
361 PINMUX_SINGLE(AVB0_RD2),
362 PINMUX_SINGLE(AVB0_RD3),
363 PINMUX_SINGLE(AVB0_TX_CTL),
364 PINMUX_SINGLE(AVB0_TXC),
365 PINMUX_SINGLE(AVB0_TD0),
366 PINMUX_SINGLE(AVB0_TD1),
367 PINMUX_SINGLE(AVB0_TD2),
368 PINMUX_SINGLE(AVB0_TD3),
369 PINMUX_SINGLE(AVB0_TXCREFCLK),
370 PINMUX_SINGLE(AVB0_MDIO),
371 PINMUX_SINGLE(AVB0_MDC),
372 PINMUX_SINGLE(AVB0_MAGIC),
373 PINMUX_SINGLE(AVB0_PHY_INT),
374 PINMUX_SINGLE(AVB0_LINK),
375 PINMUX_SINGLE(AVB0_AVTP_MATCH),
376
377 PINMUX_SINGLE(QSPI0_SPCLK),
378 PINMUX_SINGLE(QSPI0_MOSI_IO0),
379 PINMUX_SINGLE(QSPI0_MISO_IO1),
380 PINMUX_SINGLE(QSPI0_IO2),
381 PINMUX_SINGLE(QSPI0_IO3),
382 PINMUX_SINGLE(QSPI0_SSL),
383 PINMUX_SINGLE(QSPI1_SPCLK),
384 PINMUX_SINGLE(QSPI1_MOSI_IO0),
385 PINMUX_SINGLE(QSPI1_MISO_IO1),
386 PINMUX_SINGLE(QSPI1_IO2),
387 PINMUX_SINGLE(QSPI1_IO3),
388 PINMUX_SINGLE(QSPI1_SSL),
389 PINMUX_SINGLE(RPC_RESET_N),
390 PINMUX_SINGLE(RPC_WP_N),
391 PINMUX_SINGLE(RPC_INT_N),
392
393
394 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
395 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
396 PINMUX_IPSR_GPSR(IP0_3_0, A0),
397
398 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
399 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
400 PINMUX_IPSR_GPSR(IP0_7_4, A1),
401
402 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
403 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
404 PINMUX_IPSR_GPSR(IP0_11_8, A2),
405
406 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
407 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
408 PINMUX_IPSR_GPSR(IP0_15_12, A3),
409
410 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
411 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
412 PINMUX_IPSR_GPSR(IP0_19_16, A4),
413
414 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
415 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
416 PINMUX_IPSR_GPSR(IP0_23_20, A5),
417
418 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
419 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
420 PINMUX_IPSR_GPSR(IP0_27_24, A6),
421
422 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
423 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
424 PINMUX_IPSR_GPSR(IP0_31_28, A7),
425 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
426
427
428 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
429 PINMUX_IPSR_GPSR(IP1_3_0, A8),
430 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
431
432 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
433 PINMUX_IPSR_GPSR(IP1_7_4, A9),
434 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
435
436 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
437 PINMUX_IPSR_GPSR(IP1_11_8, A10),
438 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
439
440 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
441 PINMUX_IPSR_GPSR(IP1_15_12, A11),
442 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
443
444 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
445 PINMUX_IPSR_GPSR(IP1_19_16, A12),
446 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
447
448 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
449 PINMUX_IPSR_GPSR(IP1_23_20, A13),
450 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
451
452 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
453 PINMUX_IPSR_GPSR(IP1_27_24, A14),
454 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
455
456 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
457 PINMUX_IPSR_GPSR(IP1_31_28, A15),
458 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
459
460
461 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
462 PINMUX_IPSR_GPSR(IP2_3_0, A16),
463 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
464
465 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
466 PINMUX_IPSR_GPSR(IP2_7_4, A17),
467
468 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
469 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
470 PINMUX_IPSR_GPSR(IP2_11_8, A18),
471
472 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
473 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
474 PINMUX_IPSR_GPSR(IP2_15_12, A19),
475 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
476
477 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
478 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
479
480 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
481 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
482
483 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
484
485 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
486 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
487 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
488 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
489
490
491 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
492 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
493 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
494 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
495 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
496
497 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
498 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
499 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
500 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
501
502 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
503 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
504 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
505 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
506
507 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
508 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
509 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
510 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
511
512 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
513 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
514 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
515 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
516
517 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
518 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
519 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
520
521 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
522 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
523 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
524
525 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
526 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
527 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
528
529
530 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
531 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
532 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
533
534 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
535 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
536 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
537
538 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
539 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
540 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
541
542 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
543 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
544 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
545
546 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
547 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
548 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
549 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
550
551 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
552 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
553 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
554 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
555
556 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
557 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
558 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
559 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
560
561 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
562 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
563 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
564 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
565 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
566
567
568 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
569 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
570 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
571
572 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
573 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
574 PINMUX_IPSR_GPSR(IP5_7_4, D0),
575
576 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
577 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
578 PINMUX_IPSR_GPSR(IP5_11_8, D1),
579
580 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
581 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
582 PINMUX_IPSR_GPSR(IP5_15_12, D2),
583
584 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
585 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
586 PINMUX_IPSR_GPSR(IP5_19_16, D3),
587
588 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
589 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
590 PINMUX_IPSR_GPSR(IP5_23_20, D4),
591 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
592
593 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
594 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
595 PINMUX_IPSR_GPSR(IP5_27_24, D5),
596 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
597
598 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
599 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
600 PINMUX_IPSR_GPSR(IP5_31_28, D6),
601 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
602
603
604 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
605 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
606 PINMUX_IPSR_GPSR(IP6_3_0, D7),
607 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
608
609 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
610 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
611 PINMUX_IPSR_GPSR(IP6_7_4, D8),
612 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
613
614 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
615 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
616 PINMUX_IPSR_GPSR(IP6_11_8, D9),
617 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
618
619 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
620 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
621 PINMUX_IPSR_GPSR(IP6_15_12, D10),
622 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
623
624 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
625 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
626 PINMUX_IPSR_GPSR(IP6_19_16, D11),
627 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
628
629 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
630 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
631 PINMUX_IPSR_GPSR(IP6_23_20, D12),
632 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
633 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
634
635 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
636 PINMUX_IPSR_GPSR(IP6_27_24, D13),
637 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
638 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
639
640 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
641 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
642 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
643 PINMUX_IPSR_GPSR(IP6_31_28, D14),
644
645
646 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
647 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
648 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
649 PINMUX_IPSR_GPSR(IP7_3_0, D15),
650
651 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
652 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
653 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
654 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
655 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
656
657 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
658 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
659 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
660 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
661 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
662 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
663
664 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
665 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
666 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
667 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
668 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
669 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
670
671 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
672 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
673 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
674 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
675 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
676 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
677
678 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
679 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
680 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
681 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
682 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
683 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
684
685 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
686 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
687 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
688 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
689 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
690 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
691
692 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
693 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
694
695
696 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
697 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
698 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
699 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
700 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
701
702 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
703 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
704 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
705 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
706
707 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
708 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
709 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
710 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
711 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
712
713 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
714 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
715 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
716 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
717 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
718
719 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
720 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
721 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
722 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
723 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
724
725 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
726 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
727
728 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
729 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
730};
731
732
733
734
735enum {
736 GP_ASSIGN_LAST(),
737 NOGP_ALL(),
738};
739
740static const struct sh_pfc_pin pinmux_pins[] = {
741 PINMUX_GPIO_GP_ALL(),
742 PINMUX_NOGP_ALL(),
743};
744
745
746static const unsigned int avb0_link_pins[] = {
747
748 RCAR_GP_PIN(1, 18),
749};
750static const unsigned int avb0_link_mux[] = {
751 AVB0_LINK_MARK,
752};
753static const unsigned int avb0_magic_pins[] = {
754
755 RCAR_GP_PIN(1, 16),
756};
757static const unsigned int avb0_magic_mux[] = {
758 AVB0_MAGIC_MARK,
759};
760static const unsigned int avb0_phy_int_pins[] = {
761
762 RCAR_GP_PIN(1, 17),
763};
764static const unsigned int avb0_phy_int_mux[] = {
765 AVB0_PHY_INT_MARK,
766};
767static const unsigned int avb0_mdio_pins[] = {
768
769 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
770};
771static const unsigned int avb0_mdio_mux[] = {
772 AVB0_MDC_MARK, AVB0_MDIO_MARK,
773};
774static const unsigned int avb0_rgmii_pins[] = {
775
776
777
778
779 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
780 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
781 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
782 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
783 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
784 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
785};
786static const unsigned int avb0_rgmii_mux[] = {
787 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
788 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
789 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
790 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
791};
792static const unsigned int avb0_txcrefclk_pins[] = {
793
794 RCAR_GP_PIN(1, 13),
795};
796static const unsigned int avb0_txcrefclk_mux[] = {
797 AVB0_TXCREFCLK_MARK,
798};
799static const unsigned int avb0_avtp_pps_pins[] = {
800
801 RCAR_GP_PIN(2, 6),
802};
803static const unsigned int avb0_avtp_pps_mux[] = {
804 AVB0_AVTP_PPS_MARK,
805};
806static const unsigned int avb0_avtp_capture_pins[] = {
807
808 RCAR_GP_PIN(1, 20),
809};
810static const unsigned int avb0_avtp_capture_mux[] = {
811 AVB0_AVTP_CAPTURE_MARK,
812};
813static const unsigned int avb0_avtp_match_pins[] = {
814
815 RCAR_GP_PIN(1, 19),
816};
817static const unsigned int avb0_avtp_match_mux[] = {
818 AVB0_AVTP_MATCH_MARK,
819};
820
821
822static const unsigned int canfd_clk_a_pins[] = {
823
824 RCAR_GP_PIN(1, 25),
825};
826static const unsigned int canfd_clk_a_mux[] = {
827 CANFD_CLK_A_MARK,
828};
829static const unsigned int canfd_clk_b_pins[] = {
830
831 RCAR_GP_PIN(3, 8),
832};
833static const unsigned int canfd_clk_b_mux[] = {
834 CANFD_CLK_B_MARK,
835};
836
837
838static const unsigned int canfd0_data_a_pins[] = {
839
840 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
841};
842static const unsigned int canfd0_data_a_mux[] = {
843 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
844};
845static const unsigned int canfd0_data_b_pins[] = {
846
847 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
848};
849static const unsigned int canfd0_data_b_mux[] = {
850 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
851};
852
853
854static const unsigned int canfd1_data_pins[] = {
855
856 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
857};
858static const unsigned int canfd1_data_mux[] = {
859 CANFD1_TX_MARK, CANFD1_RX_MARK,
860};
861
862
863static const unsigned int du_rgb666_pins[] = {
864
865 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
866 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
867 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
868 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
869 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
870 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
871};
872static const unsigned int du_rgb666_mux[] = {
873 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
874 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
875 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
876 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
877 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
878 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
879};
880static const unsigned int du_clk_out_pins[] = {
881
882 RCAR_GP_PIN(0, 18),
883};
884static const unsigned int du_clk_out_mux[] = {
885 DU_DOTCLKOUT_MARK,
886};
887static const unsigned int du_sync_pins[] = {
888
889 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
890};
891static const unsigned int du_sync_mux[] = {
892 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
893};
894static const unsigned int du_oddf_pins[] = {
895
896 RCAR_GP_PIN(0, 21),
897};
898static const unsigned int du_oddf_mux[] = {
899 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
900};
901static const unsigned int du_cde_pins[] = {
902
903 RCAR_GP_PIN(1, 22),
904};
905static const unsigned int du_cde_mux[] = {
906 DU_CDE_MARK,
907};
908static const unsigned int du_disp_pins[] = {
909
910 RCAR_GP_PIN(1, 21),
911};
912static const unsigned int du_disp_mux[] = {
913 DU_DISP_MARK,
914};
915
916
917static const unsigned int hscif0_data_pins[] = {
918
919 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
920};
921static const unsigned int hscif0_data_mux[] = {
922 HRX0_MARK, HTX0_MARK,
923};
924static const unsigned int hscif0_clk_pins[] = {
925
926 RCAR_GP_PIN(0, 0),
927};
928static const unsigned int hscif0_clk_mux[] = {
929 HSCK0_MARK,
930};
931static const unsigned int hscif0_ctrl_pins[] = {
932
933 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
934};
935static const unsigned int hscif0_ctrl_mux[] = {
936 HRTS0_N_MARK, HCTS0_N_MARK,
937};
938
939
940static const unsigned int hscif1_data_pins[] = {
941
942 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
943};
944static const unsigned int hscif1_data_mux[] = {
945 HRX1_MARK, HTX1_MARK,
946};
947static const unsigned int hscif1_clk_pins[] = {
948
949 RCAR_GP_PIN(2, 7),
950};
951static const unsigned int hscif1_clk_mux[] = {
952 HSCK1_MARK,
953};
954static const unsigned int hscif1_ctrl_pins[] = {
955
956 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
957};
958static const unsigned int hscif1_ctrl_mux[] = {
959 HRTS1_N_MARK, HCTS1_N_MARK,
960};
961
962
963static const unsigned int hscif2_data_pins[] = {
964
965 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
966};
967static const unsigned int hscif2_data_mux[] = {
968 HRX2_MARK, HTX2_MARK,
969};
970static const unsigned int hscif2_clk_pins[] = {
971
972 RCAR_GP_PIN(2, 12),
973};
974static const unsigned int hscif2_clk_mux[] = {
975 HSCK2_MARK,
976};
977static const unsigned int hscif2_ctrl_pins[] = {
978
979 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
980};
981static const unsigned int hscif2_ctrl_mux[] = {
982 HRTS2_N_MARK, HCTS2_N_MARK,
983};
984
985
986static const unsigned int hscif3_data_pins[] = {
987
988 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
989};
990static const unsigned int hscif3_data_mux[] = {
991 HRX3_MARK, HTX3_MARK,
992};
993static const unsigned int hscif3_clk_pins[] = {
994
995 RCAR_GP_PIN(2, 0),
996};
997static const unsigned int hscif3_clk_mux[] = {
998 HSCK3_MARK,
999};
1000static const unsigned int hscif3_ctrl_pins[] = {
1001
1002 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1003};
1004static const unsigned int hscif3_ctrl_mux[] = {
1005 HRTS3_N_MARK, HCTS3_N_MARK,
1006};
1007
1008
1009static const unsigned int i2c0_pins[] = {
1010
1011 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1012};
1013static const unsigned int i2c0_mux[] = {
1014 SDA0_MARK, SCL0_MARK,
1015};
1016
1017
1018static const unsigned int i2c1_pins[] = {
1019
1020 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1021};
1022static const unsigned int i2c1_mux[] = {
1023 SDA1_MARK, SCL1_MARK,
1024};
1025
1026
1027static const unsigned int i2c2_pins[] = {
1028
1029 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1030};
1031static const unsigned int i2c2_mux[] = {
1032 SDA2_MARK, SCL2_MARK,
1033};
1034
1035
1036static const unsigned int i2c3_a_pins[] = {
1037
1038 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1039};
1040static const unsigned int i2c3_a_mux[] = {
1041 SDA3_A_MARK, SCL3_A_MARK,
1042};
1043static const unsigned int i2c3_b_pins[] = {
1044
1045 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1046};
1047static const unsigned int i2c3_b_mux[] = {
1048 SDA3_B_MARK, SCL3_B_MARK,
1049};
1050
1051
1052static const unsigned int i2c4_pins[] = {
1053
1054 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1055};
1056static const unsigned int i2c4_mux[] = {
1057 SDA4_MARK, SCL4_MARK,
1058};
1059
1060
1061static const unsigned int intc_ex_irq0_pins[] = {
1062
1063 RCAR_GP_PIN(1, 0),
1064};
1065static const unsigned int intc_ex_irq0_mux[] = {
1066 IRQ0_MARK,
1067};
1068static const unsigned int intc_ex_irq1_pins[] = {
1069
1070 RCAR_GP_PIN(0, 11),
1071};
1072static const unsigned int intc_ex_irq1_mux[] = {
1073 IRQ1_MARK,
1074};
1075static const unsigned int intc_ex_irq2_pins[] = {
1076
1077 RCAR_GP_PIN(0, 12),
1078};
1079static const unsigned int intc_ex_irq2_mux[] = {
1080 IRQ2_MARK,
1081};
1082static const unsigned int intc_ex_irq3_pins[] = {
1083
1084 RCAR_GP_PIN(0, 19),
1085};
1086static const unsigned int intc_ex_irq3_mux[] = {
1087 IRQ3_MARK,
1088};
1089static const unsigned int intc_ex_irq4_pins[] = {
1090
1091 RCAR_GP_PIN(3, 15),
1092};
1093static const unsigned int intc_ex_irq4_mux[] = {
1094 IRQ4_MARK,
1095};
1096static const unsigned int intc_ex_irq5_pins[] = {
1097
1098 RCAR_GP_PIN(3, 16),
1099};
1100static const unsigned int intc_ex_irq5_mux[] = {
1101 IRQ5_MARK,
1102};
1103
1104
1105static const unsigned int mmc_data1_pins[] = {
1106
1107 RCAR_GP_PIN(3, 6),
1108};
1109static const unsigned int mmc_data1_mux[] = {
1110 MMC_D0_MARK,
1111};
1112static const unsigned int mmc_data4_pins[] = {
1113
1114 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1115 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1116};
1117static const unsigned int mmc_data4_mux[] = {
1118 MMC_D0_MARK, MMC_D1_MARK,
1119 MMC_D2_MARK, MMC_D3_MARK,
1120};
1121static const unsigned int mmc_data8_pins[] = {
1122
1123 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1124 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1125 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1126 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1127};
1128static const unsigned int mmc_data8_mux[] = {
1129 MMC_D0_MARK, MMC_D1_MARK,
1130 MMC_D2_MARK, MMC_D3_MARK,
1131 MMC_D4_MARK, MMC_D5_MARK,
1132 MMC_D6_MARK, MMC_D7_MARK,
1133};
1134static const unsigned int mmc_ctrl_pins[] = {
1135
1136 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1137};
1138static const unsigned int mmc_ctrl_mux[] = {
1139 MMC_CLK_MARK, MMC_CMD_MARK,
1140};
1141
1142
1143static const unsigned int msiof0_clk_pins[] = {
1144
1145 RCAR_GP_PIN(4, 2),
1146};
1147static const unsigned int msiof0_clk_mux[] = {
1148 MSIOF0_SCK_MARK,
1149};
1150static const unsigned int msiof0_sync_pins[] = {
1151
1152 RCAR_GP_PIN(4, 3),
1153};
1154static const unsigned int msiof0_sync_mux[] = {
1155 MSIOF0_SYNC_MARK,
1156};
1157static const unsigned int msiof0_ss1_pins[] = {
1158
1159 RCAR_GP_PIN(4, 4),
1160};
1161static const unsigned int msiof0_ss1_mux[] = {
1162 MSIOF0_SS1_MARK,
1163};
1164static const unsigned int msiof0_ss2_pins[] = {
1165
1166 RCAR_GP_PIN(4, 5),
1167};
1168static const unsigned int msiof0_ss2_mux[] = {
1169 MSIOF0_SS2_MARK,
1170};
1171static const unsigned int msiof0_txd_pins[] = {
1172
1173 RCAR_GP_PIN(4, 1),
1174};
1175static const unsigned int msiof0_txd_mux[] = {
1176 MSIOF0_TXD_MARK,
1177};
1178static const unsigned int msiof0_rxd_pins[] = {
1179
1180 RCAR_GP_PIN(4, 0),
1181};
1182static const unsigned int msiof0_rxd_mux[] = {
1183 MSIOF0_RXD_MARK,
1184};
1185
1186
1187static const unsigned int msiof1_clk_pins[] = {
1188
1189 RCAR_GP_PIN(3, 2),
1190};
1191static const unsigned int msiof1_clk_mux[] = {
1192 MSIOF1_SCK_MARK,
1193};
1194static const unsigned int msiof1_sync_pins[] = {
1195
1196 RCAR_GP_PIN(3, 3),
1197};
1198static const unsigned int msiof1_sync_mux[] = {
1199 MSIOF1_SYNC_MARK,
1200};
1201static const unsigned int msiof1_ss1_pins[] = {
1202
1203 RCAR_GP_PIN(3, 4),
1204};
1205static const unsigned int msiof1_ss1_mux[] = {
1206 MSIOF1_SS1_MARK,
1207};
1208static const unsigned int msiof1_ss2_pins[] = {
1209
1210 RCAR_GP_PIN(3, 5),
1211};
1212static const unsigned int msiof1_ss2_mux[] = {
1213 MSIOF1_SS2_MARK,
1214};
1215static const unsigned int msiof1_txd_pins[] = {
1216
1217 RCAR_GP_PIN(3, 1),
1218};
1219static const unsigned int msiof1_txd_mux[] = {
1220 MSIOF1_TXD_MARK,
1221};
1222static const unsigned int msiof1_rxd_pins[] = {
1223
1224 RCAR_GP_PIN(3, 0),
1225};
1226static const unsigned int msiof1_rxd_mux[] = {
1227 MSIOF1_RXD_MARK,
1228};
1229
1230
1231static const unsigned int msiof2_clk_pins[] = {
1232
1233 RCAR_GP_PIN(2, 0),
1234};
1235static const unsigned int msiof2_clk_mux[] = {
1236 MSIOF2_SCK_MARK,
1237};
1238static const unsigned int msiof2_sync_pins[] = {
1239
1240 RCAR_GP_PIN(2, 3),
1241};
1242static const unsigned int msiof2_sync_mux[] = {
1243 MSIOF2_SYNC_MARK,
1244};
1245static const unsigned int msiof2_ss1_pins[] = {
1246
1247 RCAR_GP_PIN(2, 4),
1248};
1249static const unsigned int msiof2_ss1_mux[] = {
1250 MSIOF2_SS1_MARK,
1251};
1252static const unsigned int msiof2_ss2_pins[] = {
1253
1254 RCAR_GP_PIN(2, 5),
1255};
1256static const unsigned int msiof2_ss2_mux[] = {
1257 MSIOF2_SS2_MARK,
1258};
1259static const unsigned int msiof2_txd_pins[] = {
1260
1261 RCAR_GP_PIN(2, 2),
1262};
1263static const unsigned int msiof2_txd_mux[] = {
1264 MSIOF2_TXD_MARK,
1265};
1266static const unsigned int msiof2_rxd_pins[] = {
1267
1268 RCAR_GP_PIN(2, 1),
1269};
1270static const unsigned int msiof2_rxd_mux[] = {
1271 MSIOF2_RXD_MARK,
1272};
1273
1274
1275static const unsigned int msiof3_clk_pins[] = {
1276
1277 RCAR_GP_PIN(0, 20),
1278};
1279static const unsigned int msiof3_clk_mux[] = {
1280 MSIOF3_SCK_MARK,
1281};
1282static const unsigned int msiof3_sync_pins[] = {
1283
1284 RCAR_GP_PIN(0, 21),
1285};
1286static const unsigned int msiof3_sync_mux[] = {
1287 MSIOF3_SYNC_MARK,
1288};
1289static const unsigned int msiof3_ss1_pins[] = {
1290
1291 RCAR_GP_PIN(0, 6),
1292};
1293static const unsigned int msiof3_ss1_mux[] = {
1294 MSIOF3_SS1_MARK,
1295};
1296static const unsigned int msiof3_ss2_pins[] = {
1297
1298 RCAR_GP_PIN(0, 7),
1299};
1300static const unsigned int msiof3_ss2_mux[] = {
1301 MSIOF3_SS2_MARK,
1302};
1303static const unsigned int msiof3_txd_pins[] = {
1304
1305 RCAR_GP_PIN(0, 5),
1306};
1307static const unsigned int msiof3_txd_mux[] = {
1308 MSIOF3_TXD_MARK,
1309};
1310static const unsigned int msiof3_rxd_pins[] = {
1311
1312 RCAR_GP_PIN(0, 4),
1313};
1314static const unsigned int msiof3_rxd_mux[] = {
1315 MSIOF3_RXD_MARK,
1316};
1317
1318
1319static const unsigned int pwm0_a_pins[] = {
1320 RCAR_GP_PIN(2, 12),
1321};
1322static const unsigned int pwm0_a_mux[] = {
1323 PWM0_A_MARK,
1324};
1325static const unsigned int pwm0_b_pins[] = {
1326 RCAR_GP_PIN(1, 21),
1327};
1328static const unsigned int pwm0_b_mux[] = {
1329 PWM0_B_MARK,
1330};
1331
1332
1333static const unsigned int pwm1_a_pins[] = {
1334 RCAR_GP_PIN(2, 13),
1335};
1336static const unsigned int pwm1_a_mux[] = {
1337 PWM1_A_MARK,
1338};
1339static const unsigned int pwm1_b_pins[] = {
1340 RCAR_GP_PIN(1, 22),
1341};
1342static const unsigned int pwm1_b_mux[] = {
1343 PWM1_B_MARK,
1344};
1345
1346
1347static const unsigned int pwm2_a_pins[] = {
1348 RCAR_GP_PIN(2, 14),
1349};
1350static const unsigned int pwm2_a_mux[] = {
1351 PWM2_A_MARK,
1352};
1353static const unsigned int pwm2_b_pins[] = {
1354 RCAR_GP_PIN(1, 23),
1355};
1356static const unsigned int pwm2_b_mux[] = {
1357 PWM2_B_MARK,
1358};
1359
1360
1361static const unsigned int pwm3_a_pins[] = {
1362 RCAR_GP_PIN(2, 15),
1363};
1364static const unsigned int pwm3_a_mux[] = {
1365 PWM3_A_MARK,
1366};
1367static const unsigned int pwm3_b_pins[] = {
1368 RCAR_GP_PIN(1, 24),
1369};
1370static const unsigned int pwm3_b_mux[] = {
1371 PWM3_B_MARK,
1372};
1373
1374
1375static const unsigned int pwm4_a_pins[] = {
1376 RCAR_GP_PIN(2, 16),
1377};
1378static const unsigned int pwm4_a_mux[] = {
1379 PWM4_A_MARK,
1380};
1381static const unsigned int pwm4_b_pins[] = {
1382 RCAR_GP_PIN(1, 25),
1383};
1384static const unsigned int pwm4_b_mux[] = {
1385 PWM4_B_MARK,
1386};
1387
1388
1389static const unsigned int qspi0_ctrl_pins[] = {
1390
1391 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1392};
1393static const unsigned int qspi0_ctrl_mux[] = {
1394 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1395};
1396static const unsigned int qspi0_data2_pins[] = {
1397
1398 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1399};
1400static const unsigned int qspi0_data2_mux[] = {
1401 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1402};
1403static const unsigned int qspi0_data4_pins[] = {
1404
1405 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1406 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1407};
1408static const unsigned int qspi0_data4_mux[] = {
1409 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1410 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1411};
1412
1413
1414static const unsigned int qspi1_ctrl_pins[] = {
1415
1416 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1417};
1418static const unsigned int qspi1_ctrl_mux[] = {
1419 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1420};
1421static const unsigned int qspi1_data2_pins[] = {
1422
1423 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1424};
1425static const unsigned int qspi1_data2_mux[] = {
1426 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1427};
1428static const unsigned int qspi1_data4_pins[] = {
1429
1430 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1431 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1432};
1433static const unsigned int qspi1_data4_mux[] = {
1434 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1435 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1436};
1437
1438
1439static const unsigned int rpc_clk1_pins[] = {
1440
1441 RCAR_GP_PIN(5, 0),
1442};
1443static const unsigned int rpc_clk1_mux[] = {
1444 QSPI0_SPCLK_MARK,
1445};
1446static const unsigned int rpc_clk2_pins[] = {
1447
1448 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1449};
1450static const unsigned int rpc_clk2_mux[] = {
1451 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1452};
1453static const unsigned int rpc_ctrl_pins[] = {
1454
1455
1456 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1457};
1458static const unsigned int rpc_ctrl_mux[] = {
1459 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1460};
1461static const unsigned int rpc_data_pins[] = {
1462
1463 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1464 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1465 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1466 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1467};
1468static const unsigned int rpc_data_mux[] = {
1469 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1470 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1471 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1472 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1473};
1474static const unsigned int rpc_reset_pins[] = {
1475
1476 RCAR_GP_PIN(5, 12),
1477};
1478static const unsigned int rpc_reset_mux[] = {
1479 RPC_RESET_N_MARK,
1480};
1481static const unsigned int rpc_int_pins[] = {
1482
1483 RCAR_GP_PIN(5, 14),
1484};
1485static const unsigned int rpc_int_mux[] = {
1486 RPC_INT_N_MARK,
1487};
1488static const unsigned int rpc_wp_pins[] = {
1489
1490 RCAR_GP_PIN(5, 13),
1491};
1492static const unsigned int rpc_wp_mux[] = {
1493 RPC_WP_N_MARK,
1494};
1495
1496
1497static const unsigned int scif_clk_a_pins[] = {
1498
1499 RCAR_GP_PIN(0, 18),
1500};
1501static const unsigned int scif_clk_a_mux[] = {
1502 SCIF_CLK_A_MARK,
1503};
1504static const unsigned int scif_clk_b_pins[] = {
1505
1506 RCAR_GP_PIN(1, 25),
1507};
1508static const unsigned int scif_clk_b_mux[] = {
1509 SCIF_CLK_B_MARK,
1510};
1511
1512
1513static const unsigned int scif0_data_pins[] = {
1514
1515 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1516};
1517static const unsigned int scif0_data_mux[] = {
1518 RX0_MARK, TX0_MARK,
1519};
1520static const unsigned int scif0_clk_pins[] = {
1521
1522 RCAR_GP_PIN(4, 1),
1523};
1524static const unsigned int scif0_clk_mux[] = {
1525 SCK0_MARK,
1526};
1527static const unsigned int scif0_ctrl_pins[] = {
1528
1529 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1530};
1531static const unsigned int scif0_ctrl_mux[] = {
1532 RTS0_N_MARK, CTS0_N_MARK,
1533};
1534
1535
1536static const unsigned int scif1_data_a_pins[] = {
1537
1538 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1539};
1540static const unsigned int scif1_data_a_mux[] = {
1541 RX1_A_MARK, TX1_A_MARK,
1542};
1543static const unsigned int scif1_clk_pins[] = {
1544
1545 RCAR_GP_PIN(2, 5),
1546};
1547static const unsigned int scif1_clk_mux[] = {
1548 SCK1_MARK,
1549};
1550static const unsigned int scif1_ctrl_pins[] = {
1551
1552 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1553};
1554static const unsigned int scif1_ctrl_mux[] = {
1555 RTS1_N_MARK, CTS1_N_MARK,
1556};
1557static const unsigned int scif1_data_b_pins[] = {
1558
1559 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1560};
1561static const unsigned int scif1_data_b_mux[] = {
1562 RX1_B_MARK, TX1_B_MARK,
1563};
1564
1565
1566static const unsigned int scif3_data_pins[] = {
1567
1568 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1569};
1570static const unsigned int scif3_data_mux[] = {
1571 RX3_MARK, TX3_MARK,
1572};
1573static const unsigned int scif3_clk_pins[] = {
1574
1575 RCAR_GP_PIN(2, 0),
1576};
1577static const unsigned int scif3_clk_mux[] = {
1578 SCK3_MARK,
1579};
1580static const unsigned int scif3_ctrl_pins[] = {
1581
1582 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1583};
1584static const unsigned int scif3_ctrl_mux[] = {
1585 RTS3_N_MARK, CTS3_N_MARK,
1586};
1587
1588
1589static const unsigned int scif4_data_pins[] = {
1590
1591 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1592};
1593static const unsigned int scif4_data_mux[] = {
1594 RX4_MARK, TX4_MARK,
1595};
1596static const unsigned int scif4_clk_pins[] = {
1597
1598 RCAR_GP_PIN(3, 9),
1599};
1600static const unsigned int scif4_clk_mux[] = {
1601 SCK4_MARK,
1602};
1603static const unsigned int scif4_ctrl_pins[] = {
1604
1605 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1606};
1607static const unsigned int scif4_ctrl_mux[] = {
1608 RTS4_N_MARK, CTS4_N_MARK,
1609};
1610
1611
1612static const unsigned int tmu_tclk1_a_pins[] = {
1613
1614 RCAR_GP_PIN(4, 4),
1615};
1616static const unsigned int tmu_tclk1_a_mux[] = {
1617 TCLK1_A_MARK,
1618};
1619static const unsigned int tmu_tclk1_b_pins[] = {
1620
1621 RCAR_GP_PIN(1, 23),
1622};
1623static const unsigned int tmu_tclk1_b_mux[] = {
1624 TCLK1_B_MARK,
1625};
1626static const unsigned int tmu_tclk2_a_pins[] = {
1627
1628 RCAR_GP_PIN(4, 5),
1629};
1630static const unsigned int tmu_tclk2_a_mux[] = {
1631 TCLK2_A_MARK,
1632};
1633static const unsigned int tmu_tclk2_b_pins[] = {
1634
1635 RCAR_GP_PIN(1, 24),
1636};
1637static const unsigned int tmu_tclk2_b_mux[] = {
1638 TCLK2_B_MARK,
1639};
1640
1641
1642static const union vin_data12 vin0_data_pins = {
1643 .data12 = {
1644 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1645 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1646 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1647 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1648 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1649 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1650 },
1651};
1652static const union vin_data12 vin0_data_mux = {
1653 .data12 = {
1654 VI0_DATA0_MARK, VI0_DATA1_MARK,
1655 VI0_DATA2_MARK, VI0_DATA3_MARK,
1656 VI0_DATA4_MARK, VI0_DATA5_MARK,
1657 VI0_DATA6_MARK, VI0_DATA7_MARK,
1658 VI0_DATA8_MARK, VI0_DATA9_MARK,
1659 VI0_DATA10_MARK, VI0_DATA11_MARK,
1660 },
1661};
1662static const unsigned int vin0_sync_pins[] = {
1663
1664 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1665};
1666static const unsigned int vin0_sync_mux[] = {
1667 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1668};
1669static const unsigned int vin0_field_pins[] = {
1670
1671 RCAR_GP_PIN(2, 16),
1672};
1673static const unsigned int vin0_field_mux[] = {
1674 VI0_FIELD_MARK,
1675};
1676static const unsigned int vin0_clkenb_pins[] = {
1677
1678 RCAR_GP_PIN(2, 1),
1679};
1680static const unsigned int vin0_clkenb_mux[] = {
1681 VI0_CLKENB_MARK,
1682};
1683static const unsigned int vin0_clk_pins[] = {
1684
1685 RCAR_GP_PIN(2, 0),
1686};
1687static const unsigned int vin0_clk_mux[] = {
1688 VI0_CLK_MARK,
1689};
1690
1691
1692static const union vin_data12 vin1_data_pins = {
1693 .data12 = {
1694 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1695 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1696 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1697 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1698 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1699 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1700 },
1701};
1702static const union vin_data12 vin1_data_mux = {
1703 .data12 = {
1704 VI1_DATA0_MARK, VI1_DATA1_MARK,
1705 VI1_DATA2_MARK, VI1_DATA3_MARK,
1706 VI1_DATA4_MARK, VI1_DATA5_MARK,
1707 VI1_DATA6_MARK, VI1_DATA7_MARK,
1708 VI1_DATA8_MARK, VI1_DATA9_MARK,
1709 VI1_DATA10_MARK, VI1_DATA11_MARK,
1710 },
1711};
1712static const unsigned int vin1_sync_pins[] = {
1713
1714 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1715};
1716static const unsigned int vin1_sync_mux[] = {
1717 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1718};
1719static const unsigned int vin1_field_pins[] = {
1720 RCAR_GP_PIN(3, 16),
1721};
1722static const unsigned int vin1_field_mux[] = {
1723
1724 VI1_FIELD_MARK,
1725};
1726static const unsigned int vin1_clkenb_pins[] = {
1727 RCAR_GP_PIN(3, 1),
1728};
1729static const unsigned int vin1_clkenb_mux[] = {
1730
1731 VI1_CLKENB_MARK,
1732};
1733static const unsigned int vin1_clk_pins[] = {
1734 RCAR_GP_PIN(3, 0),
1735};
1736static const unsigned int vin1_clk_mux[] = {
1737
1738 VI1_CLK_MARK,
1739};
1740
1741static const struct sh_pfc_pin_group pinmux_groups[] = {
1742 SH_PFC_PIN_GROUP(avb0_link),
1743 SH_PFC_PIN_GROUP(avb0_magic),
1744 SH_PFC_PIN_GROUP(avb0_phy_int),
1745 SH_PFC_PIN_GROUP(avb0_mdio),
1746 SH_PFC_PIN_GROUP(avb0_rgmii),
1747 SH_PFC_PIN_GROUP(avb0_txcrefclk),
1748 SH_PFC_PIN_GROUP(avb0_avtp_pps),
1749 SH_PFC_PIN_GROUP(avb0_avtp_capture),
1750 SH_PFC_PIN_GROUP(avb0_avtp_match),
1751 SH_PFC_PIN_GROUP(canfd_clk_a),
1752 SH_PFC_PIN_GROUP(canfd_clk_b),
1753 SH_PFC_PIN_GROUP(canfd0_data_a),
1754 SH_PFC_PIN_GROUP(canfd0_data_b),
1755 SH_PFC_PIN_GROUP(canfd1_data),
1756 SH_PFC_PIN_GROUP(du_rgb666),
1757 SH_PFC_PIN_GROUP(du_clk_out),
1758 SH_PFC_PIN_GROUP(du_sync),
1759 SH_PFC_PIN_GROUP(du_oddf),
1760 SH_PFC_PIN_GROUP(du_cde),
1761 SH_PFC_PIN_GROUP(du_disp),
1762 SH_PFC_PIN_GROUP(hscif0_data),
1763 SH_PFC_PIN_GROUP(hscif0_clk),
1764 SH_PFC_PIN_GROUP(hscif0_ctrl),
1765 SH_PFC_PIN_GROUP(hscif1_data),
1766 SH_PFC_PIN_GROUP(hscif1_clk),
1767 SH_PFC_PIN_GROUP(hscif1_ctrl),
1768 SH_PFC_PIN_GROUP(hscif2_data),
1769 SH_PFC_PIN_GROUP(hscif2_clk),
1770 SH_PFC_PIN_GROUP(hscif2_ctrl),
1771 SH_PFC_PIN_GROUP(hscif3_data),
1772 SH_PFC_PIN_GROUP(hscif3_clk),
1773 SH_PFC_PIN_GROUP(hscif3_ctrl),
1774 SH_PFC_PIN_GROUP(i2c0),
1775 SH_PFC_PIN_GROUP(i2c1),
1776 SH_PFC_PIN_GROUP(i2c2),
1777 SH_PFC_PIN_GROUP(i2c3_a),
1778 SH_PFC_PIN_GROUP(i2c3_b),
1779 SH_PFC_PIN_GROUP(i2c4),
1780 SH_PFC_PIN_GROUP(intc_ex_irq0),
1781 SH_PFC_PIN_GROUP(intc_ex_irq1),
1782 SH_PFC_PIN_GROUP(intc_ex_irq2),
1783 SH_PFC_PIN_GROUP(intc_ex_irq3),
1784 SH_PFC_PIN_GROUP(intc_ex_irq4),
1785 SH_PFC_PIN_GROUP(intc_ex_irq5),
1786 SH_PFC_PIN_GROUP(mmc_data1),
1787 SH_PFC_PIN_GROUP(mmc_data4),
1788 SH_PFC_PIN_GROUP(mmc_data8),
1789 SH_PFC_PIN_GROUP(mmc_ctrl),
1790 SH_PFC_PIN_GROUP(msiof0_clk),
1791 SH_PFC_PIN_GROUP(msiof0_sync),
1792 SH_PFC_PIN_GROUP(msiof0_ss1),
1793 SH_PFC_PIN_GROUP(msiof0_ss2),
1794 SH_PFC_PIN_GROUP(msiof0_txd),
1795 SH_PFC_PIN_GROUP(msiof0_rxd),
1796 SH_PFC_PIN_GROUP(msiof1_clk),
1797 SH_PFC_PIN_GROUP(msiof1_sync),
1798 SH_PFC_PIN_GROUP(msiof1_ss1),
1799 SH_PFC_PIN_GROUP(msiof1_ss2),
1800 SH_PFC_PIN_GROUP(msiof1_txd),
1801 SH_PFC_PIN_GROUP(msiof1_rxd),
1802 SH_PFC_PIN_GROUP(msiof2_clk),
1803 SH_PFC_PIN_GROUP(msiof2_sync),
1804 SH_PFC_PIN_GROUP(msiof2_ss1),
1805 SH_PFC_PIN_GROUP(msiof2_ss2),
1806 SH_PFC_PIN_GROUP(msiof2_txd),
1807 SH_PFC_PIN_GROUP(msiof2_rxd),
1808 SH_PFC_PIN_GROUP(msiof3_clk),
1809 SH_PFC_PIN_GROUP(msiof3_sync),
1810 SH_PFC_PIN_GROUP(msiof3_ss1),
1811 SH_PFC_PIN_GROUP(msiof3_ss2),
1812 SH_PFC_PIN_GROUP(msiof3_txd),
1813 SH_PFC_PIN_GROUP(msiof3_rxd),
1814 SH_PFC_PIN_GROUP(pwm0_a),
1815 SH_PFC_PIN_GROUP(pwm0_b),
1816 SH_PFC_PIN_GROUP(pwm1_a),
1817 SH_PFC_PIN_GROUP(pwm1_b),
1818 SH_PFC_PIN_GROUP(pwm2_a),
1819 SH_PFC_PIN_GROUP(pwm2_b),
1820 SH_PFC_PIN_GROUP(pwm3_a),
1821 SH_PFC_PIN_GROUP(pwm3_b),
1822 SH_PFC_PIN_GROUP(pwm4_a),
1823 SH_PFC_PIN_GROUP(pwm4_b),
1824 SH_PFC_PIN_GROUP(qspi0_ctrl),
1825 SH_PFC_PIN_GROUP(qspi0_data2),
1826 SH_PFC_PIN_GROUP(qspi0_data4),
1827 SH_PFC_PIN_GROUP(qspi1_ctrl),
1828 SH_PFC_PIN_GROUP(qspi1_data2),
1829 SH_PFC_PIN_GROUP(qspi1_data4),
1830 SH_PFC_PIN_GROUP(rpc_clk1),
1831 SH_PFC_PIN_GROUP(rpc_clk2),
1832 SH_PFC_PIN_GROUP(rpc_ctrl),
1833 SH_PFC_PIN_GROUP(rpc_data),
1834 SH_PFC_PIN_GROUP(rpc_reset),
1835 SH_PFC_PIN_GROUP(rpc_int),
1836 SH_PFC_PIN_GROUP(rpc_wp),
1837 SH_PFC_PIN_GROUP(scif_clk_a),
1838 SH_PFC_PIN_GROUP(scif_clk_b),
1839 SH_PFC_PIN_GROUP(scif0_data),
1840 SH_PFC_PIN_GROUP(scif0_clk),
1841 SH_PFC_PIN_GROUP(scif0_ctrl),
1842 SH_PFC_PIN_GROUP(scif1_data_a),
1843 SH_PFC_PIN_GROUP(scif1_clk),
1844 SH_PFC_PIN_GROUP(scif1_ctrl),
1845 SH_PFC_PIN_GROUP(scif1_data_b),
1846 SH_PFC_PIN_GROUP(scif3_data),
1847 SH_PFC_PIN_GROUP(scif3_clk),
1848 SH_PFC_PIN_GROUP(scif3_ctrl),
1849 SH_PFC_PIN_GROUP(scif4_data),
1850 SH_PFC_PIN_GROUP(scif4_clk),
1851 SH_PFC_PIN_GROUP(scif4_ctrl),
1852 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1853 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1854 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1855 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1856 VIN_DATA_PIN_GROUP(vin0_data, 8),
1857 VIN_DATA_PIN_GROUP(vin0_data, 10),
1858 VIN_DATA_PIN_GROUP(vin0_data, 12),
1859 SH_PFC_PIN_GROUP(vin0_sync),
1860 SH_PFC_PIN_GROUP(vin0_field),
1861 SH_PFC_PIN_GROUP(vin0_clkenb),
1862 SH_PFC_PIN_GROUP(vin0_clk),
1863 VIN_DATA_PIN_GROUP(vin1_data, 8),
1864 VIN_DATA_PIN_GROUP(vin1_data, 10),
1865 VIN_DATA_PIN_GROUP(vin1_data, 12),
1866 SH_PFC_PIN_GROUP(vin1_sync),
1867 SH_PFC_PIN_GROUP(vin1_field),
1868 SH_PFC_PIN_GROUP(vin1_clkenb),
1869 SH_PFC_PIN_GROUP(vin1_clk),
1870};
1871
1872static const char * const avb0_groups[] = {
1873 "avb0_link",
1874 "avb0_magic",
1875 "avb0_phy_int",
1876 "avb0_mdio",
1877 "avb0_rgmii",
1878 "avb0_txcrefclk",
1879 "avb0_avtp_pps",
1880 "avb0_avtp_capture",
1881 "avb0_avtp_match",
1882};
1883
1884static const char * const canfd_clk_groups[] = {
1885 "canfd_clk_a",
1886 "canfd_clk_b",
1887};
1888
1889static const char * const canfd0_groups[] = {
1890 "canfd0_data_a",
1891 "canfd0_data_b",
1892};
1893
1894static const char * const canfd1_groups[] = {
1895 "canfd1_data",
1896};
1897
1898static const char * const du_groups[] = {
1899 "du_rgb666",
1900 "du_clk_out",
1901 "du_sync",
1902 "du_oddf",
1903 "du_cde",
1904 "du_disp",
1905};
1906
1907static const char * const hscif0_groups[] = {
1908 "hscif0_data",
1909 "hscif0_clk",
1910 "hscif0_ctrl",
1911};
1912
1913static const char * const hscif1_groups[] = {
1914 "hscif1_data",
1915 "hscif1_clk",
1916 "hscif1_ctrl",
1917};
1918
1919static const char * const hscif2_groups[] = {
1920 "hscif2_data",
1921 "hscif2_clk",
1922 "hscif2_ctrl",
1923};
1924
1925static const char * const hscif3_groups[] = {
1926 "hscif3_data",
1927 "hscif3_clk",
1928 "hscif3_ctrl",
1929};
1930
1931static const char * const i2c0_groups[] = {
1932 "i2c0",
1933};
1934
1935static const char * const i2c1_groups[] = {
1936 "i2c1",
1937};
1938
1939static const char * const i2c2_groups[] = {
1940 "i2c2",
1941};
1942
1943static const char * const i2c3_groups[] = {
1944 "i2c3_a",
1945 "i2c3_b",
1946};
1947
1948static const char * const i2c4_groups[] = {
1949 "i2c4",
1950};
1951
1952static const char * const intc_ex_groups[] = {
1953 "intc_ex_irq0",
1954 "intc_ex_irq1",
1955 "intc_ex_irq2",
1956 "intc_ex_irq3",
1957 "intc_ex_irq4",
1958 "intc_ex_irq5",
1959};
1960
1961static const char * const mmc_groups[] = {
1962 "mmc_data1",
1963 "mmc_data4",
1964 "mmc_data8",
1965 "mmc_ctrl",
1966};
1967
1968static const char * const msiof0_groups[] = {
1969 "msiof0_clk",
1970 "msiof0_sync",
1971 "msiof0_ss1",
1972 "msiof0_ss2",
1973 "msiof0_txd",
1974 "msiof0_rxd",
1975};
1976
1977static const char * const msiof1_groups[] = {
1978 "msiof1_clk",
1979 "msiof1_sync",
1980 "msiof1_ss1",
1981 "msiof1_ss2",
1982 "msiof1_txd",
1983 "msiof1_rxd",
1984};
1985
1986static const char * const msiof2_groups[] = {
1987 "msiof2_clk",
1988 "msiof2_sync",
1989 "msiof2_ss1",
1990 "msiof2_ss2",
1991 "msiof2_txd",
1992 "msiof2_rxd",
1993};
1994
1995static const char * const msiof3_groups[] = {
1996 "msiof3_clk",
1997 "msiof3_sync",
1998 "msiof3_ss1",
1999 "msiof3_ss2",
2000 "msiof3_txd",
2001 "msiof3_rxd",
2002};
2003
2004static const char * const pwm0_groups[] = {
2005 "pwm0_a",
2006 "pwm0_b",
2007};
2008
2009static const char * const pwm1_groups[] = {
2010 "pwm1_a",
2011 "pwm1_b",
2012};
2013
2014static const char * const pwm2_groups[] = {
2015 "pwm2_a",
2016 "pwm2_b",
2017};
2018
2019static const char * const pwm3_groups[] = {
2020 "pwm3_a",
2021 "pwm3_b",
2022};
2023
2024static const char * const pwm4_groups[] = {
2025 "pwm4_a",
2026 "pwm4_b",
2027};
2028
2029static const char * const qspi0_groups[] = {
2030 "qspi0_ctrl",
2031 "qspi0_data2",
2032 "qspi0_data4",
2033};
2034
2035static const char * const qspi1_groups[] = {
2036 "qspi1_ctrl",
2037 "qspi1_data2",
2038 "qspi1_data4",
2039};
2040
2041static const char * const rpc_groups[] = {
2042 "rpc_clk1",
2043 "rpc_clk2",
2044 "rpc_ctrl",
2045 "rpc_data",
2046 "rpc_reset",
2047 "rpc_int",
2048 "rpc_wp",
2049};
2050
2051static const char * const scif_clk_groups[] = {
2052 "scif_clk_a",
2053 "scif_clk_b",
2054};
2055
2056static const char * const scif0_groups[] = {
2057 "scif0_data",
2058 "scif0_clk",
2059 "scif0_ctrl",
2060};
2061
2062static const char * const scif1_groups[] = {
2063 "scif1_data_a",
2064 "scif1_clk",
2065 "scif1_ctrl",
2066 "scif1_data_b",
2067};
2068
2069static const char * const scif3_groups[] = {
2070 "scif3_data",
2071 "scif3_clk",
2072 "scif3_ctrl",
2073};
2074
2075static const char * const scif4_groups[] = {
2076 "scif4_data",
2077 "scif4_clk",
2078 "scif4_ctrl",
2079};
2080
2081static const char * const tmu_groups[] = {
2082 "tmu_tclk1_a",
2083 "tmu_tclk1_b",
2084 "tmu_tclk2_a",
2085 "tmu_tclk2_b",
2086};
2087
2088static const char * const vin0_groups[] = {
2089 "vin0_data8",
2090 "vin0_data10",
2091 "vin0_data12",
2092 "vin0_sync",
2093 "vin0_field",
2094 "vin0_clkenb",
2095 "vin0_clk",
2096};
2097
2098static const char * const vin1_groups[] = {
2099 "vin1_data8",
2100 "vin1_data10",
2101 "vin1_data12",
2102 "vin1_sync",
2103 "vin1_field",
2104 "vin1_clkenb",
2105 "vin1_clk",
2106};
2107
2108static const struct sh_pfc_function pinmux_functions[] = {
2109 SH_PFC_FUNCTION(avb0),
2110 SH_PFC_FUNCTION(canfd_clk),
2111 SH_PFC_FUNCTION(canfd0),
2112 SH_PFC_FUNCTION(canfd1),
2113 SH_PFC_FUNCTION(du),
2114 SH_PFC_FUNCTION(hscif0),
2115 SH_PFC_FUNCTION(hscif1),
2116 SH_PFC_FUNCTION(hscif2),
2117 SH_PFC_FUNCTION(hscif3),
2118 SH_PFC_FUNCTION(i2c0),
2119 SH_PFC_FUNCTION(i2c1),
2120 SH_PFC_FUNCTION(i2c2),
2121 SH_PFC_FUNCTION(i2c3),
2122 SH_PFC_FUNCTION(i2c4),
2123 SH_PFC_FUNCTION(intc_ex),
2124 SH_PFC_FUNCTION(mmc),
2125 SH_PFC_FUNCTION(msiof0),
2126 SH_PFC_FUNCTION(msiof1),
2127 SH_PFC_FUNCTION(msiof2),
2128 SH_PFC_FUNCTION(msiof3),
2129 SH_PFC_FUNCTION(pwm0),
2130 SH_PFC_FUNCTION(pwm1),
2131 SH_PFC_FUNCTION(pwm2),
2132 SH_PFC_FUNCTION(pwm3),
2133 SH_PFC_FUNCTION(pwm4),
2134 SH_PFC_FUNCTION(qspi0),
2135 SH_PFC_FUNCTION(qspi1),
2136 SH_PFC_FUNCTION(rpc),
2137 SH_PFC_FUNCTION(scif_clk),
2138 SH_PFC_FUNCTION(scif0),
2139 SH_PFC_FUNCTION(scif1),
2140 SH_PFC_FUNCTION(scif3),
2141 SH_PFC_FUNCTION(scif4),
2142 SH_PFC_FUNCTION(tmu),
2143 SH_PFC_FUNCTION(vin0),
2144 SH_PFC_FUNCTION(vin1),
2145};
2146
2147static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2148#define F_(x, y) FN_##y
2149#define FM(x) FN_##x
2150 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2151 0, 0,
2152 0, 0,
2153 0, 0,
2154 0, 0,
2155 0, 0,
2156 0, 0,
2157 0, 0,
2158 0, 0,
2159 0, 0,
2160 0, 0,
2161 GP_0_21_FN, GPSR0_21,
2162 GP_0_20_FN, GPSR0_20,
2163 GP_0_19_FN, GPSR0_19,
2164 GP_0_18_FN, GPSR0_18,
2165 GP_0_17_FN, GPSR0_17,
2166 GP_0_16_FN, GPSR0_16,
2167 GP_0_15_FN, GPSR0_15,
2168 GP_0_14_FN, GPSR0_14,
2169 GP_0_13_FN, GPSR0_13,
2170 GP_0_12_FN, GPSR0_12,
2171 GP_0_11_FN, GPSR0_11,
2172 GP_0_10_FN, GPSR0_10,
2173 GP_0_9_FN, GPSR0_9,
2174 GP_0_8_FN, GPSR0_8,
2175 GP_0_7_FN, GPSR0_7,
2176 GP_0_6_FN, GPSR0_6,
2177 GP_0_5_FN, GPSR0_5,
2178 GP_0_4_FN, GPSR0_4,
2179 GP_0_3_FN, GPSR0_3,
2180 GP_0_2_FN, GPSR0_2,
2181 GP_0_1_FN, GPSR0_1,
2182 GP_0_0_FN, GPSR0_0, ))
2183 },
2184 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2185 0, 0,
2186 0, 0,
2187 0, 0,
2188 0, 0,
2189 GP_1_27_FN, GPSR1_27,
2190 GP_1_26_FN, GPSR1_26,
2191 GP_1_25_FN, GPSR1_25,
2192 GP_1_24_FN, GPSR1_24,
2193 GP_1_23_FN, GPSR1_23,
2194 GP_1_22_FN, GPSR1_22,
2195 GP_1_21_FN, GPSR1_21,
2196 GP_1_20_FN, GPSR1_20,
2197 GP_1_19_FN, GPSR1_19,
2198 GP_1_18_FN, GPSR1_18,
2199 GP_1_17_FN, GPSR1_17,
2200 GP_1_16_FN, GPSR1_16,
2201 GP_1_15_FN, GPSR1_15,
2202 GP_1_14_FN, GPSR1_14,
2203 GP_1_13_FN, GPSR1_13,
2204 GP_1_12_FN, GPSR1_12,
2205 GP_1_11_FN, GPSR1_11,
2206 GP_1_10_FN, GPSR1_10,
2207 GP_1_9_FN, GPSR1_9,
2208 GP_1_8_FN, GPSR1_8,
2209 GP_1_7_FN, GPSR1_7,
2210 GP_1_6_FN, GPSR1_6,
2211 GP_1_5_FN, GPSR1_5,
2212 GP_1_4_FN, GPSR1_4,
2213 GP_1_3_FN, GPSR1_3,
2214 GP_1_2_FN, GPSR1_2,
2215 GP_1_1_FN, GPSR1_1,
2216 GP_1_0_FN, GPSR1_0, ))
2217 },
2218 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2219 0, 0,
2220 0, 0,
2221 0, 0,
2222 0, 0,
2223 0, 0,
2224 0, 0,
2225 0, 0,
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 GP_2_16_FN, GPSR2_16,
2235 GP_2_15_FN, GPSR2_15,
2236 GP_2_14_FN, GPSR2_14,
2237 GP_2_13_FN, GPSR2_13,
2238 GP_2_12_FN, GPSR2_12,
2239 GP_2_11_FN, GPSR2_11,
2240 GP_2_10_FN, GPSR2_10,
2241 GP_2_9_FN, GPSR2_9,
2242 GP_2_8_FN, GPSR2_8,
2243 GP_2_7_FN, GPSR2_7,
2244 GP_2_6_FN, GPSR2_6,
2245 GP_2_5_FN, GPSR2_5,
2246 GP_2_4_FN, GPSR2_4,
2247 GP_2_3_FN, GPSR2_3,
2248 GP_2_2_FN, GPSR2_2,
2249 GP_2_1_FN, GPSR2_1,
2250 GP_2_0_FN, GPSR2_0, ))
2251 },
2252 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2253 0, 0,
2254 0, 0,
2255 0, 0,
2256 0, 0,
2257 0, 0,
2258 0, 0,
2259 0, 0,
2260 0, 0,
2261 0, 0,
2262 0, 0,
2263 0, 0,
2264 0, 0,
2265 0, 0,
2266 0, 0,
2267 0, 0,
2268 GP_3_16_FN, GPSR3_16,
2269 GP_3_15_FN, GPSR3_15,
2270 GP_3_14_FN, GPSR3_14,
2271 GP_3_13_FN, GPSR3_13,
2272 GP_3_12_FN, GPSR3_12,
2273 GP_3_11_FN, GPSR3_11,
2274 GP_3_10_FN, GPSR3_10,
2275 GP_3_9_FN, GPSR3_9,
2276 GP_3_8_FN, GPSR3_8,
2277 GP_3_7_FN, GPSR3_7,
2278 GP_3_6_FN, GPSR3_6,
2279 GP_3_5_FN, GPSR3_5,
2280 GP_3_4_FN, GPSR3_4,
2281 GP_3_3_FN, GPSR3_3,
2282 GP_3_2_FN, GPSR3_2,
2283 GP_3_1_FN, GPSR3_1,
2284 GP_3_0_FN, GPSR3_0, ))
2285 },
2286 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 0, 0,
2292 0, 0,
2293 0, 0,
2294 0, 0,
2295 0, 0,
2296 0, 0,
2297 0, 0,
2298 0, 0,
2299 0, 0,
2300 0, 0,
2301 0, 0,
2302 0, 0,
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 0, 0,
2312 0, 0,
2313 GP_4_5_FN, GPSR4_5,
2314 GP_4_4_FN, GPSR4_4,
2315 GP_4_3_FN, GPSR4_3,
2316 GP_4_2_FN, GPSR4_2,
2317 GP_4_1_FN, GPSR4_1,
2318 GP_4_0_FN, GPSR4_0, ))
2319 },
2320 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2321 0, 0,
2322 0, 0,
2323 0, 0,
2324 0, 0,
2325 0, 0,
2326 0, 0,
2327 0, 0,
2328 0, 0,
2329 0, 0,
2330 0, 0,
2331 0, 0,
2332 0, 0,
2333 0, 0,
2334 0, 0,
2335 0, 0,
2336 0, 0,
2337 0, 0,
2338 GP_5_14_FN, GPSR5_14,
2339 GP_5_13_FN, GPSR5_13,
2340 GP_5_12_FN, GPSR5_12,
2341 GP_5_11_FN, GPSR5_11,
2342 GP_5_10_FN, GPSR5_10,
2343 GP_5_9_FN, GPSR5_9,
2344 GP_5_8_FN, GPSR5_8,
2345 GP_5_7_FN, GPSR5_7,
2346 GP_5_6_FN, GPSR5_6,
2347 GP_5_5_FN, GPSR5_5,
2348 GP_5_4_FN, GPSR5_4,
2349 GP_5_3_FN, GPSR5_3,
2350 GP_5_2_FN, GPSR5_2,
2351 GP_5_1_FN, GPSR5_1,
2352 GP_5_0_FN, GPSR5_0, ))
2353 },
2354#undef F_
2355#undef FM
2356
2357#define F_(x, y) x,
2358#define FM(x) FN_##x,
2359 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2360 IP0_31_28
2361 IP0_27_24
2362 IP0_23_20
2363 IP0_19_16
2364 IP0_15_12
2365 IP0_11_8
2366 IP0_7_4
2367 IP0_3_0 ))
2368 },
2369 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2370 IP1_31_28
2371 IP1_27_24
2372 IP1_23_20
2373 IP1_19_16
2374 IP1_15_12
2375 IP1_11_8
2376 IP1_7_4
2377 IP1_3_0 ))
2378 },
2379 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2380 IP2_31_28
2381 IP2_27_24
2382 IP2_23_20
2383 IP2_19_16
2384 IP2_15_12
2385 IP2_11_8
2386 IP2_7_4
2387 IP2_3_0 ))
2388 },
2389 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2390 IP3_31_28
2391 IP3_27_24
2392 IP3_23_20
2393 IP3_19_16
2394 IP3_15_12
2395 IP3_11_8
2396 IP3_7_4
2397 IP3_3_0 ))
2398 },
2399 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2400 IP4_31_28
2401 IP4_27_24
2402 IP4_23_20
2403 IP4_19_16
2404 IP4_15_12
2405 IP4_11_8
2406 IP4_7_4
2407 IP4_3_0 ))
2408 },
2409 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2410 IP5_31_28
2411 IP5_27_24
2412 IP5_23_20
2413 IP5_19_16
2414 IP5_15_12
2415 IP5_11_8
2416 IP5_7_4
2417 IP5_3_0 ))
2418 },
2419 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2420 IP6_31_28
2421 IP6_27_24
2422 IP6_23_20
2423 IP6_19_16
2424 IP6_15_12
2425 IP6_11_8
2426 IP6_7_4
2427 IP6_3_0 ))
2428 },
2429 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2430 IP7_31_28
2431 IP7_27_24
2432 IP7_23_20
2433 IP7_19_16
2434 IP7_15_12
2435 IP7_11_8
2436 IP7_7_4
2437 IP7_3_0 ))
2438 },
2439 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2440 IP8_31_28
2441 IP8_27_24
2442 IP8_23_20
2443 IP8_19_16
2444 IP8_15_12
2445 IP8_11_8
2446 IP8_7_4
2447 IP8_3_0 ))
2448 },
2449#undef F_
2450#undef FM
2451
2452#define F_(x, y) x,
2453#define FM(x) FN_##x,
2454 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2455 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2456 1, 1, 1, 1, 1),
2457 GROUP(
2458
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460
2461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2462
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464
2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 MOD_SEL0_11
2469 MOD_SEL0_10
2470 MOD_SEL0_9
2471 MOD_SEL0_8
2472 MOD_SEL0_7
2473 MOD_SEL0_6
2474 MOD_SEL0_5
2475 MOD_SEL0_4
2476 MOD_SEL0_3
2477 MOD_SEL0_2
2478 MOD_SEL0_1
2479 MOD_SEL0_0 ))
2480 },
2481 { },
2482};
2483
2484enum ioctrl_regs {
2485 POCCTRL0,
2486 POCCTRL1,
2487 POCCTRL2,
2488 TDSELCTRL,
2489};
2490
2491static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2492 [POCCTRL0] = { 0xe6060380 },
2493 [POCCTRL1] = { 0xe6060384 },
2494 [POCCTRL2] = { 0xe6060388 },
2495 [TDSELCTRL] = { 0xe60603c0, },
2496 { },
2497};
2498
2499static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2500 u32 *pocctrl)
2501{
2502 int bit = pin & 0x1f;
2503
2504 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2505 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2506 return bit;
2507 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2508 return bit + 22;
2509
2510 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2511 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2512 return bit - 10;
2513 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2514 return bit + 7;
2515
2516 return -EINVAL;
2517}
2518
2519static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2520 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2521 [ 0] = RCAR_GP_PIN(0, 0),
2522 [ 1] = RCAR_GP_PIN(0, 1),
2523 [ 2] = RCAR_GP_PIN(0, 2),
2524 [ 3] = RCAR_GP_PIN(0, 3),
2525 [ 4] = RCAR_GP_PIN(0, 4),
2526 [ 5] = RCAR_GP_PIN(0, 5),
2527 [ 6] = RCAR_GP_PIN(0, 6),
2528 [ 7] = RCAR_GP_PIN(0, 7),
2529 [ 8] = RCAR_GP_PIN(0, 8),
2530 [ 9] = RCAR_GP_PIN(0, 9),
2531 [10] = RCAR_GP_PIN(0, 10),
2532 [11] = RCAR_GP_PIN(0, 11),
2533 [12] = RCAR_GP_PIN(0, 12),
2534 [13] = RCAR_GP_PIN(0, 13),
2535 [14] = RCAR_GP_PIN(0, 14),
2536 [15] = RCAR_GP_PIN(0, 15),
2537 [16] = RCAR_GP_PIN(0, 16),
2538 [17] = RCAR_GP_PIN(0, 17),
2539 [18] = RCAR_GP_PIN(0, 18),
2540 [19] = RCAR_GP_PIN(0, 19),
2541 [20] = RCAR_GP_PIN(0, 20),
2542 [21] = RCAR_GP_PIN(0, 21),
2543 [22] = PIN_DU_DOTCLKIN,
2544 [23] = PIN_PRESETOUT_N,
2545 [24] = PIN_EXTALR,
2546 [25] = PIN_FSCLKST_N,
2547 [26] = RCAR_GP_PIN(1, 0),
2548 [27] = PIN_TRST_N,
2549 [28] = PIN_TCK,
2550 [29] = PIN_TMS,
2551 [30] = PIN_TDI,
2552 [31] = RCAR_GP_PIN(2, 0),
2553 } },
2554 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2555 [ 0] = RCAR_GP_PIN(2, 1),
2556 [ 1] = RCAR_GP_PIN(2, 2),
2557 [ 2] = RCAR_GP_PIN(2, 3),
2558 [ 3] = RCAR_GP_PIN(2, 4),
2559 [ 4] = RCAR_GP_PIN(2, 5),
2560 [ 5] = RCAR_GP_PIN(2, 6),
2561 [ 6] = RCAR_GP_PIN(2, 7),
2562 [ 7] = RCAR_GP_PIN(2, 8),
2563 [ 8] = RCAR_GP_PIN(2, 9),
2564 [ 9] = RCAR_GP_PIN(2, 10),
2565 [10] = RCAR_GP_PIN(2, 11),
2566 [11] = RCAR_GP_PIN(2, 12),
2567 [12] = RCAR_GP_PIN(2, 13),
2568 [13] = RCAR_GP_PIN(2, 14),
2569 [14] = RCAR_GP_PIN(2, 15),
2570 [15] = RCAR_GP_PIN(2, 16),
2571 [16] = RCAR_GP_PIN(3, 0),
2572 [17] = RCAR_GP_PIN(3, 1),
2573 [18] = RCAR_GP_PIN(3, 2),
2574 [19] = RCAR_GP_PIN(3, 3),
2575 [20] = RCAR_GP_PIN(3, 4),
2576 [21] = RCAR_GP_PIN(3, 5),
2577 [22] = RCAR_GP_PIN(3, 6),
2578 [23] = RCAR_GP_PIN(3, 7),
2579 [24] = RCAR_GP_PIN(3, 8),
2580 [25] = RCAR_GP_PIN(3, 9),
2581 [26] = RCAR_GP_PIN(3, 10),
2582 [27] = RCAR_GP_PIN(3, 11),
2583 [28] = RCAR_GP_PIN(3, 12),
2584 [29] = RCAR_GP_PIN(3, 13),
2585 [30] = RCAR_GP_PIN(3, 14),
2586 [31] = RCAR_GP_PIN(3, 15),
2587 } },
2588 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2589 [ 0] = RCAR_GP_PIN(3, 16),
2590 [ 1] = RCAR_GP_PIN(4, 0),
2591 [ 2] = RCAR_GP_PIN(4, 1),
2592 [ 3] = RCAR_GP_PIN(4, 2),
2593 [ 4] = RCAR_GP_PIN(4, 3),
2594 [ 5] = RCAR_GP_PIN(4, 4),
2595 [ 6] = RCAR_GP_PIN(4, 5),
2596 [ 7] = RCAR_GP_PIN(1, 1),
2597 [ 8] = RCAR_GP_PIN(1, 2),
2598 [ 9] = RCAR_GP_PIN(1, 3),
2599 [10] = RCAR_GP_PIN(1, 4),
2600 [11] = RCAR_GP_PIN(1, 5),
2601 [12] = RCAR_GP_PIN(1, 6),
2602 [13] = RCAR_GP_PIN(1, 7),
2603 [14] = RCAR_GP_PIN(1, 8),
2604 [15] = RCAR_GP_PIN(1, 9),
2605 [16] = RCAR_GP_PIN(1, 10),
2606 [17] = RCAR_GP_PIN(1, 11),
2607 [18] = RCAR_GP_PIN(1, 12),
2608 [19] = RCAR_GP_PIN(1, 13),
2609 [20] = RCAR_GP_PIN(1, 14),
2610 [21] = RCAR_GP_PIN(1, 15),
2611 [22] = RCAR_GP_PIN(1, 16),
2612 [23] = RCAR_GP_PIN(1, 17),
2613 [24] = RCAR_GP_PIN(1, 18),
2614 [25] = RCAR_GP_PIN(1, 19),
2615 [26] = RCAR_GP_PIN(1, 20),
2616 [27] = RCAR_GP_PIN(1, 21),
2617 [28] = RCAR_GP_PIN(1, 22),
2618 [29] = RCAR_GP_PIN(1, 23),
2619 [30] = RCAR_GP_PIN(1, 24),
2620 [31] = RCAR_GP_PIN(1, 25),
2621 } },
2622 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2623 [ 0] = RCAR_GP_PIN(5, 0),
2624 [ 1] = RCAR_GP_PIN(5, 1),
2625 [ 2] = RCAR_GP_PIN(5, 2),
2626 [ 3] = RCAR_GP_PIN(5, 3),
2627 [ 4] = RCAR_GP_PIN(5, 4),
2628 [ 5] = RCAR_GP_PIN(5, 5),
2629 [ 6] = RCAR_GP_PIN(5, 6),
2630 [ 7] = RCAR_GP_PIN(5, 7),
2631 [ 8] = RCAR_GP_PIN(5, 8),
2632 [ 9] = RCAR_GP_PIN(5, 9),
2633 [10] = RCAR_GP_PIN(5, 10),
2634 [11] = RCAR_GP_PIN(5, 11),
2635 [12] = RCAR_GP_PIN(5, 12),
2636 [13] = RCAR_GP_PIN(5, 13),
2637 [14] = RCAR_GP_PIN(5, 14),
2638 [15] = RCAR_GP_PIN(1, 26),
2639 [16] = RCAR_GP_PIN(1, 27),
2640 [17] = SH_PFC_PIN_NONE,
2641 [18] = SH_PFC_PIN_NONE,
2642 [19] = SH_PFC_PIN_NONE,
2643 [20] = SH_PFC_PIN_NONE,
2644 [21] = SH_PFC_PIN_NONE,
2645 [22] = SH_PFC_PIN_NONE,
2646 [23] = SH_PFC_PIN_NONE,
2647 [24] = SH_PFC_PIN_NONE,
2648 [25] = SH_PFC_PIN_NONE,
2649 [26] = SH_PFC_PIN_NONE,
2650 [27] = SH_PFC_PIN_NONE,
2651 [28] = SH_PFC_PIN_NONE,
2652 [29] = SH_PFC_PIN_NONE,
2653 [30] = SH_PFC_PIN_NONE,
2654 [31] = SH_PFC_PIN_NONE,
2655 } },
2656 { }
2657};
2658
2659static const struct sh_pfc_soc_operations pinmux_ops = {
2660 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2661 .get_bias = rcar_pinmux_get_bias,
2662 .set_bias = rcar_pinmux_set_bias,
2663};
2664
2665const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2666 .name = "r8a77970_pfc",
2667 .ops = &pinmux_ops,
2668 .unlock_reg = 0xe6060000,
2669
2670 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2671
2672 .pins = pinmux_pins,
2673 .nr_pins = ARRAY_SIZE(pinmux_pins),
2674 .groups = pinmux_groups,
2675 .nr_groups = ARRAY_SIZE(pinmux_groups),
2676 .functions = pinmux_functions,
2677 .nr_functions = ARRAY_SIZE(pinmux_functions),
2678
2679 .cfg_regs = pinmux_config_regs,
2680 .bias_regs = pinmux_bias_regs,
2681 .ioctrl_regs = pinmux_ioctrl_regs,
2682
2683 .pinmux_data = pinmux_data,
2684 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2685};
2686
