1
2
3
4
5
6
7
8#ifndef __SH_PFC_H
9#define __SH_PFC_H
10
11#include <linux/bug.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/spinlock.h>
14#include <linux/stringify.h>
15
16enum {
17 PINMUX_TYPE_NONE,
18 PINMUX_TYPE_FUNCTION,
19 PINMUX_TYPE_GPIO,
20 PINMUX_TYPE_OUTPUT,
21 PINMUX_TYPE_INPUT,
22};
23
24#define SH_PFC_PIN_NONE U16_MAX
25
26#define SH_PFC_PIN_CFG_INPUT (1 << 0)
27#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
28#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
29#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
31 SH_PFC_PIN_CFG_PULL_DOWN)
32#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
33#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
34
35#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
36#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
37
38#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
39 SH_PFC_PIN_VOLTAGE_18_33)
40#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
41 SH_PFC_PIN_VOLTAGE_25_33)
42
43#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
44
45struct sh_pfc_pin {
46 const char *name;
47 unsigned int configs;
48 u16 pin;
49 u16 enum_id;
50};
51
52#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
53 { \
54 .name = #alias, \
55 .pins = n##_pins, \
56 .mux = n##_mux, \
57 .nr_pins = ARRAY_SIZE(n##_pins) + \
58 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
59 }
60#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
61
62struct sh_pfc_pin_group {
63 const char *name;
64 const unsigned int *pins;
65 const unsigned int *mux;
66 unsigned int nr_pins;
67};
68
69
70
71
72
73
74
75#define VIN_DATA_PIN_GROUP(n, s, ...) \
76 { \
77 .name = #n#s#__VA_ARGS__, \
78 .pins = n##__VA_ARGS__##_pins.data##s, \
79 .mux = n##__VA_ARGS__##_mux.data##s, \
80 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
81 }
82
83union vin_data12 {
84 unsigned int data12[12];
85 unsigned int data10[10];
86 unsigned int data8[8];
87};
88
89union vin_data16 {
90 unsigned int data16[16];
91 unsigned int data12[12];
92 unsigned int data10[10];
93 unsigned int data8[8];
94};
95
96union vin_data {
97 unsigned int data24[24];
98 unsigned int data20[20];
99 unsigned int data16[16];
100 unsigned int data12[12];
101 unsigned int data10[10];
102 unsigned int data8[8];
103 unsigned int data4[4];
104};
105
106#define SH_PFC_FUNCTION(n) \
107 { \
108 .name = #n, \
109 .groups = n##_groups, \
110 .nr_groups = ARRAY_SIZE(n##_groups), \
111 }
112
113struct sh_pfc_function {
114 const char *name;
115 const char * const *groups;
116 unsigned int nr_groups;
117};
118
119struct pinmux_func {
120 u16 enum_id;
121 const char *name;
122};
123
124struct pinmux_cfg_reg {
125 u32 reg;
126 u8 reg_width, field_width;
127#ifdef DEBUG
128 u16 nr_enum_ids;
129#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
130#else
131#define SET_NR_ENUM_IDS(n)
132#endif
133 const u16 *enum_ids;
134 const u8 *var_field_width;
135};
136
137#define GROUP(...) __VA_ARGS__
138
139
140
141
142
143
144
145
146
147
148
149
150#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
151 .reg = r, .reg_width = r_width, \
152 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
153 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
154 (r_width / f_width) * (1 << f_width)), \
155 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
156 { ids }
157
158
159
160
161
162
163
164
165
166
167
168
169
170#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
171 .reg = r, .reg_width = r_width, \
172 .var_field_width = (const u8 []) { f_widths, 0 }, \
173 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
174 .enum_ids = (const u16 []) { ids }
175
176struct pinmux_drive_reg_field {
177 u16 pin;
178 u8 offset;
179 u8 size;
180};
181
182struct pinmux_drive_reg {
183 u32 reg;
184 const struct pinmux_drive_reg_field fields[8];
185};
186
187#define PINMUX_DRIVE_REG(name, r) \
188 .reg = r, \
189 .fields =
190
191struct pinmux_bias_reg {
192 u32 puen;
193 u32 pud;
194 const u16 pins[32];
195};
196
197#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
198 .puen = r1, \
199 .pud = r2, \
200 .pins =
201
202struct pinmux_ioctrl_reg {
203 u32 reg;
204};
205
206struct pinmux_data_reg {
207 u32 reg;
208 u8 reg_width;
209 const u16 *enum_ids;
210};
211
212
213
214
215
216
217
218
219
220#define PINMUX_DATA_REG(name, r, r_width, ids) \
221 .reg = r, .reg_width = r_width + \
222 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
223 r_width), \
224 .enum_ids = (const u16 [r_width]) { ids }
225
226struct pinmux_irq {
227 const short *gpios;
228};
229
230
231
232
233
234#define PINMUX_IRQ(ids...) \
235 { .gpios = (const short []) { ids, -1 } }
236
237struct pinmux_range {
238 u16 begin;
239 u16 end;
240 u16 force;
241};
242
243struct sh_pfc_window {
244 phys_addr_t phys;
245 void __iomem *virt;
246 unsigned long size;
247};
248
249struct sh_pfc_pin_range;
250
251struct sh_pfc {
252 struct device *dev;
253 const struct sh_pfc_soc_info *info;
254 spinlock_t lock;
255
256 unsigned int num_windows;
257 struct sh_pfc_window *windows;
258 unsigned int num_irqs;
259 unsigned int *irqs;
260
261 struct sh_pfc_pin_range *ranges;
262 unsigned int nr_ranges;
263
264 unsigned int nr_gpio_pins;
265
266 struct sh_pfc_chip *gpio;
267 u32 *saved_regs;
268};
269
270struct sh_pfc_soc_operations {
271 int (*init)(struct sh_pfc *pfc);
272 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
273 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
274 unsigned int bias);
275 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
276 void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
277};
278
279struct sh_pfc_soc_info {
280 const char *name;
281 const struct sh_pfc_soc_operations *ops;
282
283#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
284 struct pinmux_range input;
285 struct pinmux_range output;
286 const struct pinmux_irq *gpio_irq;
287 unsigned int gpio_irq_size;
288#endif
289
290 struct pinmux_range function;
291
292 const struct sh_pfc_pin *pins;
293 unsigned int nr_pins;
294 const struct sh_pfc_pin_group *groups;
295 unsigned int nr_groups;
296 const struct sh_pfc_function *functions;
297 unsigned int nr_functions;
298
299#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
300 const struct pinmux_func *func_gpios;
301 unsigned int nr_func_gpios;
302#endif
303
304 const struct pinmux_cfg_reg *cfg_regs;
305 const struct pinmux_drive_reg *drive_regs;
306 const struct pinmux_bias_reg *bias_regs;
307 const struct pinmux_ioctrl_reg *ioctrl_regs;
308 const struct pinmux_data_reg *data_regs;
309
310 const u16 *pinmux_data;
311 unsigned int pinmux_data_size;
312
313 u32 unlock_reg;
314};
315
316extern const struct sh_pfc_soc_info emev2_pinmux_info;
317extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
318extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
319extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
320extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
321extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
322extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
323extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
324extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
325extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
326extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
327extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
328extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
329extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
330extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
331extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
332extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
333extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
334extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
335extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
336extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
337extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
338extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
339extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
340extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
341extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
342extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
343extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
344extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
345extern const struct sh_pfc_soc_info sh7203_pinmux_info;
346extern const struct sh_pfc_soc_info sh7264_pinmux_info;
347extern const struct sh_pfc_soc_info sh7269_pinmux_info;
348extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
349extern const struct sh_pfc_soc_info sh7720_pinmux_info;
350extern const struct sh_pfc_soc_info sh7722_pinmux_info;
351extern const struct sh_pfc_soc_info sh7723_pinmux_info;
352extern const struct sh_pfc_soc_info sh7724_pinmux_info;
353extern const struct sh_pfc_soc_info sh7734_pinmux_info;
354extern const struct sh_pfc_soc_info sh7757_pinmux_info;
355extern const struct sh_pfc_soc_info sh7785_pinmux_info;
356extern const struct sh_pfc_soc_info sh7786_pinmux_info;
357extern const struct sh_pfc_soc_info shx3_pinmux_info;
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
373
374
375
376
377
378
379
380#define PINMUX_IPSR_NOGP(ipsr, fn) \
381 PINMUX_DATA(fn##_MARK, FN_##fn)
382
383
384
385
386
387
388
389
390#define PINMUX_IPSR_GPSR(ipsr, fn) \
391 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
392
393
394
395
396
397
398
399
400
401#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
402 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
403
404
405
406
407
408
409
410
411
412#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
413 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
414
415
416
417
418
419
420
421
422
423
424#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
425 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
426
427
428
429
430
431
432
433
434
435
436#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
437 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
438
439
440
441
442
443
444
445
446#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
447 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
448
449
450
451
452
453
454#define PINMUX_SINGLE(fn) \
455 PINMUX_DATA(fn##_MARK, FN_##fn)
456
457
458
459
460
461#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
462 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
463#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
464
465#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
466 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
467 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
468#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
469
470#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
471 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
472 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
473 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
474#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
475
476#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
477 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
478 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
479 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
480#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
481
482#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
483 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
484 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
485#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
486
487#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
488 PORT_GP_CFG_7(bank, fn, sfx, cfg), \
489 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
490#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
491
492#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
493 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
494 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
495#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
496
497#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
498 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
499 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
500#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
501
502#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
503 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
504 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
505#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
506
507#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
508 PORT_GP_CFG_11(bank, fn, sfx, cfg), \
509 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
510#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
511
512#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
513 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
514 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
515 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
516#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
517
518#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
519 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
520 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
521#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
522
523#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
524 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
525 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
526#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
527
528#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
529 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
530 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
531#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
532
533#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
534 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
535 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
536#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
537
538#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
539 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
540 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
541 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
542#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
543
544#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
545 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
546 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
547#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
548
549#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
550 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
551 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
552#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
553
554#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
555 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
556 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
557#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
558
559#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
560 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
561 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
562#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
563
564#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
565 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
566 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
567#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
568
569#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
570 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
571 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
572#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
573
574#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
575 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
576 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
577#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
578
579#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
580 PORT_GP_CFG_27(bank, fn, sfx, cfg), \
581 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
582#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
583
584#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
585 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
586 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
587#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
588
589#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
590 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
591 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
592#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
593
594#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
595 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
596 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
597#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
598
599#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
600 PORT_GP_CFG_31(bank, fn, sfx, cfg), \
601 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
602#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
603
604#define PORT_GP_32_REV(bank, fn, sfx) \
605 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
606 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
607 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
608 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
609 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
610 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
611 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
612 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
613 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
614 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
615 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
616 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
617 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
618 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
619 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
620 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
621
622
623#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
624#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
625
626
627#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
628 { \
629 .pin = (bank * 32) + _pin, \
630 .name = __stringify(_name), \
631 .enum_id = _name##_DATA, \
632 .configs = cfg, \
633 }
634#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
635
636
637#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
638#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
639
640
641
642
643
644
645
646
647
648
649#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
650 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
651#define GP_ASSIGN_LAST() \
652 GP_LAST = sizeof(union { \
653 char dummy[0] __attribute__((deprecated, \
654 CPU_ALL_GP(_GP_ENTRY, unused), \
655 deprecated)); \
656 })
657
658
659
660
661
662#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
663
664#define PORT_10(pn, fn, pfx, sfx) \
665 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
666 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
667 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
668 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
669 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
670
671#define PORT_90(pn, fn, pfx, sfx) \
672 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
673 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
674 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
675 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
676 PORT_10(pn+90, fn, pfx##9, sfx)
677
678
679#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
680#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
681
682
683#define PINMUX_GPIO(_pin) \
684 [GPIO_##_pin] = { \
685 .pin = (u16)-1, \
686 .name = __stringify(GPIO_##_pin), \
687 .enum_id = _pin##_DATA, \
688 }
689
690
691#define SH_PFC_PIN_CFG(_pin, cfgs) \
692 { \
693 .pin = _pin, \
694 .name = __stringify(PORT##_pin), \
695 .enum_id = PORT##_pin##_DATA, \
696 .configs = cfgs, \
697 }
698
699
700
701
702#define _PORT_DATA(pn, pfx, sfx) \
703 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
704 PORT##pfx##_OUT, PORT##pfx##_IN)
705#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
706
707
708
709
710
711
712
713
714
715
716#define _PORT_ENTRY(pn, pfx, sfx) \
717 deprecated)); char pfx[pn] __attribute__((deprecated
718#define PORT_ASSIGN_LAST() \
719 PORT_LAST = sizeof(union { \
720 char dummy[0] __attribute__((deprecated, \
721 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
722 deprecated)); \
723 })
724
725
726#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
727 [gpio - (base)] = { \
728 .name = __stringify(gpio), \
729 .enum_id = data_or_mark, \
730 }
731#define GPIO_FN(str) \
732 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
733
734
735
736
737
738#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
739#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
740
741
742#define _NOGP_ALL(pin, name, cfg) PIN_##pin
743#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
744
745
746#define _NOGP_PINMUX(_pin, _name, cfg) \
747 { \
748 .pin = PIN_##_pin, \
749 .name = "PIN_" _name, \
750 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
751 }
752#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
753
754
755
756
757#define PORTCR(nr, reg) \
758 { \
759 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
760 GROUP(2, 2, 1, 3), \
761 GROUP( \
762 \
763 0, 0, 0, 0, \
764 \
765 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
766 \
767 0, 0, \
768 \
769 PORT##nr##_FN0, PORT##nr##_FN1, \
770 PORT##nr##_FN2, PORT##nr##_FN3, \
771 PORT##nr##_FN4, PORT##nr##_FN5, \
772 PORT##nr##_FN6, PORT##nr##_FN7 \
773 )) \
774 }
775
776
777
778
779#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
780
781
782
783
784const struct pinmux_bias_reg *
785rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
786 unsigned int *bit);
787unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
788void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
789 unsigned int bias);
790
791unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
792void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
793 unsigned int bias);
794
795#endif
796