LXR linux/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

   1// SPDX-License-Identifier: GPL-2.0+
   2//
   3// Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
   4// with eint support.
   5//
   6// Copyright (c) 2012 Samsung Electronics Co., Ltd.
   7//              http://www.samsung.com
   8// Copyright (c) 2012 Linaro Ltd
   9//              http://www.linaro.org
  10// Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
  11//
  12// This file contains the Samsung Exynos specific information required by the
  13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  14// external gpio and wakeup interrupt support.
  15
  16#include <linux/slab.h>
  17#include <linux/soc/samsung/exynos-regs-pmu.h>
  18
  19#include "pinctrl-samsung.h"
  20#include "pinctrl-exynos.h"
  21
  22static const struct samsung_pin_bank_type bank_type_off = {
  23        .fld_width = { 4, 1, 2, 2, 2, 2, },
  24        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  25};
  26
  27static const struct samsung_pin_bank_type bank_type_alive = {
  28        .fld_width = { 4, 1, 2, 2, },
  29        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  30};
  31
  32/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
  33static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
  34        .fld_width = { 4, 1, 2, 4, 2, 2, },
  35        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  36};
  37
  38static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
  39        .fld_width = { 4, 1, 2, 4, },
  40        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  41};
  42
  43/*
  44 * Bank type for non-alive type. Bit fields:
  45 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
  46 */
  47static const struct samsung_pin_bank_type exynos850_bank_type_off  = {
  48        .fld_width = { 4, 1, 4, 4, 2, 4, },
  49        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  50};
  51
  52/*
  53 * Bank type for alive type. Bit fields:
  54 * CON: 4, DAT: 1, PUD: 4, DRV: 4
  55 */
  56static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
  57        .fld_width = { 4, 1, 4, 4, },
  58        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  59};
  60
  61/* Pad retention control code for accessing PMU regmap */
  62static atomic_t exynos_shared_retention_refcnt;
  63
  64/* pin banks of exynos5433 pin-controller - ALIVE */
  65static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
  66        /* Must start with EINTG banks, ordered by EINT group number. */
  67        EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
  68        EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
  69        EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
  70        EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
  71        EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
  72        EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
  73        EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
  74        EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
  75        EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
  76};
  77
  78/* pin banks of exynos5433 pin-controller - AUD */
  79static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
  80        /* Must start with EINTG banks, ordered by EINT group number. */
  81        EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
  82        EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
  83};
  84
  85/* pin banks of exynos5433 pin-controller - CPIF */
  86static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
  87        /* Must start with EINTG banks, ordered by EINT group number. */
  88        EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
  89};
  90
  91/* pin banks of exynos5433 pin-controller - eSE */
  92static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
  93        /* Must start with EINTG banks, ordered by EINT group number. */
  94        EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
  95};
  96
  97/* pin banks of exynos5433 pin-controller - FINGER */
  98static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
  99        /* Must start with EINTG banks, ordered by EINT group number. */
 100        EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
 101};
 102
 103/* pin banks of exynos5433 pin-controller - FSYS */
 104static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
 105        /* Must start with EINTG banks, ordered by EINT group number. */
 106        EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
 107        EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
 108        EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
 109        EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
 110        EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
 111        EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
 112};
 113
 114/* pin banks of exynos5433 pin-controller - IMEM */
 115static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
 116        /* Must start with EINTG banks, ordered by EINT group number. */
 117        EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
 118};
 119
 120/* pin banks of exynos5433 pin-controller - NFC */
 121static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
 122        /* Must start with EINTG banks, ordered by EINT group number. */
 123        EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 124};
 125
 126/* pin banks of exynos5433 pin-controller - PERIC */
 127static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
 128        /* Must start with EINTG banks, ordered by EINT group number. */
 129        EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
 130        EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
 131        EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
 132        EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
 133        EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
 134        EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
 135        EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
 136        EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
 137        EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
 138        EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
 139        EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
 140        EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
 141        EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
 142        EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
 143        EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
 144        EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
 145        EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
 146};
 147
 148/* pin banks of exynos5433 pin-controller - TOUCH */
 149static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
 150        /* Must start with EINTG banks, ordered by EINT group number. */
 151        EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 152};
 153
 154/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
 155static const u32 exynos5433_retention_regs[] = {
 156        EXYNOS5433_PAD_RETENTION_TOP_OPTION,
 157        EXYNOS5433_PAD_RETENTION_UART_OPTION,
 158        EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
 159        EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
 160        EXYNOS5433_PAD_RETENTION_SPI_OPTION,
 161        EXYNOS5433_PAD_RETENTION_MIF_OPTION,
 162        EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
 163        EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
 164        EXYNOS5433_PAD_RETENTION_UFS_OPTION,
 165        EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
 166};
 167
 168static const struct samsung_retention_data exynos5433_retention_data __initconst = {
 169        .regs    = exynos5433_retention_regs,
 170        .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
 171        .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 172        .refcnt  = &exynos_shared_retention_refcnt,
 173        .init    = exynos_retention_init,
 174};
 175
 176/* PMU retention control for audio pins can be tied to audio pin bank */
 177static const u32 exynos5433_audio_retention_regs[] = {
 178        EXYNOS5433_PAD_RETENTION_AUD_OPTION,
 179};
 180
 181static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
 182        .regs    = exynos5433_audio_retention_regs,
 183        .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
 184        .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 185        .init    = exynos_retention_init,
 186};
 187
 188/* PMU retention control for mmc pins can be tied to fsys pin bank */
 189static const u32 exynos5433_fsys_retention_regs[] = {
 190        EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
 191        EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
 192        EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
 193};
 194
 195static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
 196        .regs    = exynos5433_fsys_retention_regs,
 197        .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
 198        .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 199        .init    = exynos_retention_init,
 200};
 201
 202/*
 203 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
 204 * ten gpio/pin-mux/pinconfig controllers.
 205 */
 206static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
 207        {
 208                /* pin-controller instance 0 data */
 209                .pin_banks      = exynos5433_pin_banks0,
 210                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks0),
 211                .eint_wkup_init = exynos_eint_wkup_init,
 212                .suspend        = exynos_pinctrl_suspend,
 213                .resume         = exynos_pinctrl_resume,
 214                .nr_ext_resources = 1,
 215                .retention_data = &exynos5433_retention_data,
 216        }, {
 217                /* pin-controller instance 1 data */
 218                .pin_banks      = exynos5433_pin_banks1,
 219                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks1),
 220                .eint_gpio_init = exynos_eint_gpio_init,
 221                .suspend        = exynos_pinctrl_suspend,
 222                .resume         = exynos_pinctrl_resume,
 223                .retention_data = &exynos5433_audio_retention_data,
 224        }, {
 225                /* pin-controller instance 2 data */
 226                .pin_banks      = exynos5433_pin_banks2,
 227                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks2),
 228                .eint_gpio_init = exynos_eint_gpio_init,
 229                .suspend        = exynos_pinctrl_suspend,
 230                .resume         = exynos_pinctrl_resume,
 231                .retention_data = &exynos5433_retention_data,
 232        }, {
 233                /* pin-controller instance 3 data */
 234                .pin_banks      = exynos5433_pin_banks3,
 235                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks3),
 236                .eint_gpio_init = exynos_eint_gpio_init,
 237                .suspend        = exynos_pinctrl_suspend,
 238                .resume         = exynos_pinctrl_resume,
 239                .retention_data = &exynos5433_retention_data,
 240        }, {
 241                /* pin-controller instance 4 data */
 242                .pin_banks      = exynos5433_pin_banks4,
 243                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks4),
 244                .eint_gpio_init = exynos_eint_gpio_init,
 245                .suspend        = exynos_pinctrl_suspend,
 246                .resume         = exynos_pinctrl_resume,
 247                .retention_data = &exynos5433_retention_data,
 248        }, {
 249                /* pin-controller instance 5 data */
 250                .pin_banks      = exynos5433_pin_banks5,
 251                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks5),
 252                .eint_gpio_init = exynos_eint_gpio_init,
 253                .suspend        = exynos_pinctrl_suspend,
 254                .resume         = exynos_pinctrl_resume,
 255                .retention_data = &exynos5433_fsys_retention_data,
 256        }, {
 257                /* pin-controller instance 6 data */
 258                .pin_banks      = exynos5433_pin_banks6,
 259                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks6),
 260                .eint_gpio_init = exynos_eint_gpio_init,
 261                .suspend        = exynos_pinctrl_suspend,
 262                .resume         = exynos_pinctrl_resume,
 263                .retention_data = &exynos5433_retention_data,
 264        }, {
 265                /* pin-controller instance 7 data */
 266                .pin_banks      = exynos5433_pin_banks7,
 267                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks7),
 268                .eint_gpio_init = exynos_eint_gpio_init,
 269                .suspend        = exynos_pinctrl_suspend,
 270                .resume         = exynos_pinctrl_resume,
 271                .retention_data = &exynos5433_retention_data,
 272        }, {
 273                /* pin-controller instance 8 data */
 274                .pin_banks      = exynos5433_pin_banks8,
 275                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks8),
 276                .eint_gpio_init = exynos_eint_gpio_init,
 277                .suspend        = exynos_pinctrl_suspend,
 278                .resume         = exynos_pinctrl_resume,
 279                .retention_data = &exynos5433_retention_data,
 280        }, {
 281                /* pin-controller instance 9 data */
 282                .pin_banks      = exynos5433_pin_banks9,
 283                .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks9),
 284                .eint_gpio_init = exynos_eint_gpio_init,
 285                .suspend        = exynos_pinctrl_suspend,
 286                .resume         = exynos_pinctrl_resume,
 287                .retention_data = &exynos5433_retention_data,
 288        },
 289};
 290
 291const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
 292        .ctrl           = exynos5433_pin_ctrl,
 293        .num_ctrl       = ARRAY_SIZE(exynos5433_pin_ctrl),
 294};
 295
 296/* pin banks of exynos7 pin-controller - ALIVE */
 297static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
 298        /* Must start with EINTG banks, ordered by EINT group number. */
 299        EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
 300        EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
 301        EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
 302        EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
 303};
 304
 305/* pin banks of exynos7 pin-controller - BUS0 */
 306static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
 307        /* Must start with EINTG banks, ordered by EINT group number. */
 308        EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
 309        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
 310        EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
 311        EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
 312        EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
 313        EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 314        EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 315        EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
 316        EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
 317        EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
 318        EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
 319        EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
 320        EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
 321        EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
 322        EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
 323};
 324
 325/* pin banks of exynos7 pin-controller - NFC */
 326static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
 327        /* Must start with EINTG banks, ordered by EINT group number. */
 328        EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 329};
 330
 331/* pin banks of exynos7 pin-controller - TOUCH */
 332static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
 333        /* Must start with EINTG banks, ordered by EINT group number. */
 334        EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 335};
 336
 337/* pin banks of exynos7 pin-controller - FF */
 338static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
 339        /* Must start with EINTG banks, ordered by EINT group number. */
 340        EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
 341};
 342
 343/* pin banks of exynos7 pin-controller - ESE */
 344static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
 345        /* Must start with EINTG banks, ordered by EINT group number. */
 346        EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
 347};
 348
 349/* pin banks of exynos7 pin-controller - FSYS0 */
 350static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
 351        /* Must start with EINTG banks, ordered by EINT group number. */
 352        EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
 353};
 354
 355/* pin banks of exynos7 pin-controller - FSYS1 */
 356static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 357        /* Must start with EINTG banks, ordered by EINT group number. */
 358        EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
 359        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
 360        EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
 361        EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 362};
 363
 364/* pin banks of exynos7 pin-controller - BUS1 */
 365static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
 366        /* Must start with EINTG banks, ordered by EINT group number. */
 367        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
 368        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
 369        EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
 370        EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
 371        EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
 372        EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
 373        EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
 374        EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
 375        EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
 376        EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
 377};
 378
 379static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
 380        /* Must start with EINTG banks, ordered by EINT group number. */
 381        EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
 382        EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 383};
 384
 385static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 386        {
 387                /* pin-controller instance 0 Alive data */
 388                .pin_banks      = exynos7_pin_banks0,
 389                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks0),
 390                .eint_wkup_init = exynos_eint_wkup_init,
 391        }, {
 392                /* pin-controller instance 1 BUS0 data */
 393                .pin_banks      = exynos7_pin_banks1,
 394                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks1),
 395                .eint_gpio_init = exynos_eint_gpio_init,
 396        }, {
 397                /* pin-controller instance 2 NFC data */
 398                .pin_banks      = exynos7_pin_banks2,
 399                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks2),
 400                .eint_gpio_init = exynos_eint_gpio_init,
 401        }, {
 402                /* pin-controller instance 3 TOUCH data */
 403                .pin_banks      = exynos7_pin_banks3,
 404                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks3),
 405                .eint_gpio_init = exynos_eint_gpio_init,
 406        }, {
 407                /* pin-controller instance 4 FF data */
 408                .pin_banks      = exynos7_pin_banks4,
 409                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks4),
 410                .eint_gpio_init = exynos_eint_gpio_init,
 411        }, {
 412                /* pin-controller instance 5 ESE data */
 413                .pin_banks      = exynos7_pin_banks5,
 414                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks5),
 415                .eint_gpio_init = exynos_eint_gpio_init,
 416        }, {
 417                /* pin-controller instance 6 FSYS0 data */
 418                .pin_banks      = exynos7_pin_banks6,
 419                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks6),
 420                .eint_gpio_init = exynos_eint_gpio_init,
 421        }, {
 422                /* pin-controller instance 7 FSYS1 data */
 423                .pin_banks      = exynos7_pin_banks7,
 424                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
 425                .eint_gpio_init = exynos_eint_gpio_init,
 426        }, {
 427                /* pin-controller instance 8 BUS1 data */
 428                .pin_banks      = exynos7_pin_banks8,
 429                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
 430                .eint_gpio_init = exynos_eint_gpio_init,
 431        }, {
 432                /* pin-controller instance 9 AUD data */
 433                .pin_banks      = exynos7_pin_banks9,
 434                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks9),
 435                .eint_gpio_init = exynos_eint_gpio_init,
 436        },
 437};
 438
 439const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
 440        .ctrl           = exynos7_pin_ctrl,
 441        .num_ctrl       = ARRAY_SIZE(exynos7_pin_ctrl),
 442};
 443
 444/* pin banks of exynos850 pin-controller 0 (ALIVE) */
 445static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
 446        /* Must start with EINTG banks, ordered by EINT group number. */
 447        EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
 448        EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
 449        EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
 450        EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
 451        EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
 452        EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"),
 453};
 454
 455/* pin banks of exynos850 pin-controller 1 (CMGP) */
 456static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
 457        /* Must start with EINTG banks, ordered by EINT group number. */
 458        EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
 459        EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
 460        EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
 461        EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c),
 462        EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
 463        EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14),
 464        EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18),
 465        EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c),
 466};
 467
 468/* pin banks of exynos850 pin-controller 2 (AUD) */
 469static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
 470        /* Must start with EINTG banks, ordered by EINT group number. */
 471        EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
 472        EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
 473};
 474
 475/* pin banks of exynos850 pin-controller 3 (HSI) */
 476static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
 477        /* Must start with EINTG banks, ordered by EINT group number. */
 478        EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
 479};
 480
 481/* pin banks of exynos850 pin-controller 4 (CORE) */
 482static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
 483        /* Must start with EINTG banks, ordered by EINT group number. */
 484        EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
 485        EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
 486};
 487
 488/* pin banks of exynos850 pin-controller 5 (PERI) */
 489static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
 490        /* Must start with EINTG banks, ordered by EINT group number. */
 491        EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
 492        EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
 493        EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
 494        EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
 495        EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
 496        EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14),
 497        EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18),
 498        EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c),
 499        EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
 500};
 501
 502static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
 503        {
 504                /* pin-controller instance 0 ALIVE data */
 505                .pin_banks      = exynos850_pin_banks0,
 506                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks0),
 507                .eint_gpio_init = exynos_eint_gpio_init,
 508                .eint_wkup_init = exynos_eint_wkup_init,
 509        }, {
 510                /* pin-controller instance 1 CMGP data */
 511                .pin_banks      = exynos850_pin_banks1,
 512                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks1),
 513                .eint_gpio_init = exynos_eint_gpio_init,
 514                .eint_wkup_init = exynos_eint_wkup_init,
 515        }, {
 516                /* pin-controller instance 2 AUD data */
 517                .pin_banks      = exynos850_pin_banks2,
 518                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks2),
 519        }, {
 520                /* pin-controller instance 3 HSI data */
 521                .pin_banks      = exynos850_pin_banks3,
 522                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks3),
 523                .eint_gpio_init = exynos_eint_gpio_init,
 524        }, {
 525                /* pin-controller instance 4 CORE data */
 526                .pin_banks      = exynos850_pin_banks4,
 527                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks4),
 528                .eint_gpio_init = exynos_eint_gpio_init,
 529        }, {
 530                /* pin-controller instance 5 PERI data */
 531                .pin_banks      = exynos850_pin_banks5,
 532                .nr_banks       = ARRAY_SIZE(exynos850_pin_banks5),
 533                .eint_gpio_init = exynos_eint_gpio_init,
 534        },
 535};
 536
 537const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
 538        .ctrl           = exynos850_pin_ctrl,
 539        .num_ctrl       = ARRAY_SIZE(exynos850_pin_ctrl),
 540};
 541