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13#include <linux/io.h>
14#include <linux/clk.h>
15#include <linux/gpio/driver.h>
16#include <linux/interrupt.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/export.h>
20#include <linux/of.h>
21#include <linux/of_clk.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinconf-generic.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/regulator/consumer.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33
34#include <dt-bindings/pinctrl/sun4i-a10.h>
35
36#include "../core.h"
37#include "pinctrl-sunxi.h"
38
39static struct irq_chip sunxi_pinctrl_edge_irq_chip;
40static struct irq_chip sunxi_pinctrl_level_irq_chip;
41
42static struct sunxi_pinctrl_group *
43sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
44{
45 int i;
46
47 for (i = 0; i < pctl->ngroups; i++) {
48 struct sunxi_pinctrl_group *grp = pctl->groups + i;
49
50 if (!strcmp(grp->name, group))
51 return grp;
52 }
53
54 return NULL;
55}
56
57static struct sunxi_pinctrl_function *
58sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
59 const char *name)
60{
61 struct sunxi_pinctrl_function *func = pctl->functions;
62 int i;
63
64 for (i = 0; i < pctl->nfunctions; i++) {
65 if (!func[i].name)
66 break;
67
68 if (!strcmp(func[i].name, name))
69 return func + i;
70 }
71
72 return NULL;
73}
74
75static struct sunxi_desc_function *
76sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
77 const char *pin_name,
78 const char *func_name)
79{
80 int i;
81
82 for (i = 0; i < pctl->desc->npins; i++) {
83 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
84
85 if (!strcmp(pin->pin.name, pin_name)) {
86 struct sunxi_desc_function *func = pin->functions;
87
88 while (func->name) {
89 if (!strcmp(func->name, func_name) &&
90 (!func->variant ||
91 func->variant & pctl->variant))
92 return func;
93
94 func++;
95 }
96 }
97 }
98
99 return NULL;
100}
101
102static struct sunxi_desc_function *
103sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
104 const u16 pin_num,
105 const char *func_name)
106{
107 int i;
108
109 for (i = 0; i < pctl->desc->npins; i++) {
110 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
111
112 if (pin->pin.number == pin_num) {
113 struct sunxi_desc_function *func = pin->functions;
114
115 while (func->name) {
116 if (!strcmp(func->name, func_name))
117 return func;
118
119 func++;
120 }
121 }
122 }
123
124 return NULL;
125}
126
127static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
128{
129 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
130
131 return pctl->ngroups;
132}
133
134static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
135 unsigned group)
136{
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138
139 return pctl->groups[group].name;
140}
141
142static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
143 unsigned group,
144 const unsigned **pins,
145 unsigned *num_pins)
146{
147 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
148
149 *pins = (unsigned *)&pctl->groups[group].pin;
150 *num_pins = 1;
151
152 return 0;
153}
154
155static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
156{
157 return of_find_property(node, "bias-pull-up", NULL) ||
158 of_find_property(node, "bias-pull-down", NULL) ||
159 of_find_property(node, "bias-disable", NULL) ||
160 of_find_property(node, "allwinner,pull", NULL);
161}
162
163static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
164{
165 return of_find_property(node, "drive-strength", NULL) ||
166 of_find_property(node, "allwinner,drive", NULL);
167}
168
169static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
170{
171 u32 val;
172
173
174 if (of_find_property(node, "bias-pull-up", NULL))
175 return PIN_CONFIG_BIAS_PULL_UP;
176
177 if (of_find_property(node, "bias-pull-down", NULL))
178 return PIN_CONFIG_BIAS_PULL_DOWN;
179
180 if (of_find_property(node, "bias-disable", NULL))
181 return PIN_CONFIG_BIAS_DISABLE;
182
183
184 if (of_property_read_u32(node, "allwinner,pull", &val))
185 return -EINVAL;
186
187 switch (val) {
188 case SUN4I_PINCTRL_NO_PULL:
189 return PIN_CONFIG_BIAS_DISABLE;
190 case SUN4I_PINCTRL_PULL_UP:
191 return PIN_CONFIG_BIAS_PULL_UP;
192 case SUN4I_PINCTRL_PULL_DOWN:
193 return PIN_CONFIG_BIAS_PULL_DOWN;
194 }
195
196 return -EINVAL;
197}
198
199static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
200{
201 u32 val;
202
203
204 if (!of_property_read_u32(node, "drive-strength", &val)) {
205
206 if (val < 10)
207 return -EINVAL;
208
209
210 if (val > 40)
211 val = 40;
212
213
214 return rounddown(val, 10);
215 }
216
217
218 if (of_property_read_u32(node, "allwinner,drive", &val))
219 return -EINVAL;
220
221 return (val + 1) * 10;
222}
223
224static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
225{
226 const char *function;
227 int ret;
228
229
230 ret = of_property_read_string(node, "function", &function);
231 if (!ret)
232 return function;
233
234
235 ret = of_property_read_string(node, "allwinner,function", &function);
236 if (!ret)
237 return function;
238
239 return NULL;
240}
241
242static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
243 int *npins)
244{
245 int count;
246
247
248 count = of_property_count_strings(node, "pins");
249 if (count > 0) {
250 *npins = count;
251 return "pins";
252 }
253
254
255 count = of_property_count_strings(node, "allwinner,pins");
256 if (count > 0) {
257 *npins = count;
258 return "allwinner,pins";
259 }
260
261 return NULL;
262}
263
264static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
265 unsigned int *len)
266{
267 unsigned long *pinconfig;
268 unsigned int configlen = 0, idx = 0;
269 int ret;
270
271 if (sunxi_pctrl_has_drive_prop(node))
272 configlen++;
273 if (sunxi_pctrl_has_bias_prop(node))
274 configlen++;
275
276
277
278
279 if (!configlen)
280 return NULL;
281
282 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
283 if (!pinconfig)
284 return ERR_PTR(-ENOMEM);
285
286 if (sunxi_pctrl_has_drive_prop(node)) {
287 int drive = sunxi_pctrl_parse_drive_prop(node);
288 if (drive < 0) {
289 ret = drive;
290 goto err_free;
291 }
292
293 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
294 drive);
295 }
296
297 if (sunxi_pctrl_has_bias_prop(node)) {
298 int pull = sunxi_pctrl_parse_bias_prop(node);
299 int arg = 0;
300 if (pull < 0) {
301 ret = pull;
302 goto err_free;
303 }
304
305 if (pull != PIN_CONFIG_BIAS_DISABLE)
306 arg = 1;
307
308 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
309 }
310
311
312 *len = configlen;
313 return pinconfig;
314
315err_free:
316 kfree(pinconfig);
317 return ERR_PTR(ret);
318}
319
320static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
321 struct device_node *node,
322 struct pinctrl_map **map,
323 unsigned *num_maps)
324{
325 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
326 unsigned long *pinconfig;
327 struct property *prop;
328 const char *function, *pin_prop;
329 const char *group;
330 int ret, npins, nmaps, configlen = 0, i = 0;
331
332 *map = NULL;
333 *num_maps = 0;
334
335 function = sunxi_pctrl_parse_function_prop(node);
336 if (!function) {
337 dev_err(pctl->dev, "missing function property in node %pOFn\n",
338 node);
339 return -EINVAL;
340 }
341
342 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
343 if (!pin_prop) {
344 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
345 node);
346 return -EINVAL;
347 }
348
349
350
351
352
353
354
355
356 nmaps = npins * 2;
357 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
358 if (!*map)
359 return -ENOMEM;
360
361 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
362 if (IS_ERR(pinconfig)) {
363 ret = PTR_ERR(pinconfig);
364 goto err_free_map;
365 }
366
367 of_property_for_each_string(node, pin_prop, prop, group) {
368 struct sunxi_pinctrl_group *grp =
369 sunxi_pinctrl_find_group_by_name(pctl, group);
370
371 if (!grp) {
372 dev_err(pctl->dev, "unknown pin %s", group);
373 continue;
374 }
375
376 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
377 grp->name,
378 function)) {
379 dev_err(pctl->dev, "unsupported function %s on pin %s",
380 function, group);
381 continue;
382 }
383
384 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
385 (*map)[i].data.mux.group = group;
386 (*map)[i].data.mux.function = function;
387
388 i++;
389
390 if (pinconfig) {
391 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
392 (*map)[i].data.configs.group_or_pin = group;
393 (*map)[i].data.configs.configs = pinconfig;
394 (*map)[i].data.configs.num_configs = configlen;
395 i++;
396 }
397 }
398
399 *num_maps = i;
400
401
402
403
404
405 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
406 if (!*map)
407 return -ENOMEM;
408
409 return 0;
410
411err_free_map:
412 kfree(*map);
413 *map = NULL;
414 return ret;
415}
416
417static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
418 struct pinctrl_map *map,
419 unsigned num_maps)
420{
421 int i;
422
423
424 for (i = 1; i < num_maps; i++) {
425 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
426 continue;
427
428
429
430
431
432 kfree(map[i].data.configs.configs);
433 break;
434 }
435
436 kfree(map);
437}
438
439static const struct pinctrl_ops sunxi_pctrl_ops = {
440 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
441 .dt_free_map = sunxi_pctrl_dt_free_map,
442 .get_groups_count = sunxi_pctrl_get_groups_count,
443 .get_group_name = sunxi_pctrl_get_group_name,
444 .get_group_pins = sunxi_pctrl_get_group_pins,
445};
446
447static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
448 u32 *offset, u32 *shift, u32 *mask)
449{
450 switch (param) {
451 case PIN_CONFIG_DRIVE_STRENGTH:
452 *offset = sunxi_dlevel_reg(pin);
453 *shift = sunxi_dlevel_offset(pin);
454 *mask = DLEVEL_PINS_MASK;
455 break;
456
457 case PIN_CONFIG_BIAS_PULL_UP:
458 case PIN_CONFIG_BIAS_PULL_DOWN:
459 case PIN_CONFIG_BIAS_DISABLE:
460 *offset = sunxi_pull_reg(pin);
461 *shift = sunxi_pull_offset(pin);
462 *mask = PULL_PINS_MASK;
463 break;
464
465 default:
466 return -ENOTSUPP;
467 }
468
469 return 0;
470}
471
472static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
473 unsigned long *config)
474{
475 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
476 enum pin_config_param param = pinconf_to_config_param(*config);
477 u32 offset, shift, mask, val;
478 u16 arg;
479 int ret;
480
481 pin -= pctl->desc->pin_base;
482
483 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
484 if (ret < 0)
485 return ret;
486
487 val = (readl(pctl->membase + offset) >> shift) & mask;
488
489 switch (pinconf_to_config_param(*config)) {
490 case PIN_CONFIG_DRIVE_STRENGTH:
491 arg = (val + 1) * 10;
492 break;
493
494 case PIN_CONFIG_BIAS_PULL_UP:
495 if (val != SUN4I_PINCTRL_PULL_UP)
496 return -EINVAL;
497 arg = 1;
498 break;
499
500 case PIN_CONFIG_BIAS_PULL_DOWN:
501 if (val != SUN4I_PINCTRL_PULL_DOWN)
502 return -EINVAL;
503 arg = 1;
504 break;
505
506 case PIN_CONFIG_BIAS_DISABLE:
507 if (val != SUN4I_PINCTRL_NO_PULL)
508 return -EINVAL;
509 arg = 0;
510 break;
511
512 default:
513
514 WARN_ON(1);
515 return -ENOTSUPP;
516 }
517
518 *config = pinconf_to_config_packed(param, arg);
519
520 return 0;
521}
522
523static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
524 unsigned group,
525 unsigned long *config)
526{
527 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
528 struct sunxi_pinctrl_group *g = &pctl->groups[group];
529
530
531 return sunxi_pconf_get(pctldev, g->pin, config);
532}
533
534static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
535 unsigned long *configs, unsigned num_configs)
536{
537 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
538 int i;
539
540 for (i = 0; i < num_configs; i++) {
541 enum pin_config_param param;
542 unsigned long flags;
543 u32 offset, shift, mask, reg;
544 u32 arg, val;
545 int ret;
546
547 param = pinconf_to_config_param(configs[i]);
548 arg = pinconf_to_config_argument(configs[i]);
549
550 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
551 if (ret < 0)
552 return ret;
553
554 switch (param) {
555 case PIN_CONFIG_DRIVE_STRENGTH:
556 if (arg < 10 || arg > 40)
557 return -EINVAL;
558
559
560
561
562
563
564
565 val = arg / 10 - 1;
566 break;
567 case PIN_CONFIG_BIAS_DISABLE:
568 val = 0;
569 break;
570 case PIN_CONFIG_BIAS_PULL_UP:
571 if (arg == 0)
572 return -EINVAL;
573 val = 1;
574 break;
575 case PIN_CONFIG_BIAS_PULL_DOWN:
576 if (arg == 0)
577 return -EINVAL;
578 val = 2;
579 break;
580 default:
581
582 WARN_ON(1);
583 return -ENOTSUPP;
584 }
585
586 raw_spin_lock_irqsave(&pctl->lock, flags);
587 reg = readl(pctl->membase + offset);
588 reg &= ~(mask << shift);
589 writel(reg | val << shift, pctl->membase + offset);
590 raw_spin_unlock_irqrestore(&pctl->lock, flags);
591 }
592
593 return 0;
594}
595
596static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
597 unsigned long *configs, unsigned num_configs)
598{
599 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
600 struct sunxi_pinctrl_group *g = &pctl->groups[group];
601
602
603 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
604}
605
606static const struct pinconf_ops sunxi_pconf_ops = {
607 .is_generic = true,
608 .pin_config_get = sunxi_pconf_get,
609 .pin_config_set = sunxi_pconf_set,
610 .pin_config_group_get = sunxi_pconf_group_get,
611 .pin_config_group_set = sunxi_pconf_group_set,
612};
613
614static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
615 unsigned pin,
616 struct regulator *supply)
617{
618 unsigned short bank = pin / PINS_PER_BANK;
619 unsigned long flags;
620 u32 val, reg;
621 int uV;
622
623 if (!pctl->desc->io_bias_cfg_variant)
624 return 0;
625
626 uV = regulator_get_voltage(supply);
627 if (uV < 0)
628 return uV;
629
630
631 if (uV == 0)
632 return 0;
633
634 switch (pctl->desc->io_bias_cfg_variant) {
635 case BIAS_VOLTAGE_GRP_CONFIG:
636
637
638
639
640 if (uV <= 1800000)
641 val = 0x0;
642 else if (uV <= 2500000)
643 val = 0x6;
644 else if (uV <= 2800000)
645 val = 0x9;
646 else if (uV <= 3000000)
647 val = 0xA;
648 else
649 val = 0xD;
650
651 pin -= pctl->desc->pin_base;
652
653 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
654 reg &= ~IO_BIAS_MASK;
655 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
656 return 0;
657 case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
658 val = uV <= 1800000 ? 1 : 0;
659
660 raw_spin_lock_irqsave(&pctl->lock, flags);
661 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
662 reg &= ~(1 << bank);
663 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
664 raw_spin_unlock_irqrestore(&pctl->lock, flags);
665 return 0;
666 default:
667 return -EINVAL;
668 }
669}
670
671static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
672{
673 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
674
675 return pctl->nfunctions;
676}
677
678static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
679 unsigned function)
680{
681 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
682
683 return pctl->functions[function].name;
684}
685
686static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
687 unsigned function,
688 const char * const **groups,
689 unsigned * const num_groups)
690{
691 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
692
693 *groups = pctl->functions[function].groups;
694 *num_groups = pctl->functions[function].ngroups;
695
696 return 0;
697}
698
699static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
700 unsigned pin,
701 u8 config)
702{
703 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
704 unsigned long flags;
705 u32 val, mask;
706
707 raw_spin_lock_irqsave(&pctl->lock, flags);
708
709 pin -= pctl->desc->pin_base;
710 val = readl(pctl->membase + sunxi_mux_reg(pin));
711 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
712 writel((val & ~mask) | config << sunxi_mux_offset(pin),
713 pctl->membase + sunxi_mux_reg(pin));
714
715 raw_spin_unlock_irqrestore(&pctl->lock, flags);
716}
717
718static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
719 unsigned function,
720 unsigned group)
721{
722 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
723 struct sunxi_pinctrl_group *g = pctl->groups + group;
724 struct sunxi_pinctrl_function *func = pctl->functions + function;
725 struct sunxi_desc_function *desc =
726 sunxi_pinctrl_desc_find_function_by_name(pctl,
727 g->name,
728 func->name);
729
730 if (!desc)
731 return -EINVAL;
732
733 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
734
735 return 0;
736}
737
738static int
739sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
740 struct pinctrl_gpio_range *range,
741 unsigned offset,
742 bool input)
743{
744 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
745 struct sunxi_desc_function *desc;
746 const char *func;
747
748 if (input)
749 func = "gpio_in";
750 else
751 func = "gpio_out";
752
753 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
754 if (!desc)
755 return -EINVAL;
756
757 sunxi_pmx_set(pctldev, offset, desc->muxval);
758
759 return 0;
760}
761
762static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
763{
764 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
765 unsigned short bank = offset / PINS_PER_BANK;
766 unsigned short bank_offset = bank - pctl->desc->pin_base /
767 PINS_PER_BANK;
768 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
769 struct regulator *reg = s_reg->regulator;
770 char supply[16];
771 int ret;
772
773 if (reg) {
774 refcount_inc(&s_reg->refcount);
775 return 0;
776 }
777
778 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
779 reg = regulator_get(pctl->dev, supply);
780 if (IS_ERR(reg)) {
781 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
782 'A' + bank);
783 return PTR_ERR(reg);
784 }
785
786 ret = regulator_enable(reg);
787 if (ret) {
788 dev_err(pctl->dev,
789 "Couldn't enable bank P%c regulator\n", 'A' + bank);
790 goto out;
791 }
792
793 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
794
795 s_reg->regulator = reg;
796 refcount_set(&s_reg->refcount, 1);
797
798 return 0;
799
800out:
801 regulator_put(s_reg->regulator);
802
803 return ret;
804}
805
806static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
807{
808 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
809 unsigned short bank = offset / PINS_PER_BANK;
810 unsigned short bank_offset = bank - pctl->desc->pin_base /
811 PINS_PER_BANK;
812 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
813
814 if (!refcount_dec_and_test(&s_reg->refcount))
815 return 0;
816
817 regulator_disable(s_reg->regulator);
818 regulator_put(s_reg->regulator);
819 s_reg->regulator = NULL;
820
821 return 0;
822}
823
824static const struct pinmux_ops sunxi_pmx_ops = {
825 .get_functions_count = sunxi_pmx_get_funcs_cnt,
826 .get_function_name = sunxi_pmx_get_func_name,
827 .get_function_groups = sunxi_pmx_get_func_groups,
828 .set_mux = sunxi_pmx_set_mux,
829 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
830 .request = sunxi_pmx_request,
831 .free = sunxi_pmx_free,
832 .strict = true,
833};
834
835static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
836 unsigned offset)
837{
838 return pinctrl_gpio_direction_input(chip->base + offset);
839}
840
841static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
842{
843 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
844 u32 reg = sunxi_data_reg(offset);
845 u8 index = sunxi_data_offset(offset);
846 bool set_mux = pctl->desc->irq_read_needs_mux &&
847 gpiochip_line_is_irq(chip, offset);
848 u32 pin = offset + chip->base;
849 u32 val;
850
851 if (set_mux)
852 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
853
854 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
855
856 if (set_mux)
857 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
858
859 return !!val;
860}
861
862static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
863 unsigned offset, int value)
864{
865 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
866 u32 reg = sunxi_data_reg(offset);
867 u8 index = sunxi_data_offset(offset);
868 unsigned long flags;
869 u32 regval;
870
871 raw_spin_lock_irqsave(&pctl->lock, flags);
872
873 regval = readl(pctl->membase + reg);
874
875 if (value)
876 regval |= BIT(index);
877 else
878 regval &= ~(BIT(index));
879
880 writel(regval, pctl->membase + reg);
881
882 raw_spin_unlock_irqrestore(&pctl->lock, flags);
883}
884
885static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
886 unsigned offset, int value)
887{
888 sunxi_pinctrl_gpio_set(chip, offset, value);
889 return pinctrl_gpio_direction_output(chip->base + offset);
890}
891
892static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
893 const struct of_phandle_args *gpiospec,
894 u32 *flags)
895{
896 int pin, base;
897
898 base = PINS_PER_BANK * gpiospec->args[0];
899 pin = base + gpiospec->args[1];
900
901 if (pin > gc->ngpio)
902 return -EINVAL;
903
904 if (flags)
905 *flags = gpiospec->args[2];
906
907 return pin;
908}
909
910static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
911{
912 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
913 struct sunxi_desc_function *desc;
914 unsigned pinnum = pctl->desc->pin_base + offset;
915 unsigned irqnum;
916
917 if (offset >= chip->ngpio)
918 return -ENXIO;
919
920 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
921 if (!desc)
922 return -EINVAL;
923
924 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
925
926 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
927 chip->label, offset + chip->base, irqnum);
928
929 return irq_find_mapping(pctl->domain, irqnum);
930}
931
932static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
933{
934 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
935 struct sunxi_desc_function *func;
936 int ret;
937
938 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
939 pctl->irq_array[d->hwirq], "irq");
940 if (!func)
941 return -EINVAL;
942
943 ret = gpiochip_lock_as_irq(pctl->chip,
944 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
945 if (ret) {
946 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
947 irqd_to_hwirq(d));
948 return ret;
949 }
950
951
952 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
953
954 return 0;
955}
956
957static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
958{
959 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
960
961 gpiochip_unlock_as_irq(pctl->chip,
962 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
963}
964
965static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
966{
967 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
968 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
969 u8 index = sunxi_irq_cfg_offset(d->hwirq);
970 unsigned long flags;
971 u32 regval;
972 u8 mode;
973
974 switch (type) {
975 case IRQ_TYPE_EDGE_RISING:
976 mode = IRQ_EDGE_RISING;
977 break;
978 case IRQ_TYPE_EDGE_FALLING:
979 mode = IRQ_EDGE_FALLING;
980 break;
981 case IRQ_TYPE_EDGE_BOTH:
982 mode = IRQ_EDGE_BOTH;
983 break;
984 case IRQ_TYPE_LEVEL_HIGH:
985 mode = IRQ_LEVEL_HIGH;
986 break;
987 case IRQ_TYPE_LEVEL_LOW:
988 mode = IRQ_LEVEL_LOW;
989 break;
990 default:
991 return -EINVAL;
992 }
993
994 raw_spin_lock_irqsave(&pctl->lock, flags);
995
996 if (type & IRQ_TYPE_LEVEL_MASK)
997 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
998 handle_fasteoi_irq, NULL);
999 else
1000 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1001 handle_edge_irq, NULL);
1002
1003 regval = readl(pctl->membase + reg);
1004 regval &= ~(IRQ_CFG_IRQ_MASK << index);
1005 writel(regval | (mode << index), pctl->membase + reg);
1006
1007 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1008
1009 return 0;
1010}
1011
1012static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1013{
1014 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1015 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1016 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1017
1018
1019 writel(1 << status_idx, pctl->membase + status_reg);
1020}
1021
1022static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1023{
1024 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1025 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1026 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1027 unsigned long flags;
1028 u32 val;
1029
1030 raw_spin_lock_irqsave(&pctl->lock, flags);
1031
1032
1033 val = readl(pctl->membase + reg);
1034 writel(val & ~(1 << idx), pctl->membase + reg);
1035
1036 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1037}
1038
1039static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1040{
1041 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1042 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1043 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1044 unsigned long flags;
1045 u32 val;
1046
1047 raw_spin_lock_irqsave(&pctl->lock, flags);
1048
1049
1050 val = readl(pctl->membase + reg);
1051 writel(val | (1 << idx), pctl->membase + reg);
1052
1053 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1054}
1055
1056static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1057{
1058 sunxi_pinctrl_irq_ack(d);
1059 sunxi_pinctrl_irq_unmask(d);
1060}
1061
1062static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1063{
1064 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1065 u8 bank = d->hwirq / IRQ_PER_BANK;
1066
1067 return irq_set_irq_wake(pctl->irq[bank], on);
1068}
1069
1070static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1071 .name = "sunxi_pio_edge",
1072 .irq_ack = sunxi_pinctrl_irq_ack,
1073 .irq_mask = sunxi_pinctrl_irq_mask,
1074 .irq_unmask = sunxi_pinctrl_irq_unmask,
1075 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1076 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1077 .irq_set_type = sunxi_pinctrl_irq_set_type,
1078 .irq_set_wake = sunxi_pinctrl_irq_set_wake,
1079 .flags = IRQCHIP_MASK_ON_SUSPEND,
1080};
1081
1082static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1083 .name = "sunxi_pio_level",
1084 .irq_eoi = sunxi_pinctrl_irq_ack,
1085 .irq_mask = sunxi_pinctrl_irq_mask,
1086 .irq_unmask = sunxi_pinctrl_irq_unmask,
1087
1088
1089 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
1090 .irq_disable = sunxi_pinctrl_irq_mask,
1091 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1092 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1093 .irq_set_type = sunxi_pinctrl_irq_set_type,
1094 .irq_set_wake = sunxi_pinctrl_irq_set_wake,
1095 .flags = IRQCHIP_EOI_THREADED |
1096 IRQCHIP_MASK_ON_SUSPEND |
1097 IRQCHIP_EOI_IF_HANDLED,
1098};
1099
1100static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1101 struct device_node *node,
1102 const u32 *intspec,
1103 unsigned int intsize,
1104 unsigned long *out_hwirq,
1105 unsigned int *out_type)
1106{
1107 struct sunxi_pinctrl *pctl = d->host_data;
1108 struct sunxi_desc_function *desc;
1109 int pin, base;
1110
1111 if (intsize < 3)
1112 return -EINVAL;
1113
1114 base = PINS_PER_BANK * intspec[0];
1115 pin = pctl->desc->pin_base + base + intspec[1];
1116
1117 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1118 if (!desc)
1119 return -EINVAL;
1120
1121 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1122 *out_type = intspec[2];
1123
1124 return 0;
1125}
1126
1127static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1128 .xlate = sunxi_pinctrl_irq_of_xlate,
1129};
1130
1131static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1132{
1133 unsigned int irq = irq_desc_get_irq(desc);
1134 struct irq_chip *chip = irq_desc_get_chip(desc);
1135 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1136 unsigned long bank, reg, val;
1137
1138 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1139 if (irq == pctl->irq[bank])
1140 break;
1141
1142 WARN_ON(bank == pctl->desc->irq_banks);
1143
1144 chained_irq_enter(chip, desc);
1145
1146 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1147 val = readl(pctl->membase + reg);
1148
1149 if (val) {
1150 int irqoffset;
1151
1152 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1153 generic_handle_domain_irq(pctl->domain,
1154 bank * IRQ_PER_BANK + irqoffset);
1155 }
1156
1157 chained_irq_exit(chip, desc);
1158}
1159
1160static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1161 const char *name)
1162{
1163 struct sunxi_pinctrl_function *func = pctl->functions;
1164
1165 while (func->name) {
1166
1167 if (strcmp(func->name, name) == 0) {
1168 func->ngroups++;
1169 return -EEXIST;
1170 }
1171 func++;
1172 }
1173
1174 func->name = name;
1175 func->ngroups = 1;
1176
1177 pctl->nfunctions++;
1178
1179 return 0;
1180}
1181
1182static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1183{
1184 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1185 void *ptr;
1186 int i;
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199 pctl->groups = devm_kcalloc(&pdev->dev,
1200 pctl->desc->npins, sizeof(*pctl->groups),
1201 GFP_KERNEL);
1202 if (!pctl->groups)
1203 return -ENOMEM;
1204
1205 for (i = 0; i < pctl->desc->npins; i++) {
1206 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1207 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1208
1209 if (pin->variant && !(pctl->variant & pin->variant))
1210 continue;
1211
1212 group->name = pin->pin.name;
1213 group->pin = pin->pin.number;
1214
1215
1216 pctl->ngroups++;
1217 }
1218
1219
1220
1221
1222
1223
1224
1225 pctl->functions = kcalloc(4 * pctl->ngroups + 4,
1226 sizeof(*pctl->functions),
1227 GFP_KERNEL);
1228 if (!pctl->functions)
1229 return -ENOMEM;
1230
1231
1232 for (i = 0; i < pctl->desc->npins; i++) {
1233 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1234 struct sunxi_desc_function *func;
1235
1236 if (pin->variant && !(pctl->variant & pin->variant))
1237 continue;
1238
1239 for (func = pin->functions; func->name; func++) {
1240 if (func->variant && !(pctl->variant & func->variant))
1241 continue;
1242
1243
1244 if (!strcmp(func->name, "irq")) {
1245 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1246 pctl->irq_array[irqnum] = pin->pin.number;
1247 }
1248
1249 sunxi_pinctrl_add_function(pctl, func->name);
1250 }
1251 }
1252
1253
1254 ptr = krealloc(pctl->functions,
1255 pctl->nfunctions * sizeof(*pctl->functions),
1256 GFP_KERNEL);
1257 if (!ptr) {
1258 kfree(pctl->functions);
1259 pctl->functions = NULL;
1260 return -ENOMEM;
1261 }
1262 pctl->functions = ptr;
1263
1264 for (i = 0; i < pctl->desc->npins; i++) {
1265 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1266 struct sunxi_desc_function *func;
1267
1268 if (pin->variant && !(pctl->variant & pin->variant))
1269 continue;
1270
1271 for (func = pin->functions; func->name; func++) {
1272 struct sunxi_pinctrl_function *func_item;
1273 const char **func_grp;
1274
1275 if (func->variant && !(pctl->variant & func->variant))
1276 continue;
1277
1278 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1279 func->name);
1280 if (!func_item) {
1281 kfree(pctl->functions);
1282 return -EINVAL;
1283 }
1284
1285 if (!func_item->groups) {
1286 func_item->groups =
1287 devm_kcalloc(&pdev->dev,
1288 func_item->ngroups,
1289 sizeof(*func_item->groups),
1290 GFP_KERNEL);
1291 if (!func_item->groups) {
1292 kfree(pctl->functions);
1293 return -ENOMEM;
1294 }
1295 }
1296
1297 func_grp = func_item->groups;
1298 while (*func_grp)
1299 func_grp++;
1300
1301 *func_grp = pin->pin.name;
1302 }
1303 }
1304
1305 return 0;
1306}
1307
1308static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1309{
1310 unsigned long clock = clk_get_rate(clk);
1311 unsigned int best_diff, best_div;
1312 int i;
1313
1314 best_diff = abs(freq - clock);
1315 best_div = 0;
1316
1317 for (i = 1; i < 8; i++) {
1318 int cur_diff = abs(freq - (clock >> i));
1319
1320 if (cur_diff < best_diff) {
1321 best_diff = cur_diff;
1322 best_div = i;
1323 }
1324 }
1325
1326 *diff = best_diff;
1327 return best_div;
1328}
1329
1330static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1331 struct device_node *node)
1332{
1333 unsigned int hosc_diff, losc_diff;
1334 unsigned int hosc_div, losc_div;
1335 struct clk *hosc, *losc;
1336 u8 div, src;
1337 int i, ret;
1338
1339
1340 if (of_clk_get_parent_count(node) != 3)
1341 return 0;
1342
1343
1344 if (!of_find_property(node, "input-debounce", NULL))
1345 return 0;
1346
1347 losc = devm_clk_get(pctl->dev, "losc");
1348 if (IS_ERR(losc))
1349 return PTR_ERR(losc);
1350
1351 hosc = devm_clk_get(pctl->dev, "hosc");
1352 if (IS_ERR(hosc))
1353 return PTR_ERR(hosc);
1354
1355 for (i = 0; i < pctl->desc->irq_banks; i++) {
1356 unsigned long debounce_freq;
1357 u32 debounce;
1358
1359 ret = of_property_read_u32_index(node, "input-debounce",
1360 i, &debounce);
1361 if (ret)
1362 return ret;
1363
1364 if (!debounce)
1365 continue;
1366
1367 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1368 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1369 debounce_freq,
1370 &losc_diff);
1371
1372 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1373 debounce_freq,
1374 &hosc_diff);
1375
1376 if (hosc_diff < losc_diff) {
1377 div = hosc_div;
1378 src = 1;
1379 } else {
1380 div = losc_div;
1381 src = 0;
1382 }
1383
1384 writel(src | div << 4,
1385 pctl->membase +
1386 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1387 }
1388
1389 return 0;
1390}
1391
1392int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1393 const struct sunxi_pinctrl_desc *desc,
1394 unsigned long variant)
1395{
1396 struct device_node *node = pdev->dev.of_node;
1397 struct pinctrl_desc *pctrl_desc;
1398 struct pinctrl_pin_desc *pins;
1399 struct sunxi_pinctrl *pctl;
1400 struct pinmux_ops *pmxops;
1401 int i, ret, last_pin, pin_idx;
1402 struct clk *clk;
1403
1404 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1405 if (!pctl)
1406 return -ENOMEM;
1407 platform_set_drvdata(pdev, pctl);
1408
1409 raw_spin_lock_init(&pctl->lock);
1410
1411 pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1412 if (IS_ERR(pctl->membase))
1413 return PTR_ERR(pctl->membase);
1414
1415 pctl->dev = &pdev->dev;
1416 pctl->desc = desc;
1417 pctl->variant = variant;
1418
1419 pctl->irq_array = devm_kcalloc(&pdev->dev,
1420 IRQ_PER_BANK * pctl->desc->irq_banks,
1421 sizeof(*pctl->irq_array),
1422 GFP_KERNEL);
1423 if (!pctl->irq_array)
1424 return -ENOMEM;
1425
1426 ret = sunxi_pinctrl_build_state(pdev);
1427 if (ret) {
1428 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1429 return ret;
1430 }
1431
1432 pins = devm_kcalloc(&pdev->dev,
1433 pctl->desc->npins, sizeof(*pins),
1434 GFP_KERNEL);
1435 if (!pins)
1436 return -ENOMEM;
1437
1438 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1439 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1440
1441 if (pin->variant && !(pctl->variant & pin->variant))
1442 continue;
1443
1444 pins[pin_idx++] = pin->pin;
1445 }
1446
1447 pctrl_desc = devm_kzalloc(&pdev->dev,
1448 sizeof(*pctrl_desc),
1449 GFP_KERNEL);
1450 if (!pctrl_desc)
1451 return -ENOMEM;
1452
1453 pctrl_desc->name = dev_name(&pdev->dev);
1454 pctrl_desc->owner = THIS_MODULE;
1455 pctrl_desc->pins = pins;
1456 pctrl_desc->npins = pctl->ngroups;
1457 pctrl_desc->confops = &sunxi_pconf_ops;
1458 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1459
1460 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1461 GFP_KERNEL);
1462 if (!pmxops)
1463 return -ENOMEM;
1464
1465 if (desc->disable_strict_mode)
1466 pmxops->strict = false;
1467
1468 pctrl_desc->pmxops = pmxops;
1469
1470 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1471 if (IS_ERR(pctl->pctl_dev)) {
1472 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1473 return PTR_ERR(pctl->pctl_dev);
1474 }
1475
1476 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1477 if (!pctl->chip)
1478 return -ENOMEM;
1479
1480 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1481 pctl->chip->owner = THIS_MODULE;
1482 pctl->chip->request = gpiochip_generic_request;
1483 pctl->chip->free = gpiochip_generic_free;
1484 pctl->chip->set_config = gpiochip_generic_config;
1485 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1486 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1487 pctl->chip->get = sunxi_pinctrl_gpio_get;
1488 pctl->chip->set = sunxi_pinctrl_gpio_set;
1489 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1490 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1491 pctl->chip->of_gpio_n_cells = 3;
1492 pctl->chip->can_sleep = false;
1493 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1494 pctl->desc->pin_base;
1495 pctl->chip->label = dev_name(&pdev->dev);
1496 pctl->chip->parent = &pdev->dev;
1497 pctl->chip->base = pctl->desc->pin_base;
1498
1499 ret = gpiochip_add_data(pctl->chip, pctl);
1500 if (ret)
1501 return ret;
1502
1503 for (i = 0; i < pctl->desc->npins; i++) {
1504 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1505
1506 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1507 pin->pin.number - pctl->desc->pin_base,
1508 pin->pin.number, 1);
1509 if (ret)
1510 goto gpiochip_error;
1511 }
1512
1513 ret = of_clk_get_parent_count(node);
1514 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1515 if (IS_ERR(clk)) {
1516 ret = PTR_ERR(clk);
1517 goto gpiochip_error;
1518 }
1519
1520 ret = clk_prepare_enable(clk);
1521 if (ret)
1522 goto gpiochip_error;
1523
1524 pctl->irq = devm_kcalloc(&pdev->dev,
1525 pctl->desc->irq_banks,
1526 sizeof(*pctl->irq),
1527 GFP_KERNEL);
1528 if (!pctl->irq) {
1529 ret = -ENOMEM;
1530 goto clk_error;
1531 }
1532
1533 for (i = 0; i < pctl->desc->irq_banks; i++) {
1534 pctl->irq[i] = platform_get_irq(pdev, i);
1535 if (pctl->irq[i] < 0) {
1536 ret = pctl->irq[i];
1537 goto clk_error;
1538 }
1539 }
1540
1541 pctl->domain = irq_domain_add_linear(node,
1542 pctl->desc->irq_banks * IRQ_PER_BANK,
1543 &sunxi_pinctrl_irq_domain_ops,
1544 pctl);
1545 if (!pctl->domain) {
1546 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1547 ret = -ENOMEM;
1548 goto clk_error;
1549 }
1550
1551 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1552 int irqno = irq_create_mapping(pctl->domain, i);
1553
1554 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1555 handle_edge_irq);
1556 irq_set_chip_data(irqno, pctl);
1557 }
1558
1559 for (i = 0; i < pctl->desc->irq_banks; i++) {
1560
1561 writel(0, pctl->membase +
1562 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1563 writel(0xffffffff,
1564 pctl->membase +
1565 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1566
1567 irq_set_chained_handler_and_data(pctl->irq[i],
1568 sunxi_pinctrl_irq_handler,
1569 pctl);
1570 }
1571
1572 sunxi_pinctrl_setup_debounce(pctl, node);
1573
1574 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1575
1576 return 0;
1577
1578clk_error:
1579 clk_disable_unprepare(clk);
1580gpiochip_error:
1581 gpiochip_remove(pctl->chip);
1582 return ret;
1583}
1584
