LXR linux/drivers/pwm/pwm-omap-dmtimer.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
   4 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
   5 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
   6 * Heavily based on earlier code which is:
   7 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
   8 *
   9 * Also based on pwm-samsung.c
  10 *
  11 * Description:
  12 *   This file is the core OMAP support for the generic, Linux
  13 *   PWM driver / controller, using the OMAP's dual-mode timers
  14 *   with a timer counter that goes up. When it overflows it gets
  15 *   reloaded with the load value and the pwm output goes up.
  16 *   When counter matches with match register, the output goes down.
  17 *   Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
  18 *
  19 * Limitations:
  20 * - When PWM is stopped, timer counter gets stopped immediately. This
  21 *   doesn't allow the current PWM period to complete and stops abruptly.
  22 * - When PWM is running and changing both duty cycle and period,
  23 *   we cannot prevent in software that the output might produce
  24 *   a period with mixed settings. Especially when period/duty_cyle
  25 *   is updated while the pwm pin is high, current pwm period/duty_cycle
  26 *   can get updated as below based on the current timer counter:
  27 *      - period for current cycle =  current_period + new period
  28 *      - duty_cycle for current period = current period + new duty_cycle.
  29 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
  30 *   user requests a change in polarity when in active state:
  31 *      - PWM is stopped abruptly(without completing the current cycle)
  32 *      - Polarity is changed
  33 *      - A fresh cycle is started.
  34 */
  35
  36#include <linux/clk.h>
  37#include <linux/err.h>
  38#include <linux/kernel.h>
  39#include <linux/module.h>
  40#include <linux/mutex.h>
  41#include <linux/of.h>
  42#include <linux/of_platform.h>
  43#include <clocksource/timer-ti-dm.h>
  44#include <linux/platform_data/dmtimer-omap.h>
  45#include <linux/platform_device.h>
  46#include <linux/pm_runtime.h>
  47#include <linux/pwm.h>
  48#include <linux/slab.h>
  49#include <linux/time.h>
  50
  51#define DM_TIMER_LOAD_MIN 0xfffffffe
  52#define DM_TIMER_MAX      0xffffffff
  53
  54/**
  55 * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
  56 *                                corresponding to omap dmtimer.
  57 * @chip:               PWM chip structure representing PWM controller
  58 * @mutex:              Mutex to protect pwm apply state
  59 * @dm_timer:           Pointer to omap dm timer.
  60 * @pdata:              Pointer to omap dm timer ops.
  61 * @dm_timer_pdev:      Pointer to omap dm timer platform device
  62 */
  63struct pwm_omap_dmtimer_chip {
  64        struct pwm_chip chip;
  65        /* Mutex to protect pwm apply state */
  66        struct mutex mutex;
  67        struct omap_dm_timer *dm_timer;
  68        const struct omap_dm_timer_ops *pdata;
  69        struct platform_device *dm_timer_pdev;
  70};
  71
  72static inline struct pwm_omap_dmtimer_chip *
  73to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  74{
  75        return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
  76}
  77
  78/**
  79 * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
  80 * @clk_rate:   pwm timer clock rate
  81 * @ns:         time frame in nano seconds.
  82 *
  83 * Return number of clock cycles in a given period(ins ns).
  84 */
  85static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  86{
  87        return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
  88}
  89
  90/**
  91 * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
  92 * @omap:       Pointer to pwm omap dm timer chip
  93 */
  94static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  95{
  96        /*
  97         * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  98         * started at 0xFFFFFFFE when overflow and match is used to ensure
  99         * that the PWM line is toggled on the first event.
 100         *
 101         * Note that omap_dm_timer_enable/disable is for register access and
 102         * not the timer counter itself.
 103         */
 104        omap->pdata->enable(omap->dm_timer);
 105        omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
 106        omap->pdata->disable(omap->dm_timer);
 107
 108        omap->pdata->start(omap->dm_timer);
 109}
 110
 111/**
 112 * pwm_omap_dmtimer_is_enabled() -  Detect if the pwm is enabled.
 113 * @omap:       Pointer to pwm omap dm timer chip
 114 *
 115 * Return true if pwm is enabled else false.
 116 */
 117static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
 118{
 119        u32 status;
 120
 121        status = omap->pdata->get_pwm_status(omap->dm_timer);
 122
 123        return !!(status & OMAP_TIMER_CTRL_ST);
 124}
 125
 126/**
 127 * pwm_omap_dmtimer_polarity() -  Detect the polarity of pwm.
 128 * @omap:       Pointer to pwm omap dm timer chip
 129 *
 130 * Return the polarity of pwm.
 131 */
 132static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
 133{
 134        u32 status;
 135
 136        status = omap->pdata->get_pwm_status(omap->dm_timer);
 137
 138        return !!(status & OMAP_TIMER_CTRL_SCPWM);
 139}
 140
 141/**
 142 * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
 143 * @chip:       Pointer to PWM controller
 144 * @pwm:        Pointer to PWM channel
 145 * @duty_ns:    New duty cycle in nano seconds
 146 * @period_ns:  New period in nano seconds
 147 *
 148 * Return 0 if successfully changed the period/duty_cycle else appropriate
 149 * error.
 150 */
 151static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
 152                                   struct pwm_device *pwm,
 153                                   int duty_ns, int period_ns)
 154{
 155        struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 156        u32 period_cycles, duty_cycles;
 157        u32 load_value, match_value;
 158        unsigned long clk_rate;
 159        struct clk *fclk;
 160
 161        dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
 162                duty_ns, period_ns);
 163
 164        if (duty_ns == pwm_get_duty_cycle(pwm) &&
 165            period_ns == pwm_get_period(pwm))
 166                return 0;
 167
 168        fclk = omap->pdata->get_fclk(omap->dm_timer);
 169        if (!fclk) {
 170                dev_err(chip->dev, "invalid pmtimer fclk\n");
 171                return -EINVAL;
 172        }
 173
 174        clk_rate = clk_get_rate(fclk);
 175        if (!clk_rate) {
 176                dev_err(chip->dev, "invalid pmtimer fclk rate\n");
 177                return -EINVAL;
 178        }
 179
 180        dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
 181
 182        /*
 183         * Calculate the appropriate load and match values based on the
 184         * specified period and duty cycle. The load value determines the
 185         * period time and the match value determines the duty time.
 186         *
 187         * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
 188         * Similarly, the active time lasts (match_value-load_value+1) cycles.
 189         * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
 190         * clock cycles.
 191         *
 192         * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
 193         *
 194         * References:
 195         *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
 196         *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
 197         */
 198        period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
 199        duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
 200
 201        if (period_cycles < 2) {
 202                dev_info(chip->dev,
 203                         "period %d ns too short for clock rate %lu Hz\n",
 204                         period_ns, clk_rate);
 205                return -EINVAL;
 206        }
 207
 208        if (duty_cycles < 1) {
 209                dev_dbg(chip->dev,
 210                        "duty cycle %d ns is too short for clock rate %lu Hz\n",
 211                        duty_ns, clk_rate);
 212                dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
 213                duty_cycles = 1;
 214        } else if (duty_cycles >= period_cycles) {
 215                dev_dbg(chip->dev,
 216                        "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
 217                        duty_ns, period_ns, clk_rate);
 218                dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
 219                duty_cycles = period_cycles - 1;
 220        }
 221
 222        dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
 223                DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
 224                                      clk_rate),
 225                DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
 226                                      clk_rate));
 227
 228        load_value = (DM_TIMER_MAX - period_cycles) + 1;
 229        match_value = load_value + duty_cycles - 1;
 230
 231        omap->pdata->set_load(omap->dm_timer, load_value);
 232        omap->pdata->set_match(omap->dm_timer, true, match_value);
 233
 234        dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
 235                load_value, load_value, match_value, match_value);
 236
 237        return 0;
 238}
 239
 240/**
 241 * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
 242 * @chip:       Pointer to PWM controller
 243 * @pwm:        Pointer to PWM channel
 244 * @polarity:   New pwm polarity to be set
 245 */
 246static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
 247                                          struct pwm_device *pwm,
 248                                          enum pwm_polarity polarity)
 249{
 250        struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 251        bool enabled;
 252
 253        /* Disable the PWM before changing the polarity. */
 254        enabled = pwm_omap_dmtimer_is_enabled(omap);
 255        if (enabled)
 256                omap->pdata->stop(omap->dm_timer);
 257
 258        omap->pdata->set_pwm(omap->dm_timer,
 259                             polarity == PWM_POLARITY_INVERSED,
 260                             true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
 261                             true);
 262
 263        if (enabled)
 264                pwm_omap_dmtimer_start(omap);
 265}
 266
 267/**
 268 * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
 269 * @chip:       Pointer to PWM controller
 270 * @pwm:        Pointer to PWM channel
 271 * @state:      New state to apply
 272 *
 273 * Return 0 if successfully changed the state else appropriate error.
 274 */
 275static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
 276                                  struct pwm_device *pwm,
 277                                  const struct pwm_state *state)
 278{
 279        struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 280        int ret = 0;
 281
 282        mutex_lock(&omap->mutex);
 283
 284        if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
 285                omap->pdata->stop(omap->dm_timer);
 286                goto unlock_mutex;
 287        }
 288
 289        if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
 290                pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
 291
 292        ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
 293                                      state->period);
 294        if (ret)
 295                goto unlock_mutex;
 296
 297        if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
 298                omap->pdata->set_pwm(omap->dm_timer,
 299                                     state->polarity == PWM_POLARITY_INVERSED,
 300                                     true,
 301                                     OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
 302                                     true);
 303                pwm_omap_dmtimer_start(omap);
 304        }
 305
 306unlock_mutex:
 307        mutex_unlock(&omap->mutex);
 308
 309        return ret;
 310}
 311
 312static const struct pwm_ops pwm_omap_dmtimer_ops = {
 313        .apply = pwm_omap_dmtimer_apply,
 314        .owner = THIS_MODULE,
 315};
 316
 317static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
 318{
 319        struct device_node *np = pdev->dev.of_node;
 320        struct dmtimer_platform_data *timer_pdata;
 321        const struct omap_dm_timer_ops *pdata;
 322        struct platform_device *timer_pdev;
 323        struct pwm_omap_dmtimer_chip *omap;
 324        struct omap_dm_timer *dm_timer;
 325        struct device_node *timer;
 326        int ret = 0;
 327        u32 v;
 328
 329        timer = of_parse_phandle(np, "ti,timers", 0);
 330        if (!timer)
 331                return -ENODEV;
 332
 333        timer_pdev = of_find_device_by_node(timer);
 334        if (!timer_pdev) {
 335                dev_err(&pdev->dev, "Unable to find Timer pdev\n");
 336                ret = -ENODEV;
 337                goto err_find_timer_pdev;
 338        }
 339
 340        timer_pdata = dev_get_platdata(&timer_pdev->dev);
 341        if (!timer_pdata) {
 342                dev_dbg(&pdev->dev,
 343                         "dmtimer pdata structure NULL, deferring probe\n");
 344                ret = -EPROBE_DEFER;
 345                goto err_platdata;
 346        }
 347
 348        pdata = timer_pdata->timer_ops;
 349
 350        if (!pdata || !pdata->request_by_node ||
 351            !pdata->free ||
 352            !pdata->enable ||
 353            !pdata->disable ||
 354            !pdata->get_fclk ||
 355            !pdata->start ||
 356            !pdata->stop ||
 357            !pdata->set_load ||
 358            !pdata->set_match ||
 359            !pdata->set_pwm ||
 360            !pdata->get_pwm_status ||
 361            !pdata->set_prescaler ||
 362            !pdata->write_counter) {
 363                dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
 364                ret = -EINVAL;
 365                goto err_platdata;
 366        }
 367
 368        if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
 369                dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
 370                ret = -ENODEV;
 371                goto err_timer_property;
 372        }
 373
 374        dm_timer = pdata->request_by_node(timer);
 375        if (!dm_timer) {
 376                ret = -EPROBE_DEFER;
 377                goto err_request_timer;
 378        }
 379
 380        omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
 381        if (!omap) {
 382                ret = -ENOMEM;
 383                goto err_alloc_omap;
 384        }
 385
 386        omap->pdata = pdata;
 387        omap->dm_timer = dm_timer;
 388        omap->dm_timer_pdev = timer_pdev;
 389
 390        /*
 391         * Ensure that the timer is stopped before we allow PWM core to call
 392         * pwm_enable.
 393         */
 394        if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 395                omap->pdata->stop(omap->dm_timer);
 396
 397        if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
 398                omap->pdata->set_prescaler(omap->dm_timer, v);
 399
 400        /* setup dmtimer clock source */
 401        if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
 402                omap->pdata->set_source(omap->dm_timer, v);
 403
 404        omap->chip.dev = &pdev->dev;
 405        omap->chip.ops = &pwm_omap_dmtimer_ops;
 406        omap->chip.npwm = 1;
 407
 408        mutex_init(&omap->mutex);
 409
 410        ret = pwmchip_add(&omap->chip);
 411        if (ret < 0) {
 412                dev_err(&pdev->dev, "failed to register PWM\n");
 413                goto err_pwmchip_add;
 414        }
 415
 416        of_node_put(timer);
 417
 418        platform_set_drvdata(pdev, omap);
 419
 420        return 0;
 421
 422err_pwmchip_add:
 423
 424        /*
 425         * *omap is allocated using devm_kzalloc,
 426         * so no free necessary here
 427         */
 428err_alloc_omap:
 429
 430        pdata->free(dm_timer);
 431err_request_timer:
 432
 433err_timer_property:
 434err_platdata:
 435
 436        put_device(&timer_pdev->dev);
 437err_find_timer_pdev:
 438
 439        of_node_put(timer);
 440
 441        return ret;
 442}
 443
 444static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
 445{
 446        struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
 447
 448        pwmchip_remove(&omap->chip);
 449
 450        if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 451                omap->pdata->stop(omap->dm_timer);
 452
 453        omap->pdata->free(omap->dm_timer);
 454
 455        put_device(&omap->dm_timer_pdev->dev);
 456
 457        mutex_destroy(&omap->mutex);
 458
 459        return 0;
 460}
 461
 462static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
 463        {.compatible = "ti,omap-dmtimer-pwm"},
 464        {}
 465};
 466MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
 467
 468static struct platform_driver pwm_omap_dmtimer_driver = {
 469        .driver = {
 470                .name = "omap-dmtimer-pwm",
 471                .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
 472        },
 473        .probe = pwm_omap_dmtimer_probe,
 474        .remove = pwm_omap_dmtimer_remove,
 475};
 476module_platform_driver(pwm_omap_dmtimer_driver);
 477
 478MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
 479MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
 480MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 481MODULE_LICENSE("GPL v2");
 482MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
 483