linux/drivers/reset/reset-microchip-sparx5.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/* Microchip Sparx5 Switch Reset driver
   3 *
   4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   5 *
   6 * The Sparx5 Chip Register Model can be browsed at this location:
   7 * https://github.com/microchip-ung/sparx-5_reginfo
   8 */
   9#include <linux/mfd/syscon.h>
  10#include <linux/of_device.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14#include <linux/reset-controller.h>
  15
  16#define PROTECT_REG    0x84
  17#define PROTECT_BIT    BIT(10)
  18#define SOFT_RESET_REG 0x00
  19#define SOFT_RESET_BIT BIT(1)
  20
  21struct mchp_reset_context {
  22        struct regmap *cpu_ctrl;
  23        struct regmap *gcb_ctrl;
  24        struct reset_controller_dev rcdev;
  25};
  26
  27static struct regmap_config sparx5_reset_regmap_config = {
  28        .reg_bits       = 32,
  29        .val_bits       = 32,
  30        .reg_stride     = 4,
  31};
  32
  33static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
  34                               unsigned long id)
  35{
  36        struct mchp_reset_context *ctx =
  37                container_of(rcdev, struct mchp_reset_context, rcdev);
  38        u32 val;
  39
  40        /* Make sure the core is PROTECTED from reset */
  41        regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
  42
  43        /* Start soft reset */
  44        regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
  45
  46        /* Wait for soft reset done */
  47        return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
  48                                        (val & SOFT_RESET_BIT) == 0,
  49                                        1, 100);
  50}
  51
  52static const struct reset_control_ops sparx5_reset_ops = {
  53        .reset = sparx5_switch_reset,
  54};
  55
  56static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
  57                                  struct regmap **target)
  58{
  59        struct device_node *syscon_np;
  60        struct regmap *regmap;
  61        int err;
  62
  63        syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
  64        if (!syscon_np)
  65                return -ENODEV;
  66        regmap = syscon_node_to_regmap(syscon_np);
  67        of_node_put(syscon_np);
  68        if (IS_ERR(regmap)) {
  69                err = PTR_ERR(regmap);
  70                dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
  71                return err;
  72        }
  73        *target = regmap;
  74        return 0;
  75}
  76
  77static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
  78                              struct regmap **target)
  79{
  80        struct resource *res;
  81        struct regmap *map;
  82        void __iomem *mem;
  83
  84        mem = devm_platform_get_and_ioremap_resource(pdev, index, &res);
  85        if (IS_ERR(mem)) {
  86                dev_err(&pdev->dev, "Could not map resource %d\n", index);
  87                return PTR_ERR(mem);
  88        }
  89        sparx5_reset_regmap_config.name = res->name;
  90        map = devm_regmap_init_mmio(&pdev->dev, mem, &sparx5_reset_regmap_config);
  91        if (IS_ERR(map))
  92                return PTR_ERR(map);
  93        *target = map;
  94        return 0;
  95}
  96
  97static int mchp_sparx5_reset_probe(struct platform_device *pdev)
  98{
  99        struct device_node *dn = pdev->dev.of_node;
 100        struct mchp_reset_context *ctx;
 101        int err;
 102
 103        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
 104        if (!ctx)
 105                return -ENOMEM;
 106
 107        err = mchp_sparx5_map_syscon(pdev, "cpu-syscon", &ctx->cpu_ctrl);
 108        if (err)
 109                return err;
 110        err = mchp_sparx5_map_io(pdev, 0, &ctx->gcb_ctrl);
 111        if (err)
 112                return err;
 113
 114        ctx->rcdev.owner = THIS_MODULE;
 115        ctx->rcdev.nr_resets = 1;
 116        ctx->rcdev.ops = &sparx5_reset_ops;
 117        ctx->rcdev.of_node = dn;
 118
 119        return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
 120}
 121
 122static const struct of_device_id mchp_sparx5_reset_of_match[] = {
 123        {
 124                .compatible = "microchip,sparx5-switch-reset",
 125        },
 126        { }
 127};
 128
 129static struct platform_driver mchp_sparx5_reset_driver = {
 130        .probe = mchp_sparx5_reset_probe,
 131        .driver = {
 132                .name = "sparx5-switch-reset",
 133                .of_match_table = mchp_sparx5_reset_of_match,
 134        },
 135};
 136
 137static int __init mchp_sparx5_reset_init(void)
 138{
 139        return platform_driver_register(&mchp_sparx5_reset_driver);
 140}
 141
 142postcore_initcall(mchp_sparx5_reset_init);
 143
 144MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
 145MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
 146MODULE_LICENSE("Dual MIT/GPL");
 147