LXR linux/drivers/rtc/rtc-ab-b5ze-s3.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
   4 *                  I2C RTC / Alarm chip
   5 *
   6 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
   7 *
   8 * Detailed datasheet of the chip is available here:
   9 *
  10 *  https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
  11 *
  12 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
  13 *
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/rtc.h>
  18#include <linux/i2c.h>
  19#include <linux/bcd.h>
  20#include <linux/of.h>
  21#include <linux/regmap.h>
  22#include <linux/interrupt.h>
  23
  24#define DRV_NAME "rtc-ab-b5ze-s3"
  25
  26/* Control section */
  27#define ABB5ZES3_REG_CTRL1         0x00    /* Control 1 register */
  28#define ABB5ZES3_REG_CTRL1_CIE     BIT(0)  /* Pulse interrupt enable */
  29#define ABB5ZES3_REG_CTRL1_AIE     BIT(1)  /* Alarm interrupt enable */
  30#define ABB5ZES3_REG_CTRL1_SIE     BIT(2)  /* Second interrupt enable */
  31#define ABB5ZES3_REG_CTRL1_PM      BIT(3)  /* 24h/12h mode */
  32#define ABB5ZES3_REG_CTRL1_SR      BIT(4)  /* Software reset */
  33#define ABB5ZES3_REG_CTRL1_STOP    BIT(5)  /* RTC circuit enable */
  34#define ABB5ZES3_REG_CTRL1_CAP     BIT(7)
  35
  36#define ABB5ZES3_REG_CTRL2         0x01    /* Control 2 register */
  37#define ABB5ZES3_REG_CTRL2_CTBIE   BIT(0)  /* Countdown timer B int. enable */
  38#define ABB5ZES3_REG_CTRL2_CTAIE   BIT(1)  /* Countdown timer A int. enable */
  39#define ABB5ZES3_REG_CTRL2_WTAIE   BIT(2)  /* Watchdog timer A int. enable */
  40#define ABB5ZES3_REG_CTRL2_AF      BIT(3)  /* Alarm interrupt status */
  41#define ABB5ZES3_REG_CTRL2_SF      BIT(4)  /* Second interrupt status */
  42#define ABB5ZES3_REG_CTRL2_CTBF    BIT(5)  /* Countdown timer B int. status */
  43#define ABB5ZES3_REG_CTRL2_CTAF    BIT(6)  /* Countdown timer A int. status */
  44#define ABB5ZES3_REG_CTRL2_WTAF    BIT(7)  /* Watchdog timer A int. status */
  45
  46#define ABB5ZES3_REG_CTRL3         0x02    /* Control 3 register */
  47#define ABB5ZES3_REG_CTRL3_PM2     BIT(7)  /* Power Management bit 2 */
  48#define ABB5ZES3_REG_CTRL3_PM1     BIT(6)  /* Power Management bit 1 */
  49#define ABB5ZES3_REG_CTRL3_PM0     BIT(5)  /* Power Management bit 0 */
  50#define ABB5ZES3_REG_CTRL3_BSF     BIT(3)  /* Battery switchover int. status */
  51#define ABB5ZES3_REG_CTRL3_BLF     BIT(2)  /* Battery low int. status */
  52#define ABB5ZES3_REG_CTRL3_BSIE    BIT(1)  /* Battery switchover int. enable */
  53#define ABB5ZES3_REG_CTRL3_BLIE    BIT(0)  /* Battery low int. enable */
  54
  55#define ABB5ZES3_CTRL_SEC_LEN      3
  56
  57/* RTC section */
  58#define ABB5ZES3_REG_RTC_SC        0x03    /* RTC Seconds register */
  59#define ABB5ZES3_REG_RTC_SC_OSC    BIT(7)  /* Clock integrity status */
  60#define ABB5ZES3_REG_RTC_MN        0x04    /* RTC Minutes register */
  61#define ABB5ZES3_REG_RTC_HR        0x05    /* RTC Hours register */
  62#define ABB5ZES3_REG_RTC_HR_PM     BIT(5)  /* RTC Hours PM bit */
  63#define ABB5ZES3_REG_RTC_DT        0x06    /* RTC Date register */
  64#define ABB5ZES3_REG_RTC_DW        0x07    /* RTC Day of the week register */
  65#define ABB5ZES3_REG_RTC_MO        0x08    /* RTC Month register */
  66#define ABB5ZES3_REG_RTC_YR        0x09    /* RTC Year register */
  67
  68#define ABB5ZES3_RTC_SEC_LEN       7
  69
  70/* Alarm section (enable bits are all active low) */
  71#define ABB5ZES3_REG_ALRM_MN       0x0A    /* Alarm - minute register */
  72#define ABB5ZES3_REG_ALRM_MN_AE    BIT(7)  /* Minute enable */
  73#define ABB5ZES3_REG_ALRM_HR       0x0B    /* Alarm - hours register */
  74#define ABB5ZES3_REG_ALRM_HR_AE    BIT(7)  /* Hour enable */
  75#define ABB5ZES3_REG_ALRM_DT       0x0C    /* Alarm - date register */
  76#define ABB5ZES3_REG_ALRM_DT_AE    BIT(7)  /* Date (day of the month) enable */
  77#define ABB5ZES3_REG_ALRM_DW       0x0D    /* Alarm - day of the week reg. */
  78#define ABB5ZES3_REG_ALRM_DW_AE    BIT(7)  /* Day of the week enable */
  79
  80#define ABB5ZES3_ALRM_SEC_LEN      4
  81
  82/* Frequency offset section */
  83#define ABB5ZES3_REG_FREQ_OF       0x0E    /* Frequency offset register */
  84#define ABB5ZES3_REG_FREQ_OF_MODE  0x0E    /* Offset mode: 2 hours / minute */
  85
  86/* CLOCKOUT section */
  87#define ABB5ZES3_REG_TIM_CLK       0x0F    /* Timer & Clockout register */
  88#define ABB5ZES3_REG_TIM_CLK_TAM   BIT(7)  /* Permanent/pulsed timer A/int. 2 */
  89#define ABB5ZES3_REG_TIM_CLK_TBM   BIT(6)  /* Permanent/pulsed timer B */
  90#define ABB5ZES3_REG_TIM_CLK_COF2  BIT(5)  /* Clkout Freq bit 2 */
  91#define ABB5ZES3_REG_TIM_CLK_COF1  BIT(4)  /* Clkout Freq bit 1 */
  92#define ABB5ZES3_REG_TIM_CLK_COF0  BIT(3)  /* Clkout Freq bit 0 */
  93#define ABB5ZES3_REG_TIM_CLK_TAC1  BIT(2)  /* Timer A: - 01 : countdown */
  94#define ABB5ZES3_REG_TIM_CLK_TAC0  BIT(1)  /*          - 10 : timer     */
  95#define ABB5ZES3_REG_TIM_CLK_TBC   BIT(0)  /* Timer B enable */
  96
  97/* Timer A Section */
  98#define ABB5ZES3_REG_TIMA_CLK      0x10    /* Timer A clock register */
  99#define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2)  /* Freq bit 2 */
 100#define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1)  /* Freq bit 1 */
 101#define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0)  /* Freq bit 0 */
 102#define ABB5ZES3_REG_TIMA          0x11    /* Timer A register */
 103
 104#define ABB5ZES3_TIMA_SEC_LEN      2
 105
 106/* Timer B Section */
 107#define ABB5ZES3_REG_TIMB_CLK      0x12    /* Timer B clock register */
 108#define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
 109#define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
 110#define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
 111#define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
 112#define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
 113#define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
 114#define ABB5ZES3_REG_TIMB          0x13    /* Timer B register */
 115#define ABB5ZES3_TIMB_SEC_LEN      2
 116
 117#define ABB5ZES3_MEM_MAP_LEN       0x14
 118
 119struct abb5zes3_rtc_data {
 120        struct rtc_device *rtc;
 121        struct regmap *regmap;
 122
 123        int irq;
 124
 125        bool battery_low;
 126        bool timer_alarm; /* current alarm is via timer A */
 127};
 128
 129/*
 130 * Try and match register bits w/ fixed null values to see whether we
 131 * are dealing with an ABB5ZES3.
 132 */
 133static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
 134{
 135        u8 regs[ABB5ZES3_MEM_MAP_LEN];
 136        static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
 137                                                       0x80, 0xc0, 0xc0, 0xf8,
 138                                                       0xe0, 0x00, 0x00, 0x40,
 139                                                       0x40, 0x78, 0x00, 0x00,
 140                                                       0xf8, 0x00, 0x88, 0x00 };
 141        int ret, i;
 142
 143        ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
 144        if (ret)
 145                return ret;
 146
 147        for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
 148                if (regs[i] & mask[i]) /* check if bits are cleared */
 149                        return -ENODEV;
 150        }
 151
 152        return 0;
 153}
 154
 155/* Clear alarm status bit. */
 156static int _abb5zes3_rtc_clear_alarm(struct device *dev)
 157{
 158        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 159        int ret;
 160
 161        ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
 162                                 ABB5ZES3_REG_CTRL2_AF, 0);
 163        if (ret)
 164                dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
 165
 166        return ret;
 167}
 168
 169/* Enable or disable alarm (i.e. alarm interrupt generation) */
 170static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
 171{
 172        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 173        int ret;
 174
 175        ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
 176                                 ABB5ZES3_REG_CTRL1_AIE,
 177                                 enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
 178        if (ret)
 179                dev_err(dev, "%s: writing alarm INT failed (%d)\n",
 180                        __func__, ret);
 181
 182        return ret;
 183}
 184
 185/* Enable or disable timer (watchdog timer A interrupt generation) */
 186static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
 187{
 188        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 189        int ret;
 190
 191        ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
 192                                 ABB5ZES3_REG_CTRL2_WTAIE,
 193                                 enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
 194        if (ret)
 195                dev_err(dev, "%s: writing timer INT failed (%d)\n",
 196                        __func__, ret);
 197
 198        return ret;
 199}
 200
 201/*
 202 * Note: we only read, so regmap inner lock protection is sufficient, i.e.
 203 * we do not need driver's main lock protection.
 204 */
 205static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
 206{
 207        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 208        u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
 209        int ret = 0;
 210
 211        /*
 212         * As we need to read CTRL1 register anyway to access 24/12h
 213         * mode bit, we do a single bulk read of both control and RTC
 214         * sections (they are consecutive). This also ease indexing
 215         * of register values after bulk read.
 216         */
 217        ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
 218                               sizeof(regs));
 219        if (ret) {
 220                dev_err(dev, "%s: reading RTC time failed (%d)\n",
 221                        __func__, ret);
 222                return ret;
 223        }
 224
 225        /* If clock integrity is not guaranteed, do not return a time value */
 226        if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC)
 227                return -ENODATA;
 228
 229        tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
 230        tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
 231
 232        if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
 233                tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
 234                if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
 235                        tm->tm_hour += 12;
 236        } else {                                                /* 24hr mode */
 237                tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
 238        }
 239
 240        tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
 241        tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
 242        tm->tm_mon  = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
 243        tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
 244
 245        return ret;
 246}
 247
 248static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
 249{
 250        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 251        u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
 252        int ret;
 253
 254        regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
 255        regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
 256        regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
 257        regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
 258        regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
 259        regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
 260        regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
 261
 262        ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
 263                                regs + ABB5ZES3_REG_RTC_SC,
 264                                ABB5ZES3_RTC_SEC_LEN);
 265
 266        return ret;
 267}
 268
 269/*
 270 * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
 271 * given number of seconds.
 272 */
 273static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
 274{
 275        *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
 276        *timer_a = secs;
 277}
 278
 279/*
 280 * Return current number of seconds in Timer A. As we only use
 281 * timer A with a 1Hz freq, this is what we expect to have.
 282 */
 283static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
 284{
 285        if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
 286                return -EINVAL;
 287
 288        *secs = timer_a;
 289
 290        return 0;
 291}
 292
 293/*
 294 * Read alarm currently configured via a watchdog timer using timer A. This
 295 * is done by reading current RTC time and adding remaining timer time.
 296 */
 297static int _abb5zes3_rtc_read_timer(struct device *dev,
 298                                    struct rtc_wkalrm *alarm)
 299{
 300        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 301        struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
 302        u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
 303        unsigned long rtc_secs;
 304        unsigned int reg;
 305        u8 timer_secs;
 306        int ret;
 307
 308        /*
 309         * Instead of doing two separate calls, because they are consecutive,
 310         * we grab both clockout register and Timer A section. The latter is
 311         * used to decide if timer A is enabled (as a watchdog timer).
 312         */
 313        ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
 314                               ABB5ZES3_TIMA_SEC_LEN + 1);
 315        if (ret) {
 316                dev_err(dev, "%s: reading Timer A section failed (%d)\n",
 317                        __func__, ret);
 318                return ret;
 319        }
 320
 321        /* get current time ... */
 322        ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
 323        if (ret)
 324                return ret;
 325
 326        /* ... convert to seconds ... */
 327        rtc_secs = rtc_tm_to_time64(&rtc_tm);
 328
 329        /* ... add remaining timer A time ... */
 330        ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
 331        if (ret)
 332                return ret;
 333
 334        /* ... and convert back. */
 335        rtc_time64_to_tm(rtc_secs + timer_secs, alarm_tm);
 336
 337        ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
 338        if (ret) {
 339                dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
 340                        __func__, ret);
 341                return ret;
 342        }
 343
 344        alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
 345
 346        return 0;
 347}
 348
 349/* Read alarm currently configured via a RTC alarm registers. */
 350static int _abb5zes3_rtc_read_alarm(struct device *dev,
 351                                    struct rtc_wkalrm *alarm)
 352{
 353        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 354        struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
 355        unsigned long rtc_secs, alarm_secs;
 356        u8 regs[ABB5ZES3_ALRM_SEC_LEN];
 357        unsigned int reg;
 358        int ret;
 359
 360        ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
 361                               ABB5ZES3_ALRM_SEC_LEN);
 362        if (ret) {
 363                dev_err(dev, "%s: reading alarm section failed (%d)\n",
 364                        __func__, ret);
 365                return ret;
 366        }
 367
 368        alarm_tm->tm_sec  = 0;
 369        alarm_tm->tm_min  = bcd2bin(regs[0] & 0x7f);
 370        alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
 371        alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
 372        alarm_tm->tm_wday = -1;
 373
 374        /*
 375         * The alarm section does not store year/month. We use the ones in rtc
 376         * section as a basis and increment month and then year if needed to get
 377         * alarm after current time.
 378         */
 379        ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
 380        if (ret)
 381                return ret;
 382
 383        alarm_tm->tm_year = rtc_tm.tm_year;
 384        alarm_tm->tm_mon = rtc_tm.tm_mon;
 385
 386        rtc_secs = rtc_tm_to_time64(&rtc_tm);
 387        alarm_secs = rtc_tm_to_time64(alarm_tm);
 388
 389        if (alarm_secs < rtc_secs) {
 390                if (alarm_tm->tm_mon == 11) {
 391                        alarm_tm->tm_mon = 0;
 392                        alarm_tm->tm_year += 1;
 393                } else {
 394                        alarm_tm->tm_mon += 1;
 395                }
 396        }
 397
 398        ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
 399        if (ret) {
 400                dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
 401                        __func__, ret);
 402                return ret;
 403        }
 404
 405        alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
 406
 407        return 0;
 408}
 409
 410/*
 411 * As the Alarm mechanism supported by the chip is only accurate to the
 412 * minute, we use the watchdog timer mechanism provided by timer A
 413 * (up to 256 seconds w/ a second accuracy) for low alarm values (below
 414 * 4 minutes). Otherwise, we use the common alarm mechanism provided
 415 * by the chip. In order for that to work, we keep track of currently
 416 * configured timer type via 'timer_alarm' flag in our private data
 417 * structure.
 418 */
 419static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 420{
 421        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 422        int ret;
 423
 424        if (data->timer_alarm)
 425                ret = _abb5zes3_rtc_read_timer(dev, alarm);
 426        else
 427                ret = _abb5zes3_rtc_read_alarm(dev, alarm);
 428
 429        return ret;
 430}
 431
 432/*
 433 * Set alarm using chip alarm mechanism. It is only accurate to the
 434 * minute (not the second). The function expects alarm interrupt to
 435 * be disabled.
 436 */
 437static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 438{
 439        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 440        struct rtc_time *alarm_tm = &alarm->time;
 441        u8 regs[ABB5ZES3_ALRM_SEC_LEN];
 442        struct rtc_time rtc_tm;
 443        int ret, enable = 1;
 444
 445        if (!alarm->enabled) {
 446                enable = 0;
 447        } else {
 448                unsigned long rtc_secs, alarm_secs;
 449
 450                /*
 451                 * Chip only support alarms up to one month in the future. Let's
 452                 * return an error if we get something after that limit.
 453                 * Comparison is done by incrementing rtc_tm month field by one
 454                 * and checking alarm value is still below.
 455                 */
 456                ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
 457                if (ret)
 458                        return ret;
 459
 460                if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
 461                        rtc_tm.tm_mon = 0;
 462                        rtc_tm.tm_year += 1;
 463                } else {
 464                        rtc_tm.tm_mon += 1;
 465                }
 466
 467                rtc_secs = rtc_tm_to_time64(&rtc_tm);
 468                alarm_secs = rtc_tm_to_time64(alarm_tm);
 469
 470                if (alarm_secs > rtc_secs) {
 471                        dev_err(dev, "%s: alarm maximum is one month in the future (%d)\n",
 472                                __func__, ret);
 473                        return -EINVAL;
 474                }
 475        }
 476
 477        /*
 478         * Program all alarm registers but DW one. For each register, setting
 479         * MSB to 0 enables associated alarm.
 480         */
 481        regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
 482        regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
 483        regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
 484        regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
 485
 486        ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
 487                                ABB5ZES3_ALRM_SEC_LEN);
 488        if (ret < 0) {
 489                dev_err(dev, "%s: writing ALARM section failed (%d)\n",
 490                        __func__, ret);
 491                return ret;
 492        }
 493
 494        /* Record currently configured alarm is not a timer */
 495        data->timer_alarm = 0;
 496
 497        /* Enable or disable alarm interrupt generation */
 498        return _abb5zes3_rtc_update_alarm(dev, enable);
 499}
 500
 501/*
 502 * Set alarm using timer watchdog (via timer A) mechanism. The function expects
 503 * timer A interrupt to be disabled.
 504 */
 505static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
 506                                   u8 secs)
 507{
 508        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 509        u8 regs[ABB5ZES3_TIMA_SEC_LEN];
 510        u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
 511        int ret = 0;
 512
 513        /* Program given number of seconds to Timer A registers */
 514        sec_to_timer_a(secs, &regs[0], &regs[1]);
 515        ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
 516                                ABB5ZES3_TIMA_SEC_LEN);
 517        if (ret < 0) {
 518                dev_err(dev, "%s: writing timer section failed\n", __func__);
 519                return ret;
 520        }
 521
 522        /* Configure Timer A as a watchdog timer */
 523        ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
 524                                 mask, ABB5ZES3_REG_TIM_CLK_TAC1);
 525        if (ret)
 526                dev_err(dev, "%s: failed to update timer\n", __func__);
 527
 528        /* Record currently configured alarm is a timer */
 529        data->timer_alarm = 1;
 530
 531        /* Enable or disable timer interrupt generation */
 532        return _abb5zes3_rtc_update_timer(dev, alarm->enabled);
 533}
 534
 535/*
 536 * The chip has an alarm which is only accurate to the minute. In order to
 537 * handle alarms below that limit, we use the watchdog timer function of
 538 * timer A. More precisely, the timer method is used for alarms below 240
 539 * seconds.
 540 */
 541static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 542{
 543        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 544        struct rtc_time *alarm_tm = &alarm->time;
 545        unsigned long rtc_secs, alarm_secs;
 546        struct rtc_time rtc_tm;
 547        int ret;
 548
 549        ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
 550        if (ret)
 551                return ret;
 552
 553        rtc_secs = rtc_tm_to_time64(&rtc_tm);
 554        alarm_secs = rtc_tm_to_time64(alarm_tm);
 555
 556        /* Let's first disable both the alarm and the timer interrupts */
 557        ret = _abb5zes3_rtc_update_alarm(dev, false);
 558        if (ret < 0) {
 559                dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
 560                        ret);
 561                return ret;
 562        }
 563        ret = _abb5zes3_rtc_update_timer(dev, false);
 564        if (ret < 0) {
 565                dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
 566                        ret);
 567                return ret;
 568        }
 569
 570        data->timer_alarm = 0;
 571
 572        /*
 573         * Let's now configure the alarm; if we are expected to ring in
 574         * more than 240s, then we setup an alarm. Otherwise, a timer.
 575         */
 576        if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
 577                ret = _abb5zes3_rtc_set_timer(dev, alarm,
 578                                              alarm_secs - rtc_secs);
 579        else
 580                ret = _abb5zes3_rtc_set_alarm(dev, alarm);
 581
 582        if (ret)
 583                dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
 584                        ret);
 585
 586        return ret;
 587}
 588
 589/* Enable or disable battery low irq generation */
 590static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
 591                                                       bool enable)
 592{
 593        return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
 594                                  ABB5ZES3_REG_CTRL3_BLIE,
 595                                  enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
 596}
 597
 598/*
 599 * Check current RTC status and enable/disable what needs to be. Return 0 if
 600 * everything went ok and a negative value upon error.
 601 */
 602static int abb5zes3_rtc_check_setup(struct device *dev)
 603{
 604        struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
 605        struct regmap *regmap = data->regmap;
 606        unsigned int reg;
 607        int ret;
 608        u8 mask;
 609
 610        /*
 611         * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
 612         * is disabled here to prevent polluting the interrupt line and
 613         * uselessly triggering the IRQ handler we install for alarm and battery
 614         * low events. Note: this is done before clearing int. status below
 615         * in this function.
 616         * We also disable all timers and set timer interrupt to permanent (not
 617         * pulsed).
 618         */
 619        mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
 620                ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
 621                ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
 622                ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
 623        ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
 624                                 ABB5ZES3_REG_TIM_CLK_COF0 |
 625                                 ABB5ZES3_REG_TIM_CLK_COF1 |
 626                                 ABB5ZES3_REG_TIM_CLK_COF2);
 627        if (ret < 0) {
 628                dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
 629                        __func__, ret);
 630                return ret;
 631        }
 632
 633        /*
 634         * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
 635         * individually by clearing/setting MSB of each associated register. So,
 636         * we set all alarm enable bits to disable current alarm setting.
 637         */
 638        mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
 639                ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
 640        ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
 641        if (ret < 0) {
 642                dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
 643                        __func__, ret);
 644                return ret;
 645        }
 646
 647        /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
 648        mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
 649                ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
 650                ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
 651        ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
 652        if (ret < 0) {
 653                dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
 654                        __func__, ret);
 655                return ret;
 656        }
 657
 658        /*
 659         * Set Control 2 register (timer int. disabled, alarm status cleared).
 660         * WTAF is read-only and cleared automatically by reading the register.
 661         */
 662        mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
 663                ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
 664                ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
 665                ABB5ZES3_REG_CTRL2_CTAF);
 666        ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
 667        if (ret < 0) {
 668                dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
 669                        __func__, ret);
 670                return ret;
 671        }
 672
 673        /*
 674         * Enable battery low detection function and battery switchover function
 675         * (standard mode). Disable associated interrupts. Clear battery
 676         * switchover flag but not battery low flag. The latter is checked
 677         * later below.
 678         */
 679        mask = (ABB5ZES3_REG_CTRL3_PM0  | ABB5ZES3_REG_CTRL3_PM1 |
 680                ABB5ZES3_REG_CTRL3_PM2  | ABB5ZES3_REG_CTRL3_BLIE |
 681                ABB5ZES3_REG_CTRL3_BSIE | ABB5ZES3_REG_CTRL3_BSF);
 682        ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
 683        if (ret < 0) {
 684                dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
 685                        __func__, ret);
 686                return ret;
 687        }
 688
 689        /* Check oscillator integrity flag */
 690        ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
 691        if (ret < 0) {
 692                dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
 693                        __func__, ret);
 694                return ret;
 695        }
 696
 697        if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
 698                dev_err(dev, "clock integrity not guaranteed. Osc. has stopped or has been interrupted.\n");
 699                dev_err(dev, "change battery (if not already done) and then set time to reset osc. failure flag.\n");
 700        }
 701
 702        /*
 703         * Check battery low flag at startup: this allows reporting battery
 704         * is low at startup when IRQ line is not connected. Note: we record
 705         * current status to avoid reenabling this interrupt later in probe
 706         * function if battery is low.
 707         */
 708        ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
 709        if (ret < 0) {
 710                dev_err(dev, "%s: unable to read battery low flag (%d)\n",
 711                        __func__, ret);
 712                return ret;
 713        }
 714
 715        data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
 716        if (data->battery_low) {
 717                dev_err(dev, "RTC battery is low; please, consider changing it!\n");
 718
 719                ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
 720                if (ret)
 721                        dev_err(dev, "%s: disabling battery low interrupt generation failed (%d)\n",
 722                                __func__, ret);
 723        }
 724
 725        return ret;
 726}
 727
 728static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
 729                                         unsigned int enable)
 730{
 731        struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
 732        int ret = 0;
 733
 734        if (rtc_data->irq) {
 735                if (rtc_data->timer_alarm)
 736                        ret = _abb5zes3_rtc_update_timer(dev, enable);
 737                else
 738                        ret = _abb5zes3_rtc_update_alarm(dev, enable);
 739        }
 740
 741        return ret;
 742}
 743
 744static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
 745{
 746        struct i2c_client *client = data;
 747        struct device *dev = &client->dev;
 748        struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
 749        struct rtc_device *rtc = rtc_data->rtc;
 750        u8 regs[ABB5ZES3_CTRL_SEC_LEN];
 751        int ret, handled = IRQ_NONE;
 752
 753        ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
 754                               ABB5ZES3_CTRL_SEC_LEN);
 755        if (ret) {
 756                dev_err(dev, "%s: unable to read control section (%d)!\n",
 757                        __func__, ret);
 758                return handled;
 759        }
 760
 761        /*
 762         * Check battery low detection flag and disable battery low interrupt
 763         * generation if flag is set (interrupt can only be cleared when
 764         * battery is replaced).
 765         */
 766        if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
 767                dev_err(dev, "RTC battery is low; please change it!\n");
 768
 769                _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
 770
 771                handled = IRQ_HANDLED;
 772        }
 773
 774        /* Check alarm flag */
 775        if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
 776                dev_dbg(dev, "RTC alarm!\n");
 777
 778                rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
 779
 780                /* Acknowledge and disable the alarm */
 781                _abb5zes3_rtc_clear_alarm(dev);
 782                _abb5zes3_rtc_update_alarm(dev, 0);
 783
 784                handled = IRQ_HANDLED;
 785        }
 786
 787        /* Check watchdog Timer A flag */
 788        if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
 789                dev_dbg(dev, "RTC timer!\n");
 790
 791                rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
 792
 793                /*
 794                 * Acknowledge and disable the alarm. Note: WTAF
 795                 * flag had been cleared when reading CTRL2
 796                 */
 797                _abb5zes3_rtc_update_timer(dev, 0);
 798
 799                rtc_data->timer_alarm = 0;
 800
 801                handled = IRQ_HANDLED;
 802        }
 803
 804        return handled;
 805}
 806
 807static const struct rtc_class_ops rtc_ops = {
 808        .read_time = _abb5zes3_rtc_read_time,
 809        .set_time = abb5zes3_rtc_set_time,
 810        .read_alarm = abb5zes3_rtc_read_alarm,
 811        .set_alarm = abb5zes3_rtc_set_alarm,
 812        .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
 813};
 814
 815static const struct regmap_config abb5zes3_rtc_regmap_config = {
 816        .reg_bits = 8,
 817        .val_bits = 8,
 818};
 819
 820static int abb5zes3_probe(struct i2c_client *client,
 821                          const struct i2c_device_id *id)
 822{
 823        struct abb5zes3_rtc_data *data = NULL;
 824        struct device *dev = &client->dev;
 825        struct regmap *regmap;
 826        int ret;
 827
 828        if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
 829                                     I2C_FUNC_SMBUS_BYTE_DATA |
 830                                     I2C_FUNC_SMBUS_I2C_BLOCK))
 831                return -ENODEV;
 832
 833        regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
 834        if (IS_ERR(regmap)) {
 835                ret = PTR_ERR(regmap);
 836                dev_err(dev, "%s: regmap allocation failed: %d\n",
 837                        __func__, ret);
 838                return ret;
 839        }
 840
 841        ret = abb5zes3_i2c_validate_chip(regmap);
 842        if (ret)
 843                return ret;
 844
 845        data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 846        if (!data)
 847                return -ENOMEM;
 848
 849        data->regmap = regmap;
 850        dev_set_drvdata(dev, data);
 851
 852        ret = abb5zes3_rtc_check_setup(dev);
 853        if (ret)
 854                return ret;
 855
 856        data->rtc = devm_rtc_allocate_device(dev);
 857        ret = PTR_ERR_OR_ZERO(data->rtc);
 858        if (ret) {
 859                dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
 860                        __func__, ret);
 861                return ret;
 862        }
 863
 864        if (client->irq > 0) {
 865                ret = devm_request_threaded_irq(dev, client->irq, NULL,
 866                                                _abb5zes3_rtc_interrupt,
 867                                                IRQF_SHARED | IRQF_ONESHOT,
 868                                                DRV_NAME, client);
 869                if (!ret) {
 870                        device_init_wakeup(dev, true);
 871                        data->irq = client->irq;
 872                        dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
 873                                client->irq);
 874                } else {
 875                        dev_err(dev, "%s: irq %d unavailable (%d)\n",
 876                                __func__, client->irq, ret);
 877                        goto err;
 878                }
 879        }
 880
 881        data->rtc->ops = &rtc_ops;
 882        data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
 883        data->rtc->range_max = RTC_TIMESTAMP_END_2099;
 884
 885        /* Enable battery low detection interrupt if battery not already low */
 886        if (!data->battery_low && data->irq) {
 887                ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
 888                if (ret) {
 889                        dev_err(dev, "%s: enabling battery low interrupt generation failed (%d)\n",
 890                                __func__, ret);
 891                        goto err;
 892                }
 893        }
 894
 895        ret = devm_rtc_register_device(data->rtc);
 896
 897err:
 898        if (ret && data->irq)
 899                device_init_wakeup(dev, false);
 900        return ret;
 901}
 902
 903#ifdef CONFIG_PM_SLEEP
 904static int abb5zes3_rtc_suspend(struct device *dev)
 905{
 906        struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
 907
 908        if (device_may_wakeup(dev))
 909                return enable_irq_wake(rtc_data->irq);
 910
 911        return 0;
 912}
 913
 914static int abb5zes3_rtc_resume(struct device *dev)
 915{
 916        struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
 917
 918        if (device_may_wakeup(dev))
 919                return disable_irq_wake(rtc_data->irq);
 920
 921        return 0;
 922}
 923#endif
 924
 925static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
 926                         abb5zes3_rtc_resume);
 927
 928#ifdef CONFIG_OF
 929static const struct of_device_id abb5zes3_dt_match[] = {
 930        { .compatible = "abracon,abb5zes3" },
 931        { },
 932};
 933MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
 934#endif
 935
 936static const struct i2c_device_id abb5zes3_id[] = {
 937        { "abb5zes3", 0 },
 938        { }
 939};
 940MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
 941
 942static struct i2c_driver abb5zes3_driver = {
 943        .driver = {
 944                .name = DRV_NAME,
 945                .pm = &abb5zes3_rtc_pm_ops,
 946                .of_match_table = of_match_ptr(abb5zes3_dt_match),
 947        },
 948        .probe    = abb5zes3_probe,
 949        .id_table = abb5zes3_id,
 950};
 951module_i2c_driver(abb5zes3_driver);
 952
 953MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
 954MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
 955MODULE_LICENSE("GPL");
 956