LXR linux/drivers/rtc/rtc-at91rm9200.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *      Real Time Clock interface for Linux on Atmel AT91RM9200
   4 *
   5 *      Copyright (C) 2002 Rick Bronson
   6 *
   7 *      Converted to RTC class model by Andrew Victor
   8 *
   9 *      Ported to Linux 2.6 by Steven Scholz
  10 *      Based on s3c2410-rtc.c Simtec Electronics
  11 *
  12 *      Based on sa1100-rtc.c by Nils Faerber
  13 *      Based on rtc.c by Paul Gortmaker
  14 */
  15
  16#include <linux/bcd.h>
  17#include <linux/bitfield.h>
  18#include <linux/clk.h>
  19#include <linux/completion.h>
  20#include <linux/interrupt.h>
  21#include <linux/ioctl.h>
  22#include <linux/io.h>
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/of_device.h>
  26#include <linux/of.h>
  27#include <linux/platform_device.h>
  28#include <linux/rtc.h>
  29#include <linux/spinlock.h>
  30#include <linux/suspend.h>
  31#include <linux/time.h>
  32#include <linux/uaccess.h>
  33
  34#define AT91_RTC_CR             0x00                    /* Control Register */
  35#define         AT91_RTC_UPDTIM         BIT(0)          /* Update Request Time Register */
  36#define         AT91_RTC_UPDCAL         BIT(1)          /* Update Request Calendar Register */
  37
  38#define AT91_RTC_MR             0x04                    /* Mode Register */
  39#define         AT91_RTC_HRMOD          BIT(0)          /* 12/24 hour mode */
  40#define         AT91_RTC_NEGPPM         BIT(4)          /* Negative PPM correction */
  41#define         AT91_RTC_CORRECTION     GENMASK(14, 8)  /* Slow clock correction */
  42#define         AT91_RTC_HIGHPPM        BIT(15)         /* High PPM correction */
  43
  44#define AT91_RTC_TIMR           0x08                    /* Time Register */
  45#define         AT91_RTC_SEC            GENMASK(6, 0)   /* Current Second */
  46#define         AT91_RTC_MIN            GENMASK(14, 8)  /* Current Minute */
  47#define         AT91_RTC_HOUR           GENMASK(21, 16) /* Current Hour */
  48#define         AT91_RTC_AMPM           BIT(22)         /* Ante Meridiem Post Meridiem Indicator */
  49
  50#define AT91_RTC_CALR           0x0c                    /* Calendar Register */
  51#define         AT91_RTC_CENT           GENMASK(6, 0)   /* Current Century */
  52#define         AT91_RTC_YEAR           GENMASK(15, 8)  /* Current Year */
  53#define         AT91_RTC_MONTH          GENMASK(20, 16) /* Current Month */
  54#define         AT91_RTC_DAY            GENMASK(23, 21) /* Current Day */
  55#define         AT91_RTC_DATE           GENMASK(29, 24) /* Current Date */
  56
  57#define AT91_RTC_TIMALR         0x10                    /* Time Alarm Register */
  58#define         AT91_RTC_SECEN          BIT(7)          /* Second Alarm Enable */
  59#define         AT91_RTC_MINEN          BIT(15)         /* Minute Alarm Enable */
  60#define         AT91_RTC_HOUREN         BIT(23)         /* Hour Alarm Enable */
  61
  62#define AT91_RTC_CALALR         0x14                    /* Calendar Alarm Register */
  63#define         AT91_RTC_MTHEN          BIT(23)         /* Month Alarm Enable */
  64#define         AT91_RTC_DATEEN         BIT(31)         /* Date Alarm Enable */
  65
  66#define AT91_RTC_SR             0x18                    /* Status Register */
  67#define         AT91_RTC_ACKUPD         BIT(0)          /* Acknowledge for Update */
  68#define         AT91_RTC_ALARM          BIT(1)          /* Alarm Flag */
  69#define         AT91_RTC_SECEV          BIT(2)          /* Second Event */
  70#define         AT91_RTC_TIMEV          BIT(3)          /* Time Event */
  71#define         AT91_RTC_CALEV          BIT(4)          /* Calendar Event */
  72
  73#define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
  74#define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
  75#define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
  76#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
  77
  78#define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
  79#define         AT91_RTC_NVTIM          BIT(0)          /* Non valid Time */
  80#define         AT91_RTC_NVCAL          BIT(1)          /* Non valid Calendar */
  81#define         AT91_RTC_NVTIMALR       BIT(2)          /* Non valid Time Alarm */
  82#define         AT91_RTC_NVCALALR       BIT(3)          /* Non valid Calendar Alarm */
  83
  84#define AT91_RTC_CORR_DIVIDEND          3906000
  85#define AT91_RTC_CORR_LOW_RATIO         20
  86
  87#define at91_rtc_read(field) \
  88        readl_relaxed(at91_rtc_regs + field)
  89#define at91_rtc_write(field, val) \
  90        writel_relaxed((val), at91_rtc_regs + field)
  91
  92struct at91_rtc_config {
  93        bool use_shadow_imr;
  94        bool has_correction;
  95};
  96
  97static const struct at91_rtc_config *at91_rtc_config;
  98static DECLARE_COMPLETION(at91_rtc_updated);
  99static DECLARE_COMPLETION(at91_rtc_upd_rdy);
 100static void __iomem *at91_rtc_regs;
 101static int irq;
 102static DEFINE_SPINLOCK(at91_rtc_lock);
 103static u32 at91_rtc_shadow_imr;
 104static bool suspended;
 105static DEFINE_SPINLOCK(suspended_lock);
 106static unsigned long cached_events;
 107static u32 at91_rtc_imr;
 108static struct clk *sclk;
 109
 110static void at91_rtc_write_ier(u32 mask)
 111{
 112        unsigned long flags;
 113
 114        spin_lock_irqsave(&at91_rtc_lock, flags);
 115        at91_rtc_shadow_imr |= mask;
 116        at91_rtc_write(AT91_RTC_IER, mask);
 117        spin_unlock_irqrestore(&at91_rtc_lock, flags);
 118}
 119
 120static void at91_rtc_write_idr(u32 mask)
 121{
 122        unsigned long flags;
 123
 124        spin_lock_irqsave(&at91_rtc_lock, flags);
 125        at91_rtc_write(AT91_RTC_IDR, mask);
 126        /*
 127         * Register read back (of any RTC-register) needed to make sure
 128         * IDR-register write has reached the peripheral before updating
 129         * shadow mask.
 130         *
 131         * Note that there is still a possibility that the mask is updated
 132         * before interrupts have actually been disabled in hardware. The only
 133         * way to be certain would be to poll the IMR-register, which is is
 134         * the very register we are trying to emulate. The register read back
 135         * is a reasonable heuristic.
 136         */
 137        at91_rtc_read(AT91_RTC_SR);
 138        at91_rtc_shadow_imr &= ~mask;
 139        spin_unlock_irqrestore(&at91_rtc_lock, flags);
 140}
 141
 142static u32 at91_rtc_read_imr(void)
 143{
 144        unsigned long flags;
 145        u32 mask;
 146
 147        if (at91_rtc_config->use_shadow_imr) {
 148                spin_lock_irqsave(&at91_rtc_lock, flags);
 149                mask = at91_rtc_shadow_imr;
 150                spin_unlock_irqrestore(&at91_rtc_lock, flags);
 151        } else {
 152                mask = at91_rtc_read(AT91_RTC_IMR);
 153        }
 154
 155        return mask;
 156}
 157
 158/*
 159 * Decode time/date into rtc_time structure
 160 */
 161static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
 162                                struct rtc_time *tm)
 163{
 164        unsigned int time, date;
 165
 166        /* must read twice in case it changes */
 167        do {
 168                time = at91_rtc_read(timereg);
 169                date = at91_rtc_read(calreg);
 170        } while ((time != at91_rtc_read(timereg)) ||
 171                        (date != at91_rtc_read(calreg)));
 172
 173        tm->tm_sec  = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
 174        tm->tm_min  = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
 175        tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
 176
 177        /*
 178         * The Calendar Alarm register does not have a field for
 179         * the year - so these will return an invalid value.
 180         */
 181        tm->tm_year  = bcd2bin(date & AT91_RTC_CENT) * 100;     /* century */
 182        tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
 183
 184        tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1;       /* day of the week [0-6], Sunday=0 */
 185        tm->tm_mon  = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
 186        tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
 187}
 188
 189/*
 190 * Read current time and date in RTC
 191 */
 192static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
 193{
 194        at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
 195        tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
 196        tm->tm_year = tm->tm_year - 1900;
 197
 198        dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
 199
 200        return 0;
 201}
 202
 203/*
 204 * Set current time and date in RTC
 205 */
 206static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
 207{
 208        unsigned long cr;
 209
 210        dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
 211
 212        wait_for_completion(&at91_rtc_upd_rdy);
 213
 214        /* Stop Time/Calendar from counting */
 215        cr = at91_rtc_read(AT91_RTC_CR);
 216        at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 217
 218        at91_rtc_write_ier(AT91_RTC_ACKUPD);
 219        wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
 220        at91_rtc_write_idr(AT91_RTC_ACKUPD);
 221
 222        at91_rtc_write(AT91_RTC_TIMR,
 223                          FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
 224                        | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
 225                        | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
 226
 227        at91_rtc_write(AT91_RTC_CALR,
 228                          FIELD_PREP(AT91_RTC_CENT,
 229                                     bin2bcd((tm->tm_year + 1900) / 100))
 230                        | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
 231                        | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
 232                        | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
 233                        | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
 234
 235        /* Restart Time/Calendar */
 236        cr = at91_rtc_read(AT91_RTC_CR);
 237        at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
 238        at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
 239        at91_rtc_write_ier(AT91_RTC_SECEV);
 240
 241        return 0;
 242}
 243
 244/*
 245 * Read alarm time and date in RTC
 246 */
 247static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
 248{
 249        struct rtc_time *tm = &alrm->time;
 250
 251        at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
 252        tm->tm_year = -1;
 253
 254        alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
 255                        ? 1 : 0;
 256
 257        dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
 258                alrm->enabled ? "en" : "dis");
 259
 260        return 0;
 261}
 262
 263/*
 264 * Set alarm time and date in RTC
 265 */
 266static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 267{
 268        struct rtc_time tm = alrm->time;
 269
 270        at91_rtc_write_idr(AT91_RTC_ALARM);
 271        at91_rtc_write(AT91_RTC_TIMALR,
 272                  FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
 273                | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
 274                | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
 275                | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
 276        at91_rtc_write(AT91_RTC_CALALR,
 277                  FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
 278                | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
 279                | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
 280
 281        if (alrm->enabled) {
 282                at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
 283                at91_rtc_write_ier(AT91_RTC_ALARM);
 284        }
 285
 286        dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
 287
 288        return 0;
 289}
 290
 291static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 292{
 293        dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
 294
 295        if (enabled) {
 296                at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
 297                at91_rtc_write_ier(AT91_RTC_ALARM);
 298        } else
 299                at91_rtc_write_idr(AT91_RTC_ALARM);
 300
 301        return 0;
 302}
 303
 304static int at91_rtc_readoffset(struct device *dev, long *offset)
 305{
 306        u32 mr = at91_rtc_read(AT91_RTC_MR);
 307        long val = FIELD_GET(AT91_RTC_CORRECTION, mr);
 308
 309        if (!val) {
 310                *offset = 0;
 311                return 0;
 312        }
 313
 314        val++;
 315
 316        if (!(mr & AT91_RTC_NEGPPM))
 317                val = -val;
 318
 319        if (!(mr & AT91_RTC_HIGHPPM))
 320                val *= AT91_RTC_CORR_LOW_RATIO;
 321
 322        *offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val);
 323
 324        return 0;
 325}
 326
 327static int at91_rtc_setoffset(struct device *dev, long offset)
 328{
 329        long corr;
 330        u32 mr;
 331
 332        if (offset > AT91_RTC_CORR_DIVIDEND / 2)
 333                return -ERANGE;
 334        if (offset < -AT91_RTC_CORR_DIVIDEND / 2)
 335                return -ERANGE;
 336
 337        mr = at91_rtc_read(AT91_RTC_MR);
 338        mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM);
 339
 340        if (offset > 0)
 341                mr |= AT91_RTC_NEGPPM;
 342        else
 343                offset = -offset;
 344
 345        /* offset less than 764 ppb, disable correction*/
 346        if (offset < 764) {
 347                at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM);
 348
 349                return 0;
 350        }
 351
 352        /*
 353         * 29208 ppb is the perfect cutoff between low range and high range
 354         * low range values are never better than high range value after that.
 355         */
 356        if (offset < 29208) {
 357                corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO);
 358        } else {
 359                corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset);
 360                mr |= AT91_RTC_HIGHPPM;
 361        }
 362
 363        if (corr > 128)
 364                corr = 128;
 365
 366        mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1);
 367
 368        at91_rtc_write(AT91_RTC_MR, mr);
 369
 370        return 0;
 371}
 372
 373/*
 374 * IRQ handler for the RTC
 375 */
 376static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
 377{
 378        struct platform_device *pdev = dev_id;
 379        struct rtc_device *rtc = platform_get_drvdata(pdev);
 380        unsigned int rtsr;
 381        unsigned long events = 0;
 382        int ret = IRQ_NONE;
 383
 384        spin_lock(&suspended_lock);
 385        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
 386        if (rtsr) {             /* this interrupt is shared!  Is it ours? */
 387                if (rtsr & AT91_RTC_ALARM)
 388                        events |= (RTC_AF | RTC_IRQF);
 389                if (rtsr & AT91_RTC_SECEV) {
 390                        complete(&at91_rtc_upd_rdy);
 391                        at91_rtc_write_idr(AT91_RTC_SECEV);
 392                }
 393                if (rtsr & AT91_RTC_ACKUPD)
 394                        complete(&at91_rtc_updated);
 395
 396                at91_rtc_write(AT91_RTC_SCCR, rtsr);    /* clear status reg */
 397
 398                if (!suspended) {
 399                        rtc_update_irq(rtc, 1, events);
 400
 401                        dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
 402                                __func__, events >> 8, events & 0x000000FF);
 403                } else {
 404                        cached_events |= events;
 405                        at91_rtc_write_idr(at91_rtc_imr);
 406                        pm_system_wakeup();
 407                }
 408
 409                ret = IRQ_HANDLED;
 410        }
 411        spin_unlock(&suspended_lock);
 412
 413        return ret;
 414}
 415
 416static const struct at91_rtc_config at91rm9200_config = {
 417};
 418
 419static const struct at91_rtc_config at91sam9x5_config = {
 420        .use_shadow_imr = true,
 421};
 422
 423static const struct at91_rtc_config sama5d4_config = {
 424        .has_correction = true,
 425};
 426
 427static const struct of_device_id at91_rtc_dt_ids[] = {
 428        {
 429                .compatible = "atmel,at91rm9200-rtc",
 430                .data = &at91rm9200_config,
 431        }, {
 432                .compatible = "atmel,at91sam9x5-rtc",
 433                .data = &at91sam9x5_config,
 434        }, {
 435                .compatible = "atmel,sama5d4-rtc",
 436                .data = &sama5d4_config,
 437        }, {
 438                .compatible = "atmel,sama5d2-rtc",
 439                .data = &sama5d4_config,
 440        }, {
 441                .compatible = "microchip,sam9x60-rtc",
 442                .data = &sama5d4_config,
 443        }, {
 444                /* sentinel */
 445        }
 446};
 447MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
 448
 449static const struct rtc_class_ops at91_rtc_ops = {
 450        .read_time      = at91_rtc_readtime,
 451        .set_time       = at91_rtc_settime,
 452        .read_alarm     = at91_rtc_readalarm,
 453        .set_alarm      = at91_rtc_setalarm,
 454        .alarm_irq_enable = at91_rtc_alarm_irq_enable,
 455};
 456
 457static const struct rtc_class_ops sama5d4_rtc_ops = {
 458        .read_time      = at91_rtc_readtime,
 459        .set_time       = at91_rtc_settime,
 460        .read_alarm     = at91_rtc_readalarm,
 461        .set_alarm      = at91_rtc_setalarm,
 462        .alarm_irq_enable = at91_rtc_alarm_irq_enable,
 463        .set_offset     = at91_rtc_setoffset,
 464        .read_offset    = at91_rtc_readoffset,
 465};
 466
 467/*
 468 * Initialize and install RTC driver
 469 */
 470static int __init at91_rtc_probe(struct platform_device *pdev)
 471{
 472        struct rtc_device *rtc;
 473        struct resource *regs;
 474        int ret = 0;
 475
 476        at91_rtc_config = of_device_get_match_data(&pdev->dev);
 477        if (!at91_rtc_config)
 478                return -ENODEV;
 479
 480        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 481        if (!regs) {
 482                dev_err(&pdev->dev, "no mmio resource defined\n");
 483                return -ENXIO;
 484        }
 485
 486        irq = platform_get_irq(pdev, 0);
 487        if (irq < 0)
 488                return -ENXIO;
 489
 490        at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
 491                                     resource_size(regs));
 492        if (!at91_rtc_regs) {
 493                dev_err(&pdev->dev, "failed to map registers, aborting.\n");
 494                return -ENOMEM;
 495        }
 496
 497        rtc = devm_rtc_allocate_device(&pdev->dev);
 498        if (IS_ERR(rtc))
 499                return PTR_ERR(rtc);
 500        platform_set_drvdata(pdev, rtc);
 501
 502        sclk = devm_clk_get(&pdev->dev, NULL);
 503        if (IS_ERR(sclk))
 504                return PTR_ERR(sclk);
 505
 506        ret = clk_prepare_enable(sclk);
 507        if (ret) {
 508                dev_err(&pdev->dev, "Could not enable slow clock\n");
 509                return ret;
 510        }
 511
 512        at91_rtc_write(AT91_RTC_CR, 0);
 513        at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD);
 514
 515        /* Disable all interrupts */
 516        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
 517                                        AT91_RTC_SECEV | AT91_RTC_TIMEV |
 518                                        AT91_RTC_CALEV);
 519
 520        ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
 521                               IRQF_SHARED | IRQF_COND_SUSPEND,
 522                               "at91_rtc", pdev);
 523        if (ret) {
 524                dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
 525                goto err_clk;
 526        }
 527
 528        /* cpu init code should really have flagged this device as
 529         * being wake-capable; if it didn't, do that here.
 530         */
 531        if (!device_can_wakeup(&pdev->dev))
 532                device_init_wakeup(&pdev->dev, 1);
 533
 534        if (at91_rtc_config->has_correction)
 535                rtc->ops = &sama5d4_rtc_ops;
 536        else
 537                rtc->ops = &at91_rtc_ops;
 538
 539        rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
 540        rtc->range_max = RTC_TIMESTAMP_END_2099;
 541        ret = devm_rtc_register_device(rtc);
 542        if (ret)
 543                goto err_clk;
 544
 545        /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
 546         * completion.
 547         */
 548        at91_rtc_write_ier(AT91_RTC_SECEV);
 549
 550        dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
 551        return 0;
 552
 553err_clk:
 554        clk_disable_unprepare(sclk);
 555
 556        return ret;
 557}
 558
 559/*
 560 * Disable and remove the RTC driver
 561 */
 562static int __exit at91_rtc_remove(struct platform_device *pdev)
 563{
 564        /* Disable all interrupts */
 565        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
 566                                        AT91_RTC_SECEV | AT91_RTC_TIMEV |
 567                                        AT91_RTC_CALEV);
 568
 569        clk_disable_unprepare(sclk);
 570
 571        return 0;
 572}
 573
 574static void at91_rtc_shutdown(struct platform_device *pdev)
 575{
 576        /* Disable all interrupts */
 577        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
 578                                        AT91_RTC_SECEV | AT91_RTC_TIMEV |
 579                                        AT91_RTC_CALEV);
 580}
 581
 582#ifdef CONFIG_PM_SLEEP
 583
 584/* AT91RM9200 RTC Power management control */
 585
 586static int at91_rtc_suspend(struct device *dev)
 587{
 588        /* this IRQ is shared with DBGU and other hardware which isn't
 589         * necessarily doing PM like we are...
 590         */
 591        at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
 592
 593        at91_rtc_imr = at91_rtc_read_imr()
 594                        & (AT91_RTC_ALARM|AT91_RTC_SECEV);
 595        if (at91_rtc_imr) {
 596                if (device_may_wakeup(dev)) {
 597                        unsigned long flags;
 598
 599                        enable_irq_wake(irq);
 600
 601                        spin_lock_irqsave(&suspended_lock, flags);
 602                        suspended = true;
 603                        spin_unlock_irqrestore(&suspended_lock, flags);
 604                } else {
 605                        at91_rtc_write_idr(at91_rtc_imr);
 606                }
 607        }
 608        return 0;
 609}
 610
 611static int at91_rtc_resume(struct device *dev)
 612{
 613        struct rtc_device *rtc = dev_get_drvdata(dev);
 614
 615        if (at91_rtc_imr) {
 616                if (device_may_wakeup(dev)) {
 617                        unsigned long flags;
 618
 619                        spin_lock_irqsave(&suspended_lock, flags);
 620
 621                        if (cached_events) {
 622                                rtc_update_irq(rtc, 1, cached_events);
 623                                cached_events = 0;
 624                        }
 625
 626                        suspended = false;
 627                        spin_unlock_irqrestore(&suspended_lock, flags);
 628
 629                        disable_irq_wake(irq);
 630                }
 631                at91_rtc_write_ier(at91_rtc_imr);
 632        }
 633        return 0;
 634}
 635#endif
 636
 637static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 638
 639static struct platform_driver at91_rtc_driver = {
 640        .remove         = __exit_p(at91_rtc_remove),
 641        .shutdown       = at91_rtc_shutdown,
 642        .driver         = {
 643                .name   = "at91_rtc",
 644                .pm     = &at91_rtc_pm_ops,
 645                .of_match_table = of_match_ptr(at91_rtc_dt_ids),
 646        },
 647};
 648
 649module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
 650
 651MODULE_AUTHOR("Rick Bronson");
 652MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
 653MODULE_LICENSE("GPL");
 654MODULE_ALIAS("platform:at91_rtc");
 655