LXR linux/drivers/rtc/rtc-pcf2123.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * An SPI driver for the Philips PCF2123 RTC
   4 * Copyright 2009 Cyber Switching, Inc.
   5 *
   6 * Author: Chris Verges <chrisv@cyberswitching.com>
   7 * Maintainers: http://www.cyberswitching.com
   8 *
   9 * based on the RS5C348 driver in this same directory.
  10 *
  11 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
  12 * the sysfs contributions to this driver.
  13 *
  14 * Please note that the CS is active high, so platform data
  15 * should look something like:
  16 *
  17 * static struct spi_board_info ek_spi_devices[] = {
  18 *      ...
  19 *      {
  20 *              .modalias               = "rtc-pcf2123",
  21 *              .chip_select            = 1,
  22 *              .controller_data        = (void *)AT91_PIN_PA10,
  23 *              .max_speed_hz           = 1000 * 1000,
  24 *              .mode                   = SPI_CS_HIGH,
  25 *              .bus_num                = 0,
  26 *      },
  27 *      ...
  28 *};
  29 */
  30
  31#include <linux/bcd.h>
  32#include <linux/delay.h>
  33#include <linux/device.h>
  34#include <linux/errno.h>
  35#include <linux/init.h>
  36#include <linux/kernel.h>
  37#include <linux/of.h>
  38#include <linux/string.h>
  39#include <linux/slab.h>
  40#include <linux/rtc.h>
  41#include <linux/spi/spi.h>
  42#include <linux/module.h>
  43#include <linux/regmap.h>
  44
  45/* REGISTERS */
  46#define PCF2123_REG_CTRL1       (0x00)  /* Control Register 1 */
  47#define PCF2123_REG_CTRL2       (0x01)  /* Control Register 2 */
  48#define PCF2123_REG_SC          (0x02)  /* datetime */
  49#define PCF2123_REG_MN          (0x03)
  50#define PCF2123_REG_HR          (0x04)
  51#define PCF2123_REG_DM          (0x05)
  52#define PCF2123_REG_DW          (0x06)
  53#define PCF2123_REG_MO          (0x07)
  54#define PCF2123_REG_YR          (0x08)
  55#define PCF2123_REG_ALRM_MN     (0x09)  /* Alarm Registers */
  56#define PCF2123_REG_ALRM_HR     (0x0a)
  57#define PCF2123_REG_ALRM_DM     (0x0b)
  58#define PCF2123_REG_ALRM_DW     (0x0c)
  59#define PCF2123_REG_OFFSET      (0x0d)  /* Clock Rate Offset Register */
  60#define PCF2123_REG_TMR_CLKOUT  (0x0e)  /* Timer Registers */
  61#define PCF2123_REG_CTDWN_TMR   (0x0f)
  62
  63/* PCF2123_REG_CTRL1 BITS */
  64#define CTRL1_CLEAR             (0)     /* Clear */
  65#define CTRL1_CORR_INT          BIT(1)  /* Correction irq enable */
  66#define CTRL1_12_HOUR           BIT(2)  /* 12 hour time */
  67#define CTRL1_SW_RESET  (BIT(3) | BIT(4) | BIT(6))      /* Software reset */
  68#define CTRL1_STOP              BIT(5)  /* Stop the clock */
  69#define CTRL1_EXT_TEST          BIT(7)  /* External clock test mode */
  70
  71/* PCF2123_REG_CTRL2 BITS */
  72#define CTRL2_TIE               BIT(0)  /* Countdown timer irq enable */
  73#define CTRL2_AIE               BIT(1)  /* Alarm irq enable */
  74#define CTRL2_TF                BIT(2)  /* Countdown timer flag */
  75#define CTRL2_AF                BIT(3)  /* Alarm flag */
  76#define CTRL2_TI_TP             BIT(4)  /* Irq pin generates pulse */
  77#define CTRL2_MSF               BIT(5)  /* Minute or second irq flag */
  78#define CTRL2_SI                BIT(6)  /* Second irq enable */
  79#define CTRL2_MI                BIT(7)  /* Minute irq enable */
  80
  81/* PCF2123_REG_SC BITS */
  82#define OSC_HAS_STOPPED         BIT(7)  /* Clock has been stopped */
  83
  84/* PCF2123_REG_ALRM_XX BITS */
  85#define ALRM_DISABLE            BIT(7)  /* MN, HR, DM, or DW alarm matching */
  86
  87/* PCF2123_REG_TMR_CLKOUT BITS */
  88#define CD_TMR_4096KHZ          (0)     /* 4096 KHz countdown timer */
  89#define CD_TMR_64HZ             (1)     /* 64 Hz countdown timer */
  90#define CD_TMR_1HZ              (2)     /* 1 Hz countdown timer */
  91#define CD_TMR_60th_HZ          (3)     /* 60th Hz countdown timer */
  92#define CD_TMR_TE               BIT(3)  /* Countdown timer enable */
  93
  94/* PCF2123_REG_OFFSET BITS */
  95#define OFFSET_SIGN_BIT         6       /* 2's complement sign bit */
  96#define OFFSET_COARSE           BIT(7)  /* Coarse mode offset */
  97#define OFFSET_STEP             (2170)  /* Offset step in parts per billion */
  98#define OFFSET_MASK             GENMASK(6, 0)   /* Offset value */
  99
 100/* READ/WRITE ADDRESS BITS */
 101#define PCF2123_WRITE           BIT(4)
 102#define PCF2123_READ            (BIT(4) | BIT(7))
 103
 104
 105static struct spi_driver pcf2123_driver;
 106
 107struct pcf2123_data {
 108        struct rtc_device *rtc;
 109        struct regmap *map;
 110};
 111
 112static const struct regmap_config pcf2123_regmap_config = {
 113        .reg_bits = 8,
 114        .val_bits = 8,
 115        .read_flag_mask = PCF2123_READ,
 116        .write_flag_mask = PCF2123_WRITE,
 117        .max_register = PCF2123_REG_CTDWN_TMR,
 118};
 119
 120static int pcf2123_read_offset(struct device *dev, long *offset)
 121{
 122        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 123        int ret, val;
 124        unsigned int reg;
 125
 126        ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, &reg);
 127        if (ret)
 128                return ret;
 129
 130        val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
 131
 132        if (reg & OFFSET_COARSE)
 133                val *= 2;
 134
 135        *offset = ((long)val) * OFFSET_STEP;
 136
 137        return 0;
 138}
 139
 140/*
 141 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
 142 * The main difference between the two is normal offset adjusts the first
 143 * second of n minutes every other hour, with 61, 62 and 63 being shoved
 144 * into the 60th minute.
 145 * The coarse adjustment does the same, but every hour.
 146 * the two overlap, with every even normal offset value corresponding
 147 * to a coarse offset. Based on this algorithm, it seems that despite the
 148 * name, coarse offset is a better fit for overlapping values.
 149 */
 150static int pcf2123_set_offset(struct device *dev, long offset)
 151{
 152        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 153        s8 reg;
 154
 155        if (offset > OFFSET_STEP * 127)
 156                reg = 127;
 157        else if (offset < OFFSET_STEP * -128)
 158                reg = -128;
 159        else
 160                reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
 161
 162        /* choose fine offset only for odd values in the normal range */
 163        if (reg & 1 && reg <= 63 && reg >= -64) {
 164                /* Normal offset. Clear the coarse bit */
 165                reg &= ~OFFSET_COARSE;
 166        } else {
 167                /* Coarse offset. Divide by 2 and set the coarse bit */
 168                reg >>= 1;
 169                reg |= OFFSET_COARSE;
 170        }
 171
 172        return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg);
 173}
 174
 175static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
 176{
 177        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 178        u8 rxbuf[7];
 179        int ret;
 180
 181        ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_SC, rxbuf,
 182                                sizeof(rxbuf));
 183        if (ret)
 184                return ret;
 185
 186        if (rxbuf[0] & OSC_HAS_STOPPED) {
 187                dev_info(dev, "clock was stopped. Time is not valid\n");
 188                return -EINVAL;
 189        }
 190
 191        tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
 192        tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
 193        tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
 194        tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
 195        tm->tm_wday = rxbuf[4] & 0x07;
 196        tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
 197        tm->tm_year = bcd2bin(rxbuf[6]) + 100;
 198
 199        dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
 200
 201        return 0;
 202}
 203
 204static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
 205{
 206        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 207        u8 txbuf[7];
 208        int ret;
 209
 210        dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
 211
 212        /* Stop the counter first */
 213        ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
 214        if (ret)
 215                return ret;
 216
 217        /* Set the new time */
 218        txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
 219        txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
 220        txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
 221        txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
 222        txbuf[4] = tm->tm_wday & 0x07;
 223        txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
 224        txbuf[6] = bin2bcd(tm->tm_year - 100);
 225
 226        ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_SC, txbuf,
 227                                sizeof(txbuf));
 228        if (ret)
 229                return ret;
 230
 231        /* Start the counter */
 232        ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
 233        if (ret)
 234                return ret;
 235
 236        return 0;
 237}
 238
 239static int pcf2123_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
 240{
 241        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 242
 243        return regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE,
 244                                  en ? CTRL2_AIE : 0);
 245}
 246
 247static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 248{
 249        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 250        u8 rxbuf[4];
 251        int ret;
 252        unsigned int val = 0;
 253
 254        ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_ALRM_MN, rxbuf,
 255                                sizeof(rxbuf));
 256        if (ret)
 257                return ret;
 258
 259        alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
 260        alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
 261        alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
 262        alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
 263
 264        dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
 265
 266        ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
 267        if (ret)
 268                return ret;
 269
 270        alm->enabled = !!(val & CTRL2_AIE);
 271
 272        return 0;
 273}
 274
 275static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 276{
 277        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 278        u8 txbuf[4];
 279        int ret;
 280
 281        dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
 282
 283        /* Disable alarm interrupt */
 284        ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
 285        if (ret)
 286                return ret;
 287
 288        /* Ensure alarm flag is clear */
 289        ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
 290        if (ret)
 291                return ret;
 292
 293        /* Set new alarm */
 294        txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
 295        txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
 296        txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
 297        txbuf[3] = ALRM_DISABLE;
 298
 299        ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_ALRM_MN, txbuf,
 300                                sizeof(txbuf));
 301        if (ret)
 302                return ret;
 303
 304        return pcf2123_rtc_alarm_irq_enable(dev, alm->enabled);
 305}
 306
 307static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
 308{
 309        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 310        unsigned int val = 0;
 311        int ret = IRQ_NONE;
 312
 313        rtc_lock(pcf2123->rtc);
 314        regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
 315
 316        /* Alarm? */
 317        if (val & CTRL2_AF) {
 318                ret = IRQ_HANDLED;
 319
 320                /* Clear alarm flag */
 321                regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
 322
 323                rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF);
 324        }
 325
 326        rtc_unlock(pcf2123->rtc);
 327
 328        return ret;
 329}
 330
 331static int pcf2123_reset(struct device *dev)
 332{
 333        struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
 334        int ret;
 335        unsigned int val = 0;
 336
 337        ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
 338        if (ret)
 339                return ret;
 340
 341        /* Stop the counter */
 342        dev_dbg(dev, "stopping RTC\n");
 343        ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
 344        if (ret)
 345                return ret;
 346
 347        /* See if the counter was actually stopped */
 348        dev_dbg(dev, "checking for presence of RTC\n");
 349        ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val);
 350        if (ret)
 351                return ret;
 352
 353        dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
 354        if (!(val & CTRL1_STOP))
 355                return -ENODEV;
 356
 357        /* Start the counter */
 358        ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
 359        if (ret)
 360                return ret;
 361
 362        return 0;
 363}
 364
 365static const struct rtc_class_ops pcf2123_rtc_ops = {
 366        .read_time      = pcf2123_rtc_read_time,
 367        .set_time       = pcf2123_rtc_set_time,
 368        .read_offset    = pcf2123_read_offset,
 369        .set_offset     = pcf2123_set_offset,
 370        .read_alarm     = pcf2123_rtc_read_alarm,
 371        .set_alarm      = pcf2123_rtc_set_alarm,
 372        .alarm_irq_enable = pcf2123_rtc_alarm_irq_enable,
 373};
 374
 375static int pcf2123_probe(struct spi_device *spi)
 376{
 377        struct rtc_device *rtc;
 378        struct rtc_time tm;
 379        struct pcf2123_data *pcf2123;
 380        int ret = 0;
 381
 382        pcf2123 = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_data),
 383                                GFP_KERNEL);
 384        if (!pcf2123)
 385                return -ENOMEM;
 386
 387        dev_set_drvdata(&spi->dev, pcf2123);
 388
 389        pcf2123->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
 390        if (IS_ERR(pcf2123->map)) {
 391                dev_err(&spi->dev, "regmap init failed.\n");
 392                return PTR_ERR(pcf2123->map);
 393        }
 394
 395        ret = pcf2123_rtc_read_time(&spi->dev, &tm);
 396        if (ret < 0) {
 397                ret = pcf2123_reset(&spi->dev);
 398                if (ret < 0) {
 399                        dev_err(&spi->dev, "chip not found\n");
 400                        return ret;
 401                }
 402        }
 403
 404        dev_info(&spi->dev, "spiclk %u KHz.\n",
 405                        (spi->max_speed_hz + 500) / 1000);
 406
 407        /* Finalize the initialization */
 408        rtc = devm_rtc_allocate_device(&spi->dev);
 409        if (IS_ERR(rtc))
 410                return PTR_ERR(rtc);
 411
 412        pcf2123->rtc = rtc;
 413
 414        /* Register alarm irq */
 415        if (spi->irq > 0) {
 416                ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
 417                                pcf2123_rtc_irq,
 418                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 419                                pcf2123_driver.driver.name, &spi->dev);
 420                if (!ret)
 421                        device_init_wakeup(&spi->dev, true);
 422                else
 423                        dev_err(&spi->dev, "could not request irq.\n");
 424        }
 425
 426        /* The PCF2123's alarm only has minute accuracy. Must add timer
 427         * support to this driver to generate interrupts more than once
 428         * per minute.
 429         */
 430        rtc->uie_unsupported = 1;
 431        rtc->ops = &pcf2123_rtc_ops;
 432        rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
 433        rtc->range_max = RTC_TIMESTAMP_END_2099;
 434        rtc->set_start_time = true;
 435
 436        ret = devm_rtc_register_device(rtc);
 437        if (ret)
 438                return ret;
 439
 440        return 0;
 441}
 442
 443#ifdef CONFIG_OF
 444static const struct of_device_id pcf2123_dt_ids[] = {
 445        { .compatible = "nxp,pcf2123", },
 446        { .compatible = "microcrystal,rv2123", },
 447        /* Deprecated, do not use */
 448        { .compatible = "nxp,rtc-pcf2123", },
 449        { /* sentinel */ }
 450};
 451MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
 452#endif
 453
 454static struct spi_driver pcf2123_driver = {
 455        .driver = {
 456                        .name   = "rtc-pcf2123",
 457                        .of_match_table = of_match_ptr(pcf2123_dt_ids),
 458        },
 459        .probe  = pcf2123_probe,
 460};
 461
 462module_spi_driver(pcf2123_driver);
 463
 464MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
 465MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
 466MODULE_LICENSE("GPL");
 467