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43#include <linux/fs.h>
44#include <linux/init.h>
45#include <linux/types.h>
46#include <linux/errno.h>
47#include <linux/kernel.h>
48#include <linux/slab.h>
49#include <linux/vmalloc.h>
50#include <linux/ioport.h>
51#include <linux/delay.h>
52#include <linux/pci.h>
53#include <linux/wait.h>
54#include <linux/spinlock.h>
55#include <linux/sched.h>
56#include <linux/interrupt.h>
57#include <linux/blkdev.h>
58#include <linux/firmware.h>
59#include <linux/module.h>
60#include <linux/moduleparam.h>
61#include <linux/libata.h>
62#include <linux/hdreg.h>
63#include <linux/reboot.h>
64#include <linux/stringify.h>
65#include <asm/io.h>
66#include <asm/irq.h>
67#include <asm/processor.h>
68#include <scsi/scsi.h>
69#include <scsi/scsi_host.h>
70#include <scsi/scsi_tcq.h>
71#include <scsi/scsi_eh.h>
72#include <scsi/scsi_cmnd.h>
73#include "ipr.h"
74
75
76
77
78static LIST_HEAD(ipr_ioa_head);
79static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
80static unsigned int ipr_max_speed = 1;
81static int ipr_testmode = 0;
82static unsigned int ipr_fastfail = 0;
83static unsigned int ipr_transop_timeout = 0;
84static unsigned int ipr_debug = 0;
85static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
86static unsigned int ipr_dual_ioa_raid = 1;
87static unsigned int ipr_number_of_msix = 16;
88static unsigned int ipr_fast_reboot;
89static DEFINE_SPINLOCK(ipr_driver_lock);
90
91
92static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
93 {
94 .mailbox = 0x0042C,
95 .max_cmds = 100,
96 .cache_line_size = 0x20,
97 .clear_isr = 1,
98 .iopoll_weight = 0,
99 {
100 .set_interrupt_mask_reg = 0x0022C,
101 .clr_interrupt_mask_reg = 0x00230,
102 .clr_interrupt_mask_reg32 = 0x00230,
103 .sense_interrupt_mask_reg = 0x0022C,
104 .sense_interrupt_mask_reg32 = 0x0022C,
105 .clr_interrupt_reg = 0x00228,
106 .clr_interrupt_reg32 = 0x00228,
107 .sense_interrupt_reg = 0x00224,
108 .sense_interrupt_reg32 = 0x00224,
109 .ioarrin_reg = 0x00404,
110 .sense_uproc_interrupt_reg = 0x00214,
111 .sense_uproc_interrupt_reg32 = 0x00214,
112 .set_uproc_interrupt_reg = 0x00214,
113 .set_uproc_interrupt_reg32 = 0x00214,
114 .clr_uproc_interrupt_reg = 0x00218,
115 .clr_uproc_interrupt_reg32 = 0x00218
116 }
117 },
118 {
119 .mailbox = 0x0052C,
120 .max_cmds = 100,
121 .cache_line_size = 0x20,
122 .clear_isr = 1,
123 .iopoll_weight = 0,
124 {
125 .set_interrupt_mask_reg = 0x00288,
126 .clr_interrupt_mask_reg = 0x0028C,
127 .clr_interrupt_mask_reg32 = 0x0028C,
128 .sense_interrupt_mask_reg = 0x00288,
129 .sense_interrupt_mask_reg32 = 0x00288,
130 .clr_interrupt_reg = 0x00284,
131 .clr_interrupt_reg32 = 0x00284,
132 .sense_interrupt_reg = 0x00280,
133 .sense_interrupt_reg32 = 0x00280,
134 .ioarrin_reg = 0x00504,
135 .sense_uproc_interrupt_reg = 0x00290,
136 .sense_uproc_interrupt_reg32 = 0x00290,
137 .set_uproc_interrupt_reg = 0x00290,
138 .set_uproc_interrupt_reg32 = 0x00290,
139 .clr_uproc_interrupt_reg = 0x00294,
140 .clr_uproc_interrupt_reg32 = 0x00294
141 }
142 },
143 {
144 .mailbox = 0x00044,
145 .max_cmds = 1000,
146 .cache_line_size = 0x20,
147 .clear_isr = 0,
148 .iopoll_weight = 64,
149 {
150 .set_interrupt_mask_reg = 0x00010,
151 .clr_interrupt_mask_reg = 0x00018,
152 .clr_interrupt_mask_reg32 = 0x0001C,
153 .sense_interrupt_mask_reg = 0x00010,
154 .sense_interrupt_mask_reg32 = 0x00014,
155 .clr_interrupt_reg = 0x00008,
156 .clr_interrupt_reg32 = 0x0000C,
157 .sense_interrupt_reg = 0x00000,
158 .sense_interrupt_reg32 = 0x00004,
159 .ioarrin_reg = 0x00070,
160 .sense_uproc_interrupt_reg = 0x00020,
161 .sense_uproc_interrupt_reg32 = 0x00024,
162 .set_uproc_interrupt_reg = 0x00020,
163 .set_uproc_interrupt_reg32 = 0x00024,
164 .clr_uproc_interrupt_reg = 0x00028,
165 .clr_uproc_interrupt_reg32 = 0x0002C,
166 .init_feedback_reg = 0x0005C,
167 .dump_addr_reg = 0x00064,
168 .dump_data_reg = 0x00068,
169 .endian_swap_reg = 0x00084
170 }
171 },
172};
173
174static const struct ipr_chip_t ipr_chip[] = {
175 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
176 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
177 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
178 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
179 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, true, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
180 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
181 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
182 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
183 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
184 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
185};
186
187static int ipr_max_bus_speeds[] = {
188 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
189};
190
191MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
192MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
193module_param_named(max_speed, ipr_max_speed, uint, 0);
194MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
195module_param_named(log_level, ipr_log_level, uint, 0);
196MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
197module_param_named(testmode, ipr_testmode, int, 0);
198MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
199module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
200MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
201module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
202MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
203module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
204MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
205module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
206MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
207module_param_named(max_devs, ipr_max_devs, int, 0);
208MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
209 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
210module_param_named(number_of_msix, ipr_number_of_msix, int, 0);
211MODULE_PARM_DESC(number_of_msix, "Specify the number of MSIX interrupts to use on capable adapters (1 - 16). (default:16)");
212module_param_named(fast_reboot, ipr_fast_reboot, int, S_IRUGO | S_IWUSR);
213MODULE_PARM_DESC(fast_reboot, "Skip adapter shutdown during reboot. Set to 1 to enable. (default: 0)");
214MODULE_LICENSE("GPL");
215MODULE_VERSION(IPR_DRIVER_VERSION);
216
217
218static const
219struct ipr_error_table_t ipr_error_table[] = {
220 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
221 "8155: An unknown error was received"},
222 {0x00330000, 0, 0,
223 "Soft underlength error"},
224 {0x005A0000, 0, 0,
225 "Command to be cancelled not found"},
226 {0x00808000, 0, 0,
227 "Qualified success"},
228 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
229 "FFFE: Soft device bus error recovered by the IOA"},
230 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
231 "4101: Soft device bus fabric error"},
232 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
233 "FFFC: Logical block guard error recovered by the device"},
234 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
235 "FFFC: Logical block reference tag error recovered by the device"},
236 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
237 "4171: Recovered scatter list tag / sequence number error"},
238 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
239 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
240 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
241 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
242 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
243 "FFFD: Recovered logical block reference tag error detected by the IOA"},
244 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
245 "FFFD: Logical block guard error recovered by the IOA"},
246 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
247 "FFF9: Device sector reassign successful"},
248 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
249 "FFF7: Media error recovered by device rewrite procedures"},
250 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
251 "7001: IOA sector reassignment successful"},
252 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FFF9: Soft media error. Sector reassignment recommended"},
254 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
255 "FFF7: Media error recovered by IOA rewrite procedures"},
256 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
257 "FF3D: Soft PCI bus error recovered by the IOA"},
258 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
259 "FFF6: Device hardware error recovered by the IOA"},
260 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
261 "FFF6: Device hardware error recovered by the device"},
262 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
263 "FF3D: Soft IOA error recovered by the IOA"},
264 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
265 "FFFA: Undefined device response recovered by the IOA"},
266 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
267 "FFF6: Device bus error, message or command phase"},
268 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
269 "FFFE: Task Management Function failed"},
270 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
271 "FFF6: Failure prediction threshold exceeded"},
272 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
273 "8009: Impending cache battery pack failure"},
274 {0x02040100, 0, 0,
275 "Logical Unit in process of becoming ready"},
276 {0x02040200, 0, 0,
277 "Initializing command required"},
278 {0x02040400, 0, 0,
279 "34FF: Disk device format in progress"},
280 {0x02040C00, 0, 0,
281 "Logical unit not accessible, target port in unavailable state"},
282 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
283 "9070: IOA requested reset"},
284 {0x023F0000, 0, 0,
285 "Synchronization required"},
286 {0x02408500, 0, 0,
287 "IOA microcode download required"},
288 {0x02408600, 0, 0,
289 "Device bus connection is prohibited by host"},
290 {0x024E0000, 0, 0,
291 "No ready, IOA shutdown"},
292 {0x025A0000, 0, 0,
293 "Not ready, IOA has been shutdown"},
294 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
295 "3020: Storage subsystem configuration error"},
296 {0x03110B00, 0, 0,
297 "FFF5: Medium error, data unreadable, recommend reassign"},
298 {0x03110C00, 0, 0,
299 "7000: Medium error, data unreadable, do not reassign"},
300 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
301 "FFF3: Disk media format bad"},
302 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
303 "3002: Addressed device failed to respond to selection"},
304 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
305 "3100: Device bus error"},
306 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
307 "3109: IOA timed out a device command"},
308 {0x04088000, 0, 0,
309 "3120: SCSI bus is not operational"},
310 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
311 "4100: Hard device bus fabric error"},
312 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
313 "310C: Logical block guard error detected by the device"},
314 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
315 "310C: Logical block reference tag error detected by the device"},
316 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
317 "4170: Scatter list tag / sequence number error"},
318 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
319 "8150: Logical block CRC error on IOA to Host transfer"},
320 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
321 "4170: Logical block sequence number error on IOA to Host transfer"},
322 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
323 "310D: Logical block reference tag error detected by the IOA"},
324 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
325 "310D: Logical block guard error detected by the IOA"},
326 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
327 "9000: IOA reserved area data check"},
328 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
329 "9001: IOA reserved area invalid data pattern"},
330 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
331 "9002: IOA reserved area LRC error"},
332 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
333 "Hardware Error, IOA metadata access error"},
334 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
335 "102E: Out of alternate sectors for disk storage"},
336 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
337 "FFF4: Data transfer underlength error"},
338 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
339 "FFF4: Data transfer overlength error"},
340 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
341 "3400: Logical unit failure"},
342 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
343 "FFF4: Device microcode is corrupt"},
344 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
345 "8150: PCI bus error"},
346 {0x04430000, 1, 0,
347 "Unsupported device bus message received"},
348 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
349 "FFF4: Disk device problem"},
350 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
351 "8150: Permanent IOA failure"},
352 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
353 "3010: Disk device returned wrong response to IOA"},
354 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
355 "8151: IOA microcode error"},
356 {0x04448500, 0, 0,
357 "Device bus status error"},
358 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
359 "8157: IOA error requiring IOA reset to recover"},
360 {0x04448700, 0, 0,
361 "ATA device status error"},
362 {0x04490000, 0, 0,
363 "Message reject received from the device"},
364 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
365 "8008: A permanent cache battery pack failure occurred"},
366 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
367 "9090: Disk unit has been modified after the last known status"},
368 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
369 "9081: IOA detected device error"},
370 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
371 "9082: IOA detected device error"},
372 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
373 "3110: Device bus error, message or command phase"},
374 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
375 "3110: SAS Command / Task Management Function failed"},
376 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
377 "9091: Incorrect hardware configuration change has been detected"},
378 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
379 "9073: Invalid multi-adapter configuration"},
380 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
381 "4010: Incorrect connection between cascaded expanders"},
382 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
383 "4020: Connections exceed IOA design limits"},
384 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
385 "4030: Incorrect multipath connection"},
386 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
387 "4110: Unsupported enclosure function"},
388 {0x04679800, 0, IPR_DEFAULT_LOG_LEVEL,
389 "4120: SAS cable VPD cannot be read"},
390 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
391 "FFF4: Command to logical unit failed"},
392 {0x05240000, 1, 0,
393 "Illegal request, invalid request type or request packet"},
394 {0x05250000, 0, 0,
395 "Illegal request, invalid resource handle"},
396 {0x05258000, 0, 0,
397 "Illegal request, commands not allowed to this device"},
398 {0x05258100, 0, 0,
399 "Illegal request, command not allowed to a secondary adapter"},
400 {0x05258200, 0, 0,
401 "Illegal request, command not allowed to a non-optimized resource"},
402 {0x05260000, 0, 0,
403 "Illegal request, invalid field in parameter list"},
404 {0x05260100, 0, 0,
405 "Illegal request, parameter not supported"},
406 {0x05260200, 0, 0,
407 "Illegal request, parameter value invalid"},
408 {0x052C0000, 0, 0,
409 "Illegal request, command sequence error"},
410 {0x052C8000, 1, 0,
411 "Illegal request, dual adapter support not enabled"},
412 {0x052C8100, 1, 0,
413 "Illegal request, another cable connector was physically disabled"},
414 {0x054E8000, 1, 0,
415 "Illegal request, inconsistent group id/group count"},
416 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
417 "9031: Array protection temporarily suspended, protection resuming"},
418 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
419 "9040: Array protection temporarily suspended, protection resuming"},
420 {0x060B0100, 0, IPR_DEFAULT_LOG_LEVEL,
421 "4080: IOA exceeded maximum operating temperature"},
422 {0x060B8000, 0, IPR_DEFAULT_LOG_LEVEL,
423 "4085: Service required"},
424 {0x060B8100, 0, IPR_DEFAULT_LOG_LEVEL,
425 "4086: SAS Adapter Hardware Configuration Error"},
426 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
427 "3140: Device bus not ready to ready transition"},
428 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
429 "FFFB: SCSI bus was reset"},
430 {0x06290500, 0, 0,
431 "FFFE: SCSI bus transition to single ended"},
432 {0x06290600, 0, 0,
433 "FFFE: SCSI bus transition to LVD"},
434 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
435 "FFFB: SCSI bus was reset by another initiator"},
436 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
437 "3029: A device replacement has occurred"},
438 {0x063F8300, 0, IPR_DEFAULT_LOG_LEVEL,
439 "4102: Device bus fabric performance degradation"},
440 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
441 "9051: IOA cache data exists for a missing or failed device"},
442 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
443 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
444 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
445 "9025: Disk unit is not supported at its physical location"},
446 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
447 "3020: IOA detected a SCSI bus configuration error"},
448 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
449 "3150: SCSI bus configuration error"},
450 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
451 "9074: Asymmetric advanced function disk configuration"},
452 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
453 "4040: Incomplete multipath connection between IOA and enclosure"},
454 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
455 "4041: Incomplete multipath connection between enclosure and device"},
456 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
457 "9075: Incomplete multipath connection between IOA and remote IOA"},
458 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
459 "9076: Configuration error, missing remote IOA"},
460 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
461 "4050: Enclosure does not support a required multipath function"},
462 {0x06679800, 0, IPR_DEFAULT_LOG_LEVEL,
463 "4121: Configuration error, required cable is missing"},
464 {0x06679900, 0, IPR_DEFAULT_LOG_LEVEL,
465 "4122: Cable is not plugged into the correct location on remote IOA"},
466 {0x06679A00, 0, IPR_DEFAULT_LOG_LEVEL,
467 "4123: Configuration error, invalid cable vital product data"},
468 {0x06679B00, 0, IPR_DEFAULT_LOG_LEVEL,
469 "4124: Configuration error, both cable ends are plugged into the same IOA"},
470 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
471 "4070: Logically bad block written on device"},
472 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
473 "9041: Array protection temporarily suspended"},
474 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
475 "9042: Corrupt array parity detected on specified device"},
476 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
477 "9030: Array no longer protected due to missing or failed disk unit"},
478 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
479 "9071: Link operational transition"},
480 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
481 "9072: Link not operational transition"},
482 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
483 "9032: Array exposed but still protected"},
484 {0x066B8300, 0, IPR_DEBUG_LOG_LEVEL,
485 "70DD: Device forced failed by disrupt device command"},
486 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
487 "4061: Multipath redundancy level got better"},
488 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
489 "4060: Multipath redundancy level got worse"},
490 {0x06808100, 0, IPR_DEBUG_LOG_LEVEL,
491 "9083: Device raw mode enabled"},
492 {0x06808200, 0, IPR_DEBUG_LOG_LEVEL,
493 "9084: Device raw mode disabled"},
494 {0x07270000, 0, 0,
495 "Failure due to other device"},
496 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
497 "9008: IOA does not support functions expected by devices"},
498 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
499 "9010: Cache data associated with attached devices cannot be found"},
500 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
501 "9011: Cache data belongs to devices other than those attached"},
502 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
503 "9020: Array missing 2 or more devices with only 1 device present"},
504 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
505 "9021: Array missing 2 or more devices with 2 or more devices present"},
506 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
507 "9022: Exposed array is missing a required device"},
508 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
509 "9023: Array member(s) not at required physical locations"},
510 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
511 "9024: Array not functional due to present hardware configuration"},
512 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
513 "9026: Array not functional due to present hardware configuration"},
514 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
515 "9027: Array is missing a device and parity is out of sync"},
516 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
517 "9028: Maximum number of arrays already exist"},
518 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
519 "9050: Required cache data cannot be located for a disk unit"},
520 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
521 "9052: Cache data exists for a device that has been modified"},
522 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
523 "9054: IOA resources not available due to previous problems"},
524 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
525 "9092: Disk unit requires initialization before use"},
526 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
527 "9029: Incorrect hardware configuration change has been detected"},
528 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
529 "9060: One or more disk pairs are missing from an array"},
530 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
531 "9061: One or more disks are missing from an array"},
532 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
533 "9062: One or more disks are missing from an array"},
534 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
535 "9063: Maximum number of functional arrays has been exceeded"},
536 {0x07279A00, 0, 0,
537 "Data protect, other volume set problem"},
538 {0x0B260000, 0, 0,
539 "Aborted command, invalid descriptor"},
540 {0x0B3F9000, 0, 0,
541 "Target operating conditions have changed, dual adapter takeover"},
542 {0x0B530200, 0, 0,
543 "Aborted command, medium removal prevented"},
544 {0x0B5A0000, 0, 0,
545 "Command terminated by host"},
546 {0x0B5B8000, 0, 0,
547 "Aborted command, command terminated by host"}
548};
549
550static const struct ipr_ses_table_entry ipr_ses_table[] = {
551 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
552 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
553 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
554 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
555 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
556 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
557 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
558 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
559 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
560 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
561 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
562 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
563 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
564};
565
566
567
568
569static int ipr_reset_alert(struct ipr_cmnd *);
570static void ipr_process_ccn(struct ipr_cmnd *);
571static void ipr_process_error(struct ipr_cmnd *);
572static void ipr_reset_ioa_job(struct ipr_cmnd *);
573static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
574 enum ipr_shutdown_type);
575
576#ifdef CONFIG_SCSI_IPR_TRACE
577
578
579
580
581
582
583
584
585
586static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
587 u8 type, u32 add_data)
588{
589 struct ipr_trace_entry *trace_entry;
590 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
591 unsigned int trace_index;
592
593 trace_index = atomic_add_return(1, &ioa_cfg->trace_index) & IPR_TRACE_INDEX_MASK;
594 trace_entry = &ioa_cfg->trace[trace_index];
595 trace_entry->time = jiffies;
596 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
597 trace_entry->type = type;
598 if (ipr_cmd->ioa_cfg->sis64)
599 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
600 else
601 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
602 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
603 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
604 trace_entry->u.add_data = add_data;
605 wmb();
606}
607#else
608#define ipr_trc_hook(ipr_cmd, type, add_data) do { } while (0)
609#endif
610
611
612
613
614
615
616
617
618static void ipr_lock_and_done(struct ipr_cmnd *ipr_cmd)
619{
620 unsigned long lock_flags;
621 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
622
623 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
624 ipr_cmd->done(ipr_cmd);
625 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
626}
627
628
629
630
631
632
633
634
635static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
636{
637 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
638 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
639 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
640 dma_addr_t dma_addr = ipr_cmd->dma_addr;
641 int hrrq_id;
642
643 hrrq_id = ioarcb->cmd_pkt.hrrq_id;
644 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
645 ioarcb->cmd_pkt.hrrq_id = hrrq_id;
646 ioarcb->data_transfer_length = 0;
647 ioarcb->read_data_transfer_length = 0;
648 ioarcb->ioadl_len = 0;
649 ioarcb->read_ioadl_len = 0;
650
651 if (ipr_cmd->ioa_cfg->sis64) {
652 ioarcb->u.sis64_addr_data.data_ioadl_addr =
653 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
654 ioasa64->u.gata.status = 0;
655 } else {
656 ioarcb->write_ioadl_addr =
657 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
658 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
659 ioasa->u.gata.status = 0;
660 }
661
662 ioasa->hdr.ioasc = 0;
663 ioasa->hdr.residual_data_len = 0;
664 ipr_cmd->scsi_cmd = NULL;
665 ipr_cmd->qc = NULL;
666 ipr_cmd->sense_buffer[0] = 0;
667 ipr_cmd->dma_use_sg = 0;
668}
669
670
671
672
673
674
675
676
677
678static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
679 void (*fast_done) (struct ipr_cmnd *))
680{
681 ipr_reinit_ipr_cmnd(ipr_cmd);
682 ipr_cmd->u.scratch = 0;
683 ipr_cmd->sibling = NULL;
684 ipr_cmd->eh_comp = NULL;
685 ipr_cmd->fast_done = fast_done;
686 timer_setup(&ipr_cmd->timer, NULL, 0);
687}
688
689
690
691
692
693
694
695
696static
697struct ipr_cmnd *__ipr_get_free_ipr_cmnd(struct ipr_hrr_queue *hrrq)
698{
699 struct ipr_cmnd *ipr_cmd = NULL;
700
701 if (likely(!list_empty(&hrrq->hrrq_free_q))) {
702 ipr_cmd = list_entry(hrrq->hrrq_free_q.next,
703 struct ipr_cmnd, queue);
704 list_del(&ipr_cmd->queue);
705 }
706
707
708 return ipr_cmd;
709}
710
711
712
713
714
715
716
717
718static
719struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
720{
721 struct ipr_cmnd *ipr_cmd =
722 __ipr_get_free_ipr_cmnd(&ioa_cfg->hrrq[IPR_INIT_HRRQ]);
723 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
724 return ipr_cmd;
725}
726
727
728
729
730
731
732
733
734
735
736
737
738static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
739 u32 clr_ints)
740{
741 int i;
742
743
744 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
745 spin_lock(&ioa_cfg->hrrq[i]._lock);
746 ioa_cfg->hrrq[i].allow_interrupts = 0;
747 spin_unlock(&ioa_cfg->hrrq[i]._lock);
748 }
749
750
751 if (ioa_cfg->sis64)
752 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
753 else
754 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
755
756
757 if (ioa_cfg->sis64)
758 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
759 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
760 readl(ioa_cfg->regs.sense_interrupt_reg);
761}
762
763
764
765
766
767
768
769
770static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
771{
772 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
773
774 if (pcix_cmd_reg == 0)
775 return 0;
776
777 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
778 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
779 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
780 return -EIO;
781 }
782
783 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
784 return 0;
785}
786
787
788
789
790
791
792
793
794static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
795{
796 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
797
798 if (pcix_cmd_reg) {
799 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
800 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
801 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
802 return -EIO;
803 }
804 }
805
806 return 0;
807}
808
809
810
811
812
813
814
815
816
817
818
819static void __ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
820{
821 struct ata_queued_cmd *qc = ipr_cmd->qc;
822 struct ipr_sata_port *sata_port = qc->ap->private_data;
823
824 qc->err_mask |= AC_ERR_OTHER;
825 sata_port->ioasa.status |= ATA_BUSY;
826 ata_qc_complete(qc);
827 if (ipr_cmd->eh_comp)
828 complete(ipr_cmd->eh_comp);
829 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
830}
831
832
833
834
835
836
837
838
839
840
841
842static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
843{
844 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
845 unsigned long hrrq_flags;
846
847 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
848 __ipr_sata_eh_done(ipr_cmd);
849 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
850}
851
852
853
854
855
856
857
858
859
860
861
862static void __ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
863{
864 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
865
866 scsi_cmd->result |= (DID_ERROR << 16);
867
868 scsi_dma_unmap(ipr_cmd->scsi_cmd);
869 scsi_cmd->scsi_done(scsi_cmd);
870 if (ipr_cmd->eh_comp)
871 complete(ipr_cmd->eh_comp);
872 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
873}
874
875
876
877
878
879
880
881
882
883
884
885static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
886{
887 unsigned long hrrq_flags;
888 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
889
890 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
891 __ipr_scsi_eh_done(ipr_cmd);
892 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
893}
894
895
896
897
898
899
900
901
902
903
904static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
905{
906 struct ipr_cmnd *ipr_cmd, *temp;
907 struct ipr_hrr_queue *hrrq;
908
909 ENTER;
910 for_each_hrrq(hrrq, ioa_cfg) {
911 spin_lock(&hrrq->_lock);
912 list_for_each_entry_safe(ipr_cmd,
913 temp, &hrrq->hrrq_pending_q, queue) {
914 list_del(&ipr_cmd->queue);
915
916 ipr_cmd->s.ioasa.hdr.ioasc =
917 cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
918 ipr_cmd->s.ioasa.hdr.ilid =
919 cpu_to_be32(IPR_DRIVER_ILID);
920
921 if (ipr_cmd->scsi_cmd)
922 ipr_cmd->done = __ipr_scsi_eh_done;
923 else if (ipr_cmd->qc)
924 ipr_cmd->done = __ipr_sata_eh_done;
925
926 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH,
927 IPR_IOASC_IOA_WAS_RESET);
928 del_timer(&ipr_cmd->timer);
929 ipr_cmd->done(ipr_cmd);
930 }
931 spin_unlock(&hrrq->_lock);
932 }
933 LEAVE;
934}
935
936
937
938
939
940
941
942
943
944
945
946
947static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
948{
949 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
950 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
951
952 if (ioa_cfg->sis64) {
953
954 send_dma_addr |= 0x1;
955
956
957
958 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
959 send_dma_addr |= 0x4;
960 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
961 } else
962 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
963}
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
979 void (*done) (struct ipr_cmnd *),
980 void (*timeout_func) (struct timer_list *), u32 timeout)
981{
982 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
983
984 ipr_cmd->done = done;
985
986 ipr_cmd->timer.expires = jiffies + timeout;
987 ipr_cmd->timer.function = timeout_func;
988
989 add_timer(&ipr_cmd->timer);
990
991 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
992
993 ipr_send_command(ipr_cmd);
994}
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
1007{
1008 if (ipr_cmd->sibling)
1009 ipr_cmd->sibling = NULL;
1010 else
1011 complete(&ipr_cmd->completion);
1012}
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
1028 u32 len, int flags)
1029{
1030 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
1031 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
1032
1033 ipr_cmd->dma_use_sg = 1;
1034
1035 if (ipr_cmd->ioa_cfg->sis64) {
1036 ioadl64->flags = cpu_to_be32(flags);
1037 ioadl64->data_len = cpu_to_be32(len);
1038 ioadl64->address = cpu_to_be64(dma_addr);
1039
1040 ipr_cmd->ioarcb.ioadl_len =
1041 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
1042 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1043 } else {
1044 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
1045 ioadl->address = cpu_to_be32(dma_addr);
1046
1047 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
1048 ipr_cmd->ioarcb.read_ioadl_len =
1049 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1050 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
1051 } else {
1052 ipr_cmd->ioarcb.ioadl_len =
1053 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1054 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1055 }
1056 }
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
1069 void (*timeout_func) (struct timer_list *),
1070 u32 timeout)
1071{
1072 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1073
1074 init_completion(&ipr_cmd->completion);
1075 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
1076
1077 spin_unlock_irq(ioa_cfg->host->host_lock);
1078 wait_for_completion(&ipr_cmd->completion);
1079 spin_lock_irq(ioa_cfg->host->host_lock);
1080}
1081
1082static int ipr_get_hrrq_index(struct ipr_ioa_cfg *ioa_cfg)
1083{
1084 unsigned int hrrq;
1085
1086 if (ioa_cfg->hrrq_num == 1)
1087 hrrq = 0;
1088 else {
1089 hrrq = atomic_add_return(1, &ioa_cfg->hrrq_index);
1090 hrrq = (hrrq % (ioa_cfg->hrrq_num - 1)) + 1;
1091 }
1092 return hrrq;
1093}
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
1109 struct ipr_hostrcb *hostrcb)
1110{
1111 struct ipr_cmnd *ipr_cmd;
1112 struct ipr_ioarcb *ioarcb;
1113
1114 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
1115 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
1116 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
1117 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
1118
1119 ipr_cmd->u.hostrcb = hostrcb;
1120 ioarcb = &ipr_cmd->ioarcb;
1121
1122 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
1123 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
1124 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
1125 ioarcb->cmd_pkt.cdb[1] = type;
1126 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
1127 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
1128
1129 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
1130 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
1131
1132 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
1133 ipr_cmd->done = ipr_process_ccn;
1134 else
1135 ipr_cmd->done = ipr_process_error;
1136
1137 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
1138
1139 ipr_send_command(ipr_cmd);
1140 } else {
1141 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
1142 }
1143}
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1154{
1155 switch (proto) {
1156 case IPR_PROTO_SATA:
1157 case IPR_PROTO_SAS_STP:
1158 res->ata_class = ATA_DEV_ATA;
1159 break;
1160 case IPR_PROTO_SATA_ATAPI:
1161 case IPR_PROTO_SAS_STP_ATAPI:
1162 res->ata_class = ATA_DEV_ATAPI;
1163 break;
1164 default:
1165 res->ata_class = ATA_DEV_UNKNOWN;
1166 break;
1167 }
1168}
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178static void ipr_init_res_entry(struct ipr_resource_entry *res,
1179 struct ipr_config_table_entry_wrapper *cfgtew)
1180{
1181 int found = 0;
1182 unsigned int proto;
1183 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1184 struct ipr_resource_entry *gscsi_res = NULL;
1185
1186 res->needs_sync_complete = 0;
1187 res->in_erp = 0;
1188 res->add_to_ml = 0;
1189 res->del_from_ml = 0;
1190 res->resetting_device = 0;
1191 res->reset_occurred = 0;
1192 res->sdev = NULL;
1193 res->sata_port = NULL;
1194
1195 if (ioa_cfg->sis64) {
1196 proto = cfgtew->u.cfgte64->proto;
1197 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1198 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1199 res->qmodel = IPR_QUEUEING_MODEL64(res);
1200 res->type = cfgtew->u.cfgte64->res_type;
1201
1202 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1203 sizeof(res->res_path));
1204
1205 res->bus = 0;
1206 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1207 sizeof(res->dev_lun.scsi_lun));
1208 res->lun = scsilun_to_int(&res->dev_lun);
1209
1210 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1211 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1212 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1213 found = 1;
1214 res->target = gscsi_res->target;
1215 break;
1216 }
1217 }
1218 if (!found) {
1219 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1220 ioa_cfg->max_devs_supported);
1221 set_bit(res->target, ioa_cfg->target_ids);
1222 }
1223 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1224 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1225 res->target = 0;
1226 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1227 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1228 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1229 ioa_cfg->max_devs_supported);
1230 set_bit(res->target, ioa_cfg->array_ids);
1231 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1232 res->bus = IPR_VSET_VIRTUAL_BUS;
1233 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1234 ioa_cfg->max_devs_supported);
1235 set_bit(res->target, ioa_cfg->vset_ids);
1236 } else {
1237 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1238 ioa_cfg->max_devs_supported);
1239 set_bit(res->target, ioa_cfg->target_ids);
1240 }
1241 } else {
1242 proto = cfgtew->u.cfgte->proto;
1243 res->qmodel = IPR_QUEUEING_MODEL(res);
1244 res->flags = cfgtew->u.cfgte->flags;
1245 if (res->flags & IPR_IS_IOA_RESOURCE)
1246 res->type = IPR_RES_TYPE_IOAFP;
1247 else
1248 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1249
1250 res->bus = cfgtew->u.cfgte->res_addr.bus;
1251 res->target = cfgtew->u.cfgte->res_addr.target;
1252 res->lun = cfgtew->u.cfgte->res_addr.lun;
1253 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1254 }
1255
1256 ipr_update_ata_class(res, proto);
1257}
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267static int ipr_is_same_device(struct ipr_resource_entry *res,
1268 struct ipr_config_table_entry_wrapper *cfgtew)
1269{
1270 if (res->ioa_cfg->sis64) {
1271 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1272 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1273 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1274 sizeof(cfgtew->u.cfgte64->lun))) {
1275 return 1;
1276 }
1277 } else {
1278 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1279 res->target == cfgtew->u.cfgte->res_addr.target &&
1280 res->lun == cfgtew->u.cfgte->res_addr.lun)
1281 return 1;
1282 }
1283
1284 return 0;
1285}
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296static char *__ipr_format_res_path(u8 *res_path, char *buffer, int len)
1297{
1298 int i;
1299 char *p = buffer;
1300
1301 *p = '\0';
1302 p += scnprintf(p, buffer + len - p, "%02X", res_path[0]);
1303 for (i = 1; res_path[i] != 0xff && i < IPR_RES_PATH_BYTES; i++)
1304 p += scnprintf(p, buffer + len - p, "-%02X", res_path[i]);
1305
1306 return buffer;
1307}
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319static char *ipr_format_res_path(struct ipr_ioa_cfg *ioa_cfg,
1320 u8 *res_path, char *buffer, int len)
1321{
1322 char *p = buffer;
1323
1324 *p = '\0';
1325 p += scnprintf(p, buffer + len - p, "%d/", ioa_cfg->host->host_no);
1326 __ipr_format_res_path(res_path, p, len - (p - buffer));
1327 return buffer;
1328}
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338static void ipr_update_res_entry(struct ipr_resource_entry *res,
1339 struct ipr_config_table_entry_wrapper *cfgtew)
1340{
1341 char buffer[IPR_MAX_RES_PATH_LENGTH];
1342 unsigned int proto;
1343 int new_path = 0;
1344
1345 if (res->ioa_cfg->sis64) {
1346 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1347 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1348 res->type = cfgtew->u.cfgte64->res_type;
1349
1350 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1351 sizeof(struct ipr_std_inq_data));
1352
1353 res->qmodel = IPR_QUEUEING_MODEL64(res);
1354 proto = cfgtew->u.cfgte64->proto;
1355 res->res_handle = cfgtew->u.cfgte64->res_handle;
1356 res->dev_id = cfgtew->u.cfgte64->dev_id;
1357
1358 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1359 sizeof(res->dev_lun.scsi_lun));
1360
1361 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1362 sizeof(res->res_path))) {
1363 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1364 sizeof(res->res_path));
1365 new_path = 1;
1366 }
1367
1368 if (res->sdev && new_path)
1369 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1370 ipr_format_res_path(res->ioa_cfg,
1371 res->res_path, buffer, sizeof(buffer)));
1372 } else {
1373 res->flags = cfgtew->u.cfgte->flags;
1374 if (res->flags & IPR_IS_IOA_RESOURCE)
1375 res->type = IPR_RES_TYPE_IOAFP;
1376 else
1377 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1378
1379 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1380 sizeof(struct ipr_std_inq_data));
1381
1382 res->qmodel = IPR_QUEUEING_MODEL(res);
1383 proto = cfgtew->u.cfgte->proto;
1384 res->res_handle = cfgtew->u.cfgte->res_handle;
1385 }
1386
1387 ipr_update_ata_class(res, proto);
1388}
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398static void ipr_clear_res_target(struct ipr_resource_entry *res)
1399{
1400 struct ipr_resource_entry *gscsi_res = NULL;
1401 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1402
1403 if (!ioa_cfg->sis64)
1404 return;
1405
1406 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1407 clear_bit(res->target, ioa_cfg->array_ids);
1408 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1409 clear_bit(res->target, ioa_cfg->vset_ids);
1410 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1411 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1412 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1413 return;
1414 clear_bit(res->target, ioa_cfg->target_ids);
1415
1416 } else if (res->bus == 0)
1417 clear_bit(res->target, ioa_cfg->target_ids);
1418}
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1429 struct ipr_hostrcb *hostrcb)
1430{
1431 struct ipr_resource_entry *res = NULL;
1432 struct ipr_config_table_entry_wrapper cfgtew;
1433 __be32 cc_res_handle;
1434
1435 u32 is_ndn = 1;
1436
1437 if (ioa_cfg->sis64) {
1438 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1439 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1440 } else {
1441 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1442 cc_res_handle = cfgtew.u.cfgte->res_handle;
1443 }
1444
1445 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1446 if (res->res_handle == cc_res_handle) {
1447 is_ndn = 0;
1448 break;
1449 }
1450 }
1451
1452 if (is_ndn) {
1453 if (list_empty(&ioa_cfg->free_res_q)) {
1454 ipr_send_hcam(ioa_cfg,
1455 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1456 hostrcb);
1457 return;
1458 }
1459
1460 res = list_entry(ioa_cfg->free_res_q.next,
1461 struct ipr_resource_entry, queue);
1462
1463 list_del(&res->queue);
1464 ipr_init_res_entry(res, &cfgtew);
1465 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1466 }
1467
1468 ipr_update_res_entry(res, &cfgtew);
1469
1470 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1471 if (res->sdev) {
1472 res->del_from_ml = 1;
1473 res->res_handle = IPR_INVALID_RES_HANDLE;
1474 schedule_work(&ioa_cfg->work_q);
1475 } else {
1476 ipr_clear_res_target(res);
1477 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1478 }
1479 } else if (!res->sdev || res->del_from_ml) {
1480 res->add_to_ml = 1;
1481 schedule_work(&ioa_cfg->work_q);
1482 }
1483
1484 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1485}
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1498{
1499 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1500 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1501 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1502
1503 list_del_init(&hostrcb->queue);
1504 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
1505
1506 if (ioasc) {
1507 if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
1508 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST)
1509 dev_err(&ioa_cfg->pdev->dev,
1510 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1511
1512 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1513 } else {
1514 ipr_handle_config_change(ioa_cfg, hostrcb);
1515 }
1516}
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529static int strip_and_pad_whitespace(int i, char *buf)
1530{
1531 while (i && buf[i] == ' ')
1532 i--;
1533 buf[i+1] = ' ';
1534 buf[i+2] = '\0';
1535 return i + 2;
1536}
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1548 struct ipr_vpd *vpd)
1549{
1550 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1551 int i = 0;
1552
1553 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1554 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1555
1556 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1557 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1558
1559 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1560 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1561
1562 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1563}
1564
1565
1566
1567
1568
1569
1570
1571
1572static void ipr_log_vpd(struct ipr_vpd *vpd)
1573{
1574 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1575 + IPR_SERIAL_NUM_LEN];
1576
1577 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1578 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1579 IPR_PROD_ID_LEN);
1580 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1581 ipr_err("Vendor/Product ID: %s\n", buffer);
1582
1583 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1584 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1585 ipr_err(" Serial Number: %s\n", buffer);
1586}
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1598 struct ipr_ext_vpd *vpd)
1599{
1600 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1601 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1602 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1603}
1604
1605
1606
1607
1608
1609
1610
1611
1612static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1613{
1614 ipr_log_vpd(&vpd->vpd);
1615 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1616 be32_to_cpu(vpd->wwid[1]));
1617}
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1628 struct ipr_hostrcb *hostrcb)
1629{
1630 struct ipr_hostrcb_type_12_error *error;
1631
1632 if (ioa_cfg->sis64)
1633 error = &hostrcb->hcam.u.error64.u.type_12_error;
1634 else
1635 error = &hostrcb->hcam.u.error.u.type_12_error;
1636
1637 ipr_err("-----Current Configuration-----\n");
1638 ipr_err("Cache Directory Card Information:\n");
1639 ipr_log_ext_vpd(&error->ioa_vpd);
1640 ipr_err("Adapter Card Information:\n");
1641 ipr_log_ext_vpd(&error->cfc_vpd);
1642
1643 ipr_err("-----Expected Configuration-----\n");
1644 ipr_err("Cache Directory Card Information:\n");
1645 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1646 ipr_err("Adapter Card Information:\n");
1647 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1648
1649 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1650 be32_to_cpu(error->ioa_data[0]),
1651 be32_to_cpu(error->ioa_data[1]),
1652 be32_to_cpu(error->ioa_data[2]));
1653}
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1664 struct ipr_hostrcb *hostrcb)
1665{
1666 struct ipr_hostrcb_type_02_error *error =
1667 &hostrcb->hcam.u.error.u.type_02_error;
1668
1669 ipr_err("-----Current Configuration-----\n");
1670 ipr_err("Cache Directory Card Information:\n");
1671 ipr_log_vpd(&error->ioa_vpd);
1672 ipr_err("Adapter Card Information:\n");
1673 ipr_log_vpd(&error->cfc_vpd);
1674
1675 ipr_err("-----Expected Configuration-----\n");
1676 ipr_err("Cache Directory Card Information:\n");
1677 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1678 ipr_err("Adapter Card Information:\n");
1679 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1680
1681 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1682 be32_to_cpu(error->ioa_data[0]),
1683 be32_to_cpu(error->ioa_data[1]),
1684 be32_to_cpu(error->ioa_data[2]));
1685}
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1696 struct ipr_hostrcb *hostrcb)
1697{
1698 int errors_logged, i;
1699 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1700 struct ipr_hostrcb_type_13_error *error;
1701
1702 error = &hostrcb->hcam.u.error.u.type_13_error;
1703 errors_logged = be32_to_cpu(error->errors_logged);
1704
1705 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1706 be32_to_cpu(error->errors_detected), errors_logged);
1707
1708 dev_entry = error->dev;
1709
1710 for (i = 0; i < errors_logged; i++, dev_entry++) {
1711 ipr_err_separator;
1712
1713 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1714 ipr_log_ext_vpd(&dev_entry->vpd);
1715
1716 ipr_err("-----New Device Information-----\n");
1717 ipr_log_ext_vpd(&dev_entry->new_vpd);
1718
1719 ipr_err("Cache Directory Card Information:\n");
1720 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1721
1722 ipr_err("Adapter Card Information:\n");
1723 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1724 }
1725}
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1736 struct ipr_hostrcb *hostrcb)
1737{
1738 int errors_logged, i;
1739 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1740 struct ipr_hostrcb_type_23_error *error;
1741 char buffer[IPR_MAX_RES_PATH_LENGTH];
1742
1743 error = &hostrcb->hcam.u.error64.u.type_23_error;
1744 errors_logged = be32_to_cpu(error->errors_logged);
1745
1746 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1747 be32_to_cpu(error->errors_detected), errors_logged);
1748
1749 dev_entry = error->dev;
1750
1751 for (i = 0; i < errors_logged; i++, dev_entry++) {
1752 ipr_err_separator;
1753
1754 ipr_err("Device %d : %s", i + 1,
1755 __ipr_format_res_path(dev_entry->res_path,
1756 buffer, sizeof(buffer)));
1757 ipr_log_ext_vpd(&dev_entry->vpd);
1758
1759 ipr_err("-----New Device Information-----\n");
1760 ipr_log_ext_vpd(&dev_entry->new_vpd);
1761
1762 ipr_err("Cache Directory Card Information:\n");
1763 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1764
1765 ipr_err("Adapter Card Information:\n");
1766 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1767 }
1768}
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1779 struct ipr_hostrcb *hostrcb)
1780{
1781 int errors_logged, i;
1782 struct ipr_hostrcb_device_data_entry *dev_entry;
1783 struct ipr_hostrcb_type_03_error *error;
1784
1785 error = &hostrcb->hcam.u.error.u.type_03_error;
1786 errors_logged = be32_to_cpu(error->errors_logged);
1787
1788 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1789 be32_to_cpu(error->errors_detected), errors_logged);
1790
1791 dev_entry = error->dev;
1792
1793 for (i = 0; i < errors_logged; i++, dev_entry++) {
1794 ipr_err_separator;
1795
1796 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1797 ipr_log_vpd(&dev_entry->vpd);
1798
1799 ipr_err("-----New Device Information-----\n");
1800 ipr_log_vpd(&dev_entry->new_vpd);
1801
1802 ipr_err("Cache Directory Card Information:\n");
1803 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1804
1805 ipr_err("Adapter Card Information:\n");
1806 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1807
1808 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1809 be32_to_cpu(dev_entry->ioa_data[0]),
1810 be32_to_cpu(dev_entry->ioa_data[1]),
1811 be32_to_cpu(dev_entry->ioa_data[2]),
1812 be32_to_cpu(dev_entry->ioa_data[3]),
1813 be32_to_cpu(dev_entry->ioa_data[4]));
1814 }
1815}
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1826 struct ipr_hostrcb *hostrcb)
1827{
1828 int i, num_entries;
1829 struct ipr_hostrcb_type_14_error *error;
1830 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1831 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1832
1833 error = &hostrcb->hcam.u.error.u.type_14_error;
1834
1835 ipr_err_separator;
1836
1837 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1838 error->protection_level,
1839 ioa_cfg->host->host_no,
1840 error->last_func_vset_res_addr.bus,
1841 error->last_func_vset_res_addr.target,
1842 error->last_func_vset_res_addr.lun);
1843
1844 ipr_err_separator;
1845
1846 array_entry = error->array_member;
1847 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1848 ARRAY_SIZE(error->array_member));
1849
1850 for (i = 0; i < num_entries; i++, array_entry++) {
1851 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1852 continue;
1853
1854 if (be32_to_cpu(error->exposed_mode_adn) == i)
1855 ipr_err("Exposed Array Member %d:\n", i);
1856 else
1857 ipr_err("Array Member %d:\n", i);
1858
1859 ipr_log_ext_vpd(&array_entry->vpd);
1860 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1861 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1862 "Expected Location");
1863
1864 ipr_err_separator;
1865 }
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1877 struct ipr_hostrcb *hostrcb)
1878{
1879 int i;
1880 struct ipr_hostrcb_type_04_error *error;
1881 struct ipr_hostrcb_array_data_entry *array_entry;
1882 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1883
1884 error = &hostrcb->hcam.u.error.u.type_04_error;
1885
1886 ipr_err_separator;
1887
1888 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1889 error->protection_level,
1890 ioa_cfg->host->host_no,
1891 error->last_func_vset_res_addr.bus,
1892 error->last_func_vset_res_addr.target,
1893 error->last_func_vset_res_addr.lun);
1894
1895 ipr_err_separator;
1896
1897 array_entry = error->array_member;
1898
1899 for (i = 0; i < 18; i++) {
1900 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1901 continue;
1902
1903 if (be32_to_cpu(error->exposed_mode_adn) == i)
1904 ipr_err("Exposed Array Member %d:\n", i);
1905 else
1906 ipr_err("Array Member %d:\n", i);
1907
1908 ipr_log_vpd(&array_entry->vpd);
1909
1910 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1911 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1912 "Expected Location");
1913
1914 ipr_err_separator;
1915
1916 if (i == 9)
1917 array_entry = error->array_member2;
1918 else
1919 array_entry++;
1920 }
1921}
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, __be32 *data, int len)
1933{
1934 int i;
1935
1936 if (len == 0)
1937 return;
1938
1939 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1940 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1941
1942 for (i = 0; i < len / 4; i += 4) {
1943 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1944 be32_to_cpu(data[i]),
1945 be32_to_cpu(data[i+1]),
1946 be32_to_cpu(data[i+2]),
1947 be32_to_cpu(data[i+3]));
1948 }
1949}
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1960 struct ipr_hostrcb *hostrcb)
1961{
1962 struct ipr_hostrcb_type_17_error *error;
1963
1964 if (ioa_cfg->sis64)
1965 error = &hostrcb->hcam.u.error64.u.type_17_error;
1966 else
1967 error = &hostrcb->hcam.u.error.u.type_17_error;
1968
1969 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1970 strim(error->failure_reason);
1971
1972 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1973 be32_to_cpu(hostrcb->hcam.u.error.prc));
1974 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1975 ipr_log_hex_data(ioa_cfg, error->data,
1976 be32_to_cpu(hostrcb->hcam.length) -
1977 (offsetof(struct ipr_hostrcb_error, u) +
1978 offsetof(struct ipr_hostrcb_type_17_error, data)));
1979}
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1990 struct ipr_hostrcb *hostrcb)
1991{
1992 struct ipr_hostrcb_type_07_error *error;
1993
1994 error = &hostrcb->hcam.u.error.u.type_07_error;
1995 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1996 strim(error->failure_reason);
1997
1998 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1999 be32_to_cpu(hostrcb->hcam.u.error.prc));
2000 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
2001 ipr_log_hex_data(ioa_cfg, error->data,
2002 be32_to_cpu(hostrcb->hcam.length) -
2003 (offsetof(struct ipr_hostrcb_error, u) +
2004 offsetof(struct ipr_hostrcb_type_07_error, data)));
2005}
2006
2007static const struct {
2008 u8 active;
2009 char *desc;
2010} path_active_desc[] = {
2011 { IPR_PATH_NO_INFO, "Path" },
2012 { IPR_PATH_ACTIVE, "Active path" },
2013 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
2014};
2015
2016static const struct {
2017 u8 state;
2018 char *desc;
2019} path_state_desc[] = {
2020 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
2021 { IPR_PATH_HEALTHY, "is healthy" },
2022 { IPR_PATH_DEGRADED, "is degraded" },
2023 { IPR_PATH_FAILED, "is failed" }
2024};
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
2035 struct ipr_hostrcb_fabric_desc *fabric)
2036{
2037 int i, j;
2038 u8 path_state = fabric->path_state;
2039 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2040 u8 state = path_state & IPR_PATH_STATE_MASK;
2041
2042 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2043 if (path_active_desc[i].active != active)
2044 continue;
2045
2046 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2047 if (path_state_desc[j].state != state)
2048 continue;
2049
2050 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
2051 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
2052 path_active_desc[i].desc, path_state_desc[j].desc,
2053 fabric->ioa_port);
2054 } else if (fabric->cascaded_expander == 0xff) {
2055 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
2056 path_active_desc[i].desc, path_state_desc[j].desc,
2057 fabric->ioa_port, fabric->phy);
2058 } else if (fabric->phy == 0xff) {
2059 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
2060 path_active_desc[i].desc, path_state_desc[j].desc,
2061 fabric->ioa_port, fabric->cascaded_expander);
2062 } else {
2063 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
2064 path_active_desc[i].desc, path_state_desc[j].desc,
2065 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2066 }
2067 return;
2068 }
2069 }
2070
2071 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
2072 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2073}
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
2084 struct ipr_hostrcb64_fabric_desc *fabric)
2085{
2086 int i, j;
2087 u8 path_state = fabric->path_state;
2088 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2089 u8 state = path_state & IPR_PATH_STATE_MASK;
2090 char buffer[IPR_MAX_RES_PATH_LENGTH];
2091
2092 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2093 if (path_active_desc[i].active != active)
2094 continue;
2095
2096 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2097 if (path_state_desc[j].state != state)
2098 continue;
2099
2100 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
2101 path_active_desc[i].desc, path_state_desc[j].desc,
2102 ipr_format_res_path(hostrcb->ioa_cfg,
2103 fabric->res_path,
2104 buffer, sizeof(buffer)));
2105 return;
2106 }
2107 }
2108
2109 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
2110 ipr_format_res_path(hostrcb->ioa_cfg, fabric->res_path,
2111 buffer, sizeof(buffer)));
2112}
2113
2114static const struct {
2115 u8 type;
2116 char *desc;
2117} path_type_desc[] = {
2118 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
2119 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
2120 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
2121 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
2122};
2123
2124static const struct {
2125 u8 status;
2126 char *desc;
2127} path_status_desc[] = {
2128 { IPR_PATH_CFG_NO_PROB, "Functional" },
2129 { IPR_PATH_CFG_DEGRADED, "Degraded" },
2130 { IPR_PATH_CFG_FAILED, "Failed" },
2131 { IPR_PATH_CFG_SUSPECT, "Suspect" },
2132 { IPR_PATH_NOT_DETECTED, "Missing" },
2133 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
2134};
2135
2136static const char *link_rate[] = {
2137 "unknown",
2138 "disabled",
2139 "phy reset problem",
2140 "spinup hold",
2141 "port selector",
2142 "unknown",
2143 "unknown",
2144 "unknown",
2145 "1.5Gbps",
2146 "3.0Gbps",
2147 "unknown",
2148 "unknown",
2149 "unknown",
2150 "unknown",
2151 "unknown",
2152 "unknown"
2153};
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
2164 struct ipr_hostrcb_config_element *cfg)
2165{
2166 int i, j;
2167 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2168 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2169
2170 if (type == IPR_PATH_CFG_NOT_EXIST)
2171 return;
2172
2173 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2174 if (path_type_desc[i].type != type)
2175 continue;
2176
2177 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2178 if (path_status_desc[j].status != status)
2179 continue;
2180
2181 if (type == IPR_PATH_CFG_IOA_PORT) {
2182 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2183 path_status_desc[j].desc, path_type_desc[i].desc,
2184 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2185 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2186 } else {
2187 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2188 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2189 path_status_desc[j].desc, path_type_desc[i].desc,
2190 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2191 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2192 } else if (cfg->cascaded_expander == 0xff) {
2193 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2194 "WWN=%08X%08X\n", path_status_desc[j].desc,
2195 path_type_desc[i].desc, cfg->phy,
2196 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2197 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2198 } else if (cfg->phy == 0xff) {
2199 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2200 "WWN=%08X%08X\n", path_status_desc[j].desc,
2201 path_type_desc[i].desc, cfg->cascaded_expander,
2202 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2203 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2204 } else {
2205 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2206 "WWN=%08X%08X\n", path_status_desc[j].desc,
2207 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2208 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2209 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2210 }
2211 }
2212 return;
2213 }
2214 }
2215
2216 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2217 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2218 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2219 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2220}
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2231 struct ipr_hostrcb64_config_element *cfg)
2232{
2233 int i, j;
2234 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2235 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2236 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2237 char buffer[IPR_MAX_RES_PATH_LENGTH];
2238
2239 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2240 return;
2241
2242 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2243 if (path_type_desc[i].type != type)
2244 continue;
2245
2246 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2247 if (path_status_desc[j].status != status)
2248 continue;
2249
2250 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2251 path_status_desc[j].desc, path_type_desc[i].desc,
2252 ipr_format_res_path(hostrcb->ioa_cfg,
2253 cfg->res_path, buffer, sizeof(buffer)),
2254 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2255 be32_to_cpu(cfg->wwid[0]),
2256 be32_to_cpu(cfg->wwid[1]));
2257 return;
2258 }
2259 }
2260 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2261 "WWN=%08X%08X\n", cfg->type_status,
2262 ipr_format_res_path(hostrcb->ioa_cfg,
2263 cfg->res_path, buffer, sizeof(buffer)),
2264 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2265 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2266}
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2277 struct ipr_hostrcb *hostrcb)
2278{
2279 struct ipr_hostrcb_type_20_error *error;
2280 struct ipr_hostrcb_fabric_desc *fabric;
2281 struct ipr_hostrcb_config_element *cfg;
2282 int i, add_len;
2283
2284 error = &hostrcb->hcam.u.error.u.type_20_error;
2285 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2286 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2287
2288 add_len = be32_to_cpu(hostrcb->hcam.length) -
2289 (offsetof(struct ipr_hostrcb_error, u) +
2290 offsetof(struct ipr_hostrcb_type_20_error, desc));
2291
2292 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2293 ipr_log_fabric_path(hostrcb, fabric);
2294 for_each_fabric_cfg(fabric, cfg)
2295 ipr_log_path_elem(hostrcb, cfg);
2296
2297 add_len -= be16_to_cpu(fabric->length);
2298 fabric = (struct ipr_hostrcb_fabric_desc *)
2299 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2300 }
2301
2302 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2303}
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2314 struct ipr_hostrcb *hostrcb)
2315{
2316 int i, num_entries;
2317 struct ipr_hostrcb_type_24_error *error;
2318 struct ipr_hostrcb64_array_data_entry *array_entry;
2319 char buffer[IPR_MAX_RES_PATH_LENGTH];
2320 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2321
2322 error = &hostrcb->hcam.u.error64.u.type_24_error;
2323
2324 ipr_err_separator;
2325
2326 ipr_err("RAID %s Array Configuration: %s\n",
2327 error->protection_level,
2328 ipr_format_res_path(ioa_cfg, error->last_res_path,
2329 buffer, sizeof(buffer)));
2330
2331 ipr_err_separator;
2332
2333 array_entry = error->array_member;
2334 num_entries = min_t(u32, error->num_entries,
2335 ARRAY_SIZE(error->array_member));
2336
2337 for (i = 0; i < num_entries; i++, array_entry++) {
2338
2339 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2340 continue;
2341
2342 if (error->exposed_mode_adn == i)
2343 ipr_err("Exposed Array Member %d:\n", i);
2344 else
2345 ipr_err("Array Member %d:\n", i);
2346
2347 ipr_err("Array Member %d:\n", i);
2348 ipr_log_ext_vpd(&array_entry->vpd);
2349 ipr_err("Current Location: %s\n",
2350 ipr_format_res_path(ioa_cfg, array_entry->res_path,
2351 buffer, sizeof(buffer)));
2352 ipr_err("Expected Location: %s\n",
2353 ipr_format_res_path(ioa_cfg,
2354 array_entry->expected_res_path,
2355 buffer, sizeof(buffer)));
2356
2357 ipr_err_separator;
2358 }
2359}
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2370 struct ipr_hostrcb *hostrcb)
2371{
2372 struct ipr_hostrcb_type_30_error *error;
2373 struct ipr_hostrcb64_fabric_desc *fabric;
2374 struct ipr_hostrcb64_config_element *cfg;
2375 int i, add_len;
2376
2377 error = &hostrcb->hcam.u.error64.u.type_30_error;
2378
2379 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2380 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2381
2382 add_len = be32_to_cpu(hostrcb->hcam.length) -
2383 (offsetof(struct ipr_hostrcb64_error, u) +
2384 offsetof(struct ipr_hostrcb_type_30_error, desc));
2385
2386 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2387 ipr_log64_fabric_path(hostrcb, fabric);
2388 for_each_fabric_cfg(fabric, cfg)
2389 ipr_log64_path_elem(hostrcb, cfg);
2390
2391 add_len -= be16_to_cpu(fabric->length);
2392 fabric = (struct ipr_hostrcb64_fabric_desc *)
2393 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2394 }
2395
2396 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2397}
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407static void ipr_log_sis64_service_required_error(struct ipr_ioa_cfg *ioa_cfg,
2408 struct ipr_hostrcb *hostrcb)
2409{
2410 struct ipr_hostrcb_type_41_error *error;
2411
2412 error = &hostrcb->hcam.u.error64.u.type_41_error;
2413
2414 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2415 ipr_err("Primary Failure Reason: %s\n", error->failure_reason);
2416 ipr_log_hex_data(ioa_cfg, error->data,
2417 be32_to_cpu(hostrcb->hcam.length) -
2418 (offsetof(struct ipr_hostrcb_error, u) +
2419 offsetof(struct ipr_hostrcb_type_41_error, data)));
2420}
2421
2422
2423
2424
2425
2426
2427
2428
2429static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2430 struct ipr_hostrcb *hostrcb)
2431{
2432 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2433 be32_to_cpu(hostrcb->hcam.length));
2434}
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444static void ipr_log_sis64_device_error(struct ipr_ioa_cfg *ioa_cfg,
2445 struct ipr_hostrcb *hostrcb)
2446{
2447 struct ipr_hostrcb_type_21_error *error;
2448 char buffer[IPR_MAX_RES_PATH_LENGTH];
2449
2450 error = &hostrcb->hcam.u.error64.u.type_21_error;
2451
2452 ipr_err("-----Failing Device Information-----\n");
2453 ipr_err("World Wide Unique ID: %08X%08X%08X%08X\n",
2454 be32_to_cpu(error->wwn[0]), be32_to_cpu(error->wwn[1]),
2455 be32_to_cpu(error->wwn[2]), be32_to_cpu(error->wwn[3]));
2456 ipr_err("Device Resource Path: %s\n",
2457 __ipr_format_res_path(error->res_path,
2458 buffer, sizeof(buffer)));
2459 error->primary_problem_desc[sizeof(error->primary_problem_desc) - 1] = '\0';
2460 error->second_problem_desc[sizeof(error->second_problem_desc) - 1] = '\0';
2461 ipr_err("Primary Problem Description: %s\n", error->primary_problem_desc);
2462 ipr_err("Secondary Problem Description: %s\n", error->second_problem_desc);
2463 ipr_err("SCSI Sense Data:\n");
2464 ipr_log_hex_data(ioa_cfg, error->sense_data, sizeof(error->sense_data));
2465 ipr_err("SCSI Command Descriptor Block: \n");
2466 ipr_log_hex_data(ioa_cfg, error->cdb, sizeof(error->cdb));
2467
2468 ipr_err("Additional IOA Data:\n");
2469 ipr_log_hex_data(ioa_cfg, error->ioa_data, be32_to_cpu(error->length_of_error));
2470}
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483static u32 ipr_get_error(u32 ioasc)
2484{
2485 int i;
2486
2487 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2488 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2489 return i;
2490
2491 return 0;
2492}
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2505 struct ipr_hostrcb *hostrcb)
2506{
2507 u32 ioasc;
2508 int error_index;
2509 struct ipr_hostrcb_type_21_error *error;
2510
2511 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2512 return;
2513
2514 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2515 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2516
2517 if (ioa_cfg->sis64)
2518 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2519 else
2520 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2521
2522 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2523 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2524
2525 scsi_report_bus_reset(ioa_cfg->host,
2526 hostrcb->hcam.u.error.fd_res_addr.bus);
2527 }
2528
2529 error_index = ipr_get_error(ioasc);
2530
2531 if (!ipr_error_table[error_index].log_hcam)
2532 return;
2533
2534 if (ioasc == IPR_IOASC_HW_CMD_FAILED &&
2535 hostrcb->hcam.overlay_id == IPR_HOST_RCB_OVERLAY_ID_21) {
2536 error = &hostrcb->hcam.u.error64.u.type_21_error;
2537
2538 if (((be32_to_cpu(error->sense_data[0]) & 0x0000ff00) >> 8) == ILLEGAL_REQUEST &&
2539 ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
2540 return;
2541 }
2542
2543 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2544
2545
2546 ioa_cfg->errors_logged++;
2547
2548 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2549 return;
2550 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2551 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2552
2553 switch (hostrcb->hcam.overlay_id) {
2554 case IPR_HOST_RCB_OVERLAY_ID_2:
2555 ipr_log_cache_error(ioa_cfg, hostrcb);
2556 break;
2557 case IPR_HOST_RCB_OVERLAY_ID_3:
2558 ipr_log_config_error(ioa_cfg, hostrcb);
2559 break;
2560 case IPR_HOST_RCB_OVERLAY_ID_4:
2561 case IPR_HOST_RCB_OVERLAY_ID_6:
2562 ipr_log_array_error(ioa_cfg, hostrcb);
2563 break;
2564 case IPR_HOST_RCB_OVERLAY_ID_7:
2565 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2566 break;
2567 case IPR_HOST_RCB_OVERLAY_ID_12:
2568 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2569 break;
2570 case IPR_HOST_RCB_OVERLAY_ID_13:
2571 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2572 break;
2573 case IPR_HOST_RCB_OVERLAY_ID_14:
2574 case IPR_HOST_RCB_OVERLAY_ID_16:
2575 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2576 break;
2577 case IPR_HOST_RCB_OVERLAY_ID_17:
2578 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2579 break;
2580 case IPR_HOST_RCB_OVERLAY_ID_20:
2581 ipr_log_fabric_error(ioa_cfg, hostrcb);
2582 break;
2583 case IPR_HOST_RCB_OVERLAY_ID_21:
2584 ipr_log_sis64_device_error(ioa_cfg, hostrcb);
2585 break;
2586 case IPR_HOST_RCB_OVERLAY_ID_23:
2587 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2588 break;
2589 case IPR_HOST_RCB_OVERLAY_ID_24:
2590 case IPR_HOST_RCB_OVERLAY_ID_26:
2591 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2592 break;
2593 case IPR_HOST_RCB_OVERLAY_ID_30:
2594 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2595 break;
2596 case IPR_HOST_RCB_OVERLAY_ID_41:
2597 ipr_log_sis64_service_required_error(ioa_cfg, hostrcb);
2598 break;
2599 case IPR_HOST_RCB_OVERLAY_ID_1:
2600 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2601 default:
2602 ipr_log_generic_error(ioa_cfg, hostrcb);
2603 break;
2604 }
2605}
2606
2607static struct ipr_hostrcb *ipr_get_free_hostrcb(struct ipr_ioa_cfg *ioa)
2608{
2609 struct ipr_hostrcb *hostrcb;
2610
2611 hostrcb = list_first_entry_or_null(&ioa->hostrcb_free_q,
2612 struct ipr_hostrcb, queue);
2613
2614 if (unlikely(!hostrcb)) {
2615 dev_info(&ioa->pdev->dev, "Reclaiming async error buffers.");
2616 hostrcb = list_first_entry_or_null(&ioa->hostrcb_report_q,
2617 struct ipr_hostrcb, queue);
2618 }
2619
2620 list_del_init(&hostrcb->queue);
2621 return hostrcb;
2622}
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2636{
2637 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2638 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2639 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2640 u32 fd_ioasc;
2641
2642 if (ioa_cfg->sis64)
2643 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2644 else
2645 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2646
2647 list_del_init(&hostrcb->queue);
2648 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
2649
2650 if (!ioasc) {
2651 ipr_handle_log_data(ioa_cfg, hostrcb);
2652 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2653 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2654 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
2655 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST) {
2656 dev_err(&ioa_cfg->pdev->dev,
2657 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2658 }
2659
2660 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_report_q);
2661 schedule_work(&ioa_cfg->work_q);
2662 hostrcb = ipr_get_free_hostrcb(ioa_cfg);
2663
2664 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2665}
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677static void ipr_timeout(struct timer_list *t)
2678{
2679 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
2680 unsigned long lock_flags = 0;
2681 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2682
2683 ENTER;
2684 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2685
2686 ioa_cfg->errors_logged++;
2687 dev_err(&ioa_cfg->pdev->dev,
2688 "Adapter being reset due to command timeout.\n");
2689
2690 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2691 ioa_cfg->sdt_state = GET_DUMP;
2692
2693 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2694 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2695
2696 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2697 LEAVE;
2698}
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710static void ipr_oper_timeout(struct timer_list *t)
2711{
2712 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
2713 unsigned long lock_flags = 0;
2714 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2715
2716 ENTER;
2717 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2718
2719 ioa_cfg->errors_logged++;
2720 dev_err(&ioa_cfg->pdev->dev,
2721 "Adapter timed out transitioning to operational.\n");
2722
2723 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2724 ioa_cfg->sdt_state = GET_DUMP;
2725
2726 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2727 if (ipr_fastfail)
2728 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2729 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2730 }
2731
2732 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2733 LEAVE;
2734}
2735
2736
2737
2738
2739
2740
2741
2742
2743static const struct ipr_ses_table_entry *
2744ipr_find_ses_entry(struct ipr_resource_entry *res)
2745{
2746 int i, j, matches;
2747 struct ipr_std_inq_vpids *vpids;
2748 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2749
2750 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2751 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2752 if (ste->compare_product_id_byte[j] == 'X') {
2753 vpids = &res->std_inq_data.vpids;
2754 if (vpids->product_id[j] == ste->product_id[j])
2755 matches++;
2756 else
2757 break;
2758 } else
2759 matches++;
2760 }
2761
2762 if (matches == IPR_PROD_ID_LEN)
2763 return ste;
2764 }
2765
2766 return NULL;
2767}
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2782{
2783 struct ipr_resource_entry *res;
2784 const struct ipr_ses_table_entry *ste;
2785 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2786
2787
2788 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2789 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2790 continue;
2791
2792 if (bus != res->bus)
2793 continue;
2794
2795 if (!(ste = ipr_find_ses_entry(res)))
2796 continue;
2797
2798 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2799 }
2800
2801 return max_xfer_rate;
2802}
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2815{
2816 volatile u32 pcii_reg;
2817 int delay = 1;
2818
2819
2820 while (delay < max_delay) {
2821 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2822
2823 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2824 return 0;
2825
2826
2827 if ((delay / 1000) > MAX_UDELAY_MS)
2828 mdelay(delay / 1000);
2829 else
2830 udelay(delay);
2831
2832 delay += delay;
2833 }
2834 return -EIO;
2835}
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2848 u32 start_addr,
2849 __be32 *dest, u32 length_in_words)
2850{
2851 int i;
2852
2853 for (i = 0; i < length_in_words; i++) {
2854 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2855 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2856 dest++;
2857 }
2858
2859 return 0;
2860}
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2873 u32 start_addr,
2874 __be32 *dest, u32 length_in_words)
2875{
2876 volatile u32 temp_pcii_reg;
2877 int i, delay = 0;
2878
2879 if (ioa_cfg->sis64)
2880 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2881 dest, length_in_words);
2882
2883
2884 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2885 ioa_cfg->regs.set_uproc_interrupt_reg32);
2886
2887
2888 if (ipr_wait_iodbg_ack(ioa_cfg,
2889 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2890 dev_err(&ioa_cfg->pdev->dev,
2891 "IOA dump long data transfer timeout\n");
2892 return -EIO;
2893 }
2894
2895
2896 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2897 ioa_cfg->regs.clr_interrupt_reg);
2898
2899
2900 writel(start_addr, ioa_cfg->ioa_mailbox);
2901
2902
2903 writel(IPR_UPROCI_RESET_ALERT,
2904 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2905
2906 for (i = 0; i < length_in_words; i++) {
2907
2908 if (ipr_wait_iodbg_ack(ioa_cfg,
2909 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2910 dev_err(&ioa_cfg->pdev->dev,
2911 "IOA dump short data transfer timeout\n");
2912 return -EIO;
2913 }
2914
2915
2916 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2917 dest++;
2918
2919
2920 if (i < (length_in_words - 1)) {
2921
2922 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2923 ioa_cfg->regs.clr_interrupt_reg);
2924 }
2925 }
2926
2927
2928 writel(IPR_UPROCI_RESET_ALERT,
2929 ioa_cfg->regs.set_uproc_interrupt_reg32);
2930
2931 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2932 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2933
2934
2935 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2936 ioa_cfg->regs.clr_interrupt_reg);
2937
2938
2939 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2940 temp_pcii_reg =
2941 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2942
2943 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2944 return 0;
2945
2946 udelay(10);
2947 delay += 10;
2948 }
2949
2950 return 0;
2951}
2952
2953#ifdef CONFIG_SCSI_IPR_DUMP
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2966 unsigned long pci_address, u32 length)
2967{
2968 int bytes_copied = 0;
2969 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2970 __be32 *page;
2971 unsigned long lock_flags = 0;
2972 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2973
2974 if (ioa_cfg->sis64)
2975 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2976 else
2977 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2978
2979 while (bytes_copied < length &&
2980 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2981 if (ioa_dump->page_offset >= PAGE_SIZE ||
2982 ioa_dump->page_offset == 0) {
2983 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2984
2985 if (!page) {
2986 ipr_trace;
2987 return bytes_copied;
2988 }
2989
2990 ioa_dump->page_offset = 0;
2991 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2992 ioa_dump->next_page_index++;
2993 } else
2994 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2995
2996 rem_len = length - bytes_copied;
2997 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2998 cur_len = min(rem_len, rem_page_len);
2999
3000 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3001 if (ioa_cfg->sdt_state == ABORT_DUMP) {
3002 rc = -EIO;
3003 } else {
3004 rc = ipr_get_ldump_data_section(ioa_cfg,
3005 pci_address + bytes_copied,
3006 &page[ioa_dump->page_offset / 4],
3007 (cur_len / sizeof(u32)));
3008 }
3009 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3010
3011 if (!rc) {
3012 ioa_dump->page_offset += cur_len;
3013 bytes_copied += cur_len;
3014 } else {
3015 ipr_trace;
3016 break;
3017 }
3018 schedule();
3019 }
3020
3021 return bytes_copied;
3022}
3023
3024
3025
3026
3027
3028
3029
3030
3031static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
3032{
3033 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
3034 hdr->num_elems = 1;
3035 hdr->offset = sizeof(*hdr);
3036 hdr->status = IPR_DUMP_STATUS_SUCCESS;
3037}
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
3048 struct ipr_driver_dump *driver_dump)
3049{
3050 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3051
3052 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
3053 driver_dump->ioa_type_entry.hdr.len =
3054 sizeof(struct ipr_dump_ioa_type_entry) -
3055 sizeof(struct ipr_dump_entry_header);
3056 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3057 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
3058 driver_dump->ioa_type_entry.type = ioa_cfg->type;
3059 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
3060 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
3061 ucode_vpd->minor_release[1];
3062 driver_dump->hdr.num_entries++;
3063}
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
3074 struct ipr_driver_dump *driver_dump)
3075{
3076 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
3077 driver_dump->version_entry.hdr.len =
3078 sizeof(struct ipr_dump_version_entry) -
3079 sizeof(struct ipr_dump_entry_header);
3080 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3081 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
3082 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
3083 driver_dump->hdr.num_entries++;
3084}
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
3095 struct ipr_driver_dump *driver_dump)
3096{
3097 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
3098 driver_dump->trace_entry.hdr.len =
3099 sizeof(struct ipr_dump_trace_entry) -
3100 sizeof(struct ipr_dump_entry_header);
3101 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3102 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
3103 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
3104 driver_dump->hdr.num_entries++;
3105}
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
3116 struct ipr_driver_dump *driver_dump)
3117{
3118 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
3119 driver_dump->location_entry.hdr.len =
3120 sizeof(struct ipr_dump_location_entry) -
3121 sizeof(struct ipr_dump_entry_header);
3122 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3123 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
3124 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
3125 driver_dump->hdr.num_entries++;
3126}
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
3137{
3138 unsigned long start_addr, sdt_word;
3139 unsigned long lock_flags = 0;
3140 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
3141 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
3142 u32 num_entries, max_num_entries, start_off, end_off;
3143 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
3144 struct ipr_sdt *sdt;
3145 int valid = 1;
3146 int i;
3147
3148 ENTER;
3149
3150 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3151
3152 if (ioa_cfg->sdt_state != READ_DUMP) {
3153 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3154 return;
3155 }
3156
3157 if (ioa_cfg->sis64) {
3158 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3159 ssleep(IPR_DUMP_DELAY_SECONDS);
3160 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3161 }
3162
3163 start_addr = readl(ioa_cfg->ioa_mailbox);
3164
3165 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
3166 dev_err(&ioa_cfg->pdev->dev,
3167 "Invalid dump table format: %lx\n", start_addr);
3168 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3169 return;
3170 }
3171
3172 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
3173
3174 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
3175
3176
3177 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
3178 driver_dump->hdr.num_entries = 1;
3179 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
3180 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
3181 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
3182 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
3183
3184 ipr_dump_version_data(ioa_cfg, driver_dump);
3185 ipr_dump_location_data(ioa_cfg, driver_dump);
3186 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
3187 ipr_dump_trace_data(ioa_cfg, driver_dump);
3188
3189
3190 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
3191
3192
3193 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
3194 ioa_dump->hdr.len = 0;
3195 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3196 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
3197
3198
3199
3200
3201
3202 sdt = &ioa_dump->sdt;
3203
3204 if (ioa_cfg->sis64) {
3205 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
3206 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
3207 } else {
3208 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
3209 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
3210 }
3211
3212 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
3213 (max_num_entries * sizeof(struct ipr_sdt_entry));
3214 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
3215 bytes_to_copy / sizeof(__be32));
3216
3217
3218 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
3219 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
3220 dev_err(&ioa_cfg->pdev->dev,
3221 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
3222 rc, be32_to_cpu(sdt->hdr.state));
3223 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
3224 ioa_cfg->sdt_state = DUMP_OBTAINED;
3225 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3226 return;
3227 }
3228
3229 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
3230
3231 if (num_entries > max_num_entries)
3232 num_entries = max_num_entries;
3233
3234
3235 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
3236 if (ioa_cfg->sis64)
3237 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
3238 else
3239 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
3240
3241 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3242
3243 for (i = 0; i < num_entries; i++) {
3244 if (ioa_dump->hdr.len > max_dump_size) {
3245 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3246 break;
3247 }
3248
3249 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3250 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3251 if (ioa_cfg->sis64)
3252 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3253 else {
3254 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3255 end_off = be32_to_cpu(sdt->entry[i].end_token);
3256
3257 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3258 bytes_to_copy = end_off - start_off;
3259 else
3260 valid = 0;
3261 }
3262 if (valid) {
3263 if (bytes_to_copy > max_dump_size) {
3264 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3265 continue;
3266 }
3267
3268
3269 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3270 bytes_to_copy);
3271
3272 ioa_dump->hdr.len += bytes_copied;
3273
3274 if (bytes_copied != bytes_to_copy) {
3275 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3276 break;
3277 }
3278 }
3279 }
3280 }
3281
3282 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3283
3284
3285 driver_dump->hdr.len += ioa_dump->hdr.len;
3286 wmb();
3287 ioa_cfg->sdt_state = DUMP_OBTAINED;
3288 LEAVE;
3289}
3290
3291#else
3292#define ipr_get_ioa_dump(ioa_cfg, dump) do { } while (0)
3293#endif
3294
3295
3296
3297
3298
3299
3300
3301
3302static void ipr_release_dump(struct kref *kref)
3303{
3304 struct ipr_dump *dump = container_of(kref, struct ipr_dump, kref);
3305 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3306 unsigned long lock_flags = 0;
3307 int i;
3308
3309 ENTER;
3310 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3311 ioa_cfg->dump = NULL;
3312 ioa_cfg->sdt_state = INACTIVE;
3313 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3314
3315 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3316 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3317
3318 vfree(dump->ioa_dump.ioa_data);
3319 kfree(dump);
3320 LEAVE;
3321}
3322
3323static void ipr_add_remove_thread(struct work_struct *work)
3324{
3325 unsigned long lock_flags;
3326 struct ipr_resource_entry *res;
3327 struct scsi_device *sdev;
3328 struct ipr_ioa_cfg *ioa_cfg =
3329 container_of(work, struct ipr_ioa_cfg, scsi_add_work_q);
3330 u8 bus, target, lun;
3331 int did_work;
3332
3333 ENTER;
3334 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3335
3336restart:
3337 do {
3338 did_work = 0;
3339 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
3340 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3341 return;
3342 }
3343
3344 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3345 if (res->del_from_ml && res->sdev) {
3346 did_work = 1;
3347 sdev = res->sdev;
3348 if (!scsi_device_get(sdev)) {
3349 if (!res->add_to_ml)
3350 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3351 else
3352 res->del_from_ml = 0;
3353 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3354 scsi_remove_device(sdev);
3355 scsi_device_put(sdev);
3356 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3357 }
3358 break;
3359 }
3360 }
3361 } while (did_work);
3362
3363 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3364 if (res->add_to_ml) {
3365 bus = res->bus;
3366 target = res->target;
3367 lun = res->lun;
3368 res->add_to_ml = 0;
3369 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3370 scsi_add_device(ioa_cfg->host, bus, target, lun);
3371 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3372 goto restart;
3373 }
3374 }
3375
3376 ioa_cfg->scan_done = 1;
3377 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3378 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3379 LEAVE;
3380}
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393static void ipr_worker_thread(struct work_struct *work)
3394{
3395 unsigned long lock_flags;
3396 struct ipr_dump *dump;
3397 struct ipr_ioa_cfg *ioa_cfg =
3398 container_of(work, struct ipr_ioa_cfg, work_q);
3399
3400 ENTER;
3401 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3402
3403 if (ioa_cfg->sdt_state == READ_DUMP) {
3404 dump = ioa_cfg->dump;
3405 if (!dump) {
3406 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3407 return;
3408 }
3409 kref_get(&dump->kref);
3410 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3411 ipr_get_ioa_dump(ioa_cfg, dump);
3412 kref_put(&dump->kref, ipr_release_dump);
3413
3414 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3415 if (ioa_cfg->sdt_state == DUMP_OBTAINED && !ioa_cfg->dump_timeout)
3416 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3417 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3418 return;
3419 }
3420
3421 if (ioa_cfg->scsi_unblock) {
3422 ioa_cfg->scsi_unblock = 0;
3423 ioa_cfg->scsi_blocked = 0;
3424 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3425 scsi_unblock_requests(ioa_cfg->host);
3426 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3427 if (ioa_cfg->scsi_blocked)
3428 scsi_block_requests(ioa_cfg->host);
3429 }
3430
3431 if (!ioa_cfg->scan_enabled) {
3432 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3433 return;
3434 }
3435
3436 schedule_work(&ioa_cfg->scsi_add_work_q);
3437
3438 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3439 LEAVE;
3440}
3441
3442#ifdef CONFIG_SCSI_IPR_TRACE
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3456 struct bin_attribute *bin_attr,
3457 char *buf, loff_t off, size_t count)
3458{
3459 struct device *dev = container_of(kobj, struct device, kobj);
3460 struct Scsi_Host *shost = class_to_shost(dev);
3461 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3462 unsigned long lock_flags = 0;
3463 ssize_t ret;
3464
3465 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3466 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3467 IPR_TRACE_SIZE);
3468 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3469
3470 return ret;
3471}
3472
3473static struct bin_attribute ipr_trace_attr = {
3474 .attr = {
3475 .name = "trace",
3476 .mode = S_IRUGO,
3477 },
3478 .size = 0,
3479 .read = ipr_read_trace,
3480};
3481#endif
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492static ssize_t ipr_show_fw_version(struct device *dev,
3493 struct device_attribute *attr, char *buf)
3494{
3495 struct Scsi_Host *shost = class_to_shost(dev);
3496 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3497 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3498 unsigned long lock_flags = 0;
3499 int len;
3500
3501 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3502 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3503 ucode_vpd->major_release, ucode_vpd->card_type,
3504 ucode_vpd->minor_release[0],
3505 ucode_vpd->minor_release[1]);
3506 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3507 return len;
3508}
3509
3510static struct device_attribute ipr_fw_version_attr = {
3511 .attr = {
3512 .name = "fw_version",
3513 .mode = S_IRUGO,
3514 },
3515 .show = ipr_show_fw_version,
3516};
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527static ssize_t ipr_show_log_level(struct device *dev,
3528 struct device_attribute *attr, char *buf)
3529{
3530 struct Scsi_Host *shost = class_to_shost(dev);
3531 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3532 unsigned long lock_flags = 0;
3533 int len;
3534
3535 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3536 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3537 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3538 return len;
3539}
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551static ssize_t ipr_store_log_level(struct device *dev,
3552 struct device_attribute *attr,
3553 const char *buf, size_t count)
3554{
3555 struct Scsi_Host *shost = class_to_shost(dev);
3556 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3557 unsigned long lock_flags = 0;
3558
3559 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3560 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3561 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3562 return strlen(buf);
3563}
3564
3565static struct device_attribute ipr_log_level_attr = {
3566 .attr = {
3567 .name = "log_level",
3568 .mode = S_IRUGO | S_IWUSR,
3569 },
3570 .show = ipr_show_log_level,
3571 .store = ipr_store_log_level
3572};
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587static ssize_t ipr_store_diagnostics(struct device *dev,
3588 struct device_attribute *attr,
3589 const char *buf, size_t count)
3590{
3591 struct Scsi_Host *shost = class_to_shost(dev);
3592 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3593 unsigned long lock_flags = 0;
3594 int rc = count;
3595
3596 if (!capable(CAP_SYS_ADMIN))
3597 return -EACCES;
3598
3599 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3600 while (ioa_cfg->in_reset_reload) {
3601 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3602 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3603 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3604 }
3605
3606 ioa_cfg->errors_logged = 0;
3607 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3608
3609 if (ioa_cfg->in_reset_reload) {
3610 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3611 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3612
3613
3614 msleep(1000);
3615 } else {
3616 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3617 return -EIO;
3618 }
3619
3620 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3621 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3622 rc = -EIO;
3623 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3624
3625 return rc;
3626}
3627
3628static struct device_attribute ipr_diagnostics_attr = {
3629 .attr = {
3630 .name = "run_diagnostics",
3631 .mode = S_IWUSR,
3632 },
3633 .store = ipr_store_diagnostics
3634};
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645static ssize_t ipr_show_adapter_state(struct device *dev,
3646 struct device_attribute *attr, char *buf)
3647{
3648 struct Scsi_Host *shost = class_to_shost(dev);
3649 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3650 unsigned long lock_flags = 0;
3651 int len;
3652
3653 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3654 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
3655 len = snprintf(buf, PAGE_SIZE, "offline\n");
3656 else
3657 len = snprintf(buf, PAGE_SIZE, "online\n");
3658 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3659 return len;
3660}
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674static ssize_t ipr_store_adapter_state(struct device *dev,
3675 struct device_attribute *attr,
3676 const char *buf, size_t count)
3677{
3678 struct Scsi_Host *shost = class_to_shost(dev);
3679 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3680 unsigned long lock_flags;
3681 int result = count, i;
3682
3683 if (!capable(CAP_SYS_ADMIN))
3684 return -EACCES;
3685
3686 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3687 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead &&
3688 !strncmp(buf, "online", 6)) {
3689 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
3690 spin_lock(&ioa_cfg->hrrq[i]._lock);
3691 ioa_cfg->hrrq[i].ioa_is_dead = 0;
3692 spin_unlock(&ioa_cfg->hrrq[i]._lock);
3693 }
3694 wmb();
3695 ioa_cfg->reset_retries = 0;
3696 ioa_cfg->in_ioa_bringdown = 0;
3697 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3698 }
3699 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3700 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3701
3702 return result;
3703}
3704
3705static struct device_attribute ipr_ioa_state_attr = {
3706 .attr = {
3707 .name = "online_state",
3708 .mode = S_IRUGO | S_IWUSR,
3709 },
3710 .show = ipr_show_adapter_state,
3711 .store = ipr_store_adapter_state
3712};
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726static ssize_t ipr_store_reset_adapter(struct device *dev,
3727 struct device_attribute *attr,
3728 const char *buf, size_t count)
3729{
3730 struct Scsi_Host *shost = class_to_shost(dev);
3731 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3732 unsigned long lock_flags;
3733 int result = count;
3734
3735 if (!capable(CAP_SYS_ADMIN))
3736 return -EACCES;
3737
3738 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3739 if (!ioa_cfg->in_reset_reload)
3740 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3741 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3742 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3743
3744 return result;
3745}
3746
3747static struct device_attribute ipr_ioa_reset_attr = {
3748 .attr = {
3749 .name = "reset_host",
3750 .mode = S_IWUSR,
3751 },
3752 .store = ipr_store_reset_adapter
3753};
3754
3755static int ipr_iopoll(struct irq_poll *iop, int budget);
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765static ssize_t ipr_show_iopoll_weight(struct device *dev,
3766 struct device_attribute *attr, char *buf)
3767{
3768 struct Scsi_Host *shost = class_to_shost(dev);
3769 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3770 unsigned long lock_flags = 0;
3771 int len;
3772
3773 spin_lock_irqsave(shost->host_lock, lock_flags);
3774 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->iopoll_weight);
3775 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3776
3777 return len;
3778}
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790static ssize_t ipr_store_iopoll_weight(struct device *dev,
3791 struct device_attribute *attr,
3792 const char *buf, size_t count)
3793{
3794 struct Scsi_Host *shost = class_to_shost(dev);
3795 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3796 unsigned long user_iopoll_weight;
3797 unsigned long lock_flags = 0;
3798 int i;
3799
3800 if (!ioa_cfg->sis64) {
3801 dev_info(&ioa_cfg->pdev->dev, "irq_poll not supported on this adapter\n");
3802 return -EINVAL;
3803 }
3804 if (kstrtoul(buf, 10, &user_iopoll_weight))
3805 return -EINVAL;
3806
3807 if (user_iopoll_weight > 256) {
3808 dev_info(&ioa_cfg->pdev->dev, "Invalid irq_poll weight. It must be less than 256\n");
3809 return -EINVAL;
3810 }
3811
3812 if (user_iopoll_weight == ioa_cfg->iopoll_weight) {
3813 dev_info(&ioa_cfg->pdev->dev, "Current irq_poll weight has the same weight\n");
3814 return strlen(buf);
3815 }
3816
3817 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3818 for (i = 1; i < ioa_cfg->hrrq_num; i++)
3819 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
3820 }
3821
3822 spin_lock_irqsave(shost->host_lock, lock_flags);
3823 ioa_cfg->iopoll_weight = user_iopoll_weight;
3824 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3825 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
3826 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
3827 ioa_cfg->iopoll_weight, ipr_iopoll);
3828 }
3829 }
3830 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3831
3832 return strlen(buf);
3833}
3834
3835static struct device_attribute ipr_iopoll_weight_attr = {
3836 .attr = {
3837 .name = "iopoll_weight",
3838 .mode = S_IRUGO | S_IWUSR,
3839 },
3840 .show = ipr_show_iopoll_weight,
3841 .store = ipr_store_iopoll_weight
3842};
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3855{
3856 int sg_size, order;
3857 struct ipr_sglist *sglist;
3858
3859
3860 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3861
3862
3863 order = get_order(sg_size);
3864
3865
3866 sglist = kzalloc(sizeof(struct ipr_sglist), GFP_KERNEL);
3867 if (sglist == NULL) {
3868 ipr_trace;
3869 return NULL;
3870 }
3871 sglist->order = order;
3872 sglist->scatterlist = sgl_alloc_order(buf_len, order, false, GFP_KERNEL,
3873 &sglist->num_sg);
3874 if (!sglist->scatterlist) {
3875 kfree(sglist);
3876 return NULL;
3877 }
3878
3879 return sglist;
3880}
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3893{
3894 sgl_free_order(sglist->scatterlist, sglist->order);
3895 kfree(sglist);
3896}
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3911 u8 *buffer, u32 len)
3912{
3913 int bsize_elem, i, result = 0;
3914 struct scatterlist *sg;
3915 void *kaddr;
3916
3917
3918 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3919
3920 sg = sglist->scatterlist;
3921
3922 for (i = 0; i < (len / bsize_elem); i++, sg = sg_next(sg),
3923 buffer += bsize_elem) {
3924 struct page *page = sg_page(sg);
3925
3926 kaddr = kmap(page);
3927 memcpy(kaddr, buffer, bsize_elem);
3928 kunmap(page);
3929
3930 sg->length = bsize_elem;
3931
3932 if (result != 0) {
3933 ipr_trace;
3934 return result;
3935 }
3936 }
3937
3938 if (len % bsize_elem) {
3939 struct page *page = sg_page(sg);
3940
3941 kaddr = kmap(page);
3942 memcpy(kaddr, buffer, len % bsize_elem);
3943 kunmap(page);
3944
3945 sg->length = len % bsize_elem;
3946 }
3947
3948 sglist->buffer_len = len;
3949 return result;
3950}
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3961 struct ipr_sglist *sglist)
3962{
3963 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3964 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3965 struct scatterlist *scatterlist = sglist->scatterlist;
3966 struct scatterlist *sg;
3967 int i;
3968
3969 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3970 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3971 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3972
3973 ioarcb->ioadl_len =
3974 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3975 for_each_sg(scatterlist, sg, ipr_cmd->dma_use_sg, i) {
3976 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3977 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
3978 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
3979 }
3980
3981 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3982}
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3993 struct ipr_sglist *sglist)
3994{
3995 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3996 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3997 struct scatterlist *scatterlist = sglist->scatterlist;
3998 struct scatterlist *sg;
3999 int i;
4000
4001 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
4002 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
4003 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
4004
4005 ioarcb->ioadl_len =
4006 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
4007
4008 for_each_sg(scatterlist, sg, ipr_cmd->dma_use_sg, i) {
4009 ioadl[i].flags_and_data_len =
4010 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(sg));
4011 ioadl[i].address =
4012 cpu_to_be32(sg_dma_address(sg));
4013 }
4014
4015 ioadl[i-1].flags_and_data_len |=
4016 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
4017}
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
4030 struct ipr_sglist *sglist)
4031{
4032 unsigned long lock_flags;
4033
4034 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4035 while (ioa_cfg->in_reset_reload) {
4036 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4037 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4038 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4039 }
4040
4041 if (ioa_cfg->ucode_sglist) {
4042 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4043 dev_err(&ioa_cfg->pdev->dev,
4044 "Microcode download already in progress\n");
4045 return -EIO;
4046 }
4047
4048 sglist->num_dma_sg = dma_map_sg(&ioa_cfg->pdev->dev,
4049 sglist->scatterlist, sglist->num_sg,
4050 DMA_TO_DEVICE);
4051
4052 if (!sglist->num_dma_sg) {
4053 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4054 dev_err(&ioa_cfg->pdev->dev,
4055 "Failed to map microcode download buffer!\n");
4056 return -EIO;
4057 }
4058
4059 ioa_cfg->ucode_sglist = sglist;
4060 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
4061 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4062 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4063
4064 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4065 ioa_cfg->ucode_sglist = NULL;
4066 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4067 return 0;
4068}
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082static ssize_t ipr_store_update_fw(struct device *dev,
4083 struct device_attribute *attr,
4084 const char *buf, size_t count)
4085{
4086 struct Scsi_Host *shost = class_to_shost(dev);
4087 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4088 struct ipr_ucode_image_header *image_hdr;
4089 const struct firmware *fw_entry;
4090 struct ipr_sglist *sglist;
4091 char fname[100];
4092 char *src;
4093 char *endline;
4094 int result, dnld_size;
4095
4096 if (!capable(CAP_SYS_ADMIN))
4097 return -EACCES;
4098
4099 snprintf(fname, sizeof(fname), "%s", buf);
4100
4101 endline = strchr(fname, '\n');
4102 if (endline)
4103 *endline = '\0';
4104
4105 if (request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
4106 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
4107 return -EIO;
4108 }
4109
4110 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
4111
4112 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
4113 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
4114 sglist = ipr_alloc_ucode_buffer(dnld_size);
4115
4116 if (!sglist) {
4117 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
4118 release_firmware(fw_entry);
4119 return -ENOMEM;
4120 }
4121
4122 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
4123
4124 if (result) {
4125 dev_err(&ioa_cfg->pdev->dev,
4126 "Microcode buffer copy to DMA buffer failed\n");
4127 goto out;
4128 }
4129
4130 ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n");
4131
4132 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
4133
4134 if (!result)
4135 result = count;
4136out:
4137 ipr_free_ucode_buffer(sglist);
4138 release_firmware(fw_entry);
4139 return result;
4140}
4141
4142static struct device_attribute ipr_update_fw_attr = {
4143 .attr = {
4144 .name = "update_fw",
4145 .mode = S_IWUSR,
4146 },
4147 .store = ipr_store_update_fw
4148};
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159static ssize_t ipr_show_fw_type(struct device *dev,
4160 struct device_attribute *attr, char *buf)
4161{
4162 struct Scsi_Host *shost = class_to_shost(dev);
4163 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4164 unsigned long lock_flags = 0;
4165 int len;
4166
4167 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4168 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
4169 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4170 return len;
4171}
4172
4173static struct device_attribute ipr_ioa_fw_type_attr = {
4174 .attr = {
4175 .name = "fw_type",
4176 .mode = S_IRUGO,
4177 },
4178 .show = ipr_show_fw_type
4179};
4180
4181static ssize_t ipr_read_async_err_log(struct file *filep, struct kobject *kobj,
4182 struct bin_attribute *bin_attr, char *buf,
4183 loff_t off, size_t count)
4184{
4185 struct device *cdev = container_of(kobj, struct device, kobj);
4186 struct Scsi_Host *shost = class_to_shost(cdev);
4187 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4188 struct ipr_hostrcb *hostrcb;
4189 unsigned long lock_flags = 0;
4190 int ret;
4191
4192 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4193 hostrcb = list_first_entry_or_null(&ioa_cfg->hostrcb_report_q,
4194 struct ipr_hostrcb, queue);
4195 if (!hostrcb) {
4196 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4197 return 0;
4198 }
4199 ret = memory_read_from_buffer(buf, count, &off, &hostrcb->hcam,
4200 sizeof(hostrcb->hcam));
4201 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4202 return ret;
4203}
4204
4205static ssize_t ipr_next_async_err_log(struct file *filep, struct kobject *kobj,
4206 struct bin_attribute *bin_attr, char *buf,
4207 loff_t off, size_t count)
4208{
4209 struct device *cdev = container_of(kobj, struct device, kobj);
4210 struct Scsi_Host *shost = class_to_shost(cdev);
4211 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4212 struct ipr_hostrcb *hostrcb;
4213 unsigned long lock_flags = 0;
4214
4215 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4216 hostrcb = list_first_entry_or_null(&ioa_cfg->hostrcb_report_q,
4217 struct ipr_hostrcb, queue);
4218 if (!hostrcb) {
4219 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4220 return count;
4221 }
4222
4223
4224 list_move_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
4225 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4226 return count;
4227}
4228
4229static struct bin_attribute ipr_ioa_async_err_log = {
4230 .attr = {
4231 .name = "async_err_log",
4232 .mode = S_IRUGO | S_IWUSR,
4233 },
4234 .size = 0,
4235 .read = ipr_read_async_err_log,
4236 .write = ipr_next_async_err_log
4237};
4238
4239static struct device_attribute *ipr_ioa_attrs[] = {
4240 &ipr_fw_version_attr,
4241 &ipr_log_level_attr,
4242 &ipr_diagnostics_attr,
4243 &ipr_ioa_state_attr,
4244 &ipr_ioa_reset_attr,
4245 &ipr_update_fw_attr,
4246 &ipr_ioa_fw_type_attr,
4247 &ipr_iopoll_weight_attr,
4248 NULL,
4249};
4250
4251#ifdef CONFIG_SCSI_IPR_DUMP
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
4265 struct bin_attribute *bin_attr,
4266 char *buf, loff_t off, size_t count)
4267{
4268 struct device *cdev = container_of(kobj, struct device, kobj);
4269 struct Scsi_Host *shost = class_to_shost(cdev);
4270 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4271 struct ipr_dump *dump;
4272 unsigned long lock_flags = 0;
4273 char *src;
4274 int len, sdt_end;
4275 size_t rc = count;
4276
4277 if (!capable(CAP_SYS_ADMIN))
4278 return -EACCES;
4279
4280 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4281 dump = ioa_cfg->dump;
4282
4283 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
4284 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4285 return 0;
4286 }
4287 kref_get(&dump->kref);
4288 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4289
4290 if (off > dump->driver_dump.hdr.len) {
4291 kref_put(&dump->kref, ipr_release_dump);
4292 return 0;
4293 }
4294
4295 if (off + count > dump->driver_dump.hdr.len) {
4296 count = dump->driver_dump.hdr.len - off;
4297 rc = count;
4298 }
4299
4300 if (count && off < sizeof(dump->driver_dump)) {
4301 if (off + count > sizeof(dump->driver_dump))
4302 len = sizeof(dump->driver_dump) - off;
4303 else
4304 len = count;
4305 src = (u8 *)&dump->driver_dump + off;
4306 memcpy(buf, src, len);
4307 buf += len;
4308 off += len;
4309 count -= len;
4310 }
4311
4312 off -= sizeof(dump->driver_dump);
4313
4314 if (ioa_cfg->sis64)
4315 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4316 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
4317 sizeof(struct ipr_sdt_entry));
4318 else
4319 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4320 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
4321
4322 if (count && off < sdt_end) {
4323 if (off + count > sdt_end)
4324 len = sdt_end - off;
4325 else
4326 len = count;
4327 src = (u8 *)&dump->ioa_dump + off;
4328 memcpy(buf, src, len);
4329 buf += len;
4330 off += len;
4331 count -= len;
4332 }
4333
4334 off -= sdt_end;
4335
4336 while (count) {
4337 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
4338 len = PAGE_ALIGN(off) - off;
4339 else
4340 len = count;
4341 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
4342 src += off & ~PAGE_MASK;
4343 memcpy(buf, src, len);
4344 buf += len;
4345 off += len;
4346 count -= len;
4347 }
4348
4349 kref_put(&dump->kref, ipr_release_dump);
4350 return rc;
4351}
4352
4353
4354
4355
4356
4357
4358
4359
4360static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
4361{
4362 struct ipr_dump *dump;
4363 __be32 **ioa_data;
4364 unsigned long lock_flags = 0;
4365
4366 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
4367
4368 if (!dump) {
4369 ipr_err("Dump memory allocation failed\n");
4370 return -ENOMEM;
4371 }
4372
4373 if (ioa_cfg->sis64)
4374 ioa_data = vmalloc(array_size(IPR_FMT3_MAX_NUM_DUMP_PAGES,
4375 sizeof(__be32 *)));
4376 else
4377 ioa_data = vmalloc(array_size(IPR_FMT2_MAX_NUM_DUMP_PAGES,
4378 sizeof(__be32 *)));
4379
4380 if (!ioa_data) {
4381 ipr_err("Dump memory allocation failed\n");
4382 kfree(dump);
4383 return -ENOMEM;
4384 }
4385
4386 dump->ioa_dump.ioa_data = ioa_data;
4387
4388 kref_init(&dump->kref);
4389 dump->ioa_cfg = ioa_cfg;
4390
4391 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4392
4393 if (INACTIVE != ioa_cfg->sdt_state) {
4394 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4395 vfree(dump->ioa_dump.ioa_data);
4396 kfree(dump);
4397 return 0;
4398 }
4399
4400 ioa_cfg->dump = dump;
4401 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
4402 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead && !ioa_cfg->dump_taken) {
4403 ioa_cfg->dump_taken = 1;
4404 schedule_work(&ioa_cfg->work_q);
4405 }
4406 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4407
4408 return 0;
4409}
4410
4411
4412
4413
4414
4415
4416
4417
4418static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4419{
4420 struct ipr_dump *dump;
4421 unsigned long lock_flags = 0;
4422
4423 ENTER;
4424
4425 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4426 dump = ioa_cfg->dump;
4427 if (!dump) {
4428 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4429 return 0;
4430 }
4431
4432 ioa_cfg->dump = NULL;
4433 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4434
4435 kref_put(&dump->kref, ipr_release_dump);
4436
4437 LEAVE;
4438 return 0;
4439}
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4454 struct bin_attribute *bin_attr,
4455 char *buf, loff_t off, size_t count)
4456{
4457 struct device *cdev = container_of(kobj, struct device, kobj);
4458 struct Scsi_Host *shost = class_to_shost(cdev);
4459 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4460 int rc;
4461
4462 if (!capable(CAP_SYS_ADMIN))
4463 return -EACCES;
4464
4465 if (buf[0] == '1')
4466 rc = ipr_alloc_dump(ioa_cfg);
4467 else if (buf[0] == '0')
4468 rc = ipr_free_dump(ioa_cfg);
4469 else
4470 return -EINVAL;
4471
4472 if (rc)
4473 return rc;
4474 else
4475 return count;
4476}
4477
4478static struct bin_attribute ipr_dump_attr = {
4479 .attr = {
4480 .name = "dump",
4481 .mode = S_IRUSR | S_IWUSR,
4482 },
4483 .size = 0,
4484 .read = ipr_read_dump,
4485 .write = ipr_write_dump
4486};
4487#else
4488static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4489#endif
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth)
4500{
4501 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4502 struct ipr_resource_entry *res;
4503 unsigned long lock_flags = 0;
4504
4505 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4506 res = (struct ipr_resource_entry *)sdev->hostdata;
4507
4508 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4509 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4510 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4511
4512 scsi_change_queue_depth(sdev, qdepth);
4513 return sdev->queue_depth;
4514}
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4526{
4527 struct scsi_device *sdev = to_scsi_device(dev);
4528 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4529 struct ipr_resource_entry *res;
4530 unsigned long lock_flags = 0;
4531 ssize_t len = -ENXIO;
4532
4533 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4534 res = (struct ipr_resource_entry *)sdev->hostdata;
4535 if (res)
4536 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4537 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4538 return len;
4539}
4540
4541static struct device_attribute ipr_adapter_handle_attr = {
4542 .attr = {
4543 .name = "adapter_handle",
4544 .mode = S_IRUSR,
4545 },
4546 .show = ipr_show_adapter_handle
4547};
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4560{
4561 struct scsi_device *sdev = to_scsi_device(dev);
4562 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4563 struct ipr_resource_entry *res;
4564 unsigned long lock_flags = 0;
4565 ssize_t len = -ENXIO;
4566 char buffer[IPR_MAX_RES_PATH_LENGTH];
4567
4568 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4569 res = (struct ipr_resource_entry *)sdev->hostdata;
4570 if (res && ioa_cfg->sis64)
4571 len = snprintf(buf, PAGE_SIZE, "%s\n",
4572 __ipr_format_res_path(res->res_path, buffer,
4573 sizeof(buffer)));
4574 else if (res)
4575 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4576 res->bus, res->target, res->lun);
4577
4578 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4579 return len;
4580}
4581
4582static struct device_attribute ipr_resource_path_attr = {
4583 .attr = {
4584 .name = "resource_path",
4585 .mode = S_IRUGO,
4586 },
4587 .show = ipr_show_resource_path
4588};
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4600{
4601 struct scsi_device *sdev = to_scsi_device(dev);
4602 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4603 struct ipr_resource_entry *res;
4604 unsigned long lock_flags = 0;
4605 ssize_t len = -ENXIO;
4606
4607 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4608 res = (struct ipr_resource_entry *)sdev->hostdata;
4609 if (res && ioa_cfg->sis64)
4610 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", be64_to_cpu(res->dev_id));
4611 else if (res)
4612 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4613
4614 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4615 return len;
4616}
4617
4618static struct device_attribute ipr_device_id_attr = {
4619 .attr = {
4620 .name = "device_id",
4621 .mode = S_IRUGO,
4622 },
4623 .show = ipr_show_device_id
4624};
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4636{
4637 struct scsi_device *sdev = to_scsi_device(dev);
4638 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4639 struct ipr_resource_entry *res;
4640 unsigned long lock_flags = 0;
4641 ssize_t len = -ENXIO;
4642
4643 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4644 res = (struct ipr_resource_entry *)sdev->hostdata;
4645
4646 if (res)
4647 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4648
4649 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4650 return len;
4651}
4652
4653static struct device_attribute ipr_resource_type_attr = {
4654 .attr = {
4655 .name = "resource_type",
4656 .mode = S_IRUGO,
4657 },
4658 .show = ipr_show_resource_type
4659};
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670static ssize_t ipr_show_raw_mode(struct device *dev,
4671 struct device_attribute *attr, char *buf)
4672{
4673 struct scsi_device *sdev = to_scsi_device(dev);
4674 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4675 struct ipr_resource_entry *res;
4676 unsigned long lock_flags = 0;
4677 ssize_t len;
4678
4679 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4680 res = (struct ipr_resource_entry *)sdev->hostdata;
4681 if (res)
4682 len = snprintf(buf, PAGE_SIZE, "%d\n", res->raw_mode);
4683 else
4684 len = -ENXIO;
4685 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4686 return len;
4687}
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699static ssize_t ipr_store_raw_mode(struct device *dev,
4700 struct device_attribute *attr,
4701 const char *buf, size_t count)
4702{
4703 struct scsi_device *sdev = to_scsi_device(dev);
4704 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4705 struct ipr_resource_entry *res;
4706 unsigned long lock_flags = 0;
4707 ssize_t len;
4708
4709 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4710 res = (struct ipr_resource_entry *)sdev->hostdata;
4711 if (res) {
4712 if (ipr_is_af_dasd_device(res)) {
4713 res->raw_mode = simple_strtoul(buf, NULL, 10);
4714 len = strlen(buf);
4715 if (res->sdev)
4716 sdev_printk(KERN_INFO, res->sdev, "raw mode is %s\n",
4717 res->raw_mode ? "enabled" : "disabled");
4718 } else
4719 len = -EINVAL;
4720 } else
4721 len = -ENXIO;
4722 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4723 return len;
4724}
4725
4726static struct device_attribute ipr_raw_mode_attr = {
4727 .attr = {
4728 .name = "raw_mode",
4729 .mode = S_IRUGO | S_IWUSR,
4730 },
4731 .show = ipr_show_raw_mode,
4732 .store = ipr_store_raw_mode
4733};
4734
4735static struct device_attribute *ipr_dev_attrs[] = {
4736 &ipr_adapter_handle_attr,
4737 &ipr_resource_path_attr,
4738 &ipr_device_id_attr,
4739 &ipr_resource_type_attr,
4740 &ipr_raw_mode_attr,
4741 NULL,
4742};
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758static int ipr_biosparam(struct scsi_device *sdev,
4759 struct block_device *block_device,
4760 sector_t capacity, int *parm)
4761{
4762 int heads, sectors;
4763 sector_t cylinders;
4764
4765 heads = 128;
4766 sectors = 32;
4767
4768 cylinders = capacity;
4769 sector_div(cylinders, (128 * 32));
4770
4771
4772 parm[0] = heads;
4773 parm[1] = sectors;
4774 parm[2] = cylinders;
4775
4776 return 0;
4777}
4778
4779
4780
4781
4782
4783
4784
4785
4786static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4787{
4788 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4789 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4790 struct ipr_resource_entry *res;
4791
4792 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4793 if ((res->bus == starget->channel) &&
4794 (res->target == starget->id)) {
4795 return res;
4796 }
4797 }
4798
4799 return NULL;
4800}
4801
4802static struct ata_port_info sata_port_info;
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814static int ipr_target_alloc(struct scsi_target *starget)
4815{
4816 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4817 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4818 struct ipr_sata_port *sata_port;
4819 struct ata_port *ap;
4820 struct ipr_resource_entry *res;
4821 unsigned long lock_flags;
4822
4823 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4824 res = ipr_find_starget(starget);
4825 starget->hostdata = NULL;
4826
4827 if (res && ipr_is_gata(res)) {
4828 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4829 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4830 if (!sata_port)
4831 return -ENOMEM;
4832
4833 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4834 if (ap) {
4835 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4836 sata_port->ioa_cfg = ioa_cfg;
4837 sata_port->ap = ap;
4838 sata_port->res = res;
4839
4840 res->sata_port = sata_port;
4841 ap->private_data = sata_port;
4842 starget->hostdata = sata_port;
4843 } else {
4844 kfree(sata_port);
4845 return -ENOMEM;
4846 }
4847 }
4848 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4849
4850 return 0;
4851}
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861static void ipr_target_destroy(struct scsi_target *starget)
4862{
4863 struct ipr_sata_port *sata_port = starget->hostdata;
4864 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4865 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4866
4867 if (ioa_cfg->sis64) {
4868 if (!ipr_find_starget(starget)) {
4869 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4870 clear_bit(starget->id, ioa_cfg->array_ids);
4871 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4872 clear_bit(starget->id, ioa_cfg->vset_ids);
4873 else if (starget->channel == 0)
4874 clear_bit(starget->id, ioa_cfg->target_ids);
4875 }
4876 }
4877
4878 if (sata_port) {
4879 starget->hostdata = NULL;
4880 ata_sas_port_destroy(sata_port->ap);
4881 kfree(sata_port);
4882 }
4883}
4884
4885
4886
4887
4888
4889
4890
4891
4892static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4893{
4894 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4895 struct ipr_resource_entry *res;
4896
4897 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4898 if ((res->bus == sdev->channel) &&
4899 (res->target == sdev->id) &&
4900 (res->lun == sdev->lun))
4901 return res;
4902 }
4903
4904 return NULL;
4905}
4906
4907
4908
4909
4910
4911
4912
4913
4914static void ipr_slave_destroy(struct scsi_device *sdev)
4915{
4916 struct ipr_resource_entry *res;
4917 struct ipr_ioa_cfg *ioa_cfg;
4918 unsigned long lock_flags = 0;
4919
4920 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4921
4922 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4923 res = (struct ipr_resource_entry *) sdev->hostdata;
4924 if (res) {
4925 if (res->sata_port)
4926 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4927 sdev->hostdata = NULL;
4928 res->sdev = NULL;
4929 res->sata_port = NULL;
4930 }
4931 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4932}
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943static int ipr_slave_configure(struct scsi_device *sdev)
4944{
4945 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4946 struct ipr_resource_entry *res;
4947 struct ata_port *ap = NULL;
4948 unsigned long lock_flags = 0;
4949 char buffer[IPR_MAX_RES_PATH_LENGTH];
4950
4951 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4952 res = sdev->hostdata;
4953 if (res) {
4954 if (ipr_is_af_dasd_device(res))
4955 sdev->type = TYPE_RAID;
4956 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4957 sdev->scsi_level = 4;
4958 sdev->no_uld_attach = 1;
4959 }
4960 if (ipr_is_vset_device(res)) {
4961 sdev->scsi_level = SCSI_SPC_3;
4962 sdev->no_report_opcodes = 1;
4963 blk_queue_rq_timeout(sdev->request_queue,
4964 IPR_VSET_RW_TIMEOUT);
4965 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4966 }
4967 if (ipr_is_gata(res) && res->sata_port)
4968 ap = res->sata_port->ap;
4969 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4970
4971 if (ap) {
4972 scsi_change_queue_depth(sdev, IPR_MAX_CMD_PER_ATA_LUN);
4973 ata_sas_slave_configure(sdev, ap);
4974 }
4975
4976 if (ioa_cfg->sis64)
4977 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4978 ipr_format_res_path(ioa_cfg,
4979 res->res_path, buffer, sizeof(buffer)));
4980 return 0;
4981 }
4982 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4983 return 0;
4984}
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4997{
4998 struct ipr_sata_port *sata_port = NULL;
4999 int rc = -ENXIO;
5000
5001 ENTER;
5002 if (sdev->sdev_target)
5003 sata_port = sdev->sdev_target->hostdata;
5004 if (sata_port) {
5005 rc = ata_sas_port_init(sata_port->ap);
5006 if (rc == 0)
5007 rc = ata_sas_sync_probe(sata_port->ap);
5008 }
5009
5010 if (rc)
5011 ipr_slave_destroy(sdev);
5012
5013 LEAVE;
5014 return rc;
5015}
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029static int ipr_slave_alloc(struct scsi_device *sdev)
5030{
5031 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
5032 struct ipr_resource_entry *res;
5033 unsigned long lock_flags;
5034 int rc = -ENXIO;
5035
5036 sdev->hostdata = NULL;
5037
5038 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5039
5040 res = ipr_find_sdev(sdev);
5041 if (res) {
5042 res->sdev = sdev;
5043 res->add_to_ml = 0;
5044 res->in_erp = 0;
5045 sdev->hostdata = res;
5046 if (!ipr_is_naca_model(res))
5047 res->needs_sync_complete = 1;
5048 rc = 0;
5049 if (ipr_is_gata(res)) {
5050 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5051 return ipr_ata_slave_alloc(sdev);
5052 }
5053 }
5054
5055 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5056
5057 return rc;
5058}
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068static int ipr_match_lun(struct ipr_cmnd *ipr_cmd, void *device)
5069{
5070 if (ipr_cmd->scsi_cmd && ipr_cmd->scsi_cmd->device == device)
5071 return 1;
5072 return 0;
5073}
5074
5075
5076
5077
5078
5079
5080
5081
5082static bool ipr_cmnd_is_free(struct ipr_cmnd *ipr_cmd)
5083{
5084 struct ipr_cmnd *loop_cmd;
5085
5086 list_for_each_entry(loop_cmd, &ipr_cmd->hrrq->hrrq_free_q, queue) {
5087 if (loop_cmd == ipr_cmd)
5088 return true;
5089 }
5090
5091 return false;
5092}
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102static int ipr_match_res(struct ipr_cmnd *ipr_cmd, void *resource)
5103{
5104 struct ipr_resource_entry *res = resource;
5105
5106 if (res && ipr_cmd->ioarcb.res_handle == res->res_handle)
5107 return 1;
5108 return 0;
5109}
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120static int ipr_wait_for_ops(struct ipr_ioa_cfg *ioa_cfg, void *device,
5121 int (*match)(struct ipr_cmnd *, void *))
5122{
5123 struct ipr_cmnd *ipr_cmd;
5124 int wait, i;
5125 unsigned long flags;
5126 struct ipr_hrr_queue *hrrq;
5127 signed long timeout = IPR_ABORT_TASK_TIMEOUT;
5128 DECLARE_COMPLETION_ONSTACK(comp);
5129
5130 ENTER;
5131 do {
5132 wait = 0;
5133
5134 for_each_hrrq(hrrq, ioa_cfg) {
5135 spin_lock_irqsave(hrrq->lock, flags);
5136 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5137 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5138 if (!ipr_cmnd_is_free(ipr_cmd)) {
5139 if (match(ipr_cmd, device)) {
5140 ipr_cmd->eh_comp = ∁
5141 wait++;
5142 }
5143 }
5144 }
5145 spin_unlock_irqrestore(hrrq->lock, flags);
5146 }
5147
5148 if (wait) {
5149 timeout = wait_for_completion_timeout(&comp, timeout);
5150
5151 if (!timeout) {
5152 wait = 0;
5153
5154 for_each_hrrq(hrrq, ioa_cfg) {
5155 spin_lock_irqsave(hrrq->lock, flags);
5156 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5157 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5158 if (!ipr_cmnd_is_free(ipr_cmd)) {
5159 if (match(ipr_cmd, device)) {
5160 ipr_cmd->eh_comp = NULL;
5161 wait++;
5162 }
5163 }
5164 }
5165 spin_unlock_irqrestore(hrrq->lock, flags);
5166 }
5167
5168 if (wait)
5169 dev_err(&ioa_cfg->pdev->dev, "Timed out waiting for aborted commands\n");
5170 LEAVE;
5171 return wait ? FAILED : SUCCESS;
5172 }
5173 }
5174 } while (wait);
5175
5176 LEAVE;
5177 return SUCCESS;
5178}
5179
5180static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
5181{
5182 struct ipr_ioa_cfg *ioa_cfg;
5183 unsigned long lock_flags = 0;
5184 int rc = SUCCESS;
5185
5186 ENTER;
5187 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5188 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5189
5190 if (!ioa_cfg->in_reset_reload && !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5191 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
5192 dev_err(&ioa_cfg->pdev->dev,
5193 "Adapter being reset as a result of error recovery.\n");
5194
5195 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5196 ioa_cfg->sdt_state = GET_DUMP;
5197 }
5198
5199 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5200 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5201 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5202
5203
5204
5205 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5206 ipr_trace;
5207 rc = FAILED;
5208 }
5209
5210 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5211 LEAVE;
5212 return rc;
5213}
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
5230 struct ipr_resource_entry *res)
5231{
5232 struct ipr_cmnd *ipr_cmd;
5233 struct ipr_ioarcb *ioarcb;
5234 struct ipr_cmd_pkt *cmd_pkt;
5235 struct ipr_ioarcb_ata_regs *regs;
5236 u32 ioasc;
5237
5238 ENTER;
5239 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5240 ioarcb = &ipr_cmd->ioarcb;
5241 cmd_pkt = &ioarcb->cmd_pkt;
5242
5243 if (ipr_cmd->ioa_cfg->sis64) {
5244 regs = &ipr_cmd->i.ata_ioadl.regs;
5245 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
5246 } else
5247 regs = &ioarcb->u.add_data.u.regs;
5248
5249 ioarcb->res_handle = res->res_handle;
5250 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5251 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5252 if (ipr_is_gata(res)) {
5253 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
5254 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
5255 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
5256 }
5257
5258 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5259 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5260 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5261 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
5262 if (ipr_cmd->ioa_cfg->sis64)
5263 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
5264 sizeof(struct ipr_ioasa_gata));
5265 else
5266 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
5267 sizeof(struct ipr_ioasa_gata));
5268 }
5269
5270 LEAVE;
5271 return IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0;
5272}
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
5286 unsigned long deadline)
5287{
5288 struct ipr_sata_port *sata_port = link->ap->private_data;
5289 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
5290 struct ipr_resource_entry *res;
5291 unsigned long lock_flags = 0;
5292 int rc = -ENXIO, ret;
5293
5294 ENTER;
5295 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5296 while (ioa_cfg->in_reset_reload) {
5297 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5298 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5299 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5300 }
5301
5302 res = sata_port->res;
5303 if (res) {
5304 rc = ipr_device_reset(ioa_cfg, res);
5305 *classes = res->ata_class;
5306 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5307
5308 ret = ipr_wait_for_ops(ioa_cfg, res, ipr_match_res);
5309 if (ret != SUCCESS) {
5310 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5311 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
5312 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5313
5314 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5315 }
5316 } else
5317 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5318
5319 LEAVE;
5320 return rc;
5321}
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
5335{
5336 struct ipr_cmnd *ipr_cmd;
5337 struct ipr_ioa_cfg *ioa_cfg;
5338 struct ipr_resource_entry *res;
5339 struct ata_port *ap;
5340 int rc = 0, i;
5341 struct ipr_hrr_queue *hrrq;
5342
5343 ENTER;
5344 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5345 res = scsi_cmd->device->hostdata;
5346
5347
5348
5349
5350
5351
5352 if (ioa_cfg->in_reset_reload)
5353 return FAILED;
5354 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5355 return FAILED;
5356
5357 for_each_hrrq(hrrq, ioa_cfg) {
5358 spin_lock(&hrrq->_lock);
5359 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5360 ipr_cmd = ioa_cfg->ipr_cmnd_list[i];
5361
5362 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
5363 if (!ipr_cmd->qc)
5364 continue;
5365 if (ipr_cmnd_is_free(ipr_cmd))
5366 continue;
5367
5368 ipr_cmd->done = ipr_sata_eh_done;
5369 if (!(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
5370 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
5371 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
5372 }
5373 }
5374 }
5375 spin_unlock(&hrrq->_lock);
5376 }
5377 res->resetting_device = 1;
5378 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
5379
5380 if (ipr_is_gata(res) && res->sata_port) {
5381 ap = res->sata_port->ap;
5382 spin_unlock_irq(scsi_cmd->device->host->host_lock);
5383 ata_std_error_handler(ap);
5384 spin_lock_irq(scsi_cmd->device->host->host_lock);
5385 } else
5386 rc = ipr_device_reset(ioa_cfg, res);
5387 res->resetting_device = 0;
5388 res->reset_occurred = 1;
5389
5390 LEAVE;
5391 return rc ? FAILED : SUCCESS;
5392}
5393
5394static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
5395{
5396 int rc;
5397 struct ipr_ioa_cfg *ioa_cfg;
5398 struct ipr_resource_entry *res;
5399
5400 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5401 res = cmd->device->hostdata;
5402
5403 if (!res)
5404 return FAILED;
5405
5406 spin_lock_irq(cmd->device->host->host_lock);
5407 rc = __ipr_eh_dev_reset(cmd);
5408 spin_unlock_irq(cmd->device->host->host_lock);
5409
5410 if (rc == SUCCESS) {
5411 if (ipr_is_gata(res) && res->sata_port)
5412 rc = ipr_wait_for_ops(ioa_cfg, res, ipr_match_res);
5413 else
5414 rc = ipr_wait_for_ops(ioa_cfg, cmd->device, ipr_match_lun);
5415 }
5416
5417 return rc;
5418}
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
5430{
5431 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5432 struct ipr_resource_entry *res;
5433
5434 ENTER;
5435 if (!ioa_cfg->sis64)
5436 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
5437 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
5438 scsi_report_bus_reset(ioa_cfg->host, res->bus);
5439 break;
5440 }
5441 }
5442
5443
5444
5445
5446
5447 if (ipr_cmd->sibling->sibling)
5448 ipr_cmd->sibling->sibling = NULL;
5449 else
5450 ipr_cmd->sibling->done(ipr_cmd->sibling);
5451
5452 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5453 LEAVE;
5454}
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467static void ipr_abort_timeout(struct timer_list *t)
5468{
5469 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
5470 struct ipr_cmnd *reset_cmd;
5471 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5472 struct ipr_cmd_pkt *cmd_pkt;
5473 unsigned long lock_flags = 0;
5474
5475 ENTER;
5476 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5477 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
5478 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5479 return;
5480 }
5481
5482 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
5483 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5484 ipr_cmd->sibling = reset_cmd;
5485 reset_cmd->sibling = ipr_cmd;
5486 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
5487 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
5488 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5489 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5490 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
5491
5492 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5493 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5494 LEAVE;
5495}
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
5507{
5508 struct ipr_cmnd *ipr_cmd;
5509 struct ipr_ioa_cfg *ioa_cfg;
5510 struct ipr_resource_entry *res;
5511 struct ipr_cmd_pkt *cmd_pkt;
5512 u32 ioasc;
5513 int i, op_found = 0;
5514 struct ipr_hrr_queue *hrrq;
5515
5516 ENTER;
5517 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5518 res = scsi_cmd->device->hostdata;
5519
5520
5521
5522
5523
5524 if (ioa_cfg->in_reset_reload ||
5525 ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5526 return FAILED;
5527 if (!res)
5528 return FAILED;
5529
5530
5531
5532
5533
5534
5535 readl(ioa_cfg->regs.sense_interrupt_reg);
5536
5537 if (!ipr_is_gscsi(res))
5538 return FAILED;
5539
5540 for_each_hrrq(hrrq, ioa_cfg) {
5541 spin_lock(&hrrq->_lock);
5542 for (i = hrrq->min_cmd_id; i <= hrrq->max_cmd_id; i++) {
5543 if (ioa_cfg->ipr_cmnd_list[i]->scsi_cmd == scsi_cmd) {
5544 if (!ipr_cmnd_is_free(ioa_cfg->ipr_cmnd_list[i])) {
5545 op_found = 1;
5546 break;
5547 }
5548 }
5549 }
5550 spin_unlock(&hrrq->_lock);
5551 }
5552
5553 if (!op_found)
5554 return SUCCESS;
5555
5556 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5557 ipr_cmd->ioarcb.res_handle = res->res_handle;
5558 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5559 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5560 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5561 ipr_cmd->u.sdev = scsi_cmd->device;
5562
5563 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
5564 scsi_cmd->cmnd[0]);
5565 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
5566 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5567
5568
5569
5570
5571
5572 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
5573 ioasc = 0;
5574 ipr_trace;
5575 }
5576
5577 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5578 if (!ipr_is_naca_model(res))
5579 res->needs_sync_complete = 1;
5580
5581 LEAVE;
5582 return IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS;
5583}
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593static int ipr_scan_finished(struct Scsi_Host *shost, unsigned long elapsed_time)
5594{
5595 unsigned long lock_flags;
5596 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
5597 int rc = 0;
5598
5599 spin_lock_irqsave(shost->host_lock, lock_flags);
5600 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead || ioa_cfg->scan_done)
5601 rc = 1;
5602 if ((elapsed_time/HZ) > (ioa_cfg->transop_timeout * 2))
5603 rc = 1;
5604 spin_unlock_irqrestore(shost->host_lock, lock_flags);
5605 return rc;
5606}
5607
5608
5609
5610
5611
5612
5613
5614
5615static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5616{
5617 unsigned long flags;
5618 int rc;
5619 struct ipr_ioa_cfg *ioa_cfg;
5620
5621 ENTER;
5622
5623 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5624
5625 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5626 rc = ipr_cancel_op(scsi_cmd);
5627 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5628
5629 if (rc == SUCCESS)
5630 rc = ipr_wait_for_ops(ioa_cfg, scsi_cmd->device, ipr_match_lun);
5631 LEAVE;
5632 return rc;
5633}
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5644 u32 int_reg)
5645{
5646 irqreturn_t rc = IRQ_HANDLED;
5647 u32 int_mask_reg;
5648
5649 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5650 int_reg &= ~int_mask_reg;
5651
5652
5653
5654
5655 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5656 if (ioa_cfg->sis64) {
5657 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5658 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5659 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5660
5661
5662 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5663 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5664 list_del(&ioa_cfg->reset_cmd->queue);
5665 del_timer(&ioa_cfg->reset_cmd->timer);
5666 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5667 return IRQ_HANDLED;
5668 }
5669 }
5670
5671 return IRQ_NONE;
5672 }
5673
5674 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5675
5676 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5677 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5678
5679 list_del(&ioa_cfg->reset_cmd->queue);
5680 del_timer(&ioa_cfg->reset_cmd->timer);
5681 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5682 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5683 if (ioa_cfg->clear_isr) {
5684 if (ipr_debug && printk_ratelimit())
5685 dev_err(&ioa_cfg->pdev->dev,
5686 "Spurious interrupt detected. 0x%08X\n", int_reg);
5687 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5688 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5689 return IRQ_NONE;
5690 }
5691 } else {
5692 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5693 ioa_cfg->ioa_unit_checked = 1;
5694 else if (int_reg & IPR_PCII_NO_HOST_RRQ)
5695 dev_err(&ioa_cfg->pdev->dev,
5696 "No Host RRQ. 0x%08X\n", int_reg);
5697 else
5698 dev_err(&ioa_cfg->pdev->dev,
5699 "Permanent IOA failure. 0x%08X\n", int_reg);
5700
5701 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5702 ioa_cfg->sdt_state = GET_DUMP;
5703
5704 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5705 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5706 }
5707
5708 return rc;
5709}
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg, u16 number)
5721{
5722 ioa_cfg->errors_logged++;
5723 dev_err(&ioa_cfg->pdev->dev, "%s %d\n", msg, number);
5724
5725 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5726 ioa_cfg->sdt_state = GET_DUMP;
5727
5728 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5729}
5730
5731static int ipr_process_hrrq(struct ipr_hrr_queue *hrr_queue, int budget,
5732 struct list_head *doneq)
5733{
5734 u32 ioasc;
5735 u16 cmd_index;
5736 struct ipr_cmnd *ipr_cmd;
5737 struct ipr_ioa_cfg *ioa_cfg = hrr_queue->ioa_cfg;
5738 int num_hrrq = 0;
5739
5740
5741 if (!hrr_queue->allow_interrupts)
5742 return 0;
5743
5744 while ((be32_to_cpu(*hrr_queue->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5745 hrr_queue->toggle_bit) {
5746
5747 cmd_index = (be32_to_cpu(*hrr_queue->hrrq_curr) &
5748 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >>
5749 IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5750
5751 if (unlikely(cmd_index > hrr_queue->max_cmd_id ||
5752 cmd_index < hrr_queue->min_cmd_id)) {
5753 ipr_isr_eh(ioa_cfg,
5754 "Invalid response handle from IOA: ",
5755 cmd_index);
5756 break;
5757 }
5758
5759 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5760 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5761
5762 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5763
5764 list_move_tail(&ipr_cmd->queue, doneq);
5765
5766 if (hrr_queue->hrrq_curr < hrr_queue->hrrq_end) {
5767 hrr_queue->hrrq_curr++;
5768 } else {
5769 hrr_queue->hrrq_curr = hrr_queue->hrrq_start;
5770 hrr_queue->toggle_bit ^= 1u;
5771 }
5772 num_hrrq++;
5773 if (budget > 0 && num_hrrq >= budget)
5774 break;
5775 }
5776
5777 return num_hrrq;
5778}
5779
5780static int ipr_iopoll(struct irq_poll *iop, int budget)
5781{
5782 struct ipr_hrr_queue *hrrq;
5783 struct ipr_cmnd *ipr_cmd, *temp;
5784 unsigned long hrrq_flags;
5785 int completed_ops;
5786 LIST_HEAD(doneq);
5787
5788 hrrq = container_of(iop, struct ipr_hrr_queue, iopoll);
5789
5790 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5791 completed_ops = ipr_process_hrrq(hrrq, budget, &doneq);
5792
5793 if (completed_ops < budget)
5794 irq_poll_complete(iop);
5795 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5796
5797 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5798 list_del(&ipr_cmd->queue);
5799 del_timer(&ipr_cmd->timer);
5800 ipr_cmd->fast_done(ipr_cmd);
5801 }
5802
5803 return completed_ops;
5804}
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814static irqreturn_t ipr_isr(int irq, void *devp)
5815{
5816 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5817 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5818 unsigned long hrrq_flags = 0;
5819 u32 int_reg = 0;
5820 int num_hrrq = 0;
5821 int irq_none = 0;
5822 struct ipr_cmnd *ipr_cmd, *temp;
5823 irqreturn_t rc = IRQ_NONE;
5824 LIST_HEAD(doneq);
5825
5826 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5827
5828 if (!hrrq->allow_interrupts) {
5829 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5830 return IRQ_NONE;
5831 }
5832
5833 while (1) {
5834 if (ipr_process_hrrq(hrrq, -1, &doneq)) {
5835 rc = IRQ_HANDLED;
5836
5837 if (!ioa_cfg->clear_isr)
5838 break;
5839
5840
5841 num_hrrq = 0;
5842 do {
5843 writel(IPR_PCII_HRRQ_UPDATED,
5844 ioa_cfg->regs.clr_interrupt_reg32);
5845 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5846 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5847 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5848
5849 } else if (rc == IRQ_NONE && irq_none == 0) {
5850 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5851 irq_none++;
5852 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5853 int_reg & IPR_PCII_HRRQ_UPDATED) {
5854 ipr_isr_eh(ioa_cfg,
5855 "Error clearing HRRQ: ", num_hrrq);
5856 rc = IRQ_HANDLED;
5857 break;
5858 } else
5859 break;
5860 }
5861
5862 if (unlikely(rc == IRQ_NONE))
5863 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5864
5865 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5866 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5867 list_del(&ipr_cmd->queue);
5868 del_timer(&ipr_cmd->timer);
5869 ipr_cmd->fast_done(ipr_cmd);
5870 }
5871 return rc;
5872}
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882static irqreturn_t ipr_isr_mhrrq(int irq, void *devp)
5883{
5884 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5885 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5886 unsigned long hrrq_flags = 0;
5887 struct ipr_cmnd *ipr_cmd, *temp;
5888 irqreturn_t rc = IRQ_NONE;
5889 LIST_HEAD(doneq);
5890
5891 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5892
5893
5894 if (!hrrq->allow_interrupts) {
5895 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5896 return IRQ_NONE;
5897 }
5898
5899 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
5900 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5901 hrrq->toggle_bit) {
5902 irq_poll_sched(&hrrq->iopoll);
5903 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5904 return IRQ_HANDLED;
5905 }
5906 } else {
5907 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5908 hrrq->toggle_bit)
5909
5910 if (ipr_process_hrrq(hrrq, -1, &doneq))
5911 rc = IRQ_HANDLED;
5912 }
5913
5914 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5915
5916 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5917 list_del(&ipr_cmd->queue);
5918 del_timer(&ipr_cmd->timer);
5919 ipr_cmd->fast_done(ipr_cmd);
5920 }
5921 return rc;
5922}
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5933 struct ipr_cmnd *ipr_cmd)
5934{
5935 int i, nseg;
5936 struct scatterlist *sg;
5937 u32 length;
5938 u32 ioadl_flags = 0;
5939 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5940 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5941 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5942
5943 length = scsi_bufflen(scsi_cmd);
5944 if (!length)
5945 return 0;
5946
5947 nseg = scsi_dma_map(scsi_cmd);
5948 if (nseg < 0) {
5949 if (printk_ratelimit())
5950 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
5951 return -1;
5952 }
5953
5954 ipr_cmd->dma_use_sg = nseg;
5955
5956 ioarcb->data_transfer_length = cpu_to_be32(length);
5957 ioarcb->ioadl_len =
5958 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5959
5960 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5961 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5962 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5963 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5964 ioadl_flags = IPR_IOADL_FLAGS_READ;
5965
5966 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5967 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5968 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5969 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5970 }
5971
5972 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5973 return 0;
5974}
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5985 struct ipr_cmnd *ipr_cmd)
5986{
5987 int i, nseg;
5988 struct scatterlist *sg;
5989 u32 length;
5990 u32 ioadl_flags = 0;
5991 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5992 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5993 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5994
5995 length = scsi_bufflen(scsi_cmd);
5996 if (!length)
5997 return 0;
5998
5999 nseg = scsi_dma_map(scsi_cmd);
6000 if (nseg < 0) {
6001 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
6002 return -1;
6003 }
6004
6005 ipr_cmd->dma_use_sg = nseg;
6006
6007 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
6008 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6009 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6010 ioarcb->data_transfer_length = cpu_to_be32(length);
6011 ioarcb->ioadl_len =
6012 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6013 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
6014 ioadl_flags = IPR_IOADL_FLAGS_READ;
6015 ioarcb->read_data_transfer_length = cpu_to_be32(length);
6016 ioarcb->read_ioadl_len =
6017 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6018 }
6019
6020 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
6021 ioadl = ioarcb->u.add_data.u.ioadl;
6022 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
6023 offsetof(struct ipr_ioarcb, u.add_data));
6024 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
6025 }
6026
6027 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
6028 ioadl[i].flags_and_data_len =
6029 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6030 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
6031 }
6032
6033 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6034 return 0;
6035}
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047static void __ipr_erp_done(struct ipr_cmnd *ipr_cmd)
6048{
6049 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6050 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6051 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6052
6053 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
6054 scsi_cmd->result |= (DID_ERROR << 16);
6055 scmd_printk(KERN_ERR, scsi_cmd,
6056 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
6057 } else {
6058 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
6059 SCSI_SENSE_BUFFERSIZE);
6060 }
6061
6062 if (res) {
6063 if (!ipr_is_naca_model(res))
6064 res->needs_sync_complete = 1;
6065 res->in_erp = 0;
6066 }
6067 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6068 scsi_cmd->scsi_done(scsi_cmd);
6069 if (ipr_cmd->eh_comp)
6070 complete(ipr_cmd->eh_comp);
6071 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6072}
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
6085{
6086 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
6087 unsigned long hrrq_flags;
6088
6089 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
6090 __ipr_erp_done(ipr_cmd);
6091 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
6092}
6093
6094
6095
6096
6097
6098
6099
6100
6101static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
6102{
6103 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6104 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6105 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6106
6107 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
6108 ioarcb->data_transfer_length = 0;
6109 ioarcb->read_data_transfer_length = 0;
6110 ioarcb->ioadl_len = 0;
6111 ioarcb->read_ioadl_len = 0;
6112 ioasa->hdr.ioasc = 0;
6113 ioasa->hdr.residual_data_len = 0;
6114
6115 if (ipr_cmd->ioa_cfg->sis64)
6116 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6117 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
6118 else {
6119 ioarcb->write_ioadl_addr =
6120 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
6121 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
6122 }
6123}
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135static void __ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
6136{
6137 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
6138 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6139
6140 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
6141 __ipr_erp_done(ipr_cmd);
6142 return;
6143 }
6144
6145 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
6146
6147 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
6148 cmd_pkt->cdb[0] = REQUEST_SENSE;
6149 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
6150 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
6151 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6152 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
6153
6154 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
6155 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
6156
6157 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
6158 IPR_REQUEST_SENSE_TIMEOUT * 2);
6159}
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
6172{
6173 struct ipr_hrr_queue *hrrq = ipr_cmd->hrrq;
6174 unsigned long hrrq_flags;
6175
6176 spin_lock_irqsave(&hrrq->_lock, hrrq_flags);
6177 __ipr_erp_request_sense(ipr_cmd);
6178 spin_unlock_irqrestore(&hrrq->_lock, hrrq_flags);
6179}
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
6194{
6195 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6196 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6197 struct ipr_cmd_pkt *cmd_pkt;
6198
6199 res->in_erp = 1;
6200
6201 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
6202
6203 if (!scsi_cmd->device->simple_tags) {
6204 __ipr_erp_request_sense(ipr_cmd);
6205 return;
6206 }
6207
6208 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
6209 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
6210 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
6211
6212 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
6213 IPR_CANCEL_ALL_TIMEOUT);
6214}
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
6230 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
6231{
6232 int i;
6233 u16 data_len;
6234 u32 ioasc, fd_ioasc;
6235 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6236 __be32 *ioasa_data = (__be32 *)ioasa;
6237 int error_index;
6238
6239 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
6240 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
6241
6242 if (0 == ioasc)
6243 return;
6244
6245 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
6246 return;
6247
6248 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
6249 error_index = ipr_get_error(fd_ioasc);
6250 else
6251 error_index = ipr_get_error(ioasc);
6252
6253 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
6254
6255 if (ioasa->hdr.ilid != 0)
6256 return;
6257
6258 if (!ipr_is_gscsi(res))
6259 return;
6260
6261 if (ipr_error_table[error_index].log_ioasa == 0)
6262 return;
6263 }
6264
6265 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
6266
6267 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
6268 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
6269 data_len = sizeof(struct ipr_ioasa64);
6270 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
6271 data_len = sizeof(struct ipr_ioasa);
6272
6273 ipr_err("IOASA Dump:\n");
6274
6275 for (i = 0; i < data_len / 4; i += 4) {
6276 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
6277 be32_to_cpu(ioasa_data[i]),
6278 be32_to_cpu(ioasa_data[i+1]),
6279 be32_to_cpu(ioasa_data[i+2]),
6280 be32_to_cpu(ioasa_data[i+3]));
6281 }
6282}
6283
6284
6285
6286
6287
6288
6289
6290
6291static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
6292{
6293 u32 failing_lba;
6294 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
6295 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
6296 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6297 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
6298
6299 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
6300
6301 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
6302 return;
6303
6304 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
6305
6306 if (ipr_is_vset_device(res) &&
6307 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
6308 ioasa->u.vset.failing_lba_hi != 0) {
6309 sense_buf[0] = 0x72;
6310 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
6311 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
6312 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
6313
6314 sense_buf[7] = 12;
6315 sense_buf[8] = 0;
6316 sense_buf[9] = 0x0A;
6317 sense_buf[10] = 0x80;
6318
6319 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
6320
6321 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
6322 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
6323 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
6324 sense_buf[15] = failing_lba & 0x000000ff;
6325
6326 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6327
6328 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
6329 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
6330 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
6331 sense_buf[19] = failing_lba & 0x000000ff;
6332 } else {
6333 sense_buf[0] = 0x70;
6334 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
6335 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
6336 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
6337
6338
6339 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
6340 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
6341 sense_buf[7] = 10;
6342
6343
6344 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
6345 sense_buf[15] = 0xC0;
6346 else
6347 sense_buf[15] = 0x80;
6348
6349 sense_buf[16] =
6350 ((IPR_FIELD_POINTER_MASK &
6351 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
6352 sense_buf[17] =
6353 (IPR_FIELD_POINTER_MASK &
6354 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
6355 } else {
6356 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
6357 if (ipr_is_vset_device(res))
6358 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6359 else
6360 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
6361
6362 sense_buf[0] |= 0x80;
6363 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
6364 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
6365 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
6366 sense_buf[6] = failing_lba & 0x000000ff;
6367 }
6368
6369 sense_buf[7] = 6;
6370 }
6371 }
6372}
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
6385{
6386 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6387 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
6388
6389 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
6390 return 0;
6391
6392 if (ipr_cmd->ioa_cfg->sis64)
6393 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
6394 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
6395 SCSI_SENSE_BUFFERSIZE));
6396 else
6397 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
6398 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
6399 SCSI_SENSE_BUFFERSIZE));
6400 return 1;
6401}
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
6415 struct ipr_cmnd *ipr_cmd)
6416{
6417 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6418 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6419 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6420 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
6421
6422 if (!res) {
6423 __ipr_scsi_eh_done(ipr_cmd);
6424 return;
6425 }
6426
6427 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
6428 ipr_gen_sense(ipr_cmd);
6429
6430 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6431
6432 switch (masked_ioasc) {
6433 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
6434 if (ipr_is_naca_model(res))
6435 scsi_cmd->result |= (DID_ABORT << 16);
6436 else
6437 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6438 break;
6439 case IPR_IOASC_IR_RESOURCE_HANDLE:
6440 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
6441 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6442 break;
6443 case IPR_IOASC_HW_SEL_TIMEOUT:
6444 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6445 if (!ipr_is_naca_model(res))
6446 res->needs_sync_complete = 1;
6447 break;
6448 case IPR_IOASC_SYNC_REQUIRED:
6449 if (!res->in_erp)
6450 res->needs_sync_complete = 1;
6451 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6452 break;
6453 case IPR_IOASC_MED_DO_NOT_REALLOC:
6454 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
6455
6456
6457
6458
6459 if (scsi_cmd->result != SAM_STAT_CHECK_CONDITION)
6460 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
6461 break;
6462 case IPR_IOASC_BUS_WAS_RESET:
6463 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
6464
6465
6466
6467
6468 if (!res->resetting_device)
6469 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
6470 scsi_cmd->result |= (DID_ERROR << 16);
6471 if (!ipr_is_naca_model(res))
6472 res->needs_sync_complete = 1;
6473 break;
6474 case IPR_IOASC_HW_DEV_BUS_STATUS:
6475 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
6476 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
6477 if (!ipr_get_autosense(ipr_cmd)) {
6478 if (!ipr_is_naca_model(res)) {
6479 ipr_erp_cancel_all(ipr_cmd);
6480 return;
6481 }
6482 }
6483 }
6484 if (!ipr_is_naca_model(res))
6485 res->needs_sync_complete = 1;
6486 break;
6487 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
6488 break;
6489 case IPR_IOASC_IR_NON_OPTIMIZED:
6490 if (res->raw_mode) {
6491 res->raw_mode = 0;
6492 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6493 } else
6494 scsi_cmd->result |= (DID_ERROR << 16);
6495 break;
6496 default:
6497 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6498 scsi_cmd->result |= (DID_ERROR << 16);
6499 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
6500 res->needs_sync_complete = 1;
6501 break;
6502 }
6503
6504 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6505 scsi_cmd->scsi_done(scsi_cmd);
6506 if (ipr_cmd->eh_comp)
6507 complete(ipr_cmd->eh_comp);
6508 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6509}
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
6522{
6523 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6524 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6525 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6526 unsigned long lock_flags;
6527
6528 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
6529
6530 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
6531 scsi_dma_unmap(scsi_cmd);
6532
6533 spin_lock_irqsave(ipr_cmd->hrrq->lock, lock_flags);
6534 scsi_cmd->scsi_done(scsi_cmd);
6535 if (ipr_cmd->eh_comp)
6536 complete(ipr_cmd->eh_comp);
6537 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6538 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, lock_flags);
6539 } else {
6540 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6541 spin_lock(&ipr_cmd->hrrq->_lock);
6542 ipr_erp_start(ioa_cfg, ipr_cmd);
6543 spin_unlock(&ipr_cmd->hrrq->_lock);
6544 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6545 }
6546}
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560static int ipr_queuecommand(struct Scsi_Host *shost,
6561 struct scsi_cmnd *scsi_cmd)
6562{
6563 struct ipr_ioa_cfg *ioa_cfg;
6564 struct ipr_resource_entry *res;
6565 struct ipr_ioarcb *ioarcb;
6566 struct ipr_cmnd *ipr_cmd;
6567 unsigned long hrrq_flags, lock_flags;
6568 int rc;
6569 struct ipr_hrr_queue *hrrq;
6570 int hrrq_id;
6571
6572 ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
6573
6574 scsi_cmd->result = (DID_OK << 16);
6575 res = scsi_cmd->device->hostdata;
6576
6577 if (ipr_is_gata(res) && res->sata_port) {
6578 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6579 rc = ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
6580 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6581 return rc;
6582 }
6583
6584 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6585 hrrq = &ioa_cfg->hrrq[hrrq_id];
6586
6587 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6588
6589
6590
6591
6592
6593 if (unlikely(!hrrq->allow_cmds && !hrrq->ioa_is_dead && !hrrq->removing_ioa)) {
6594 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6595 return SCSI_MLQUEUE_HOST_BUSY;
6596 }
6597
6598
6599
6600
6601
6602 if (unlikely(hrrq->ioa_is_dead || hrrq->removing_ioa || !res)) {
6603 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6604 goto err_nodev;
6605 }
6606
6607 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6608 if (ipr_cmd == NULL) {
6609 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6610 return SCSI_MLQUEUE_HOST_BUSY;
6611 }
6612 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6613
6614 ipr_init_ipr_cmnd(ipr_cmd, ipr_scsi_done);
6615 ioarcb = &ipr_cmd->ioarcb;
6616
6617 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
6618 ipr_cmd->scsi_cmd = scsi_cmd;
6619 ipr_cmd->done = ipr_scsi_eh_done;
6620
6621 if (ipr_is_gscsi(res)) {
6622 if (scsi_cmd->underflow == 0)
6623 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6624
6625 if (res->reset_occurred) {
6626 res->reset_occurred = 0;
6627 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
6628 }
6629 }
6630
6631 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
6632 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6633
6634 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
6635 if (scsi_cmd->flags & SCMD_TAGGED)
6636 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_SIMPLE_TASK;
6637 else
6638 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_UNTAGGED_TASK;
6639 }
6640
6641 if (scsi_cmd->cmnd[0] >= 0xC0 &&
6642 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) {
6643 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6644 }
6645 if (res->raw_mode && ipr_is_af_dasd_device(res)) {
6646 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_PIPE;
6647
6648 if (scsi_cmd->underflow == 0)
6649 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6650 }
6651
6652 if (ioa_cfg->sis64)
6653 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
6654 else
6655 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
6656
6657 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6658 if (unlikely(rc || (!hrrq->allow_cmds && !hrrq->ioa_is_dead))) {
6659 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6660 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6661 if (!rc)
6662 scsi_dma_unmap(scsi_cmd);
6663 return SCSI_MLQUEUE_HOST_BUSY;
6664 }
6665
6666 if (unlikely(hrrq->ioa_is_dead)) {
6667 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6668 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6669 scsi_dma_unmap(scsi_cmd);
6670 goto err_nodev;
6671 }
6672
6673 ioarcb->res_handle = res->res_handle;
6674 if (res->needs_sync_complete) {
6675 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
6676 res->needs_sync_complete = 0;
6677 }
6678 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_pending_q);
6679 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6680 ipr_send_command(ipr_cmd);
6681 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6682 return 0;
6683
6684err_nodev:
6685 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6686 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
6687 scsi_cmd->result = (DID_NO_CONNECT << 16);
6688 scsi_cmd->scsi_done(scsi_cmd);
6689 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6690 return 0;
6691}
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702static int ipr_ioctl(struct scsi_device *sdev, unsigned int cmd,
6703 void __user *arg)
6704{
6705 struct ipr_resource_entry *res;
6706
6707 res = (struct ipr_resource_entry *)sdev->hostdata;
6708 if (res && ipr_is_gata(res)) {
6709 if (cmd == HDIO_GET_IDENTITY)
6710 return -ENOTTY;
6711 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
6712 }
6713
6714 return -EINVAL;
6715}
6716
6717
6718
6719
6720
6721
6722
6723
6724static const char *ipr_ioa_info(struct Scsi_Host *host)
6725{
6726 static char buffer[512];
6727 struct ipr_ioa_cfg *ioa_cfg;
6728 unsigned long lock_flags = 0;
6729
6730 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
6731
6732 spin_lock_irqsave(host->host_lock, lock_flags);
6733 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
6734 spin_unlock_irqrestore(host->host_lock, lock_flags);
6735
6736 return buffer;
6737}
6738
6739static struct scsi_host_template driver_template = {
6740 .module = THIS_MODULE,
6741 .name = "IPR",
6742 .info = ipr_ioa_info,
6743 .ioctl = ipr_ioctl,
6744#ifdef CONFIG_COMPAT
6745 .compat_ioctl = ipr_ioctl,
6746#endif
6747 .queuecommand = ipr_queuecommand,
6748 .dma_need_drain = ata_scsi_dma_need_drain,
6749 .eh_abort_handler = ipr_eh_abort,
6750 .eh_device_reset_handler = ipr_eh_dev_reset,
6751 .eh_host_reset_handler = ipr_eh_host_reset,
6752 .slave_alloc = ipr_slave_alloc,
6753 .slave_configure = ipr_slave_configure,
6754 .slave_destroy = ipr_slave_destroy,
6755 .scan_finished = ipr_scan_finished,
6756 .target_alloc = ipr_target_alloc,
6757 .target_destroy = ipr_target_destroy,
6758 .change_queue_depth = ipr_change_queue_depth,
6759 .bios_param = ipr_biosparam,
6760 .can_queue = IPR_MAX_COMMANDS,
6761 .this_id = -1,
6762 .sg_tablesize = IPR_MAX_SGLIST,
6763 .max_sectors = IPR_IOA_MAX_SECTORS,
6764 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
6765 .shost_attrs = ipr_ioa_attrs,
6766 .sdev_attrs = ipr_dev_attrs,
6767 .proc_name = IPR_NAME,
6768};
6769
6770
6771
6772
6773
6774
6775static void ipr_ata_phy_reset(struct ata_port *ap)
6776{
6777 unsigned long flags;
6778 struct ipr_sata_port *sata_port = ap->private_data;
6779 struct ipr_resource_entry *res = sata_port->res;
6780 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6781 int rc;
6782
6783 ENTER;
6784 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6785 while (ioa_cfg->in_reset_reload) {
6786 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6787 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6788 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6789 }
6790
6791 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6792 goto out_unlock;
6793
6794 rc = ipr_device_reset(ioa_cfg, res);
6795
6796 if (rc) {
6797 ap->link.device[0].class = ATA_DEV_NONE;
6798 goto out_unlock;
6799 }
6800
6801 ap->link.device[0].class = res->ata_class;
6802 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
6803 ap->link.device[0].class = ATA_DEV_NONE;
6804
6805out_unlock:
6806 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6807 LEAVE;
6808}
6809
6810
6811
6812
6813
6814
6815
6816
6817static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
6818{
6819 struct ipr_sata_port *sata_port = qc->ap->private_data;
6820 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6821 struct ipr_cmnd *ipr_cmd;
6822 struct ipr_hrr_queue *hrrq;
6823 unsigned long flags;
6824
6825 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6826 while (ioa_cfg->in_reset_reload) {
6827 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6828 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6829 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6830 }
6831
6832 for_each_hrrq(hrrq, ioa_cfg) {
6833 spin_lock(&hrrq->_lock);
6834 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
6835 if (ipr_cmd->qc == qc) {
6836 ipr_device_reset(ioa_cfg, sata_port->res);
6837 break;
6838 }
6839 }
6840 spin_unlock(&hrrq->_lock);
6841 }
6842 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6843}
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6854 struct ata_taskfile *tf)
6855{
6856 regs->feature = tf->feature;
6857 regs->nsect = tf->nsect;
6858 regs->lbal = tf->lbal;
6859 regs->lbam = tf->lbam;
6860 regs->lbah = tf->lbah;
6861 regs->device = tf->device;
6862 regs->command = tf->command;
6863 regs->hob_feature = tf->hob_feature;
6864 regs->hob_nsect = tf->hob_nsect;
6865 regs->hob_lbal = tf->hob_lbal;
6866 regs->hob_lbam = tf->hob_lbam;
6867 regs->hob_lbah = tf->hob_lbah;
6868 regs->ctl = tf->ctl;
6869}
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6882{
6883 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6884 struct ata_queued_cmd *qc = ipr_cmd->qc;
6885 struct ipr_sata_port *sata_port = qc->ap->private_data;
6886 struct ipr_resource_entry *res = sata_port->res;
6887 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6888
6889 spin_lock(&ipr_cmd->hrrq->_lock);
6890 if (ipr_cmd->ioa_cfg->sis64)
6891 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6892 sizeof(struct ipr_ioasa_gata));
6893 else
6894 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6895 sizeof(struct ipr_ioasa_gata));
6896 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6897
6898 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6899 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6900
6901 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6902 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6903 else
6904 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6905 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6906 spin_unlock(&ipr_cmd->hrrq->_lock);
6907 ata_qc_complete(qc);
6908}
6909
6910
6911
6912
6913
6914
6915
6916static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6917 struct ata_queued_cmd *qc)
6918{
6919 u32 ioadl_flags = 0;
6920 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6921 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ata_ioadl.ioadl64;
6922 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6923 int len = qc->nbytes;
6924 struct scatterlist *sg;
6925 unsigned int si;
6926 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6927
6928 if (len == 0)
6929 return;
6930
6931 if (qc->dma_dir == DMA_TO_DEVICE) {
6932 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6933 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6934 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6935 ioadl_flags = IPR_IOADL_FLAGS_READ;
6936
6937 ioarcb->data_transfer_length = cpu_to_be32(len);
6938 ioarcb->ioadl_len =
6939 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6940 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6941 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl.ioadl64));
6942
6943 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6944 ioadl64->flags = cpu_to_be32(ioadl_flags);
6945 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6946 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6947
6948 last_ioadl64 = ioadl64;
6949 ioadl64++;
6950 }
6951
6952 if (likely(last_ioadl64))
6953 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6954}
6955
6956
6957
6958
6959
6960
6961
6962static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6963 struct ata_queued_cmd *qc)
6964{
6965 u32 ioadl_flags = 0;
6966 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6967 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6968 struct ipr_ioadl_desc *last_ioadl = NULL;
6969 int len = qc->nbytes;
6970 struct scatterlist *sg;
6971 unsigned int si;
6972
6973 if (len == 0)
6974 return;
6975
6976 if (qc->dma_dir == DMA_TO_DEVICE) {
6977 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6978 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6979 ioarcb->data_transfer_length = cpu_to_be32(len);
6980 ioarcb->ioadl_len =
6981 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6982 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6983 ioadl_flags = IPR_IOADL_FLAGS_READ;
6984 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6985 ioarcb->read_ioadl_len =
6986 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6987 }
6988
6989 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6990 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6991 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6992
6993 last_ioadl = ioadl;
6994 ioadl++;
6995 }
6996
6997 if (likely(last_ioadl))
6998 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6999}
7000
7001
7002
7003
7004
7005
7006
7007
7008static int ipr_qc_defer(struct ata_queued_cmd *qc)
7009{
7010 struct ata_port *ap = qc->ap;
7011 struct ipr_sata_port *sata_port = ap->private_data;
7012 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
7013 struct ipr_cmnd *ipr_cmd;
7014 struct ipr_hrr_queue *hrrq;
7015 int hrrq_id;
7016
7017 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
7018 hrrq = &ioa_cfg->hrrq[hrrq_id];
7019
7020 qc->lldd_task = NULL;
7021 spin_lock(&hrrq->_lock);
7022 if (unlikely(hrrq->ioa_is_dead)) {
7023 spin_unlock(&hrrq->_lock);
7024 return 0;
7025 }
7026
7027 if (unlikely(!hrrq->allow_cmds)) {
7028 spin_unlock(&hrrq->_lock);
7029 return ATA_DEFER_LINK;
7030 }
7031
7032 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
7033 if (ipr_cmd == NULL) {
7034 spin_unlock(&hrrq->_lock);
7035 return ATA_DEFER_LINK;
7036 }
7037
7038 qc->lldd_task = ipr_cmd;
7039 spin_unlock(&hrrq->_lock);
7040 return 0;
7041}
7042
7043
7044
7045
7046
7047
7048
7049
7050static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
7051{
7052 struct ata_port *ap = qc->ap;
7053 struct ipr_sata_port *sata_port = ap->private_data;
7054 struct ipr_resource_entry *res = sata_port->res;
7055 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
7056 struct ipr_cmnd *ipr_cmd;
7057 struct ipr_ioarcb *ioarcb;
7058 struct ipr_ioarcb_ata_regs *regs;
7059
7060 if (qc->lldd_task == NULL)
7061 ipr_qc_defer(qc);
7062
7063 ipr_cmd = qc->lldd_task;
7064 if (ipr_cmd == NULL)
7065 return AC_ERR_SYSTEM;
7066
7067 qc->lldd_task = NULL;
7068 spin_lock(&ipr_cmd->hrrq->_lock);
7069 if (unlikely(!ipr_cmd->hrrq->allow_cmds ||
7070 ipr_cmd->hrrq->ioa_is_dead)) {
7071 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7072 spin_unlock(&ipr_cmd->hrrq->_lock);
7073 return AC_ERR_SYSTEM;
7074 }
7075
7076 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
7077 ioarcb = &ipr_cmd->ioarcb;
7078
7079 if (ioa_cfg->sis64) {
7080 regs = &ipr_cmd->i.ata_ioadl.regs;
7081 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
7082 } else
7083 regs = &ioarcb->u.add_data.u.regs;
7084
7085 memset(regs, 0, sizeof(*regs));
7086 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
7087
7088 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7089 ipr_cmd->qc = qc;
7090 ipr_cmd->done = ipr_sata_done;
7091 ipr_cmd->ioarcb.res_handle = res->res_handle;
7092 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
7093 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
7094 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
7095 ipr_cmd->dma_use_sg = qc->n_elem;
7096
7097 if (ioa_cfg->sis64)
7098 ipr_build_ata_ioadl64(ipr_cmd, qc);
7099 else
7100 ipr_build_ata_ioadl(ipr_cmd, qc);
7101
7102 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
7103 ipr_copy_sata_tf(regs, &qc->tf);
7104 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
7105 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
7106
7107 switch (qc->tf.protocol) {
7108 case ATA_PROT_NODATA:
7109 case ATA_PROT_PIO:
7110 break;
7111
7112 case ATA_PROT_DMA:
7113 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
7114 break;
7115
7116 case ATAPI_PROT_PIO:
7117 case ATAPI_PROT_NODATA:
7118 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
7119 break;
7120
7121 case ATAPI_PROT_DMA:
7122 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
7123 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
7124 break;
7125
7126 default:
7127 WARN_ON(1);
7128 spin_unlock(&ipr_cmd->hrrq->_lock);
7129 return AC_ERR_INVALID;
7130 }
7131
7132 ipr_send_command(ipr_cmd);
7133 spin_unlock(&ipr_cmd->hrrq->_lock);
7134
7135 return 0;
7136}
7137
7138
7139
7140
7141
7142
7143
7144
7145static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
7146{
7147 struct ipr_sata_port *sata_port = qc->ap->private_data;
7148 struct ipr_ioasa_gata *g = &sata_port->ioasa;
7149 struct ata_taskfile *tf = &qc->result_tf;
7150
7151 tf->feature = g->error;
7152 tf->nsect = g->nsect;
7153 tf->lbal = g->lbal;
7154 tf->lbam = g->lbam;
7155 tf->lbah = g->lbah;
7156 tf->device = g->device;
7157 tf->command = g->status;
7158 tf->hob_nsect = g->hob_nsect;
7159 tf->hob_lbal = g->hob_lbal;
7160 tf->hob_lbam = g->hob_lbam;
7161 tf->hob_lbah = g->hob_lbah;
7162
7163 return true;
7164}
7165
7166static struct ata_port_operations ipr_sata_ops = {
7167 .phy_reset = ipr_ata_phy_reset,
7168 .hardreset = ipr_sata_reset,
7169 .post_internal_cmd = ipr_ata_post_internal,
7170 .qc_prep = ata_noop_qc_prep,
7171 .qc_defer = ipr_qc_defer,
7172 .qc_issue = ipr_qc_issue,
7173 .qc_fill_rtf = ipr_qc_fill_rtf,
7174 .port_start = ata_sas_port_start,
7175 .port_stop = ata_sas_port_stop
7176};
7177
7178static struct ata_port_info sata_port_info = {
7179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
7180 ATA_FLAG_SAS_HOST,
7181 .pio_mask = ATA_PIO4_ONLY,
7182 .mwdma_mask = ATA_MWDMA2,
7183 .udma_mask = ATA_UDMA6,
7184 .port_ops = &ipr_sata_ops
7185};
7186
7187#ifdef CONFIG_PPC_PSERIES
7188static const u16 ipr_blocked_processors[] = {
7189 PVR_NORTHSTAR,
7190 PVR_PULSAR,
7191 PVR_POWER4,
7192 PVR_ICESTAR,
7193 PVR_SSTAR,
7194 PVR_POWER4p,
7195 PVR_630,
7196 PVR_630p
7197};
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
7211{
7212 int i;
7213
7214 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
7215 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++) {
7216 if (pvr_version_is(ipr_blocked_processors[i]))
7217 return 1;
7218 }
7219 }
7220 return 0;
7221}
7222#else
7223#define ipr_invalid_adapter(ioa_cfg) 0
7224#endif
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
7237{
7238 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7239 int i;
7240
7241 ENTER;
7242 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
7243 ipr_trace;
7244 ioa_cfg->scsi_unblock = 1;
7245 schedule_work(&ioa_cfg->work_q);
7246 }
7247
7248 ioa_cfg->in_reset_reload = 0;
7249 ioa_cfg->reset_retries = 0;
7250 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
7251 spin_lock(&ioa_cfg->hrrq[i]._lock);
7252 ioa_cfg->hrrq[i].ioa_is_dead = 1;
7253 spin_unlock(&ioa_cfg->hrrq[i]._lock);
7254 }
7255 wmb();
7256
7257 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7258 wake_up_all(&ioa_cfg->reset_wait_q);
7259 LEAVE;
7260
7261 return IPR_RC_JOB_RETURN;
7262}
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
7276{
7277 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7278 struct ipr_resource_entry *res;
7279 int j;
7280
7281 ENTER;
7282 ioa_cfg->in_reset_reload = 0;
7283 for (j = 0; j < ioa_cfg->hrrq_num; j++) {
7284 spin_lock(&ioa_cfg->hrrq[j]._lock);
7285 ioa_cfg->hrrq[j].allow_cmds = 1;
7286 spin_unlock(&ioa_cfg->hrrq[j]._lock);
7287 }
7288 wmb();
7289 ioa_cfg->reset_cmd = NULL;
7290 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
7291
7292 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
7293 if (res->add_to_ml || res->del_from_ml) {
7294 ipr_trace;
7295 break;
7296 }
7297 }
7298 schedule_work(&ioa_cfg->work_q);
7299
7300 for (j = 0; j < IPR_NUM_HCAMS; j++) {
7301 list_del_init(&ioa_cfg->hostrcb[j]->queue);
7302 if (j < IPR_NUM_LOG_HCAMS)
7303 ipr_send_hcam(ioa_cfg,
7304 IPR_HCAM_CDB_OP_CODE_LOG_DATA,
7305 ioa_cfg->hostrcb[j]);
7306 else
7307 ipr_send_hcam(ioa_cfg,
7308 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
7309 ioa_cfg->hostrcb[j]);
7310 }
7311
7312 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
7313 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
7314
7315 ioa_cfg->reset_retries = 0;
7316 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7317 wake_up_all(&ioa_cfg->reset_wait_q);
7318
7319 ioa_cfg->scsi_unblock = 1;
7320 schedule_work(&ioa_cfg->work_q);
7321 LEAVE;
7322 return IPR_RC_JOB_RETURN;
7323}
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
7334 struct ipr_std_inq_vpids *vpids)
7335{
7336 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
7337 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
7338 supported_dev->num_records = 1;
7339 supported_dev->data_length =
7340 cpu_to_be16(sizeof(struct ipr_supported_device));
7341 supported_dev->reserved = 0;
7342}
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
7354{
7355 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7356 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
7357 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7358 struct ipr_resource_entry *res = ipr_cmd->u.res;
7359
7360 ipr_cmd->job_step = ipr_ioa_reset_done;
7361
7362 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
7363 if (!ipr_is_scsi_disk(res))
7364 continue;
7365
7366 ipr_cmd->u.res = res;
7367 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
7368
7369 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7370 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7371 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7372
7373 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
7374 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
7375 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
7376 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
7377
7378 ipr_init_ioadl(ipr_cmd,
7379 ioa_cfg->vpd_cbs_dma +
7380 offsetof(struct ipr_misc_cbs, supp_dev),
7381 sizeof(struct ipr_supported_device),
7382 IPR_IOADL_FLAGS_WRITE_LAST);
7383
7384 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7385 IPR_SET_SUP_DEVICE_TIMEOUT);
7386
7387 if (!ioa_cfg->sis64)
7388 ipr_cmd->job_step = ipr_set_supported_devs;
7389 LEAVE;
7390 return IPR_RC_JOB_RETURN;
7391 }
7392
7393 LEAVE;
7394 return IPR_RC_JOB_CONTINUE;
7395}
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
7407 u32 page_code, u32 len)
7408{
7409 struct ipr_mode_page_hdr *mode_hdr;
7410 u32 page_length;
7411 u32 length;
7412
7413 if (!mode_pages || (mode_pages->hdr.length == 0))
7414 return NULL;
7415
7416 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
7417 mode_hdr = (struct ipr_mode_page_hdr *)
7418 (mode_pages->data + mode_pages->hdr.block_desc_len);
7419
7420 while (length) {
7421 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
7422 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
7423 return mode_hdr;
7424 break;
7425 } else {
7426 page_length = (sizeof(struct ipr_mode_page_hdr) +
7427 mode_hdr->page_length);
7428 length -= page_length;
7429 mode_hdr = (struct ipr_mode_page_hdr *)
7430 ((unsigned long)mode_hdr + page_length);
7431 }
7432 }
7433 return NULL;
7434}
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
7447 struct ipr_mode_pages *mode_pages)
7448{
7449 int i;
7450 int entry_length;
7451 struct ipr_dev_bus_entry *bus;
7452 struct ipr_mode_page28 *mode_page;
7453
7454 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7455 sizeof(struct ipr_mode_page28));
7456
7457 entry_length = mode_page->entry_length;
7458
7459 bus = mode_page->bus;
7460
7461 for (i = 0; i < mode_page->num_entries; i++) {
7462 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
7463 dev_err(&ioa_cfg->pdev->dev,
7464 "Term power is absent on scsi bus %d\n",
7465 bus->res_addr.bus);
7466 }
7467
7468 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
7469 }
7470}
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
7484{
7485 u32 max_xfer_rate;
7486 int i;
7487
7488 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
7489 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
7490 ioa_cfg->bus_attr[i].bus_width);
7491
7492 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
7493 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
7494 }
7495}
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
7508 struct ipr_mode_pages *mode_pages)
7509{
7510 int i, entry_length;
7511 struct ipr_dev_bus_entry *bus;
7512 struct ipr_bus_attributes *bus_attr;
7513 struct ipr_mode_page28 *mode_page;
7514
7515 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7516 sizeof(struct ipr_mode_page28));
7517
7518 entry_length = mode_page->entry_length;
7519
7520
7521 for (i = 0, bus = mode_page->bus;
7522 i < mode_page->num_entries;
7523 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
7524 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
7525 dev_err(&ioa_cfg->pdev->dev,
7526 "Invalid resource address reported: 0x%08X\n",
7527 IPR_GET_PHYS_LOC(bus->res_addr));
7528 continue;
7529 }
7530
7531 bus_attr = &ioa_cfg->bus_attr[i];
7532 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
7533 bus->bus_width = bus_attr->bus_width;
7534 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
7535 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
7536 if (bus_attr->qas_enabled)
7537 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
7538 else
7539 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
7540 }
7541}
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
7555 __be32 res_handle, u8 parm,
7556 dma_addr_t dma_addr, u8 xfer_len)
7557{
7558 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7559
7560 ioarcb->res_handle = res_handle;
7561 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7562 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7563 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
7564 ioarcb->cmd_pkt.cdb[1] = parm;
7565 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7566
7567 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
7568}
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
7581{
7582 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7583 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7584 int length;
7585
7586 ENTER;
7587 ipr_scsi_bus_speed_limit(ioa_cfg);
7588 ipr_check_term_power(ioa_cfg, mode_pages);
7589 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
7590 length = mode_pages->hdr.length + 1;
7591 mode_pages->hdr.length = 0;
7592
7593 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7594 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7595 length);
7596
7597 ipr_cmd->job_step = ipr_set_supported_devs;
7598 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7599 struct ipr_resource_entry, queue);
7600 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7601
7602 LEAVE;
7603 return IPR_RC_JOB_RETURN;
7604}
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
7618 __be32 res_handle,
7619 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
7620{
7621 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7622
7623 ioarcb->res_handle = res_handle;
7624 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
7625 ioarcb->cmd_pkt.cdb[2] = parm;
7626 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7627 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7628
7629 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7630}
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
7642{
7643 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7644 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7645
7646 dev_err(&ioa_cfg->pdev->dev,
7647 "0x%02X failed with IOASC: 0x%08X\n",
7648 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
7649
7650 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7651 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7652 return IPR_RC_JOB_RETURN;
7653}
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
7666{
7667 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7668 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7669
7670 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7671 ipr_cmd->job_step = ipr_set_supported_devs;
7672 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7673 struct ipr_resource_entry, queue);
7674 return IPR_RC_JOB_CONTINUE;
7675 }
7676
7677 return ipr_reset_cmd_failed(ipr_cmd);
7678}
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
7691{
7692 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7693
7694 ENTER;
7695 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7696 0x28, ioa_cfg->vpd_cbs_dma +
7697 offsetof(struct ipr_misc_cbs, mode_pages),
7698 sizeof(struct ipr_mode_pages));
7699
7700 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
7701 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
7702
7703 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7704
7705 LEAVE;
7706 return IPR_RC_JOB_RETURN;
7707}
7708
7709
7710
7711
7712
7713
7714
7715
7716
7717
7718static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
7719{
7720 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7721 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7722 struct ipr_mode_page24 *mode_page;
7723 int length;
7724
7725 ENTER;
7726 mode_page = ipr_get_mode_page(mode_pages, 0x24,
7727 sizeof(struct ipr_mode_page24));
7728
7729 if (mode_page)
7730 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
7731
7732 length = mode_pages->hdr.length + 1;
7733 mode_pages->hdr.length = 0;
7734
7735 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7736 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7737 length);
7738
7739 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7740 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7741
7742 LEAVE;
7743 return IPR_RC_JOB_RETURN;
7744}
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
7757{
7758 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7759
7760 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7761 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7762 return IPR_RC_JOB_CONTINUE;
7763 }
7764
7765 return ipr_reset_cmd_failed(ipr_cmd);
7766}
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776
7777
7778static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
7779{
7780 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7781
7782 ENTER;
7783 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7784 0x24, ioa_cfg->vpd_cbs_dma +
7785 offsetof(struct ipr_misc_cbs, mode_pages),
7786 sizeof(struct ipr_mode_pages));
7787
7788 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
7789 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
7790
7791 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7792
7793 LEAVE;
7794 return IPR_RC_JOB_RETURN;
7795}
7796
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808
7809static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
7810{
7811 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7812 struct ipr_resource_entry *res, *temp;
7813 struct ipr_config_table_entry_wrapper cfgtew;
7814 int entries, found, flag, i;
7815 LIST_HEAD(old_res);
7816
7817 ENTER;
7818 if (ioa_cfg->sis64)
7819 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
7820 else
7821 flag = ioa_cfg->u.cfg_table->hdr.flags;
7822
7823 if (flag & IPR_UCODE_DOWNLOAD_REQ)
7824 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
7825
7826 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
7827 list_move_tail(&res->queue, &old_res);
7828
7829 if (ioa_cfg->sis64)
7830 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
7831 else
7832 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
7833
7834 for (i = 0; i < entries; i++) {
7835 if (ioa_cfg->sis64)
7836 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
7837 else
7838 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
7839 found = 0;
7840
7841 list_for_each_entry_safe(res, temp, &old_res, queue) {
7842 if (ipr_is_same_device(res, &cfgtew)) {
7843 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7844 found = 1;
7845 break;
7846 }
7847 }
7848
7849 if (!found) {
7850 if (list_empty(&ioa_cfg->free_res_q)) {
7851 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
7852 break;
7853 }
7854
7855 found = 1;
7856 res = list_entry(ioa_cfg->free_res_q.next,
7857 struct ipr_resource_entry, queue);
7858 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7859 ipr_init_res_entry(res, &cfgtew);
7860 res->add_to_ml = 1;
7861 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
7862 res->sdev->allow_restart = 1;
7863
7864 if (found)
7865 ipr_update_res_entry(res, &cfgtew);
7866 }
7867
7868 list_for_each_entry_safe(res, temp, &old_res, queue) {
7869 if (res->sdev) {
7870 res->del_from_ml = 1;
7871 res->res_handle = IPR_INVALID_RES_HANDLE;
7872 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7873 }
7874 }
7875
7876 list_for_each_entry_safe(res, temp, &old_res, queue) {
7877 ipr_clear_res_target(res);
7878 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
7879 }
7880
7881 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7882 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
7883 else
7884 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7885
7886 LEAVE;
7887 return IPR_RC_JOB_CONTINUE;
7888}
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
7901{
7902 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7903 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7904 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
7905 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7906
7907 ENTER;
7908 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
7909 ioa_cfg->dual_raid = 1;
7910 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7911 ucode_vpd->major_release, ucode_vpd->card_type,
7912 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7913 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7914 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7915
7916 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7917 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7918 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7919 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7920
7921 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7922 IPR_IOADL_FLAGS_READ_LAST);
7923
7924 ipr_cmd->job_step = ipr_init_res_table;
7925
7926 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7927
7928 LEAVE;
7929 return IPR_RC_JOB_RETURN;
7930}
7931
7932static int ipr_ioa_service_action_failed(struct ipr_cmnd *ipr_cmd)
7933{
7934 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7935
7936 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT)
7937 return IPR_RC_JOB_CONTINUE;
7938
7939 return ipr_reset_cmd_failed(ipr_cmd);
7940}
7941
7942static void ipr_build_ioa_service_action(struct ipr_cmnd *ipr_cmd,
7943 __be32 res_handle, u8 sa_code)
7944{
7945 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7946
7947 ioarcb->res_handle = res_handle;
7948 ioarcb->cmd_pkt.cdb[0] = IPR_IOA_SERVICE_ACTION;
7949 ioarcb->cmd_pkt.cdb[1] = sa_code;
7950 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7951}
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961static int ipr_ioafp_set_caching_parameters(struct ipr_cmnd *ipr_cmd)
7962{
7963 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7964 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7965 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
7966
7967 ENTER;
7968
7969 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7970
7971 if (pageC4->cache_cap[0] & IPR_CAP_SYNC_CACHE) {
7972 ipr_build_ioa_service_action(ipr_cmd,
7973 cpu_to_be32(IPR_IOA_RES_HANDLE),
7974 IPR_IOA_SA_CHANGE_CACHE_PARAMS);
7975
7976 ioarcb->cmd_pkt.cdb[2] = 0x40;
7977
7978 ipr_cmd->job_step_failed = ipr_ioa_service_action_failed;
7979 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7980 IPR_SET_SUP_DEVICE_TIMEOUT);
7981
7982 LEAVE;
7983 return IPR_RC_JOB_RETURN;
7984 }
7985
7986 LEAVE;
7987 return IPR_RC_JOB_CONTINUE;
7988}
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002
8003static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
8004 dma_addr_t dma_addr, u8 xfer_len)
8005{
8006 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
8007
8008 ENTER;
8009 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
8010 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8011
8012 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
8013 ioarcb->cmd_pkt.cdb[1] = flags;
8014 ioarcb->cmd_pkt.cdb[2] = page;
8015 ioarcb->cmd_pkt.cdb[4] = xfer_len;
8016
8017 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
8018
8019 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
8020 LEAVE;
8021}
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
8034{
8035 int i;
8036
8037 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
8038 if (page0->page[i] == page)
8039 return 1;
8040
8041 return 0;
8042}
8043
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054static int ipr_ioafp_pageC4_inquiry(struct ipr_cmnd *ipr_cmd)
8055{
8056 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8057 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
8058 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
8059
8060 ENTER;
8061 ipr_cmd->job_step = ipr_ioafp_set_caching_parameters;
8062 memset(pageC4, 0, sizeof(*pageC4));
8063
8064 if (ipr_inquiry_page_supported(page0, 0xC4)) {
8065 ipr_ioafp_inquiry(ipr_cmd, 1, 0xC4,
8066 (ioa_cfg->vpd_cbs_dma
8067 + offsetof(struct ipr_misc_cbs,
8068 pageC4_data)),
8069 sizeof(struct ipr_inquiry_pageC4));
8070 return IPR_RC_JOB_RETURN;
8071 }
8072
8073 LEAVE;
8074 return IPR_RC_JOB_CONTINUE;
8075}
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
8088{
8089 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8090 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
8091 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
8092
8093 ENTER;
8094 ipr_cmd->job_step = ipr_ioafp_pageC4_inquiry;
8095 memset(cap, 0, sizeof(*cap));
8096
8097 if (ipr_inquiry_page_supported(page0, 0xD0)) {
8098 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
8099 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
8100 sizeof(struct ipr_inquiry_cap));
8101 return IPR_RC_JOB_RETURN;
8102 }
8103
8104 LEAVE;
8105 return IPR_RC_JOB_CONTINUE;
8106}
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117
8118static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
8119{
8120 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8121
8122 ENTER;
8123
8124 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
8125
8126 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
8127 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
8128 sizeof(struct ipr_inquiry_page3));
8129
8130 LEAVE;
8131 return IPR_RC_JOB_RETURN;
8132}
8133
8134
8135
8136
8137
8138
8139
8140
8141
8142
8143
8144static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
8145{
8146 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8147 char type[5];
8148
8149 ENTER;
8150
8151
8152 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
8153 type[4] = '\0';
8154 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
8155
8156 if (ipr_invalid_adapter(ioa_cfg)) {
8157 dev_err(&ioa_cfg->pdev->dev,
8158 "Adapter not supported in this hardware configuration.\n");
8159
8160 if (!ipr_testmode) {
8161 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
8162 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8163 list_add_tail(&ipr_cmd->queue,
8164 &ioa_cfg->hrrq->hrrq_free_q);
8165 return IPR_RC_JOB_RETURN;
8166 }
8167 }
8168
8169 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
8170
8171 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
8172 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
8173 sizeof(struct ipr_inquiry_page0));
8174
8175 LEAVE;
8176 return IPR_RC_JOB_RETURN;
8177}
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
8189{
8190 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8191
8192 ENTER;
8193 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
8194
8195 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
8196 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
8197 sizeof(struct ipr_ioa_vpd));
8198
8199 LEAVE;
8200 return IPR_RC_JOB_RETURN;
8201}
8202
8203
8204
8205
8206
8207
8208
8209
8210
8211
8212
8213static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
8214{
8215 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8216 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
8217 struct ipr_hrr_queue *hrrq;
8218
8219 ENTER;
8220 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
8221 if (ioa_cfg->identify_hrrq_index == 0)
8222 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
8223
8224 if (ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num) {
8225 hrrq = &ioa_cfg->hrrq[ioa_cfg->identify_hrrq_index];
8226
8227 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
8228 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8229
8230 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8231 if (ioa_cfg->sis64)
8232 ioarcb->cmd_pkt.cdb[1] = 0x1;
8233
8234 if (ioa_cfg->nvectors == 1)
8235 ioarcb->cmd_pkt.cdb[1] &= ~IPR_ID_HRRQ_SELE_ENABLE;
8236 else
8237 ioarcb->cmd_pkt.cdb[1] |= IPR_ID_HRRQ_SELE_ENABLE;
8238
8239 ioarcb->cmd_pkt.cdb[2] =
8240 ((u64) hrrq->host_rrq_dma >> 24) & 0xff;
8241 ioarcb->cmd_pkt.cdb[3] =
8242 ((u64) hrrq->host_rrq_dma >> 16) & 0xff;
8243 ioarcb->cmd_pkt.cdb[4] =
8244 ((u64) hrrq->host_rrq_dma >> 8) & 0xff;
8245 ioarcb->cmd_pkt.cdb[5] =
8246 ((u64) hrrq->host_rrq_dma) & 0xff;
8247 ioarcb->cmd_pkt.cdb[7] =
8248 ((sizeof(u32) * hrrq->size) >> 8) & 0xff;
8249 ioarcb->cmd_pkt.cdb[8] =
8250 (sizeof(u32) * hrrq->size) & 0xff;
8251
8252 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8253 ioarcb->cmd_pkt.cdb[9] =
8254 ioa_cfg->identify_hrrq_index;
8255
8256 if (ioa_cfg->sis64) {
8257 ioarcb->cmd_pkt.cdb[10] =
8258 ((u64) hrrq->host_rrq_dma >> 56) & 0xff;
8259 ioarcb->cmd_pkt.cdb[11] =
8260 ((u64) hrrq->host_rrq_dma >> 48) & 0xff;
8261 ioarcb->cmd_pkt.cdb[12] =
8262 ((u64) hrrq->host_rrq_dma >> 40) & 0xff;
8263 ioarcb->cmd_pkt.cdb[13] =
8264 ((u64) hrrq->host_rrq_dma >> 32) & 0xff;
8265 }
8266
8267 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8268 ioarcb->cmd_pkt.cdb[14] =
8269 ioa_cfg->identify_hrrq_index;
8270
8271 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8272 IPR_INTERNAL_TIMEOUT);
8273
8274 if (++ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num)
8275 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8276
8277 LEAVE;
8278 return IPR_RC_JOB_RETURN;
8279 }
8280
8281 LEAVE;
8282 return IPR_RC_JOB_CONTINUE;
8283}
8284
8285
8286
8287
8288
8289
8290
8291
8292
8293
8294
8295
8296
8297
8298static void ipr_reset_timer_done(struct timer_list *t)
8299{
8300 struct ipr_cmnd *ipr_cmd = from_timer(ipr_cmd, t, timer);
8301 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8302 unsigned long lock_flags = 0;
8303
8304 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8305
8306 if (ioa_cfg->reset_cmd == ipr_cmd) {
8307 list_del(&ipr_cmd->queue);
8308 ipr_cmd->done(ipr_cmd);
8309 }
8310
8311 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8312}
8313
8314
8315
8316
8317
8318
8319
8320
8321
8322
8323
8324
8325
8326
8327
8328static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
8329 unsigned long timeout)
8330{
8331
8332 ENTER;
8333 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8334 ipr_cmd->done = ipr_reset_ioa_job;
8335
8336 ipr_cmd->timer.expires = jiffies + timeout;
8337 ipr_cmd->timer.function = ipr_reset_timer_done;
8338 add_timer(&ipr_cmd->timer);
8339}
8340
8341
8342
8343
8344
8345
8346
8347
8348static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
8349{
8350 struct ipr_hrr_queue *hrrq;
8351
8352 for_each_hrrq(hrrq, ioa_cfg) {
8353 spin_lock(&hrrq->_lock);
8354 memset(hrrq->host_rrq, 0, sizeof(u32) * hrrq->size);
8355
8356
8357 hrrq->hrrq_start = hrrq->host_rrq;
8358 hrrq->hrrq_end = &hrrq->host_rrq[hrrq->size - 1];
8359 hrrq->hrrq_curr = hrrq->hrrq_start;
8360 hrrq->toggle_bit = 1;
8361 spin_unlock(&hrrq->_lock);
8362 }
8363 wmb();
8364
8365 ioa_cfg->identify_hrrq_index = 0;
8366 if (ioa_cfg->hrrq_num == 1)
8367 atomic_set(&ioa_cfg->hrrq_index, 0);
8368 else
8369 atomic_set(&ioa_cfg->hrrq_index, 1);
8370
8371
8372 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
8373}
8374
8375
8376
8377
8378
8379
8380
8381
8382static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
8383{
8384 unsigned long stage, stage_time;
8385 u32 feedback;
8386 volatile u32 int_reg;
8387 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8388 u64 maskval = 0;
8389
8390 feedback = readl(ioa_cfg->regs.init_feedback_reg);
8391 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
8392 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
8393
8394 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
8395
8396
8397 if (stage_time == 0)
8398 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
8399 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
8400 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
8401 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
8402 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
8403
8404 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
8405 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
8406 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8407 stage_time = ioa_cfg->transop_timeout;
8408 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8409 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
8410 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8411 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8412 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8413 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8414 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
8415 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
8416 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8417 return IPR_RC_JOB_CONTINUE;
8418 }
8419 }
8420
8421 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
8422 ipr_cmd->timer.function = ipr_oper_timeout;
8423 ipr_cmd->done = ipr_reset_ioa_job;
8424 add_timer(&ipr_cmd->timer);
8425
8426 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8427
8428 return IPR_RC_JOB_RETURN;
8429}
8430
8431
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
8442{
8443 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8444 volatile u32 int_reg;
8445 volatile u64 maskval;
8446 int i;
8447
8448 ENTER;
8449 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8450 ipr_init_ioa_mem(ioa_cfg);
8451
8452 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8453 spin_lock(&ioa_cfg->hrrq[i]._lock);
8454 ioa_cfg->hrrq[i].allow_interrupts = 1;
8455 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8456 }
8457 if (ioa_cfg->sis64) {
8458
8459 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8460 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8461 }
8462
8463 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8464
8465 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8466 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
8467 ioa_cfg->regs.clr_interrupt_mask_reg32);
8468 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8469 return IPR_RC_JOB_CONTINUE;
8470 }
8471
8472
8473 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
8474
8475 if (ioa_cfg->sis64) {
8476 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8477 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
8478 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
8479 } else
8480 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
8481
8482 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8483
8484 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
8485
8486 if (ioa_cfg->sis64) {
8487 ipr_cmd->job_step = ipr_reset_next_stage;
8488 return IPR_RC_JOB_CONTINUE;
8489 }
8490
8491 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
8492 ipr_cmd->timer.function = ipr_oper_timeout;
8493 ipr_cmd->done = ipr_reset_ioa_job;
8494 add_timer(&ipr_cmd->timer);
8495 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8496
8497 LEAVE;
8498 return IPR_RC_JOB_RETURN;
8499}
8500
8501
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
8512{
8513 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8514
8515 if (ioa_cfg->sdt_state == GET_DUMP)
8516 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8517 else if (ioa_cfg->sdt_state == READ_DUMP)
8518 ioa_cfg->sdt_state = ABORT_DUMP;
8519
8520 ioa_cfg->dump_timeout = 1;
8521 ipr_cmd->job_step = ipr_reset_alert;
8522
8523 return IPR_RC_JOB_CONTINUE;
8524}
8525
8526
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
8537{
8538 ioa_cfg->errors_logged++;
8539 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
8540}
8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
8551
8552static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
8553{
8554 unsigned long mailbox;
8555 struct ipr_hostrcb *hostrcb;
8556 struct ipr_uc_sdt sdt;
8557 int rc, length;
8558 u32 ioasc;
8559
8560 mailbox = readl(ioa_cfg->ioa_mailbox);
8561
8562 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
8563 ipr_unit_check_no_data(ioa_cfg);
8564 return;
8565 }
8566
8567 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
8568 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
8569 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
8570
8571 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
8572 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
8573 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
8574 ipr_unit_check_no_data(ioa_cfg);
8575 return;
8576 }
8577
8578
8579 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
8580 length = be32_to_cpu(sdt.entry[0].end_token);
8581 else
8582 length = (be32_to_cpu(sdt.entry[0].end_token) -
8583 be32_to_cpu(sdt.entry[0].start_token)) &
8584 IPR_FMT2_MBX_ADDR_MASK;
8585
8586 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
8587 struct ipr_hostrcb, queue);
8588 list_del_init(&hostrcb->queue);
8589 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
8590
8591 rc = ipr_get_ldump_data_section(ioa_cfg,
8592 be32_to_cpu(sdt.entry[0].start_token),
8593 (__be32 *)&hostrcb->hcam,
8594 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
8595
8596 if (!rc) {
8597 ipr_handle_log_data(ioa_cfg, hostrcb);
8598 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
8599 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
8600 ioa_cfg->sdt_state == GET_DUMP)
8601 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8602 } else
8603 ipr_unit_check_no_data(ioa_cfg);
8604
8605 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
8606}
8607
8608
8609
8610
8611
8612
8613
8614
8615
8616
8617static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
8618{
8619 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8620
8621 ENTER;
8622 ioa_cfg->ioa_unit_checked = 0;
8623 ipr_get_unit_check_buffer(ioa_cfg);
8624 ipr_cmd->job_step = ipr_reset_alert;
8625 ipr_reset_start_timer(ipr_cmd, 0);
8626
8627 LEAVE;
8628 return IPR_RC_JOB_RETURN;
8629}
8630
8631static int ipr_dump_mailbox_wait(struct ipr_cmnd *ipr_cmd)
8632{
8633 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8634
8635 ENTER;
8636
8637 if (ioa_cfg->sdt_state != GET_DUMP)
8638 return IPR_RC_JOB_RETURN;
8639
8640 if (!ioa_cfg->sis64 || !ipr_cmd->u.time_left ||
8641 (readl(ioa_cfg->regs.sense_interrupt_reg) &
8642 IPR_PCII_MAILBOX_STABLE)) {
8643
8644 if (!ipr_cmd->u.time_left)
8645 dev_err(&ioa_cfg->pdev->dev,
8646 "Timed out waiting for Mailbox register.\n");
8647
8648 ioa_cfg->sdt_state = READ_DUMP;
8649 ioa_cfg->dump_timeout = 0;
8650 if (ioa_cfg->sis64)
8651 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
8652 else
8653 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
8654 ipr_cmd->job_step = ipr_reset_wait_for_dump;
8655 schedule_work(&ioa_cfg->work_q);
8656
8657 } else {
8658 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8659 ipr_reset_start_timer(ipr_cmd,
8660 IPR_CHECK_FOR_RESET_TIMEOUT);
8661 }
8662
8663 LEAVE;
8664 return IPR_RC_JOB_RETURN;
8665}
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
8679{
8680 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8681
8682 ENTER;
8683 ioa_cfg->pdev->state_saved = true;
8684 pci_restore_state(ioa_cfg->pdev);
8685
8686 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
8687 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8688 return IPR_RC_JOB_CONTINUE;
8689 }
8690
8691 ipr_fail_all_ops(ioa_cfg);
8692
8693 if (ioa_cfg->sis64) {
8694
8695 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8696 readl(ioa_cfg->regs.endian_swap_reg);
8697 }
8698
8699 if (ioa_cfg->ioa_unit_checked) {
8700 if (ioa_cfg->sis64) {
8701 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
8702 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
8703 return IPR_RC_JOB_RETURN;
8704 } else {
8705 ioa_cfg->ioa_unit_checked = 0;
8706 ipr_get_unit_check_buffer(ioa_cfg);
8707 ipr_cmd->job_step = ipr_reset_alert;
8708 ipr_reset_start_timer(ipr_cmd, 0);
8709 return IPR_RC_JOB_RETURN;
8710 }
8711 }
8712
8713 if (ioa_cfg->in_ioa_bringdown) {
8714 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8715 } else if (ioa_cfg->sdt_state == GET_DUMP) {
8716 ipr_cmd->job_step = ipr_dump_mailbox_wait;
8717 ipr_cmd->u.time_left = IPR_WAIT_FOR_MAILBOX;
8718 } else {
8719 ipr_cmd->job_step = ipr_reset_enable_ioa;
8720 }
8721
8722 LEAVE;
8723 return IPR_RC_JOB_CONTINUE;
8724}
8725
8726
8727
8728
8729
8730
8731
8732
8733
8734
8735static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
8736{
8737 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8738
8739 ENTER;
8740 if (ioa_cfg->cfg_locked)
8741 pci_cfg_access_unlock(ioa_cfg->pdev);
8742 ioa_cfg->cfg_locked = 0;
8743 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
8744 LEAVE;
8745 return IPR_RC_JOB_CONTINUE;
8746}
8747
8748
8749
8750
8751
8752
8753
8754
8755
8756
8757static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
8758{
8759 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8760 int rc = PCIBIOS_SUCCESSFUL;
8761
8762 ENTER;
8763 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
8764 writel(IPR_UPROCI_SIS64_START_BIST,
8765 ioa_cfg->regs.set_uproc_interrupt_reg32);
8766 else
8767 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
8768
8769 if (rc == PCIBIOS_SUCCESSFUL) {
8770 ipr_cmd->job_step = ipr_reset_bist_done;
8771 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8772 rc = IPR_RC_JOB_RETURN;
8773 } else {
8774 if (ioa_cfg->cfg_locked)
8775 pci_cfg_access_unlock(ipr_cmd->ioa_cfg->pdev);
8776 ioa_cfg->cfg_locked = 0;
8777 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8778 rc = IPR_RC_JOB_CONTINUE;
8779 }
8780
8781 LEAVE;
8782 return rc;
8783}
8784
8785
8786
8787
8788
8789
8790
8791
8792
8793
8794static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
8795{
8796 ENTER;
8797 ipr_cmd->job_step = ipr_reset_bist_done;
8798 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8799 LEAVE;
8800 return IPR_RC_JOB_RETURN;
8801}
8802
8803
8804
8805
8806
8807
8808
8809
8810static void ipr_reset_reset_work(struct work_struct *work)
8811{
8812 struct ipr_cmnd *ipr_cmd = container_of(work, struct ipr_cmnd, work);
8813 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8814 struct pci_dev *pdev = ioa_cfg->pdev;
8815 unsigned long lock_flags = 0;
8816
8817 ENTER;
8818 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
8819 msleep(jiffies_to_msecs(IPR_PCI_RESET_TIMEOUT));
8820 pci_set_pcie_reset_state(pdev, pcie_deassert_reset);
8821
8822 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8823 if (ioa_cfg->reset_cmd == ipr_cmd)
8824 ipr_reset_ioa_job(ipr_cmd);
8825 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8826 LEAVE;
8827}
8828
8829
8830
8831
8832
8833
8834
8835
8836
8837
8838static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
8839{
8840 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8841
8842 ENTER;
8843 INIT_WORK(&ipr_cmd->work, ipr_reset_reset_work);
8844 queue_work(ioa_cfg->reset_work_q, &ipr_cmd->work);
8845 ipr_cmd->job_step = ipr_reset_slot_reset_done;
8846 LEAVE;
8847 return IPR_RC_JOB_RETURN;
8848}
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858
8859static int ipr_reset_block_config_access_wait(struct ipr_cmnd *ipr_cmd)
8860{
8861 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8862 int rc = IPR_RC_JOB_CONTINUE;
8863
8864 if (pci_cfg_access_trylock(ioa_cfg->pdev)) {
8865 ioa_cfg->cfg_locked = 1;
8866 ipr_cmd->job_step = ioa_cfg->reset;
8867 } else {
8868 if (ipr_cmd->u.time_left) {
8869 rc = IPR_RC_JOB_RETURN;
8870 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8871 ipr_reset_start_timer(ipr_cmd,
8872 IPR_CHECK_FOR_RESET_TIMEOUT);
8873 } else {
8874 ipr_cmd->job_step = ioa_cfg->reset;
8875 dev_err(&ioa_cfg->pdev->dev,
8876 "Timed out waiting to lock config access. Resetting anyway.\n");
8877 }
8878 }
8879
8880 return rc;
8881}
8882
8883
8884
8885
8886
8887
8888
8889
8890
8891
8892static int ipr_reset_block_config_access(struct ipr_cmnd *ipr_cmd)
8893{
8894 ipr_cmd->ioa_cfg->cfg_locked = 0;
8895 ipr_cmd->job_step = ipr_reset_block_config_access_wait;
8896 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8897 return IPR_RC_JOB_CONTINUE;
8898}
8899
8900
8901
8902
8903
8904
8905
8906
8907static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
8908{
8909 volatile u32 temp_reg;
8910
8911 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8912 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
8913}
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924
8925
8926
8927
8928
8929
8930static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
8931{
8932 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8933 int rc = IPR_RC_JOB_RETURN;
8934
8935 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
8936 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8937 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8938 } else {
8939 ipr_cmd->job_step = ipr_reset_block_config_access;
8940 rc = IPR_RC_JOB_CONTINUE;
8941 }
8942
8943 return rc;
8944}
8945
8946
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
8959{
8960 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8961 u16 cmd_reg;
8962 int rc;
8963
8964 ENTER;
8965 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
8966
8967 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
8968 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
8969 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
8970 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
8971 } else {
8972 ipr_cmd->job_step = ipr_reset_block_config_access;
8973 }
8974
8975 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8976 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8977
8978 LEAVE;
8979 return IPR_RC_JOB_RETURN;
8980}
8981
8982
8983
8984
8985
8986
8987
8988
8989
8990
8991static int ipr_reset_quiesce_done(struct ipr_cmnd *ipr_cmd)
8992{
8993 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8994
8995 ENTER;
8996 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8997 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8998 LEAVE;
8999 return IPR_RC_JOB_CONTINUE;
9000}
9001
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012static int ipr_reset_cancel_hcam_done(struct ipr_cmnd *ipr_cmd)
9013{
9014 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9015 struct ipr_cmnd *loop_cmd;
9016 struct ipr_hrr_queue *hrrq;
9017 int rc = IPR_RC_JOB_CONTINUE;
9018 int count = 0;
9019
9020 ENTER;
9021 ipr_cmd->job_step = ipr_reset_quiesce_done;
9022
9023 for_each_hrrq(hrrq, ioa_cfg) {
9024 spin_lock(&hrrq->_lock);
9025 list_for_each_entry(loop_cmd, &hrrq->hrrq_pending_q, queue) {
9026 count++;
9027 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9028 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9029 rc = IPR_RC_JOB_RETURN;
9030 break;
9031 }
9032 spin_unlock(&hrrq->_lock);
9033
9034 if (count)
9035 break;
9036 }
9037
9038 LEAVE;
9039 return rc;
9040}
9041
9042
9043
9044
9045
9046
9047
9048
9049
9050
9051static int ipr_reset_cancel_hcam(struct ipr_cmnd *ipr_cmd)
9052{
9053 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9054 int rc = IPR_RC_JOB_CONTINUE;
9055 struct ipr_cmd_pkt *cmd_pkt;
9056 struct ipr_cmnd *hcam_cmd;
9057 struct ipr_hrr_queue *hrrq = &ioa_cfg->hrrq[IPR_INIT_HRRQ];
9058
9059 ENTER;
9060 ipr_cmd->job_step = ipr_reset_cancel_hcam_done;
9061
9062 if (!hrrq->ioa_is_dead) {
9063 if (!list_empty(&ioa_cfg->hostrcb_pending_q)) {
9064 list_for_each_entry(hcam_cmd, &hrrq->hrrq_pending_q, queue) {
9065 if (hcam_cmd->ioarcb.cmd_pkt.cdb[0] != IPR_HOST_CONTROLLED_ASYNC)
9066 continue;
9067
9068 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9069 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
9070 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
9071 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
9072 cmd_pkt->cdb[0] = IPR_CANCEL_REQUEST;
9073 cmd_pkt->cdb[1] = IPR_CANCEL_64BIT_IOARCB;
9074 cmd_pkt->cdb[10] = ((u64) hcam_cmd->dma_addr >> 56) & 0xff;
9075 cmd_pkt->cdb[11] = ((u64) hcam_cmd->dma_addr >> 48) & 0xff;
9076 cmd_pkt->cdb[12] = ((u64) hcam_cmd->dma_addr >> 40) & 0xff;
9077 cmd_pkt->cdb[13] = ((u64) hcam_cmd->dma_addr >> 32) & 0xff;
9078 cmd_pkt->cdb[2] = ((u64) hcam_cmd->dma_addr >> 24) & 0xff;
9079 cmd_pkt->cdb[3] = ((u64) hcam_cmd->dma_addr >> 16) & 0xff;
9080 cmd_pkt->cdb[4] = ((u64) hcam_cmd->dma_addr >> 8) & 0xff;
9081 cmd_pkt->cdb[5] = ((u64) hcam_cmd->dma_addr) & 0xff;
9082
9083 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
9084 IPR_CANCEL_TIMEOUT);
9085
9086 rc = IPR_RC_JOB_RETURN;
9087 ipr_cmd->job_step = ipr_reset_cancel_hcam;
9088 break;
9089 }
9090 }
9091 } else
9092 ipr_cmd->job_step = ipr_reset_alert;
9093
9094 LEAVE;
9095 return rc;
9096}
9097
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
9108{
9109 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9110 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
9111
9112 dma_unmap_sg(&ioa_cfg->pdev->dev, sglist->scatterlist,
9113 sglist->num_sg, DMA_TO_DEVICE);
9114
9115 ipr_cmd->job_step = ipr_reset_alert;
9116 return IPR_RC_JOB_CONTINUE;
9117}
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
9130{
9131 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9132 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
9133
9134 ENTER;
9135 ipr_cmd->job_step = ipr_reset_alert;
9136
9137 if (!sglist)
9138 return IPR_RC_JOB_CONTINUE;
9139
9140 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9141 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
9142 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
9143 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
9144 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
9145 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
9146 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
9147
9148 if (ioa_cfg->sis64)
9149 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
9150 else
9151 ipr_build_ucode_ioadl(ipr_cmd, sglist);
9152 ipr_cmd->job_step = ipr_reset_ucode_download_done;
9153
9154 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
9155 IPR_WRITE_BUFFER_TIMEOUT);
9156
9157 LEAVE;
9158 return IPR_RC_JOB_RETURN;
9159}
9160
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170
9171
9172static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
9173{
9174 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9175 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
9176 unsigned long timeout;
9177 int rc = IPR_RC_JOB_CONTINUE;
9178
9179 ENTER;
9180 if (shutdown_type == IPR_SHUTDOWN_QUIESCE)
9181 ipr_cmd->job_step = ipr_reset_cancel_hcam;
9182 else if (shutdown_type != IPR_SHUTDOWN_NONE &&
9183 !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
9184 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
9185 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
9186 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
9187 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
9188
9189 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
9190 timeout = IPR_SHUTDOWN_TIMEOUT;
9191 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
9192 timeout = IPR_INTERNAL_TIMEOUT;
9193 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
9194 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
9195 else
9196 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
9197
9198 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
9199
9200 rc = IPR_RC_JOB_RETURN;
9201 ipr_cmd->job_step = ipr_reset_ucode_download;
9202 } else
9203 ipr_cmd->job_step = ipr_reset_alert;
9204
9205 LEAVE;
9206 return rc;
9207}
9208
9209
9210
9211
9212
9213
9214
9215
9216
9217
9218static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
9219{
9220 u32 rc, ioasc;
9221 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9222
9223 do {
9224 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
9225
9226 if (ioa_cfg->reset_cmd != ipr_cmd) {
9227
9228
9229
9230
9231 list_add_tail(&ipr_cmd->queue,
9232 &ipr_cmd->hrrq->hrrq_free_q);
9233 return;
9234 }
9235
9236 if (IPR_IOASC_SENSE_KEY(ioasc)) {
9237 rc = ipr_cmd->job_step_failed(ipr_cmd);
9238 if (rc == IPR_RC_JOB_RETURN)
9239 return;
9240 }
9241
9242 ipr_reinit_ipr_cmnd(ipr_cmd);
9243 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
9244 rc = ipr_cmd->job_step(ipr_cmd);
9245 } while (rc == IPR_RC_JOB_CONTINUE);
9246}
9247
9248
9249
9250
9251
9252
9253
9254
9255
9256
9257
9258
9259
9260
9261
9262static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9263 int (*job_step) (struct ipr_cmnd *),
9264 enum ipr_shutdown_type shutdown_type)
9265{
9266 struct ipr_cmnd *ipr_cmd;
9267 int i;
9268
9269 ioa_cfg->in_reset_reload = 1;
9270 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9271 spin_lock(&ioa_cfg->hrrq[i]._lock);
9272 ioa_cfg->hrrq[i].allow_cmds = 0;
9273 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9274 }
9275 wmb();
9276 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
9277 ioa_cfg->scsi_unblock = 0;
9278 ioa_cfg->scsi_blocked = 1;
9279 scsi_block_requests(ioa_cfg->host);
9280 }
9281
9282 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
9283 ioa_cfg->reset_cmd = ipr_cmd;
9284 ipr_cmd->job_step = job_step;
9285 ipr_cmd->u.shutdown_type = shutdown_type;
9286
9287 ipr_reset_ioa_job(ipr_cmd);
9288}
9289
9290
9291
9292
9293
9294
9295
9296
9297
9298
9299
9300
9301
9302static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9303 enum ipr_shutdown_type shutdown_type)
9304{
9305 int i;
9306
9307 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
9308 return;
9309
9310 if (ioa_cfg->in_reset_reload) {
9311 if (ioa_cfg->sdt_state == GET_DUMP)
9312 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
9313 else if (ioa_cfg->sdt_state == READ_DUMP)
9314 ioa_cfg->sdt_state = ABORT_DUMP;
9315 }
9316
9317 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
9318 dev_err(&ioa_cfg->pdev->dev,
9319 "IOA taken offline - error recovery failed\n");
9320
9321 ioa_cfg->reset_retries = 0;
9322 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9323 spin_lock(&ioa_cfg->hrrq[i]._lock);
9324 ioa_cfg->hrrq[i].ioa_is_dead = 1;
9325 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9326 }
9327 wmb();
9328
9329 if (ioa_cfg->in_ioa_bringdown) {
9330 ioa_cfg->reset_cmd = NULL;
9331 ioa_cfg->in_reset_reload = 0;
9332 ipr_fail_all_ops(ioa_cfg);
9333 wake_up_all(&ioa_cfg->reset_wait_q);
9334
9335 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
9336 ioa_cfg->scsi_unblock = 1;
9337 schedule_work(&ioa_cfg->work_q);
9338 }
9339 return;
9340 } else {
9341 ioa_cfg->in_ioa_bringdown = 1;
9342 shutdown_type = IPR_SHUTDOWN_NONE;
9343 }
9344 }
9345
9346 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
9347 shutdown_type);
9348}
9349
9350
9351
9352
9353
9354
9355
9356
9357
9358static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
9359{
9360 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9361 int i;
9362
9363
9364 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9365 spin_lock(&ioa_cfg->hrrq[i]._lock);
9366 ioa_cfg->hrrq[i].allow_interrupts = 0;
9367 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9368 }
9369 wmb();
9370 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
9371 ipr_cmd->done = ipr_reset_ioa_job;
9372 return IPR_RC_JOB_RETURN;
9373}
9374
9375
9376
9377
9378
9379
9380
9381
9382static pci_ers_result_t ipr_pci_mmio_enabled(struct pci_dev *pdev)
9383{
9384 unsigned long flags = 0;
9385 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9386
9387 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9388 if (!ioa_cfg->probe_done)
9389 pci_save_state(pdev);
9390 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9391 return PCI_ERS_RESULT_NEED_RESET;
9392}
9393
9394
9395
9396
9397
9398
9399
9400
9401
9402static void ipr_pci_frozen(struct pci_dev *pdev)
9403{
9404 unsigned long flags = 0;
9405 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9406
9407 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9408 if (ioa_cfg->probe_done)
9409 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
9410 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9411}
9412
9413
9414
9415
9416
9417
9418
9419
9420
9421static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
9422{
9423 unsigned long flags = 0;
9424 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9425
9426 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9427 if (ioa_cfg->probe_done) {
9428 if (ioa_cfg->needs_warm_reset)
9429 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9430 else
9431 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
9432 IPR_SHUTDOWN_NONE);
9433 } else
9434 wake_up_all(&ioa_cfg->eeh_wait_q);
9435 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9436 return PCI_ERS_RESULT_RECOVERED;
9437}
9438
9439
9440
9441
9442
9443
9444
9445
9446static void ipr_pci_perm_failure(struct pci_dev *pdev)
9447{
9448 unsigned long flags = 0;
9449 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9450 int i;
9451
9452 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9453 if (ioa_cfg->probe_done) {
9454 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
9455 ioa_cfg->sdt_state = ABORT_DUMP;
9456 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES - 1;
9457 ioa_cfg->in_ioa_bringdown = 1;
9458 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9459 spin_lock(&ioa_cfg->hrrq[i]._lock);
9460 ioa_cfg->hrrq[i].allow_cmds = 0;
9461 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9462 }
9463 wmb();
9464 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9465 } else
9466 wake_up_all(&ioa_cfg->eeh_wait_q);
9467 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9468}
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478
9479
9480static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
9481 pci_channel_state_t state)
9482{
9483 switch (state) {
9484 case pci_channel_io_frozen:
9485 ipr_pci_frozen(pdev);
9486 return PCI_ERS_RESULT_CAN_RECOVER;
9487 case pci_channel_io_perm_failure:
9488 ipr_pci_perm_failure(pdev);
9489 return PCI_ERS_RESULT_DISCONNECT;
9490 default:
9491 break;
9492 }
9493 return PCI_ERS_RESULT_NEED_RESET;
9494}
9495
9496
9497
9498
9499
9500
9501
9502
9503
9504
9505
9506static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
9507{
9508 int rc = 0;
9509 unsigned long host_lock_flags = 0;
9510
9511 ENTER;
9512 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9513 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
9514 ioa_cfg->probe_done = 1;
9515 if (ioa_cfg->needs_hard_reset) {
9516 ioa_cfg->needs_hard_reset = 0;
9517 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9518 } else
9519 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
9520 IPR_SHUTDOWN_NONE);
9521 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9522
9523 LEAVE;
9524 return rc;
9525}
9526
9527
9528
9529
9530
9531
9532
9533
9534static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9535{
9536 int i;
9537
9538 if (ioa_cfg->ipr_cmnd_list) {
9539 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9540 if (ioa_cfg->ipr_cmnd_list[i])
9541 dma_pool_free(ioa_cfg->ipr_cmd_pool,
9542 ioa_cfg->ipr_cmnd_list[i],
9543 ioa_cfg->ipr_cmnd_list_dma[i]);
9544
9545 ioa_cfg->ipr_cmnd_list[i] = NULL;
9546 }
9547 }
9548
9549 dma_pool_destroy(ioa_cfg->ipr_cmd_pool);
9550
9551 kfree(ioa_cfg->ipr_cmnd_list);
9552 kfree(ioa_cfg->ipr_cmnd_list_dma);
9553 ioa_cfg->ipr_cmnd_list = NULL;
9554 ioa_cfg->ipr_cmnd_list_dma = NULL;
9555 ioa_cfg->ipr_cmd_pool = NULL;
9556}
9557
9558
9559
9560
9561
9562
9563
9564
9565static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
9566{
9567 int i;
9568
9569 kfree(ioa_cfg->res_entries);
9570 dma_free_coherent(&ioa_cfg->pdev->dev, sizeof(struct ipr_misc_cbs),
9571 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9572 ipr_free_cmd_blks(ioa_cfg);
9573
9574 for (i = 0; i < ioa_cfg->hrrq_num; i++)
9575 dma_free_coherent(&ioa_cfg->pdev->dev,
9576 sizeof(u32) * ioa_cfg->hrrq[i].size,
9577 ioa_cfg->hrrq[i].host_rrq,
9578 ioa_cfg->hrrq[i].host_rrq_dma);
9579
9580 dma_free_coherent(&ioa_cfg->pdev->dev, ioa_cfg->cfg_table_size,
9581 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9582
9583 for (i = 0; i < IPR_MAX_HCAMS; i++) {
9584 dma_free_coherent(&ioa_cfg->pdev->dev,
9585 sizeof(struct ipr_hostrcb),
9586 ioa_cfg->hostrcb[i],
9587 ioa_cfg->hostrcb_dma[i]);
9588 }
9589
9590 ipr_free_dump(ioa_cfg);
9591 kfree(ioa_cfg->trace);
9592}
9593
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604static void ipr_free_irqs(struct ipr_ioa_cfg *ioa_cfg)
9605{
9606 struct pci_dev *pdev = ioa_cfg->pdev;
9607 int i;
9608
9609 for (i = 0; i < ioa_cfg->nvectors; i++)
9610 free_irq(pci_irq_vector(pdev, i), &ioa_cfg->hrrq[i]);
9611 pci_free_irq_vectors(pdev);
9612}
9613
9614
9615
9616
9617
9618
9619
9620
9621
9622
9623
9624static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
9625{
9626 struct pci_dev *pdev = ioa_cfg->pdev;
9627
9628 ENTER;
9629 ipr_free_irqs(ioa_cfg);
9630 if (ioa_cfg->reset_work_q)
9631 destroy_workqueue(ioa_cfg->reset_work_q);
9632 iounmap(ioa_cfg->hdw_dma_regs);
9633 pci_release_regions(pdev);
9634 ipr_free_mem(ioa_cfg);
9635 scsi_host_put(ioa_cfg->host);
9636 pci_disable_device(pdev);
9637 LEAVE;
9638}
9639
9640
9641
9642
9643
9644
9645
9646
9647static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9648{
9649 struct ipr_cmnd *ipr_cmd;
9650 struct ipr_ioarcb *ioarcb;
9651 dma_addr_t dma_addr;
9652 int i, entries_each_hrrq, hrrq_id = 0;
9653
9654 ioa_cfg->ipr_cmd_pool = dma_pool_create(IPR_NAME, &ioa_cfg->pdev->dev,
9655 sizeof(struct ipr_cmnd), 512, 0);
9656
9657 if (!ioa_cfg->ipr_cmd_pool)
9658 return -ENOMEM;
9659
9660 ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
9661 ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
9662
9663 if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
9664 ipr_free_cmd_blks(ioa_cfg);
9665 return -ENOMEM;
9666 }
9667
9668 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9669 if (ioa_cfg->hrrq_num > 1) {
9670 if (i == 0) {
9671 entries_each_hrrq = IPR_NUM_INTERNAL_CMD_BLKS;
9672 ioa_cfg->hrrq[i].min_cmd_id = 0;
9673 ioa_cfg->hrrq[i].max_cmd_id =
9674 (entries_each_hrrq - 1);
9675 } else {
9676 entries_each_hrrq =
9677 IPR_NUM_BASE_CMD_BLKS/
9678 (ioa_cfg->hrrq_num - 1);
9679 ioa_cfg->hrrq[i].min_cmd_id =
9680 IPR_NUM_INTERNAL_CMD_BLKS +
9681 (i - 1) * entries_each_hrrq;
9682 ioa_cfg->hrrq[i].max_cmd_id =
9683 (IPR_NUM_INTERNAL_CMD_BLKS +
9684 i * entries_each_hrrq - 1);
9685 }
9686 } else {
9687 entries_each_hrrq = IPR_NUM_CMD_BLKS;
9688 ioa_cfg->hrrq[i].min_cmd_id = 0;
9689 ioa_cfg->hrrq[i].max_cmd_id = (entries_each_hrrq - 1);
9690 }
9691 ioa_cfg->hrrq[i].size = entries_each_hrrq;
9692 }
9693
9694 BUG_ON(ioa_cfg->hrrq_num == 0);
9695
9696 i = IPR_NUM_CMD_BLKS -
9697 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id - 1;
9698 if (i > 0) {
9699 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].size += i;
9700 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id += i;
9701 }
9702
9703 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9704 ipr_cmd = dma_pool_zalloc(ioa_cfg->ipr_cmd_pool,
9705 GFP_KERNEL, &dma_addr);
9706
9707 if (!ipr_cmd) {
9708 ipr_free_cmd_blks(ioa_cfg);
9709 return -ENOMEM;
9710 }
9711
9712 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
9713 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
9714
9715 ioarcb = &ipr_cmd->ioarcb;
9716 ipr_cmd->dma_addr = dma_addr;
9717 if (ioa_cfg->sis64)
9718 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
9719 else
9720 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
9721
9722 ioarcb->host_response_handle = cpu_to_be32(i << 2);
9723 if (ioa_cfg->sis64) {
9724 ioarcb->u.sis64_addr_data.data_ioadl_addr =
9725 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
9726 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
9727 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
9728 } else {
9729 ioarcb->write_ioadl_addr =
9730 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
9731 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
9732 ioarcb->ioasa_host_pci_addr =
9733 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
9734 }
9735 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
9736 ipr_cmd->cmd_index = i;
9737 ipr_cmd->ioa_cfg = ioa_cfg;
9738 ipr_cmd->sense_buffer_dma = dma_addr +
9739 offsetof(struct ipr_cmnd, sense_buffer);
9740
9741 ipr_cmd->ioarcb.cmd_pkt.hrrq_id = hrrq_id;
9742 ipr_cmd->hrrq = &ioa_cfg->hrrq[hrrq_id];
9743 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9744 if (i >= ioa_cfg->hrrq[hrrq_id].max_cmd_id)
9745 hrrq_id++;
9746 }
9747
9748 return 0;
9749}
9750
9751
9752
9753
9754
9755
9756
9757
9758static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
9759{
9760 struct pci_dev *pdev = ioa_cfg->pdev;
9761 int i, rc = -ENOMEM;
9762
9763 ENTER;
9764 ioa_cfg->res_entries = kcalloc(ioa_cfg->max_devs_supported,
9765 sizeof(struct ipr_resource_entry),
9766 GFP_KERNEL);
9767
9768 if (!ioa_cfg->res_entries)
9769 goto out;
9770
9771 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
9772 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
9773 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
9774 }
9775
9776 ioa_cfg->vpd_cbs = dma_alloc_coherent(&pdev->dev,
9777 sizeof(struct ipr_misc_cbs),
9778 &ioa_cfg->vpd_cbs_dma,
9779 GFP_KERNEL);
9780
9781 if (!ioa_cfg->vpd_cbs)
9782 goto out_free_res_entries;
9783
9784 if (ipr_alloc_cmd_blks(ioa_cfg))
9785 goto out_free_vpd_cbs;
9786
9787 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9788 ioa_cfg->hrrq[i].host_rrq = dma_alloc_coherent(&pdev->dev,
9789 sizeof(u32) * ioa_cfg->hrrq[i].size,
9790 &ioa_cfg->hrrq[i].host_rrq_dma,
9791 GFP_KERNEL);
9792
9793 if (!ioa_cfg->hrrq[i].host_rrq) {
9794 while (--i > 0)
9795 dma_free_coherent(&pdev->dev,
9796 sizeof(u32) * ioa_cfg->hrrq[i].size,
9797 ioa_cfg->hrrq[i].host_rrq,
9798 ioa_cfg->hrrq[i].host_rrq_dma);
9799 goto out_ipr_free_cmd_blocks;
9800 }
9801 ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
9802 }
9803
9804 ioa_cfg->u.cfg_table = dma_alloc_coherent(&pdev->dev,
9805 ioa_cfg->cfg_table_size,
9806 &ioa_cfg->cfg_table_dma,
9807 GFP_KERNEL);
9808
9809 if (!ioa_cfg->u.cfg_table)
9810 goto out_free_host_rrq;
9811
9812 for (i = 0; i < IPR_MAX_HCAMS; i++) {
9813 ioa_cfg->hostrcb[i] = dma_alloc_coherent(&pdev->dev,
9814 sizeof(struct ipr_hostrcb),
9815 &ioa_cfg->hostrcb_dma[i],
9816 GFP_KERNEL);
9817
9818 if (!ioa_cfg->hostrcb[i])
9819 goto out_free_hostrcb_dma;
9820
9821 ioa_cfg->hostrcb[i]->hostrcb_dma =
9822 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
9823 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
9824 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
9825 }
9826
9827 ioa_cfg->trace = kcalloc(IPR_NUM_TRACE_ENTRIES,
9828 sizeof(struct ipr_trace_entry),
9829 GFP_KERNEL);
9830
9831 if (!ioa_cfg->trace)
9832 goto out_free_hostrcb_dma;
9833
9834 rc = 0;
9835out:
9836 LEAVE;
9837 return rc;
9838
9839out_free_hostrcb_dma:
9840 while (i-- > 0) {
9841 dma_free_coherent(&pdev->dev, sizeof(struct ipr_hostrcb),
9842 ioa_cfg->hostrcb[i],
9843 ioa_cfg->hostrcb_dma[i]);
9844 }
9845 dma_free_coherent(&pdev->dev, ioa_cfg->cfg_table_size,
9846 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9847out_free_host_rrq:
9848 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9849 dma_free_coherent(&pdev->dev,
9850 sizeof(u32) * ioa_cfg->hrrq[i].size,
9851 ioa_cfg->hrrq[i].host_rrq,
9852 ioa_cfg->hrrq[i].host_rrq_dma);
9853 }
9854out_ipr_free_cmd_blocks:
9855 ipr_free_cmd_blks(ioa_cfg);
9856out_free_vpd_cbs:
9857 dma_free_coherent(&pdev->dev, sizeof(struct ipr_misc_cbs),
9858 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9859out_free_res_entries:
9860 kfree(ioa_cfg->res_entries);
9861 goto out;
9862}
9863
9864
9865
9866
9867
9868
9869
9870
9871static void ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
9872{
9873 int i;
9874
9875 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
9876 ioa_cfg->bus_attr[i].bus = i;
9877 ioa_cfg->bus_attr[i].qas_enabled = 0;
9878 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
9879 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
9880 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
9881 else
9882 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
9883 }
9884}
9885
9886
9887
9888
9889
9890
9891
9892
9893static void ipr_init_regs(struct ipr_ioa_cfg *ioa_cfg)
9894{
9895 const struct ipr_interrupt_offsets *p;
9896 struct ipr_interrupts *t;
9897 void __iomem *base;
9898
9899 p = &ioa_cfg->chip_cfg->regs;
9900 t = &ioa_cfg->regs;
9901 base = ioa_cfg->hdw_dma_regs;
9902
9903 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
9904 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
9905 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
9906 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
9907 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
9908 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
9909 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
9910 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
9911 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
9912 t->ioarrin_reg = base + p->ioarrin_reg;
9913 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
9914 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
9915 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
9916 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
9917 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
9918 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
9919
9920 if (ioa_cfg->sis64) {
9921 t->init_feedback_reg = base + p->init_feedback_reg;
9922 t->dump_addr_reg = base + p->dump_addr_reg;
9923 t->dump_data_reg = base + p->dump_data_reg;
9924 t->endian_swap_reg = base + p->endian_swap_reg;
9925 }
9926}
9927
9928
9929
9930
9931
9932
9933
9934
9935
9936
9937static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
9938 struct Scsi_Host *host, struct pci_dev *pdev)
9939{
9940 int i;
9941
9942 ioa_cfg->host = host;
9943 ioa_cfg->pdev = pdev;
9944 ioa_cfg->log_level = ipr_log_level;
9945 ioa_cfg->doorbell = IPR_DOORBELL;
9946 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
9947 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
9948 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
9949 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
9950 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
9951 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
9952
9953 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
9954 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
9955 INIT_LIST_HEAD(&ioa_cfg->hostrcb_report_q);
9956 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
9957 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9958 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
9959 INIT_WORK(&ioa_cfg->scsi_add_work_q, ipr_add_remove_thread);
9960 init_waitqueue_head(&ioa_cfg->reset_wait_q);
9961 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9962 init_waitqueue_head(&ioa_cfg->eeh_wait_q);
9963 ioa_cfg->sdt_state = INACTIVE;
9964
9965 ipr_initialize_bus_attr(ioa_cfg);
9966 ioa_cfg->max_devs_supported = ipr_max_devs;
9967
9968 if (ioa_cfg->sis64) {
9969 host->max_channel = IPR_MAX_SIS64_BUSES;
9970 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
9971 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
9972 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
9973 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
9974 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
9975 + ((sizeof(struct ipr_config_table_entry64)
9976 * ioa_cfg->max_devs_supported)));
9977 } else {
9978 host->max_channel = IPR_VSET_BUS;
9979 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
9980 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
9981 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
9982 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
9983 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
9984 + ((sizeof(struct ipr_config_table_entry)
9985 * ioa_cfg->max_devs_supported)));
9986 }
9987
9988 host->unique_id = host->host_no;
9989 host->max_cmd_len = IPR_MAX_CDB_LEN;
9990 host->can_queue = ioa_cfg->max_cmds;
9991 pci_set_drvdata(pdev, ioa_cfg);
9992
9993 for (i = 0; i < ARRAY_SIZE(ioa_cfg->hrrq); i++) {
9994 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_free_q);
9995 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_pending_q);
9996 spin_lock_init(&ioa_cfg->hrrq[i]._lock);
9997 if (i == 0)
9998 ioa_cfg->hrrq[i].lock = ioa_cfg->host->host_lock;
9999 else
10000 ioa_cfg->hrrq[i].lock = &ioa_cfg->hrrq[i]._lock;
10001 }
10002}
10003
10004
10005
10006
10007
10008
10009
10010
10011static const struct ipr_chip_t *
10012ipr_get_chip_info(const struct pci_device_id *dev_id)
10013{
10014 int i;
10015
10016 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
10017 if (ipr_chip[i].vendor == dev_id->vendor &&
10018 ipr_chip[i].device == dev_id->device)
10019 return &ipr_chip[i];
10020 return NULL;
10021}
10022
10023
10024
10025
10026
10027
10028
10029
10030
10031static void ipr_wait_for_pci_err_recovery(struct ipr_ioa_cfg *ioa_cfg)
10032{
10033 struct pci_dev *pdev = ioa_cfg->pdev;
10034
10035 if (pci_channel_offline(pdev)) {
10036 wait_event_timeout(ioa_cfg->eeh_wait_q,
10037 !pci_channel_offline(pdev),
10038 IPR_PCI_ERROR_RECOVERY_TIMEOUT);
10039 pci_restore_state(pdev);
10040 }
10041}
10042
10043static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
10044{
10045 int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
10046
10047 for (vec_idx = 0; vec_idx < ioa_cfg->nvectors; vec_idx++) {
10048 snprintf(ioa_cfg->vectors_info[vec_idx].desc, n,
10049 "host%d-%d", ioa_cfg->host->host_no, vec_idx);
10050 ioa_cfg->vectors_info[vec_idx].
10051 desc[strlen(ioa_cfg->vectors_info[vec_idx].desc)] = 0;
10052 }
10053}
10054
10055static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg,
10056 struct pci_dev *pdev)
10057{
10058 int i, rc;
10059
10060 for (i = 1; i < ioa_cfg->nvectors; i++) {
10061 rc = request_irq(pci_irq_vector(pdev, i),
10062 ipr_isr_mhrrq,
10063 0,
10064 ioa_cfg->vectors_info[i].desc,
10065 &ioa_cfg->hrrq[i]);
10066 if (rc) {
10067 while (--i >= 0)
10068 free_irq(pci_irq_vector(pdev, i),
10069 &ioa_cfg->hrrq[i]);
10070 return rc;
10071 }
10072 }
10073 return 0;
10074}
10075
10076
10077
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087static irqreturn_t ipr_test_intr(int irq, void *devp)
10088{
10089 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
10090 unsigned long lock_flags = 0;
10091 irqreturn_t rc = IRQ_HANDLED;
10092
10093 dev_info(&ioa_cfg->pdev->dev, "Received IRQ : %d\n", irq);
10094 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10095
10096 ioa_cfg->msi_received = 1;
10097 wake_up(&ioa_cfg->msi_wait_q);
10098
10099 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10100 return rc;
10101}
10102
10103
10104
10105
10106
10107
10108
10109
10110
10111
10112
10113
10114
10115static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
10116{
10117 int rc;
10118 unsigned long lock_flags = 0;
10119 int irq = pci_irq_vector(pdev, 0);
10120
10121 ENTER;
10122
10123 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10124 init_waitqueue_head(&ioa_cfg->msi_wait_q);
10125 ioa_cfg->msi_received = 0;
10126 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10127 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
10128 readl(ioa_cfg->regs.sense_interrupt_mask_reg);
10129 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10130
10131 rc = request_irq(irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
10132 if (rc) {
10133 dev_err(&pdev->dev, "Can not assign irq %d\n", irq);
10134 return rc;
10135 } else if (ipr_debug)
10136 dev_info(&pdev->dev, "IRQ assigned: %d\n", irq);
10137
10138 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
10139 readl(ioa_cfg->regs.sense_interrupt_reg);
10140 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
10141 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10142 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10143
10144 if (!ioa_cfg->msi_received) {
10145
10146 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
10147 rc = -EOPNOTSUPP;
10148 } else if (ipr_debug)
10149 dev_info(&pdev->dev, "MSI test succeeded.\n");
10150
10151 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10152
10153 free_irq(irq, ioa_cfg);
10154
10155 LEAVE;
10156
10157 return rc;
10158}
10159
10160
10161
10162
10163
10164
10165
10166
10167static int ipr_probe_ioa(struct pci_dev *pdev,
10168 const struct pci_device_id *dev_id)
10169{
10170 struct ipr_ioa_cfg *ioa_cfg;
10171 struct Scsi_Host *host;
10172 unsigned long ipr_regs_pci;
10173 void __iomem *ipr_regs;
10174 int rc = PCIBIOS_SUCCESSFUL;
10175 volatile u32 mask, uproc, interrupts;
10176 unsigned long lock_flags, driver_lock_flags;
10177 unsigned int irq_flag;
10178
10179 ENTER;
10180
10181 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
10182 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
10183
10184 if (!host) {
10185 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
10186 rc = -ENOMEM;
10187 goto out;
10188 }
10189
10190 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
10191 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
10192 ata_host_init(&ioa_cfg->ata_host, &pdev->dev, &ipr_sata_ops);
10193
10194 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
10195
10196 if (!ioa_cfg->ipr_chip) {
10197 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
10198 dev_id->vendor, dev_id->device);
10199 goto out_scsi_host_put;
10200 }
10201
10202
10203 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
10204 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
10205 ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
10206 ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
10207
10208 if (ipr_transop_timeout)
10209 ioa_cfg->transop_timeout = ipr_transop_timeout;
10210 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
10211 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
10212 else
10213 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
10214
10215 ioa_cfg->revid = pdev->revision;
10216
10217 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
10218
10219 ipr_regs_pci = pci_resource_start(pdev, 0);
10220
10221 rc = pci_request_regions(pdev, IPR_NAME);
10222 if (rc < 0) {
10223 dev_err(&pdev->dev,
10224 "Couldn't register memory range of registers\n");
10225 goto out_scsi_host_put;
10226 }
10227
10228 rc = pci_enable_device(pdev);
10229
10230 if (rc || pci_channel_offline(pdev)) {
10231 if (pci_channel_offline(pdev)) {
10232 ipr_wait_for_pci_err_recovery(ioa_cfg);
10233 rc = pci_enable_device(pdev);
10234 }
10235
10236 if (rc) {
10237 dev_err(&pdev->dev, "Cannot enable adapter\n");
10238 ipr_wait_for_pci_err_recovery(ioa_cfg);
10239 goto out_release_regions;
10240 }
10241 }
10242
10243 ipr_regs = pci_ioremap_bar(pdev, 0);
10244
10245 if (!ipr_regs) {
10246 dev_err(&pdev->dev,
10247 "Couldn't map memory range of registers\n");
10248 rc = -ENOMEM;
10249 goto out_disable;
10250 }
10251
10252 ioa_cfg->hdw_dma_regs = ipr_regs;
10253 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
10254 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
10255
10256 ipr_init_regs(ioa_cfg);
10257
10258 if (ioa_cfg->sis64) {
10259 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10260 if (rc < 0) {
10261 dev_dbg(&pdev->dev, "Failed to set 64 bit DMA mask\n");
10262 rc = dma_set_mask_and_coherent(&pdev->dev,
10263 DMA_BIT_MASK(32));
10264 }
10265 } else
10266 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10267
10268 if (rc < 0) {
10269 dev_err(&pdev->dev, "Failed to set DMA mask\n");
10270 goto cleanup_nomem;
10271 }
10272
10273 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
10274 ioa_cfg->chip_cfg->cache_line_size);
10275
10276 if (rc != PCIBIOS_SUCCESSFUL) {
10277 dev_err(&pdev->dev, "Write of cache line size failed\n");
10278 ipr_wait_for_pci_err_recovery(ioa_cfg);
10279 rc = -EIO;
10280 goto cleanup_nomem;
10281 }
10282
10283
10284 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg);
10285 ipr_wait_for_pci_err_recovery(ioa_cfg);
10286
10287 if (ipr_number_of_msix > IPR_MAX_MSIX_VECTORS) {
10288 dev_err(&pdev->dev, "The max number of MSIX is %d\n",
10289 IPR_MAX_MSIX_VECTORS);
10290 ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
10291 }
10292
10293 irq_flag = PCI_IRQ_LEGACY;
10294 if (ioa_cfg->ipr_chip->has_msi)
10295 irq_flag |= PCI_IRQ_MSI | PCI_IRQ_MSIX;
10296 rc = pci_alloc_irq_vectors(pdev, 1, ipr_number_of_msix, irq_flag);
10297 if (rc < 0) {
10298 ipr_wait_for_pci_err_recovery(ioa_cfg);
10299 goto cleanup_nomem;
10300 }
10301 ioa_cfg->nvectors = rc;
10302
10303 if (!pdev->msi_enabled && !pdev->msix_enabled)
10304 ioa_cfg->clear_isr = 1;
10305
10306 pci_set_master(pdev);
10307
10308 if (pci_channel_offline(pdev)) {
10309 ipr_wait_for_pci_err_recovery(ioa_cfg);
10310 pci_set_master(pdev);
10311 if (pci_channel_offline(pdev)) {
10312 rc = -EIO;
10313 goto out_msi_disable;
10314 }
10315 }
10316
10317 if (pdev->msi_enabled || pdev->msix_enabled) {
10318 rc = ipr_test_msi(ioa_cfg, pdev);
10319 switch (rc) {
10320 case 0:
10321 dev_info(&pdev->dev,
10322 "Request for %d MSI%ss succeeded.", ioa_cfg->nvectors,
10323 pdev->msix_enabled ? "-X" : "");
10324 break;
10325 case -EOPNOTSUPP:
10326 ipr_wait_for_pci_err_recovery(ioa_cfg);
10327 pci_free_irq_vectors(pdev);
10328
10329 ioa_cfg->nvectors = 1;
10330 ioa_cfg->clear_isr = 1;
10331 break;
10332 default:
10333 goto out_msi_disable;
10334 }
10335 }
10336
10337 ioa_cfg->hrrq_num = min3(ioa_cfg->nvectors,
10338 (unsigned int)num_online_cpus(),
10339 (unsigned int)IPR_MAX_HRRQ_NUM);
10340
10341 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
10342 goto out_msi_disable;
10343
10344 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
10345 goto out_msi_disable;
10346
10347 rc = ipr_alloc_mem(ioa_cfg);
10348 if (rc < 0) {
10349 dev_err(&pdev->dev,
10350 "Couldn't allocate enough memory for device driver!\n");
10351 goto out_msi_disable;
10352 }
10353
10354
10355 rc = pci_save_state(pdev);
10356
10357 if (rc != PCIBIOS_SUCCESSFUL) {
10358 dev_err(&pdev->dev, "Failed to save PCI config space\n");
10359 rc = -EIO;
10360 goto cleanup_nolog;
10361 }
10362
10363
10364
10365
10366
10367 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
10368 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
10369 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
10370 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
10371 ioa_cfg->needs_hard_reset = 1;
10372 if ((interrupts & IPR_PCII_ERROR_INTERRUPTS) || reset_devices)
10373 ioa_cfg->needs_hard_reset = 1;
10374 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
10375 ioa_cfg->ioa_unit_checked = 1;
10376
10377 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10378 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10379 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10380
10381 if (pdev->msi_enabled || pdev->msix_enabled) {
10382 name_msi_vectors(ioa_cfg);
10383 rc = request_irq(pci_irq_vector(pdev, 0), ipr_isr, 0,
10384 ioa_cfg->vectors_info[0].desc,
10385 &ioa_cfg->hrrq[0]);
10386 if (!rc)
10387 rc = ipr_request_other_msi_irqs(ioa_cfg, pdev);
10388 } else {
10389 rc = request_irq(pdev->irq, ipr_isr,
10390 IRQF_SHARED,
10391 IPR_NAME, &ioa_cfg->hrrq[0]);
10392 }
10393 if (rc) {
10394 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
10395 pdev->irq, rc);
10396 goto cleanup_nolog;
10397 }
10398
10399 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
10400 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
10401 ioa_cfg->needs_warm_reset = 1;
10402 ioa_cfg->reset = ipr_reset_slot_reset;
10403
10404 ioa_cfg->reset_work_q = alloc_ordered_workqueue("ipr_reset_%d",
10405 WQ_MEM_RECLAIM, host->host_no);
10406
10407 if (!ioa_cfg->reset_work_q) {
10408 dev_err(&pdev->dev, "Couldn't register reset workqueue\n");
10409 rc = -ENOMEM;
10410 goto out_free_irq;
10411 }
10412 } else
10413 ioa_cfg->reset = ipr_reset_start_bist;
10414
10415 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10416 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
10417 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10418
10419 LEAVE;
10420out:
10421 return rc;
10422
10423out_free_irq:
10424 ipr_free_irqs(ioa_cfg);
10425cleanup_nolog:
10426 ipr_free_mem(ioa_cfg);
10427out_msi_disable:
10428 ipr_wait_for_pci_err_recovery(ioa_cfg);
10429 pci_free_irq_vectors(pdev);
10430cleanup_nomem:
10431 iounmap(ipr_regs);
10432out_disable:
10433 pci_disable_device(pdev);
10434out_release_regions:
10435 pci_release_regions(pdev);
10436out_scsi_host_put:
10437 scsi_host_put(host);
10438 goto out;
10439}
10440
10441
10442
10443
10444
10445
10446
10447
10448
10449
10450
10451
10452
10453
10454
10455static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
10456 enum ipr_shutdown_type shutdown_type)
10457{
10458 ENTER;
10459 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
10460 ioa_cfg->sdt_state = ABORT_DUMP;
10461 ioa_cfg->reset_retries = 0;
10462 ioa_cfg->in_ioa_bringdown = 1;
10463 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
10464 LEAVE;
10465}
10466
10467
10468
10469
10470
10471
10472
10473
10474
10475
10476static void __ipr_remove(struct pci_dev *pdev)
10477{
10478 unsigned long host_lock_flags = 0;
10479 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10480 int i;
10481 unsigned long driver_lock_flags;
10482 ENTER;
10483
10484 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10485 while (ioa_cfg->in_reset_reload) {
10486 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10487 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10488 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10489 }
10490
10491 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
10492 spin_lock(&ioa_cfg->hrrq[i]._lock);
10493 ioa_cfg->hrrq[i].removing_ioa = 1;
10494 spin_unlock(&ioa_cfg->hrrq[i]._lock);
10495 }
10496 wmb();
10497 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
10498
10499 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10500 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10501 flush_work(&ioa_cfg->work_q);
10502 if (ioa_cfg->reset_work_q)
10503 flush_workqueue(ioa_cfg->reset_work_q);
10504 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
10505 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10506
10507 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10508 list_del(&ioa_cfg->queue);
10509 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10510
10511 if (ioa_cfg->sdt_state == ABORT_DUMP)
10512 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
10513 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10514
10515 ipr_free_all_resources(ioa_cfg);
10516
10517 LEAVE;
10518}
10519
10520
10521
10522
10523
10524
10525
10526
10527
10528
10529static void ipr_remove(struct pci_dev *pdev)
10530{
10531 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10532
10533 ENTER;
10534
10535 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10536 &ipr_trace_attr);
10537 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
10538 &ipr_dump_attr);
10539 sysfs_remove_bin_file(&ioa_cfg->host->shost_dev.kobj,
10540 &ipr_ioa_async_err_log);
10541 scsi_remove_host(ioa_cfg->host);
10542
10543 __ipr_remove(pdev);
10544
10545 LEAVE;
10546}
10547
10548
10549
10550
10551
10552
10553
10554
10555
10556static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
10557{
10558 struct ipr_ioa_cfg *ioa_cfg;
10559 unsigned long flags;
10560 int rc, i;
10561
10562 rc = ipr_probe_ioa(pdev, dev_id);
10563
10564 if (rc)
10565 return rc;
10566
10567 ioa_cfg = pci_get_drvdata(pdev);
10568 rc = ipr_probe_ioa_part2(ioa_cfg);
10569
10570 if (rc) {
10571 __ipr_remove(pdev);
10572 return rc;
10573 }
10574
10575 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
10576
10577 if (rc) {
10578 __ipr_remove(pdev);
10579 return rc;
10580 }
10581
10582 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
10583 &ipr_trace_attr);
10584
10585 if (rc) {
10586 scsi_remove_host(ioa_cfg->host);
10587 __ipr_remove(pdev);
10588 return rc;
10589 }
10590
10591 rc = sysfs_create_bin_file(&ioa_cfg->host->shost_dev.kobj,
10592 &ipr_ioa_async_err_log);
10593
10594 if (rc) {
10595 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
10596 &ipr_dump_attr);
10597 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10598 &ipr_trace_attr);
10599 scsi_remove_host(ioa_cfg->host);
10600 __ipr_remove(pdev);
10601 return rc;
10602 }
10603
10604 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
10605 &ipr_dump_attr);
10606
10607 if (rc) {
10608 sysfs_remove_bin_file(&ioa_cfg->host->shost_dev.kobj,
10609 &ipr_ioa_async_err_log);
10610 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10611 &ipr_trace_attr);
10612 scsi_remove_host(ioa_cfg->host);
10613 __ipr_remove(pdev);
10614 return rc;
10615 }
10616 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10617 ioa_cfg->scan_enabled = 1;
10618 schedule_work(&ioa_cfg->work_q);
10619 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10620
10621 ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
10622
10623 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10624 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
10625 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
10626 ioa_cfg->iopoll_weight, ipr_iopoll);
10627 }
10628 }
10629
10630 scsi_scan_host(ioa_cfg->host);
10631
10632 return 0;
10633}
10634
10635
10636
10637
10638
10639
10640
10641
10642
10643
10644
10645static void ipr_shutdown(struct pci_dev *pdev)
10646{
10647 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10648 unsigned long lock_flags = 0;
10649 enum ipr_shutdown_type shutdown_type = IPR_SHUTDOWN_NORMAL;
10650 int i;
10651
10652 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10653 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10654 ioa_cfg->iopoll_weight = 0;
10655 for (i = 1; i < ioa_cfg->hrrq_num; i++)
10656 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
10657 }
10658
10659 while (ioa_cfg->in_reset_reload) {
10660 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10661 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10662 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10663 }
10664
10665 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64)
10666 shutdown_type = IPR_SHUTDOWN_QUIESCE;
10667
10668 ipr_initiate_ioa_bringdown(ioa_cfg, shutdown_type);
10669 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10670 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10671 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64) {
10672 ipr_free_irqs(ioa_cfg);
10673 pci_disable_device(ioa_cfg->pdev);
10674 }
10675}
10676
10677static struct pci_device_id ipr_pci_table[] = {
10678 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10679 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
10680 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10681 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
10682 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10683 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
10684 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10685 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
10686 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10687 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
10688 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10689 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
10690 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10691 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
10692 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10693 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
10694 IPR_USE_LONG_TRANSOP_TIMEOUT },
10695 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10696 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10697 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10698 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10699 IPR_USE_LONG_TRANSOP_TIMEOUT },
10700 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10701 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10702 IPR_USE_LONG_TRANSOP_TIMEOUT },
10703 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10704 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10705 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10706 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10707 IPR_USE_LONG_TRANSOP_TIMEOUT},
10708 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10709 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10710 IPR_USE_LONG_TRANSOP_TIMEOUT },
10711 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10712 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
10713 IPR_USE_LONG_TRANSOP_TIMEOUT },
10714 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10715 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
10716 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10717 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
10718 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10719 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
10720 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
10721 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
10722 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
10723 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10724 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
10725 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10726 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
10727 IPR_USE_LONG_TRANSOP_TIMEOUT },
10728 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10729 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
10730 IPR_USE_LONG_TRANSOP_TIMEOUT },
10731 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10732 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
10733 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10734 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
10735 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10736 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
10737 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10738 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C0, 0, 0, 0 },
10739 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10740 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },
10741 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10742 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
10743 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10744 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
10745 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10746 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
10747 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10748 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
10749 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10750 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },
10751 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10752 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
10753 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10754 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D5, 0, 0, 0 },
10755 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10756 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D6, 0, 0, 0 },
10757 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10758 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D7, 0, 0, 0 },
10759 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10760 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D8, 0, 0, 0 },
10761 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10762 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D9, 0, 0, 0 },
10763 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10764 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57DA, 0, 0, 0 },
10765 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10766 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EB, 0, 0, 0 },
10767 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10768 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EC, 0, 0, 0 },
10769 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10770 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57ED, 0, 0, 0 },
10771 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10772 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EE, 0, 0, 0 },
10773 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10774 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EF, 0, 0, 0 },
10775 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10776 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57F0, 0, 0, 0 },
10777 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10778 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCA, 0, 0, 0 },
10779 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10780 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CD2, 0, 0, 0 },
10781 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10782 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCD, 0, 0, 0 },
10783 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10784 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580A, 0, 0, 0 },
10785 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10786 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580B, 0, 0, 0 },
10787 { }
10788};
10789MODULE_DEVICE_TABLE(pci, ipr_pci_table);
10790
10791static const struct pci_error_handlers ipr_err_handler = {
10792 .error_detected = ipr_pci_error_detected,
10793 .mmio_enabled = ipr_pci_mmio_enabled,
10794 .slot_reset = ipr_pci_slot_reset,
10795};
10796
10797static struct pci_driver ipr_driver = {
10798 .name = IPR_NAME,
10799 .id_table = ipr_pci_table,
10800 .probe = ipr_probe,
10801 .remove = ipr_remove,
10802 .shutdown = ipr_shutdown,
10803 .err_handler = &ipr_err_handler,
10804};
10805
10806
10807
10808
10809
10810
10811
10812
10813static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
10814{
10815 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
10816}
10817
10818
10819
10820
10821
10822
10823
10824
10825
10826
10827static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
10828{
10829 struct ipr_cmnd *ipr_cmd;
10830 struct ipr_ioa_cfg *ioa_cfg;
10831 unsigned long flags = 0, driver_lock_flags;
10832
10833 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
10834 return NOTIFY_DONE;
10835
10836 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10837
10838 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
10839 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10840 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
10841 (ipr_fast_reboot && event == SYS_RESTART && ioa_cfg->sis64)) {
10842 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10843 continue;
10844 }
10845
10846 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
10847 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
10848 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
10849 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
10850 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
10851
10852 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
10853 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10854 }
10855 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10856
10857 return NOTIFY_OK;
10858}
10859
10860static struct notifier_block ipr_notifier = {
10861 ipr_halt, NULL, 0
10862};
10863
10864
10865
10866
10867
10868
10869
10870static int __init ipr_init(void)
10871{
10872 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
10873 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
10874
10875 register_reboot_notifier(&ipr_notifier);
10876 return pci_register_driver(&ipr_driver);
10877}
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887static void __exit ipr_exit(void)
10888{
10889 unregister_reboot_notifier(&ipr_notifier);
10890 pci_unregister_driver(&ipr_driver);
10891}
10892
10893module_init(ipr_init);
10894module_exit(ipr_exit);
10895
