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20#ifndef _MEGARAID_SAS_FUSION_H_
21#define _MEGARAID_SAS_FUSION_H_
22
23
24#define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
25#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
26#define MEGASAS_MAX_CHAIN_SHIFT 5
27#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
28#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
29#define MEGASAS_256K_IO 128
30#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
31#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
32#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
33#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
34#define MEGASAS_LOAD_BALANCE_FLAG 0x1
35#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
36#define HOST_DIAG_WRITE_ENABLE 0x80
37#define HOST_DIAG_RESET_ADAPTER 0x4
38#define MEGASAS_FUSION_MAX_RESET_TRIES 3
39#define MAX_MSIX_QUEUES_FUSION 128
40#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
41#define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
42
43
44#define MPI2_TYPE_CUDA 0x2
45#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
46#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
47#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
48#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
49#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
50#define MR_RL_WRITE_THROUGH_MODE 0x00
51#define MR_RL_WRITE_BACK_MODE 0x01
52
53
54#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
55#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
56#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
57#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
58#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
59#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
60#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
61
62#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
63#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
64
65
66
67
68
69#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
70#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
71enum MR_RAID_FLAGS_IO_SUB_TYPE {
72 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
73 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
74 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
75 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
76 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
77 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
78 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7,
79 MR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD = 8
80};
81
82
83
84
85#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
86#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
87#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
88#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
89
90#define MEGASAS_FP_CMD_LEN 16
91#define MEGASAS_FUSION_IN_RESET 0
92#define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
93#define RAID_1_PEER_CMDS 2
94#define JBOD_MAPS_COUNT 2
95#define MEGASAS_REDUCE_QD_COUNT 64
96#define IOC_INIT_FRAME_SIZE 4096
97
98
99
100
101
102
103struct RAID_CONTEXT {
104#if defined(__BIG_ENDIAN_BITFIELD)
105 u8 nseg:4;
106 u8 type:4;
107#else
108 u8 type:4;
109 u8 nseg:4;
110#endif
111 u8 resvd0;
112 __le16 timeout_value;
113 u8 reg_lock_flags;
114 u8 resvd1;
115 __le16 virtual_disk_tgt_id;
116 __le64 reg_lock_row_lba;
117 __le32 reg_lock_length;
118 __le16 next_lmid;
119 u8 ex_status;
120 u8 status;
121 u8 raid_flags;
122 u8 num_sge;
123 __le16 config_seq_num;
124 u8 span_arm;
125 u8 priority;
126 u8 num_sge_ext;
127 u8 resvd2;
128};
129
130
131
132
133
134
135struct RAID_CONTEXT_G35 {
136 #define RAID_CONTEXT_NSEG_MASK 0x00F0
137 #define RAID_CONTEXT_NSEG_SHIFT 4
138 #define RAID_CONTEXT_TYPE_MASK 0x000F
139 #define RAID_CONTEXT_TYPE_SHIFT 0
140 u16 nseg_type;
141 u16 timeout_value;
142 u16 routing_flags;
143 u16 virtual_disk_tgt_id;
144 __le64 reg_lock_row_lba;
145 u32 reg_lock_length;
146 union {
147 u16 rmw_op_index;
148 u16 peer_smid;
149 u16 r56_arm_map;
150
151 } flow_specific;
152
153 u8 ex_status;
154 u8 status;
155 u8 raid_flags;
156
157
158 u8 span_arm;
159 u16 config_seq_num;
160 union {
161
162
163
164
165
166
167
168
169
170
171 #define NUM_SGE_MASK_LOWER 0xFF
172 #define NUM_SGE_MASK_UPPER 0x0F
173 #define NUM_SGE_SHIFT_UPPER 8
174 #define STREAM_DETECT_SHIFT 7
175 #define STREAM_DETECT_MASK 0x80
176 struct {
177#if defined(__BIG_ENDIAN_BITFIELD)
178 u16 stream_detected:1;
179 u16 reserved:3;
180 u16 num_sge:12;
181#else
182 u16 num_sge:12;
183 u16 reserved:3;
184 u16 stream_detected:1;
185#endif
186 } bits;
187 u8 bytes[2];
188 } u;
189 u8 resvd2[2];
190};
191
192#define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
193#define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
194#define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
195#define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
196#define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
197#define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
198#define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
199#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
200#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
201#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
202#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
203
204static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
205 u16 sge_count)
206{
207 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
208 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
209 & NUM_SGE_MASK_UPPER);
210}
211
212static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
213{
214 u16 sge_count;
215
216 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
217 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
218 return sge_count;
219}
220
221#define SET_STREAM_DETECTED(rctx_g35) \
222 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
223
224#define CLEAR_STREAM_DETECTED(rctx_g35) \
225 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
226
227static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
228{
229 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
230}
231
232union RAID_CONTEXT_UNION {
233 struct RAID_CONTEXT raid_context;
234 struct RAID_CONTEXT_G35 raid_context_g35;
235};
236
237#define RAID_CTX_SPANARM_ARM_SHIFT (0)
238#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
239
240#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
241#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
242
243
244#define RAID_CTX_R56_Q_ARM_MASK (0x1F)
245#define RAID_CTX_R56_P_ARM_SHIFT (5)
246#define RAID_CTX_R56_P_ARM_MASK (0x3E0)
247#define RAID_CTX_R56_LOG_ARM_SHIFT (10)
248#define RAID_CTX_R56_LOG_ARM_MASK (0x7C00)
249
250
251#define BITS_PER_INDEX_STREAM 4
252#define INVALID_STREAM_NUM 16
253#define MR_STREAM_BITMAP 0x76543210
254#define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
255#define ZERO_LAST_STREAM 0x0fffffff
256#define MAX_STREAMS_TRACKED 8
257
258
259
260
261enum REGION_TYPE {
262 REGION_TYPE_UNUSED = 0,
263 REGION_TYPE_SHARED_READ = 1,
264 REGION_TYPE_SHARED_WRITE = 2,
265 REGION_TYPE_EXCLUSIVE = 3,
266};
267
268
269#define MPI2_FUNCTION_IOC_INIT (0x02)
270#define MPI2_WHOINIT_HOST_DRIVER (0x04)
271#define MPI2_VERSION_MAJOR (0x02)
272#define MPI2_VERSION_MINOR (0x00)
273#define MPI2_VERSION_MAJOR_MASK (0xFF00)
274#define MPI2_VERSION_MAJOR_SHIFT (8)
275#define MPI2_VERSION_MINOR_MASK (0x00FF)
276#define MPI2_VERSION_MINOR_SHIFT (0)
277#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
278 MPI2_VERSION_MINOR)
279#define MPI2_HEADER_VERSION_UNIT (0x10)
280#define MPI2_HEADER_VERSION_DEV (0x00)
281#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
282#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
283#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
284#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
285#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
286 MPI2_HEADER_VERSION_DEV)
287#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
288#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
289#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
290#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
291#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
292#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
293#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
294
295#define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
296#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
297#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
298#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
299#define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
300#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
301#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
302#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
303#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
304#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
305#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
306#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
307#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
308#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
309#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
310#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
311#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
312#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
313#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
314#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
315#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
316
317struct MPI25_IEEE_SGE_CHAIN64 {
318 __le64 Address;
319 __le32 Length;
320 __le16 Reserved1;
321 u8 NextChainOffset;
322 u8 Flags;
323};
324
325struct MPI2_SGE_SIMPLE_UNION {
326 __le32 FlagsLength;
327 union {
328 __le32 Address32;
329 __le64 Address64;
330 } u;
331};
332
333struct MPI2_SCSI_IO_CDB_EEDP32 {
334 u8 CDB[20];
335 __be32 PrimaryReferenceTag;
336 __be16 PrimaryApplicationTag;
337 __be16 PrimaryApplicationTagMask;
338 __le32 TransferLength;
339};
340
341struct MPI2_SGE_CHAIN_UNION {
342 __le16 Length;
343 u8 NextChainOffset;
344 u8 Flags;
345 union {
346 __le32 Address32;
347 __le64 Address64;
348 } u;
349};
350
351struct MPI2_IEEE_SGE_SIMPLE32 {
352 __le32 Address;
353 __le32 FlagsLength;
354};
355
356struct MPI2_IEEE_SGE_CHAIN32 {
357 __le32 Address;
358 __le32 FlagsLength;
359};
360
361struct MPI2_IEEE_SGE_SIMPLE64 {
362 __le64 Address;
363 __le32 Length;
364 __le16 Reserved1;
365 u8 Reserved2;
366 u8 Flags;
367};
368
369struct MPI2_IEEE_SGE_CHAIN64 {
370 __le64 Address;
371 __le32 Length;
372 __le16 Reserved1;
373 u8 Reserved2;
374 u8 Flags;
375};
376
377union MPI2_IEEE_SGE_SIMPLE_UNION {
378 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
379 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
380};
381
382union MPI2_IEEE_SGE_CHAIN_UNION {
383 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
384 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
385};
386
387union MPI2_SGE_IO_UNION {
388 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
389 struct MPI2_SGE_CHAIN_UNION MpiChain;
390 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
391 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
392};
393
394union MPI2_SCSI_IO_CDB_UNION {
395 u8 CDB32[32];
396 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
397 struct MPI2_SGE_SIMPLE_UNION SGE;
398};
399
400
401
402
403
404
405struct MPI2_SCSI_TASK_MANAGE_REQUEST {
406 u16 DevHandle;
407 u8 ChainOffset;
408 u8 Function;
409 u8 Reserved1;
410 u8 TaskType;
411 u8 Reserved2;
412 u8 MsgFlags;
413 u8 VP_ID;
414 u8 VF_ID;
415 u16 Reserved3;
416 u8 LUN[8];
417 u32 Reserved4[7];
418 u16 TaskMID;
419 u16 Reserved5;
420};
421
422
423
424struct MPI2_SCSI_TASK_MANAGE_REPLY {
425 u16 DevHandle;
426 u8 MsgLength;
427 u8 Function;
428 u8 ResponseCode;
429 u8 TaskType;
430 u8 Reserved1;
431 u8 MsgFlags;
432 u8 VP_ID;
433 u8 VF_ID;
434 u16 Reserved2;
435 u16 Reserved3;
436 u16 IOCStatus;
437 u32 IOCLogInfo;
438 u32 TerminationCount;
439 u32 ResponseInfo;
440};
441
442struct MR_TM_REQUEST {
443 char request[128];
444};
445
446struct MR_TM_REPLY {
447 char reply[128];
448};
449
450
451struct MR_TASK_MANAGE_REQUEST {
452
453 struct MR_TM_REQUEST TmRequest;
454 union {
455 struct {
456#if defined(__BIG_ENDIAN_BITFIELD)
457 u32 reserved1:30;
458 u32 isTMForPD:1;
459 u32 isTMForLD:1;
460#else
461 u32 isTMForLD:1;
462 u32 isTMForPD:1;
463 u32 reserved1:30;
464#endif
465 u32 reserved2;
466 } tmReqFlags;
467 struct MR_TM_REPLY TMReply;
468 };
469};
470
471
472
473#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
474#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
475#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
476#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
477#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
478#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
479#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
480#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
481#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
482
483
484
485#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
486#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
487#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
488#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
489#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
490#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
491#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
492#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
493
494
495
496
497
498struct MPI2_RAID_SCSI_IO_REQUEST {
499 __le16 DevHandle;
500 u8 ChainOffset;
501 u8 Function;
502 __le16 Reserved1;
503 u8 Reserved2;
504 u8 MsgFlags;
505 u8 VP_ID;
506 u8 VF_ID;
507 __le16 Reserved3;
508 __le32 SenseBufferLowAddress;
509 __le16 SGLFlags;
510 u8 SenseBufferLength;
511 u8 Reserved4;
512 u8 SGLOffset0;
513 u8 SGLOffset1;
514 u8 SGLOffset2;
515 u8 SGLOffset3;
516 __le32 SkipCount;
517 __le32 DataLength;
518 __le32 BidirectionalDataLength;
519 __le16 IoFlags;
520 __le16 EEDPFlags;
521 __le32 EEDPBlockSize;
522 __le32 SecondaryReferenceTag;
523 __le16 SecondaryApplicationTag;
524 __le16 ApplicationTagTranslationMask;
525 u8 LUN[8];
526 __le32 Control;
527 union MPI2_SCSI_IO_CDB_UNION CDB;
528 union RAID_CONTEXT_UNION RaidContext;
529 union MPI2_SGE_IO_UNION SGL;
530};
531
532
533
534
535struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
536 u32 RequestFlags:8;
537 u32 MessageAddress1:24;
538 u32 MessageAddress2;
539};
540
541
542struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
543 u8 RequestFlags;
544 u8 MSIxIndex;
545 __le16 SMID;
546 __le16 LMID;
547 __le16 DescriptorTypeDependent;
548};
549
550
551struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
552 u8 RequestFlags;
553 u8 MSIxIndex;
554 __le16 SMID;
555 __le16 LMID;
556 __le16 Reserved1;
557};
558
559
560struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
561 u8 RequestFlags;
562 u8 MSIxIndex;
563 __le16 SMID;
564 __le16 LMID;
565 __le16 DevHandle;
566};
567
568
569struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
570 u8 RequestFlags;
571 u8 MSIxIndex;
572 __le16 SMID;
573 __le16 LMID;
574 __le16 IoIndex;
575};
576
577
578struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
579 u8 RequestFlags;
580 u8 MSIxIndex;
581 __le16 SMID;
582 __le16 LMID;
583 __le16 Reserved;
584};
585
586
587union MEGASAS_REQUEST_DESCRIPTOR_UNION {
588 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
589 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
590 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
591 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
592 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
593 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
594 union {
595 struct {
596 __le32 low;
597 __le32 high;
598 } u;
599 __le64 Words;
600 };
601};
602
603
604struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
605 u8 ReplyFlags;
606 u8 MSIxIndex;
607 __le16 DescriptorTypeDependent1;
608 __le32 DescriptorTypeDependent2;
609};
610
611
612struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
613 u8 ReplyFlags;
614 u8 MSIxIndex;
615 __le16 SMID;
616 __le32 ReplyFrameAddress;
617};
618
619
620struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
621 u8 ReplyFlags;
622 u8 MSIxIndex;
623 __le16 SMID;
624 __le16 TaskTag;
625 __le16 Reserved1;
626};
627
628
629struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
630 u8 ReplyFlags;
631 u8 MSIxIndex;
632 __le16 SMID;
633 u8 SequenceNumber;
634 u8 Reserved1;
635 __le16 IoIndex;
636};
637
638
639struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
640 u8 ReplyFlags;
641 u8 MSIxIndex;
642 u8 VP_ID;
643 u8 Flags;
644 __le16 InitiatorDevHandle;
645 __le16 IoIndex;
646};
647
648
649struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
650 u8 ReplyFlags;
651 u8 MSIxIndex;
652 __le16 SMID;
653 __le32 Reserved;
654};
655
656
657union MPI2_REPLY_DESCRIPTORS_UNION {
658 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
659 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
660 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
661 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
662 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
663 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
664 RAIDAcceleratorSuccess;
665 __le64 Words;
666};
667
668
669struct MPI2_IOC_INIT_REQUEST {
670 u8 WhoInit;
671 u8 Reserved1;
672 u8 ChainOffset;
673 u8 Function;
674 __le16 Reserved2;
675 u8 Reserved3;
676 u8 MsgFlags;
677 u8 VP_ID;
678 u8 VF_ID;
679 __le16 Reserved4;
680 __le16 MsgVersion;
681 __le16 HeaderVersion;
682 u32 Reserved5;
683 __le16 Reserved6;
684 u8 HostPageSize;
685 u8 HostMSIxVectors;
686 __le16 Reserved8;
687 __le16 SystemRequestFrameSize;
688 __le16 ReplyDescriptorPostQueueDepth;
689 __le16 ReplyFreeQueueDepth;
690 __le32 SenseBufferAddressHigh;
691 __le32 SystemReplyAddressHigh;
692 __le64 SystemRequestFrameBaseAddress;
693 __le64 ReplyDescriptorPostQueueAddress;
694 __le64 ReplyFreeQueueAddress;
695 __le64 TimeStamp;
696};
697
698
699#define MR_PD_INVALID 0xFFFF
700#define MR_DEVHANDLE_INVALID 0xFFFF
701#define MAX_SPAN_DEPTH 8
702#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
703#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
704#define MAX_ROW_SIZE 32
705#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
706#define MAX_LOGICAL_DRIVES 64
707#define MAX_LOGICAL_DRIVES_EXT 256
708#define MAX_LOGICAL_DRIVES_DYN 512
709#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
710#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
711#define MAX_ARRAYS 128
712#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
713#define MAX_ARRAYS_EXT 256
714#define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
715#define MAX_API_ARRAYS_DYN 512
716#define MAX_PHYSICAL_DEVICES 256
717#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
718#define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
719#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
720#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
721#define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
722#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485
723#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
724#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
725#define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES 0x01200100
726#define MR_DCMD_CTRL_DEVICE_LIST_GET 0x01190600
727
728struct MR_DEV_HANDLE_INFO {
729 __le16 curDevHdl;
730 u8 validHandles;
731 u8 interfaceType;
732 __le16 devHandle[2];
733};
734
735struct MR_ARRAY_INFO {
736 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
737};
738
739struct MR_QUAD_ELEMENT {
740 __le64 logStart;
741 __le64 logEnd;
742 __le64 offsetInSpan;
743 __le32 diff;
744 __le32 reserved1;
745};
746
747struct MR_SPAN_INFO {
748 __le32 noElements;
749 __le32 reserved1;
750 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
751};
752
753struct MR_LD_SPAN {
754 __le64 startBlk;
755 __le64 numBlks;
756 __le16 arrayRef;
757 u8 spanRowSize;
758 u8 spanRowDataSize;
759 u8 reserved[4];
760};
761
762struct MR_SPAN_BLOCK_INFO {
763 __le64 num_rows;
764 struct MR_LD_SPAN span;
765 struct MR_SPAN_INFO block_span_info;
766};
767
768#define MR_RAID_CTX_CPUSEL_0 0
769#define MR_RAID_CTX_CPUSEL_1 1
770#define MR_RAID_CTX_CPUSEL_2 2
771#define MR_RAID_CTX_CPUSEL_3 3
772#define MR_RAID_CTX_CPUSEL_FCFS 0xF
773
774struct MR_CPU_AFFINITY_MASK {
775 union {
776 struct {
777#ifndef __BIG_ENDIAN_BITFIELD
778 u8 hw_path:1;
779 u8 cpu0:1;
780 u8 cpu1:1;
781 u8 cpu2:1;
782 u8 cpu3:1;
783 u8 reserved:3;
784#else
785 u8 reserved:3;
786 u8 cpu3:1;
787 u8 cpu2:1;
788 u8 cpu1:1;
789 u8 cpu0:1;
790 u8 hw_path:1;
791#endif
792 };
793 u8 core_mask;
794 };
795};
796
797struct MR_IO_AFFINITY {
798 union {
799 struct {
800 struct MR_CPU_AFFINITY_MASK pdRead;
801 struct MR_CPU_AFFINITY_MASK pdWrite;
802 struct MR_CPU_AFFINITY_MASK ldRead;
803 struct MR_CPU_AFFINITY_MASK ldWrite;
804 };
805 u32 word;
806 };
807 u8 maxCores;
808 u8 reserved[3];
809};
810
811struct MR_LD_RAID {
812 struct {
813#if defined(__BIG_ENDIAN_BITFIELD)
814 u32 reserved4:2;
815 u32 fp_cache_bypass_capable:1;
816 u32 fp_rmw_capable:1;
817 u32 disable_coalescing:1;
818 u32 fpBypassRegionLock:1;
819 u32 tmCapable:1;
820 u32 fpNonRWCapable:1;
821 u32 fpReadAcrossStripe:1;
822 u32 fpWriteAcrossStripe:1;
823 u32 fpReadCapable:1;
824 u32 fpWriteCapable:1;
825 u32 encryptionType:8;
826 u32 pdPiMode:4;
827 u32 ldPiMode:4;
828 u32 reserved5:2;
829 u32 ra_capable:1;
830 u32 fpCapable:1;
831#else
832 u32 fpCapable:1;
833 u32 ra_capable:1;
834 u32 reserved5:2;
835 u32 ldPiMode:4;
836 u32 pdPiMode:4;
837 u32 encryptionType:8;
838 u32 fpWriteCapable:1;
839 u32 fpReadCapable:1;
840 u32 fpWriteAcrossStripe:1;
841 u32 fpReadAcrossStripe:1;
842 u32 fpNonRWCapable:1;
843 u32 tmCapable:1;
844 u32 fpBypassRegionLock:1;
845 u32 disable_coalescing:1;
846 u32 fp_rmw_capable:1;
847 u32 fp_cache_bypass_capable:1;
848 u32 reserved4:2;
849#endif
850 } capability;
851 __le32 reserved6;
852 __le64 size;
853 u8 spanDepth;
854 u8 level;
855 u8 stripeShift;
856 u8 rowSize;
857 u8 rowDataSize;
858 u8 writeMode;
859 u8 PRL;
860 u8 SRL;
861 __le16 targetId;
862 u8 ldState;
863 u8 regTypeReqOnWrite;
864 u8 modFactor;
865 u8 regTypeReqOnRead;
866 __le16 seqNum;
867
868struct {
869#ifndef __BIG_ENDIAN_BITFIELD
870 u32 ldSyncRequired:1;
871 u32 regTypeReqOnReadIsValid:1;
872 u32 isEPD:1;
873 u32 enableSLDOnAllRWIOs:1;
874 u32 reserved:28;
875#else
876 u32 reserved:28;
877 u32 enableSLDOnAllRWIOs:1;
878 u32 isEPD:1;
879 u32 regTypeReqOnReadIsValid:1;
880 u32 ldSyncRequired:1;
881#endif
882 } flags;
883
884 u8 LUN[8];
885 u8 fpIoTimeoutForLd;
886
887 u8 ld_accept_priority_type;
888 u8 reserved2[2];
889
890 u32 logical_block_length;
891 struct {
892#ifndef __BIG_ENDIAN_BITFIELD
893
894 u32 ld_pi_exp:4;
895
896
897
898 u32 ld_logical_block_exp:4;
899 u32 reserved1:24;
900#else
901 u32 reserved1:24;
902
903
904
905 u32 ld_logical_block_exp:4;
906
907 u32 ld_pi_exp:4;
908#endif
909 };
910
911
912
913 struct MR_IO_AFFINITY cpuAffinity;
914
915 u8 reserved3[0x80 - 0x40];
916};
917
918struct MR_LD_SPAN_MAP {
919 struct MR_LD_RAID ldRaid;
920 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
921 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
922};
923
924struct MR_FW_RAID_MAP {
925 __le32 totalSize;
926 union {
927 struct {
928 __le32 maxLd;
929 __le32 maxSpanDepth;
930 __le32 maxRowSize;
931 __le32 maxPdCount;
932 __le32 maxArrays;
933 } validationInfo;
934 __le32 version[5];
935 };
936
937 __le32 ldCount;
938 __le32 Reserved1;
939 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
940 MAX_RAIDMAP_VIEWS];
941 u8 fpPdIoTimeoutSec;
942 u8 reserved2[7];
943 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
944 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
945 struct MR_LD_SPAN_MAP ldSpanMap[1];
946};
947
948struct IO_REQUEST_INFO {
949 u64 ldStartBlock;
950 u32 numBlocks;
951 u16 ldTgtId;
952 u8 isRead;
953 __le16 devHandle;
954 u8 pd_interface;
955 u64 pdBlock;
956 u8 fpOkForIo;
957 u8 IoforUnevenSpan;
958 u8 start_span;
959 u8 do_fp_rlbypass;
960 u64 start_row;
961 u8 span_arm;
962 u8 pd_after_lb;
963 u16 r1_alt_dev_handle;
964 bool ra_capable;
965 u8 data_arms;
966};
967
968struct MR_LD_TARGET_SYNC {
969 u8 targetId;
970 u8 reserved;
971 __le16 seqNum;
972};
973
974
975
976
977
978enum MR_RAID_MAP_DESC_TYPE {
979
980 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
981
982 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
983
984 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
985
986 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
987 RAID_MAP_DESC_TYPE_COUNT,
988};
989
990
991
992
993
994struct MR_RAID_MAP_DESC_TABLE {
995
996 u32 raid_map_desc_type;
997
998
999
1000 u32 raid_map_desc_offset;
1001
1002
1003
1004 u32 raid_map_desc_buffer_size;
1005
1006
1007
1008 u32 raid_map_desc_elements;
1009};
1010
1011
1012
1013
1014struct MR_FW_RAID_MAP_DYNAMIC {
1015 u32 raid_map_size;
1016 u32 desc_table_offset;
1017 u32 desc_table_size;
1018
1019 u32 desc_table_num_elements;
1020 u64 reserved1;
1021 u32 reserved2[3];
1022
1023 u8 fp_pd_io_timeout_sec;
1024 u8 reserved3[3];
1025
1026
1027
1028 u32 rmw_fp_seq_num;
1029 u16 ld_count;
1030 u16 ar_count;
1031 u16 span_count;
1032 u16 reserved4[3];
1033
1034
1035
1036
1037
1038
1039 union {
1040 struct {
1041 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1042 u16 *ld_tgt_id_to_ld;
1043 struct MR_ARRAY_INFO *ar_map_info;
1044 struct MR_LD_SPAN_MAP *ld_span_map;
1045 };
1046 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1047 };
1048
1049
1050
1051
1052
1053 struct MR_RAID_MAP_DESC_TABLE
1054 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1055
1056 u32 raid_map_desc_data[1];
1057};
1058
1059#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1060#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1061#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1062#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1063#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1064#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1065#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1066
1067#define MPI2_SGE_FLAGS_SHIFT (0x02)
1068#define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1069#define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1070#define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1071
1072#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1073#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1074#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1075#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1076
1077#define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15
1078#define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60
1079
1080struct megasas_register_set;
1081struct megasas_instance;
1082
1083union desc_word {
1084 u64 word;
1085 struct {
1086 u32 low;
1087 u32 high;
1088 } u;
1089};
1090
1091struct megasas_cmd_fusion {
1092 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1093 dma_addr_t io_request_phys_addr;
1094
1095 union MPI2_SGE_IO_UNION *sg_frame;
1096 dma_addr_t sg_frame_phys_addr;
1097
1098 u8 *sense;
1099 dma_addr_t sense_phys_addr;
1100
1101 struct list_head list;
1102 struct scsi_cmnd *scmd;
1103 struct megasas_instance *instance;
1104
1105 u8 retry_for_fw_reset;
1106 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1107
1108
1109
1110
1111
1112 u32 sync_cmd_idx;
1113 u32 index;
1114 u8 pd_r1_lb;
1115 struct completion done;
1116 u8 pd_interface;
1117 u16 r1_alt_dev_handle;
1118 bool cmd_completed;
1119
1120};
1121
1122struct LD_LOAD_BALANCE_INFO {
1123 u8 loadBalanceFlag;
1124 u8 reserved1;
1125 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1126 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
1127};
1128
1129
1130typedef struct _LD_SPAN_SET {
1131 u64 log_start_lba;
1132 u64 log_end_lba;
1133 u64 span_row_start;
1134 u64 span_row_end;
1135 u64 data_strip_start;
1136 u64 data_strip_end;
1137 u64 data_row_start;
1138 u64 data_row_end;
1139 u8 strip_offset[MAX_SPAN_DEPTH];
1140 u32 span_row_data_width;
1141 u32 diff;
1142 u32 reserved[2];
1143} LD_SPAN_SET, *PLD_SPAN_SET;
1144
1145typedef struct LOG_BLOCK_SPAN_INFO {
1146 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1147} LD_SPAN_INFO, *PLD_SPAN_INFO;
1148
1149struct MR_FW_RAID_MAP_ALL {
1150 struct MR_FW_RAID_MAP raidMap;
1151 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1152} __attribute__ ((packed));
1153
1154struct MR_DRV_RAID_MAP {
1155
1156
1157
1158
1159 __le32 totalSize;
1160
1161 union {
1162 struct {
1163 __le32 maxLd;
1164 __le32 maxSpanDepth;
1165 __le32 maxRowSize;
1166 __le32 maxPdCount;
1167 __le32 maxArrays;
1168 } validationInfo;
1169 __le32 version[5];
1170 };
1171
1172
1173 u8 fpPdIoTimeoutSec;
1174 u8 reserved2[7];
1175
1176 __le16 ldCount;
1177 __le16 arCount;
1178 __le16 spanCount;
1179 __le16 reserve3;
1180
1181 struct MR_DEV_HANDLE_INFO
1182 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1183 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1184 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1185 struct MR_LD_SPAN_MAP ldSpanMap[1];
1186
1187};
1188
1189
1190
1191
1192
1193struct MR_DRV_RAID_MAP_ALL {
1194
1195 struct MR_DRV_RAID_MAP raidMap;
1196 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1197} __packed;
1198
1199
1200
1201struct MR_FW_RAID_MAP_EXT {
1202
1203 u32 reserved;
1204
1205 union {
1206 struct {
1207 u32 maxLd;
1208 u32 maxSpanDepth;
1209 u32 maxRowSize;
1210 u32 maxPdCount;
1211 u32 maxArrays;
1212 } validationInfo;
1213 u32 version[5];
1214 };
1215
1216 u8 fpPdIoTimeoutSec;
1217 u8 reserved2[7];
1218
1219 __le16 ldCount;
1220 __le16 arCount;
1221 __le16 spanCount;
1222 __le16 reserve3;
1223
1224 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1225 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1226 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1227 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1228};
1229
1230
1231
1232
1233struct MR_PD_CFG_SEQ {
1234 u16 seqNum;
1235 u16 devHandle;
1236 struct {
1237#if defined(__BIG_ENDIAN_BITFIELD)
1238 u8 reserved:7;
1239 u8 tmCapable:1;
1240#else
1241 u8 tmCapable:1;
1242 u8 reserved:7;
1243#endif
1244 } capability;
1245 u8 reserved;
1246 u16 pd_target_id;
1247} __packed;
1248
1249struct MR_PD_CFG_SEQ_NUM_SYNC {
1250 __le32 size;
1251 __le32 count;
1252 struct MR_PD_CFG_SEQ seq[1];
1253} __packed;
1254
1255
1256struct STREAM_DETECT {
1257 u64 next_seq_lba;
1258 struct megasas_cmd_fusion *first_cmd_fusion;
1259 struct megasas_cmd_fusion *last_cmd_fusion;
1260 u32 count_cmds_in_stream;
1261 u16 num_sges_in_group;
1262 u8 is_read;
1263 u8 group_depth;
1264
1265 bool group_flush;
1266 u8 reserved[7];
1267};
1268
1269struct LD_STREAM_DETECT {
1270 bool write_back;
1271 bool fp_write_enabled;
1272 bool members_ssds;
1273 bool fp_cache_bypass_capable;
1274 u32 mru_bit_map;
1275
1276 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1277};
1278
1279struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1280 u64 RDPQBaseAddress;
1281 u32 Reserved1;
1282 u32 Reserved2;
1283};
1284
1285struct rdpq_alloc_detail {
1286 struct dma_pool *dma_pool_ptr;
1287 dma_addr_t pool_entry_phys;
1288 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1289};
1290
1291struct fusion_context {
1292 struct megasas_cmd_fusion **cmd_list;
1293 dma_addr_t req_frames_desc_phys;
1294 u8 *req_frames_desc;
1295
1296 struct dma_pool *io_request_frames_pool;
1297 dma_addr_t io_request_frames_phys;
1298 u8 *io_request_frames;
1299
1300 struct dma_pool *sg_dma_pool;
1301 struct dma_pool *sense_dma_pool;
1302
1303 u8 *sense;
1304 dma_addr_t sense_phys_addr;
1305
1306 atomic_t busy_mq_poll[MAX_MSIX_QUEUES_FUSION];
1307
1308 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1309 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1310 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
1311 struct dma_pool *reply_frames_desc_pool;
1312 struct dma_pool *reply_frames_desc_pool_align;
1313
1314 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1315
1316 u32 reply_q_depth;
1317 u32 request_alloc_sz;
1318 u32 reply_alloc_sz;
1319 u32 io_frames_alloc_sz;
1320
1321 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1322 dma_addr_t rdpq_phys;
1323 u16 max_sge_in_main_msg;
1324 u16 max_sge_in_chain;
1325
1326 u8 chain_offset_io_request;
1327 u8 chain_offset_mfi_pthru;
1328
1329 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1330 dma_addr_t ld_map_phys[2];
1331
1332
1333 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1334
1335 u32 max_map_sz;
1336 u32 current_map_sz;
1337 u32 old_map_sz;
1338 u32 new_map_sz;
1339 u32 drv_map_sz;
1340 u32 drv_map_pages;
1341 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1342 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1343 u8 fast_path_io;
1344 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1345 u32 load_balance_info_pages;
1346 LD_SPAN_INFO *log_to_span;
1347 u32 log_to_span_pages;
1348 struct LD_STREAM_DETECT **stream_detect_by_ld;
1349 dma_addr_t ioc_init_request_phys;
1350 struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1351 struct megasas_cmd *ioc_init_cmd;
1352 bool pcie_bw_limitation;
1353 bool r56_div_offload;
1354};
1355
1356union desc_value {
1357 __le64 word;
1358 struct {
1359 __le32 low;
1360 __le32 high;
1361 } u;
1362};
1363
1364enum CMD_RET_VALUES {
1365 REFIRE_CMD = 1,
1366 COMPLETE_CMD = 2,
1367 RETURN_CMD = 3,
1368};
1369
1370struct MR_SNAPDUMP_PROPERTIES {
1371 u8 offload_num;
1372 u8 max_num_supported;
1373 u8 cur_num_supported;
1374 u8 trigger_min_num_sec_before_ocr;
1375 u8 reserved[12];
1376};
1377
1378struct megasas_debugfs_buffer {
1379 void *buf;
1380 u32 len;
1381};
1382
1383void megasas_free_cmds_fusion(struct megasas_instance *instance);
1384int megasas_ioc_init_fusion(struct megasas_instance *instance);
1385u8 megasas_get_map_info(struct megasas_instance *instance);
1386int megasas_sync_map_info(struct megasas_instance *instance);
1387void megasas_release_fusion(struct megasas_instance *instance);
1388void megasas_reset_reply_desc(struct megasas_instance *instance);
1389int megasas_check_mpio_paths(struct megasas_instance *instance,
1390 struct scsi_cmnd *scmd);
1391void megasas_fusion_ocr_wq(struct work_struct *work);
1392
1393#endif
1394
