linux/drivers/scsi/qla1280.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/******************************************************************************
   3*                  QLOGIC LINUX SOFTWARE
   4*
   5* QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
   6* Copyright (C) 2000 Qlogic Corporation
   7* (www.qlogic.com)
   8*
   9******************************************************************************/
  10
  11#ifndef _QLA1280_H
  12#define _QLA1280_H
  13
  14/*
  15 * Data bit definitions.
  16 */
  17#define BIT_0   0x1
  18#define BIT_1   0x2
  19#define BIT_2   0x4
  20#define BIT_3   0x8
  21#define BIT_4   0x10
  22#define BIT_5   0x20
  23#define BIT_6   0x40
  24#define BIT_7   0x80
  25#define BIT_8   0x100
  26#define BIT_9   0x200
  27#define BIT_10  0x400
  28#define BIT_11  0x800
  29#define BIT_12  0x1000
  30#define BIT_13  0x2000
  31#define BIT_14  0x4000
  32#define BIT_15  0x8000
  33#define BIT_16  0x10000
  34#define BIT_17  0x20000
  35#define BIT_18  0x40000
  36#define BIT_19  0x80000
  37#define BIT_20  0x100000
  38#define BIT_21  0x200000
  39#define BIT_22  0x400000
  40#define BIT_23  0x800000
  41#define BIT_24  0x1000000
  42#define BIT_25  0x2000000
  43#define BIT_26  0x4000000
  44#define BIT_27  0x8000000
  45#define BIT_28  0x10000000
  46#define BIT_29  0x20000000
  47#define BIT_30  0x40000000
  48#define BIT_31  0x80000000
  49
  50#if MEMORY_MAPPED_IO
  51#define RD_REG_WORD(addr)               readw_relaxed(addr)
  52#define RD_REG_WORD_dmasync(addr)       readw(addr)
  53#define WRT_REG_WORD(addr, data)        writew(data, addr)
  54#else                           /* MEMORY_MAPPED_IO */
  55#define RD_REG_WORD(addr)               inw((unsigned long)addr)
  56#define RD_REG_WORD_dmasync(addr)       RD_REG_WORD(addr)
  57#define WRT_REG_WORD(addr, data)        outw(data, (unsigned long)addr)
  58#endif                          /* MEMORY_MAPPED_IO */
  59
  60/*
  61 * Host adapter default definitions.
  62 */
  63#define MAX_BUSES       2       /* 2 */
  64#define MAX_B_BITS      1
  65
  66#define MAX_TARGETS     16      /* 16 */
  67#define MAX_T_BITS      4       /* 4 */
  68
  69#define MAX_LUNS        8       /* 32 */
  70#define MAX_L_BITS      3       /* 5 */
  71
  72/*
  73 * Watchdog time quantum
  74 */
  75#define QLA1280_WDG_TIME_QUANTUM        5       /* In seconds */
  76
  77/* Command retry count (0-65535) */
  78#define COMMAND_RETRY_COUNT             255
  79
  80/* Maximum outstanding commands in ISP queues */
  81#define MAX_OUTSTANDING_COMMANDS        512
  82#define COMPLETED_HANDLE                ((unsigned char *) \
  83                                        (MAX_OUTSTANDING_COMMANDS + 2))
  84
  85/* ISP request and response entry counts (37-65535) */
  86#define REQUEST_ENTRY_CNT               255 /* Number of request entries. */
  87#define RESPONSE_ENTRY_CNT              63  /* Number of response entries. */
  88
  89/*
  90 * SCSI Request Block structure  (sp)  that is placed
  91 * on cmd->SCp location of every I/O
  92 */
  93struct srb {
  94        struct list_head list;          /* (8/16) LU queue */
  95        struct scsi_cmnd *cmd;  /* (4/8) SCSI command block */
  96        /* NOTE: the sp->cmd will be NULL when this completion is
  97         * called, so you should know the scsi_cmnd when using this */
  98        struct completion *wait;
  99        dma_addr_t saved_dma_handle;    /* for unmap of single transfers */
 100        uint8_t flags;          /* (1) Status flags. */
 101        uint8_t dir;            /* direction of transfer */
 102};
 103
 104/*
 105 * SRB flag definitions
 106 */
 107#define SRB_TIMEOUT             (1 << 0)        /* Command timed out */
 108#define SRB_SENT                (1 << 1)        /* Command sent to ISP */
 109#define SRB_ABORT_PENDING       (1 << 2)        /* Command abort sent to device */
 110#define SRB_ABORTED             (1 << 3)        /* Command aborted command already */
 111
 112/*
 113 *  ISP I/O Register Set structure definitions.
 114 */
 115struct device_reg {
 116        uint16_t id_l;          /* ID low */
 117        uint16_t id_h;          /* ID high */
 118        uint16_t cfg_0;         /* Configuration 0 */
 119#define ISP_CFG0_HWMSK   0x000f /* Hardware revision mask */
 120#define ISP_CFG0_1020    BIT_0  /* ISP1020 */
 121#define ISP_CFG0_1020A   BIT_1  /* ISP1020A */
 122#define ISP_CFG0_1040    BIT_2  /* ISP1040 */
 123#define ISP_CFG0_1040A   BIT_3  /* ISP1040A */
 124#define ISP_CFG0_1040B   BIT_4  /* ISP1040B */
 125#define ISP_CFG0_1040C   BIT_5  /* ISP1040C */
 126        uint16_t cfg_1;         /* Configuration 1 */
 127#define ISP_CFG1_F128    BIT_6  /* 128-byte FIFO threshold */
 128#define ISP_CFG1_F64     BIT_4|BIT_5 /* 128-byte FIFO threshold */
 129#define ISP_CFG1_F32     BIT_5  /* 128-byte FIFO threshold */
 130#define ISP_CFG1_F16     BIT_4  /* 128-byte FIFO threshold */
 131#define ISP_CFG1_BENAB   BIT_2  /* Global Bus burst enable */
 132#define ISP_CFG1_SXP     BIT_0  /* SXP register select */
 133        uint16_t ictrl;         /* Interface control */
 134#define ISP_RESET        BIT_0  /* ISP soft reset */
 135#define ISP_EN_INT       BIT_1  /* ISP enable interrupts. */
 136#define ISP_EN_RISC      BIT_2  /* ISP enable RISC interrupts. */
 137#define ISP_FLASH_ENABLE BIT_8  /* Flash BIOS Read/Write enable */
 138#define ISP_FLASH_UPPER  BIT_9  /* Flash upper bank select */
 139        uint16_t istatus;       /* Interface status */
 140#define PCI_64BIT_SLOT   BIT_14 /* PCI 64-bit slot indicator. */
 141#define RISC_INT         BIT_2  /* RISC interrupt */
 142#define PCI_INT          BIT_1  /* PCI interrupt */
 143        uint16_t semaphore;     /* Semaphore */
 144        uint16_t nvram;         /* NVRAM register. */
 145#define NV_DESELECT     0
 146#define NV_CLOCK        BIT_0
 147#define NV_SELECT       BIT_1
 148#define NV_DATA_OUT     BIT_2
 149#define NV_DATA_IN      BIT_3
 150        uint16_t flash_data;    /* Flash BIOS data */
 151        uint16_t flash_address; /* Flash BIOS address */
 152
 153        uint16_t unused_1[0x06];
 154        
 155        /* cdma_* and ddma_* are 1040 only */
 156        uint16_t cdma_cfg;
 157#define CDMA_CONF_SENAB  BIT_3  /* SXP to DMA Data enable */
 158#define CDMA_CONF_RIRQ   BIT_2  /* RISC interrupt enable */
 159#define CDMA_CONF_BENAB  BIT_1  /* Bus burst enable */
 160#define CDMA_CONF_DIR    BIT_0  /* DMA direction (0=fifo->host 1=host->fifo) */
 161        uint16_t cdma_ctrl; 
 162        uint16_t cdma_status;   
 163        uint16_t cdma_fifo_status;
 164        uint16_t cdma_count;
 165        uint16_t cdma_reserved;
 166        uint16_t cdma_address_count_0;
 167        uint16_t cdma_address_count_1;
 168        uint16_t cdma_address_count_2;
 169        uint16_t cdma_address_count_3;
 170
 171        uint16_t unused_2[0x06];
 172
 173        uint16_t ddma_cfg;
 174#define DDMA_CONF_SENAB  BIT_3  /* SXP to DMA Data enable */
 175#define DDMA_CONF_RIRQ   BIT_2  /* RISC interrupt enable */
 176#define DDMA_CONF_BENAB  BIT_1  /* Bus burst enable */
 177#define DDMA_CONF_DIR    BIT_0  /* DMA direction (0=fifo->host 1=host->fifo) */
 178        uint16_t ddma_ctrl;
 179        uint16_t ddma_status; 
 180        uint16_t ddma_fifo_status;
 181        uint16_t ddma_xfer_count_low;
 182        uint16_t ddma_xfer_count_high;
 183        uint16_t ddma_addr_count_0;
 184        uint16_t ddma_addr_count_1;
 185        uint16_t ddma_addr_count_2;
 186        uint16_t ddma_addr_count_3; 
 187
 188        uint16_t unused_3[0x0e];
 189
 190        uint16_t mailbox0;      /* Mailbox 0 */
 191        uint16_t mailbox1;      /* Mailbox 1 */
 192        uint16_t mailbox2;      /* Mailbox 2 */
 193        uint16_t mailbox3;      /* Mailbox 3 */
 194        uint16_t mailbox4;      /* Mailbox 4 */
 195        uint16_t mailbox5;      /* Mailbox 5 */
 196        uint16_t mailbox6;      /* Mailbox 6 */
 197        uint16_t mailbox7;      /* Mailbox 7 */
 198
 199        uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
 200
 201        uint16_t host_cmd;      /* Host command and control */
 202#define HOST_INT      BIT_7     /* host interrupt bit */
 203#define BIOS_ENABLE   BIT_0
 204
 205        uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
 206
 207        uint16_t gpio_data;
 208        uint16_t gpio_enable;
 209
 210        uint16_t unused_6[0x11];        /* d0-f0 */
 211        uint16_t scsiControlPins;       /* f2 */
 212};
 213
 214#define MAILBOX_REGISTER_COUNT  8
 215
 216/*
 217 *  ISP product identification definitions in mailboxes after reset.
 218 */
 219#define PROD_ID_1               0x4953
 220#define PROD_ID_2               0x0000
 221#define PROD_ID_2a              0x5020
 222#define PROD_ID_3               0x2020
 223#define PROD_ID_4               0x1
 224
 225/*
 226 * ISP host command and control register command definitions
 227 */
 228#define HC_RESET_RISC           0x1000  /* Reset RISC */
 229#define HC_PAUSE_RISC           0x2000  /* Pause RISC */
 230#define HC_RELEASE_RISC         0x3000  /* Release RISC from reset. */
 231#define HC_SET_HOST_INT         0x5000  /* Set host interrupt */
 232#define HC_CLR_HOST_INT         0x6000  /* Clear HOST interrupt */
 233#define HC_CLR_RISC_INT         0x7000  /* Clear RISC interrupt */
 234#define HC_DISABLE_BIOS         0x9000  /* Disable BIOS. */
 235
 236/*
 237 * ISP mailbox Self-Test status codes
 238 */
 239#define MBS_FRM_ALIVE           0       /* Firmware Alive. */
 240#define MBS_CHKSUM_ERR          1       /* Checksum Error. */
 241#define MBS_SHADOW_LD_ERR       2       /* Shadow Load Error. */
 242#define MBS_BUSY                4       /* Busy. */
 243
 244/*
 245 * ISP mailbox command complete status codes
 246 */
 247#define MBS_CMD_CMP             0x4000  /* Command Complete. */
 248#define MBS_INV_CMD             0x4001  /* Invalid Command. */
 249#define MBS_HOST_INF_ERR        0x4002  /* Host Interface Error. */
 250#define MBS_TEST_FAILED         0x4003  /* Test Failed. */
 251#define MBS_CMD_ERR             0x4005  /* Command Error. */
 252#define MBS_CMD_PARAM_ERR       0x4006  /* Command Parameter Error. */
 253
 254/*
 255 * ISP mailbox asynchronous event status codes
 256 */
 257#define MBA_ASYNC_EVENT         0x8000  /* Asynchronous event. */
 258#define MBA_BUS_RESET           0x8001  /* SCSI Bus Reset. */
 259#define MBA_SYSTEM_ERR          0x8002  /* System Error. */
 260#define MBA_REQ_TRANSFER_ERR    0x8003  /* Request Transfer Error. */
 261#define MBA_RSP_TRANSFER_ERR    0x8004  /* Response Transfer Error. */
 262#define MBA_WAKEUP_THRES        0x8005  /* Request Queue Wake-up. */
 263#define MBA_TIMEOUT_RESET       0x8006  /* Execution Timeout Reset. */
 264#define MBA_DEVICE_RESET        0x8007  /* Bus Device Reset. */
 265#define MBA_BUS_MODE_CHANGE     0x800E  /* SCSI bus mode transition. */
 266#define MBA_SCSI_COMPLETION     0x8020  /* Completion response. */
 267
 268/*
 269 * ISP mailbox commands
 270 */
 271#define MBC_NOP                         0       /* No Operation */
 272#define MBC_LOAD_RAM                    1       /* Load RAM */
 273#define MBC_EXECUTE_FIRMWARE            2       /* Execute firmware */
 274#define MBC_DUMP_RAM                    3       /* Dump RAM contents */
 275#define MBC_WRITE_RAM_WORD              4       /* Write ram word */
 276#define MBC_READ_RAM_WORD               5       /* Read ram word */
 277#define MBC_MAILBOX_REGISTER_TEST       6       /* Wrap incoming mailboxes */
 278#define MBC_VERIFY_CHECKSUM             7       /* Verify checksum */
 279#define MBC_ABOUT_FIRMWARE              8       /* Get firmware revision */
 280#define MBC_INIT_REQUEST_QUEUE          0x10    /* Initialize request queue */
 281#define MBC_INIT_RESPONSE_QUEUE         0x11    /* Initialize response queue */
 282#define MBC_EXECUTE_IOCB                0x12    /* Execute IOCB command */
 283#define MBC_ABORT_COMMAND               0x15    /* Abort IOCB command */
 284#define MBC_ABORT_DEVICE                0x16    /* Abort device (ID/LUN) */
 285#define MBC_ABORT_TARGET                0x17    /* Abort target (ID) */
 286#define MBC_BUS_RESET                   0x18    /* SCSI bus reset */
 287#define MBC_GET_RETRY_COUNT             0x22    /* Get retry count and delay */
 288#define MBC_GET_TARGET_PARAMETERS       0x28    /* Get target parameters */
 289#define MBC_SET_INITIATOR_ID            0x30    /* Set initiator SCSI ID */
 290#define MBC_SET_SELECTION_TIMEOUT       0x31    /* Set selection timeout */
 291#define MBC_SET_RETRY_COUNT             0x32    /* Set retry count and delay */
 292#define MBC_SET_TAG_AGE_LIMIT           0x33    /* Set tag age limit */
 293#define MBC_SET_CLOCK_RATE              0x34    /* Set clock rate */
 294#define MBC_SET_ACTIVE_NEGATION         0x35    /* Set active negation state */
 295#define MBC_SET_ASYNC_DATA_SETUP        0x36    /* Set async data setup time */
 296#define MBC_SET_PCI_CONTROL             0x37    /* Set BUS control parameters */
 297#define MBC_SET_TARGET_PARAMETERS       0x38    /* Set target parameters */
 298#define MBC_SET_DEVICE_QUEUE            0x39    /* Set device queue parameters */
 299#define MBC_SET_RESET_DELAY_PARAMETERS  0x3A    /* Set reset delay parameters */
 300#define MBC_SET_SYSTEM_PARAMETER        0x45    /* Set system parameter word */
 301#define MBC_SET_FIRMWARE_FEATURES       0x4A    /* Set firmware feature word */
 302#define MBC_INIT_REQUEST_QUEUE_A64      0x52    /* Initialize request queue A64 */
 303#define MBC_INIT_RESPONSE_QUEUE_A64     0x53    /* Initialize response q A64 */
 304#define MBC_ENABLE_TARGET_MODE          0x55    /* Enable target mode */
 305#define MBC_SET_DATA_OVERRUN_RECOVERY   0x5A    /* Set data overrun recovery mode */
 306
 307/*
 308 * ISP Get/Set Target Parameters mailbox command control flags.
 309 */
 310#define TP_PPR                  BIT_5   /* PPR */
 311#define TP_RENEGOTIATE          BIT_8   /* Renegotiate on error. */
 312#define TP_STOP_QUEUE           BIT_9   /* Stop que on check condition */
 313#define TP_AUTO_REQUEST_SENSE   BIT_10  /* Automatic request sense. */
 314#define TP_TAGGED_QUEUE         BIT_11  /* Tagged queuing. */
 315#define TP_SYNC                 BIT_12  /* Synchronous data transfers. */
 316#define TP_WIDE                 BIT_13  /* Wide data transfers. */
 317#define TP_PARITY               BIT_14  /* Parity checking. */
 318#define TP_DISCONNECT           BIT_15  /* Disconnect privilege. */
 319
 320/*
 321 * NVRAM Command values.
 322 */
 323#define NV_START_BIT            BIT_2
 324#define NV_WRITE_OP             (BIT_26 | BIT_24)
 325#define NV_READ_OP              (BIT_26 | BIT_25)
 326#define NV_ERASE_OP             (BIT_26 | BIT_25 | BIT_24)
 327#define NV_MASK_OP              (BIT_26 | BIT_25 | BIT_24)
 328#define NV_DELAY_COUNT          10
 329
 330/*
 331 *  QLogic ISP1280/ISP12160 NVRAM structure definition.
 332 */
 333struct nvram {
 334        uint8_t id0;            /* 0 */
 335        uint8_t id1;            /* 1 */
 336        uint8_t id2;            /* 2 */
 337        uint8_t id3;            /* 3 */
 338        uint8_t version;        /* 4 */
 339
 340        struct {
 341                uint8_t bios_configuration_mode:2;
 342                uint8_t bios_disable:1;
 343                uint8_t selectable_scsi_boot_enable:1;
 344                uint8_t cd_rom_boot_enable:1;
 345                uint8_t disable_loading_risc_code:1;
 346                uint8_t enable_64bit_addressing:1;
 347                uint8_t unused_7:1;
 348        } cntr_flags_1;         /* 5 */
 349
 350        struct {
 351                uint8_t boot_lun_number:5;
 352                uint8_t scsi_bus_number:1;
 353                uint8_t unused_6:1;
 354                uint8_t unused_7:1;
 355        } cntr_flags_2l;        /* 7 */
 356
 357        struct {
 358                uint8_t boot_target_number:4;
 359                uint8_t unused_12:1;
 360                uint8_t unused_13:1;
 361                uint8_t unused_14:1;
 362                uint8_t unused_15:1;
 363        } cntr_flags_2h;        /* 8 */
 364
 365        uint16_t unused_8;      /* 8, 9 */
 366        uint16_t unused_10;     /* 10, 11 */
 367        uint16_t unused_12;     /* 12, 13 */
 368        uint16_t unused_14;     /* 14, 15 */
 369
 370        struct {
 371                uint8_t reserved:2;
 372                uint8_t burst_enable:1;
 373                uint8_t reserved_1:1;
 374                uint8_t fifo_threshold:4;
 375        } isp_config;           /* 16 */
 376
 377        /* Termination
 378         * 0 = Disable, 1 = high only, 3 = Auto term
 379         */
 380        struct {
 381                uint8_t scsi_bus_1_control:2;
 382                uint8_t scsi_bus_0_control:2;
 383                uint8_t unused_0:1;
 384                uint8_t unused_1:1;
 385                uint8_t unused_2:1;
 386                uint8_t auto_term_support:1;
 387        } termination;          /* 17 */
 388
 389        uint16_t isp_parameter; /* 18, 19 */
 390
 391        union {
 392                uint16_t w;
 393                struct {
 394                        uint16_t enable_fast_posting:1;
 395                        uint16_t report_lvd_bus_transition:1;
 396                        uint16_t unused_2:1;
 397                        uint16_t unused_3:1;
 398                        uint16_t disable_iosbs_with_bus_reset_status:1;
 399                        uint16_t disable_synchronous_backoff:1;
 400                        uint16_t unused_6:1;
 401                        uint16_t synchronous_backoff_reporting:1;
 402                        uint16_t disable_reselection_fairness:1;
 403                        uint16_t unused_9:1;
 404                        uint16_t unused_10:1;
 405                        uint16_t unused_11:1;
 406                        uint16_t unused_12:1;
 407                        uint16_t unused_13:1;
 408                        uint16_t unused_14:1;
 409                        uint16_t unused_15:1;
 410                } f;
 411        } firmware_feature;     /* 20, 21 */
 412
 413        uint16_t unused_22;     /* 22, 23 */
 414
 415        struct {
 416                struct {
 417                        uint8_t initiator_id:4;
 418                        uint8_t scsi_reset_disable:1;
 419                        uint8_t scsi_bus_size:1;
 420                        uint8_t scsi_bus_type:1;
 421                        uint8_t unused_7:1;
 422                } config_1;     /* 24 */
 423
 424                uint8_t bus_reset_delay;        /* 25 */
 425                uint8_t retry_count;    /* 26 */
 426                uint8_t retry_delay;    /* 27 */
 427
 428                struct {
 429                        uint8_t async_data_setup_time:4;
 430                        uint8_t req_ack_active_negation:1;
 431                        uint8_t data_line_active_negation:1;
 432                        uint8_t unused_6:1;
 433                        uint8_t unused_7:1;
 434                } config_2;     /* 28 */
 435
 436                uint8_t unused_29;      /* 29 */
 437
 438                uint16_t selection_timeout;     /* 30, 31 */
 439                uint16_t max_queue_depth;       /* 32, 33 */
 440
 441                uint16_t unused_34;     /* 34, 35 */
 442                uint16_t unused_36;     /* 36, 37 */
 443                uint16_t unused_38;     /* 38, 39 */
 444
 445                struct {
 446                        struct {
 447                                uint8_t renegotiate_on_error:1;
 448                                uint8_t stop_queue_on_check:1;
 449                                uint8_t auto_request_sense:1;
 450                                uint8_t tag_queuing:1;
 451                                uint8_t enable_sync:1;
 452                                uint8_t enable_wide:1;
 453                                uint8_t parity_checking:1;
 454                                uint8_t disconnect_allowed:1;
 455                        } parameter;    /* 40 */
 456
 457                        uint8_t execution_throttle;     /* 41 */
 458                        uint8_t sync_period;    /* 42 */
 459
 460                        union {         /* 43 */
 461                                uint8_t flags_43;
 462                                struct {
 463                                        uint8_t sync_offset:4;
 464                                        uint8_t device_enable:1;
 465                                        uint8_t lun_disable:1;
 466                                        uint8_t unused_6:1;
 467                                        uint8_t unused_7:1;
 468                                } flags1x80;
 469                                struct {
 470                                        uint8_t sync_offset:5;
 471                                        uint8_t device_enable:1;
 472                                        uint8_t unused_6:1;
 473                                        uint8_t unused_7:1;
 474                                } flags1x160;
 475                        } flags;
 476                        union { /* PPR flags for the 1x160 controllers */
 477                                uint8_t unused_44;
 478                                struct {
 479                                        uint8_t ppr_options:4;
 480                                        uint8_t ppr_bus_width:2;
 481                                        uint8_t unused_8:1;
 482                                        uint8_t enable_ppr:1;
 483                                } flags;        /* 44 */
 484                        } ppr_1x160;
 485                        uint8_t unused_45;      /* 45 */
 486                } target[MAX_TARGETS];
 487        } bus[MAX_BUSES];
 488
 489        uint16_t unused_248;    /* 248, 249 */
 490
 491        uint16_t subsystem_id[2];       /* 250, 251, 252, 253 */
 492
 493        union {                         /* 254 */
 494                uint8_t unused_254;
 495                uint8_t system_id_pointer;
 496        } sysid_1x160;
 497
 498        uint8_t chksum;         /* 255 */
 499};
 500
 501/*
 502 * ISP queue - command entry structure definition.
 503 */
 504#define MAX_CMDSZ       12              /* SCSI maximum CDB size. */
 505struct cmd_entry {
 506        uint8_t entry_type;             /* Entry type. */
 507#define COMMAND_TYPE    1               /* Command entry */
 508        uint8_t entry_count;            /* Entry count. */
 509        uint8_t sys_define;             /* System defined. */
 510        uint8_t entry_status;           /* Entry Status. */
 511        __le32 handle;                  /* System handle. */
 512        uint8_t lun;                    /* SCSI LUN */
 513        uint8_t target;                 /* SCSI ID */
 514        __le16 cdb_len;                 /* SCSI command length. */
 515        __le16 control_flags;           /* Control flags. */
 516        __le16 reserved;
 517        __le16 timeout;                 /* Command timeout. */
 518        __le16 dseg_count;              /* Data segment count. */
 519        uint8_t scsi_cdb[MAX_CMDSZ];    /* SCSI command words. */
 520        __le32 dseg_0_address;          /* Data segment 0 address. */
 521        __le32 dseg_0_length;           /* Data segment 0 length. */
 522        __le32 dseg_1_address;          /* Data segment 1 address. */
 523        __le32 dseg_1_length;           /* Data segment 1 length. */
 524        __le32 dseg_2_address;          /* Data segment 2 address. */
 525        __le32 dseg_2_length;           /* Data segment 2 length. */
 526        __le32 dseg_3_address;          /* Data segment 3 address. */
 527        __le32 dseg_3_length;           /* Data segment 3 length. */
 528};
 529
 530/*
 531 * ISP queue - continuation entry structure definition.
 532 */
 533struct cont_entry {
 534        uint8_t entry_type;             /* Entry type. */
 535#define CONTINUE_TYPE   2               /* Continuation entry. */
 536        uint8_t entry_count;            /* Entry count. */
 537        uint8_t sys_define;             /* System defined. */
 538        uint8_t entry_status;           /* Entry Status. */
 539        __le32 reserved;                /* Reserved */
 540        __le32 dseg_0_address;          /* Data segment 0 address. */
 541        __le32 dseg_0_length;           /* Data segment 0 length. */
 542        __le32 dseg_1_address;          /* Data segment 1 address. */
 543        __le32 dseg_1_length;           /* Data segment 1 length. */
 544        __le32 dseg_2_address;          /* Data segment 2 address. */
 545        __le32 dseg_2_length;           /* Data segment 2 length. */
 546        __le32 dseg_3_address;          /* Data segment 3 address. */
 547        __le32 dseg_3_length;           /* Data segment 3 length. */
 548        __le32 dseg_4_address;          /* Data segment 4 address. */
 549        __le32 dseg_4_length;           /* Data segment 4 length. */
 550        __le32 dseg_5_address;          /* Data segment 5 address. */
 551        __le32 dseg_5_length;           /* Data segment 5 length. */
 552        __le32 dseg_6_address;          /* Data segment 6 address. */
 553        __le32 dseg_6_length;           /* Data segment 6 length. */
 554};
 555
 556/*
 557 * ISP queue - status entry structure definition.
 558 */
 559struct response {
 560        uint8_t entry_type;     /* Entry type. */
 561#define STATUS_TYPE     3       /* Status entry. */
 562        uint8_t entry_count;    /* Entry count. */
 563        uint8_t sys_define;     /* System defined. */
 564        uint8_t entry_status;   /* Entry Status. */
 565#define RF_CONT         BIT_0   /* Continuation. */
 566#define RF_FULL         BIT_1   /* Full */
 567#define RF_BAD_HEADER   BIT_2   /* Bad header. */
 568#define RF_BAD_PAYLOAD  BIT_3   /* Bad payload. */
 569        __le32 handle;          /* System handle. */
 570        __le16 scsi_status;     /* SCSI status. */
 571        __le16 comp_status;     /* Completion status. */
 572        __le16 state_flags;     /* State flags. */
 573#define SF_TRANSFER_CMPL        BIT_14  /* Transfer Complete. */
 574#define SF_GOT_SENSE            BIT_13  /* Got Sense */
 575#define SF_GOT_STATUS           BIT_12  /* Got Status */
 576#define SF_TRANSFERRED_DATA     BIT_11  /* Transferred data */
 577#define SF_SENT_CDB             BIT_10  /* Send CDB */
 578#define SF_GOT_TARGET           BIT_9   /*  */
 579#define SF_GOT_BUS              BIT_8   /*  */
 580        __le16 status_flags;    /* Status flags. */
 581        __le16 time;            /* Time. */
 582        __le16 req_sense_length;/* Request sense data length. */
 583        __le32 residual_length; /* Residual transfer length. */
 584        __le16 reserved[4];
 585        uint8_t req_sense_data[32];     /* Request sense data. */
 586};
 587
 588/*
 589 * ISP queue - marker entry structure definition.
 590 */
 591struct mrk_entry {
 592        uint8_t entry_type;     /* Entry type. */
 593#define MARKER_TYPE     4       /* Marker entry. */
 594        uint8_t entry_count;    /* Entry count. */
 595        uint8_t sys_define;     /* System defined. */
 596        uint8_t entry_status;   /* Entry Status. */
 597        __le32 reserved;
 598        uint8_t lun;            /* SCSI LUN */
 599        uint8_t target;         /* SCSI ID */
 600        uint8_t modifier;       /* Modifier (7-0). */
 601#define MK_SYNC_ID_LUN      0   /* Synchronize ID/LUN */
 602#define MK_SYNC_ID          1   /* Synchronize ID */
 603#define MK_SYNC_ALL         2   /* Synchronize all ID/LUN */
 604        uint8_t reserved_1[53];
 605};
 606
 607/*
 608 * ISP queue - extended command entry structure definition.
 609 *
 610 * Unused by the driver!
 611 */
 612struct ecmd_entry {
 613        uint8_t entry_type;     /* Entry type. */
 614#define EXTENDED_CMD_TYPE  5    /* Extended command entry. */
 615        uint8_t entry_count;    /* Entry count. */
 616        uint8_t sys_define;     /* System defined. */
 617        uint8_t entry_status;   /* Entry Status. */
 618        uint32_t handle;        /* System handle. */
 619        uint8_t lun;            /* SCSI LUN */
 620        uint8_t target;         /* SCSI ID */
 621        __le16 cdb_len;         /* SCSI command length. */
 622        __le16 control_flags;   /* Control flags. */
 623        __le16 reserved;
 624        __le16 timeout;         /* Command timeout. */
 625        __le16 dseg_count;      /* Data segment count. */
 626        uint8_t scsi_cdb[88];   /* SCSI command words. */
 627};
 628
 629/*
 630 * ISP queue - 64-Bit addressing, command entry structure definition.
 631 */
 632typedef struct {
 633        uint8_t entry_type;     /* Entry type. */
 634#define COMMAND_A64_TYPE 9      /* Command A64 entry */
 635        uint8_t entry_count;    /* Entry count. */
 636        uint8_t sys_define;     /* System defined. */
 637        uint8_t entry_status;   /* Entry Status. */
 638        __le32 handle;  /* System handle. */
 639        uint8_t lun;            /* SCSI LUN */
 640        uint8_t target;         /* SCSI ID */
 641        __le16 cdb_len; /* SCSI command length. */
 642        __le16 control_flags;   /* Control flags. */
 643        __le16 reserved;
 644        __le16 timeout; /* Command timeout. */
 645        __le16 dseg_count;      /* Data segment count. */
 646        uint8_t scsi_cdb[MAX_CMDSZ];    /* SCSI command words. */
 647        __le32 reserved_1[2];   /* unused */
 648        __le32 dseg_0_address[2];       /* Data segment 0 address. */
 649        __le32 dseg_0_length;   /* Data segment 0 length. */
 650        __le32 dseg_1_address[2];       /* Data segment 1 address. */
 651        __le32 dseg_1_length;   /* Data segment 1 length. */
 652} cmd_a64_entry_t, request_t;
 653
 654/*
 655 * ISP queue - 64-Bit addressing, continuation entry structure definition.
 656 */
 657struct cont_a64_entry {
 658        uint8_t entry_type;     /* Entry type. */
 659#define CONTINUE_A64_TYPE 0xA   /* Continuation A64 entry. */
 660        uint8_t entry_count;    /* Entry count. */
 661        uint8_t sys_define;     /* System defined. */
 662        uint8_t entry_status;   /* Entry Status. */
 663        __le32 dseg_0_address[2];       /* Data segment 0 address. */
 664        __le32 dseg_0_length;           /* Data segment 0 length. */
 665        __le32 dseg_1_address[2];       /* Data segment 1 address. */
 666        __le32 dseg_1_length;           /* Data segment 1 length. */
 667        __le32 dseg_2_address[2];       /* Data segment 2 address. */
 668        __le32 dseg_2_length;           /* Data segment 2 length. */
 669        __le32 dseg_3_address[2];       /* Data segment 3 address. */
 670        __le32 dseg_3_length;           /* Data segment 3 length. */
 671        __le32 dseg_4_address[2];       /* Data segment 4 address. */
 672        __le32 dseg_4_length;           /* Data segment 4 length. */
 673};
 674
 675/*
 676 * ISP queue - enable LUN entry structure definition.
 677 */
 678struct elun_entry {
 679        uint8_t entry_type;     /* Entry type. */
 680#define ENABLE_LUN_TYPE 0xB     /* Enable LUN entry. */
 681        uint8_t entry_count;    /* Entry count. */
 682        uint8_t reserved_1;
 683        uint8_t entry_status;   /* Entry Status not used. */
 684        __le32 reserved_2;
 685        __le16 lun;             /* Bit 15 is bus number. */
 686        __le16 reserved_4;
 687        __le32 option_flags;
 688        uint8_t status;
 689        uint8_t reserved_5;
 690        uint8_t command_count;  /* Number of ATIOs allocated. */
 691        uint8_t immed_notify_count;     /* Number of Immediate Notify */
 692        /* entries allocated. */
 693        uint8_t group_6_length; /* SCSI CDB length for group 6 */
 694        /* commands (2-26). */
 695        uint8_t group_7_length; /* SCSI CDB length for group 7 */
 696        /* commands (2-26). */
 697        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 698        __le16 reserved_6[20];
 699};
 700
 701/*
 702 * ISP queue - modify LUN entry structure definition.
 703 *
 704 * Unused by the driver!
 705 */
 706struct modify_lun_entry {
 707        uint8_t entry_type;     /* Entry type. */
 708#define MODIFY_LUN_TYPE 0xC     /* Modify LUN entry. */
 709        uint8_t entry_count;    /* Entry count. */
 710        uint8_t reserved_1;
 711        uint8_t entry_status;   /* Entry Status. */
 712        __le32 reserved_2;
 713        uint8_t lun;            /* SCSI LUN */
 714        uint8_t reserved_3;
 715        uint8_t operators;
 716        uint8_t reserved_4;
 717        __le32 option_flags;
 718        uint8_t status;
 719        uint8_t reserved_5;
 720        uint8_t command_count;  /* Number of ATIOs allocated. */
 721        uint8_t immed_notify_count;     /* Number of Immediate Notify */
 722        /* entries allocated. */
 723        __le16 reserved_6;
 724        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 725        __le16 reserved_7[20];
 726};
 727
 728/*
 729 * ISP queue - immediate notify entry structure definition.
 730 */
 731struct notify_entry {
 732        uint8_t entry_type;     /* Entry type. */
 733#define IMMED_NOTIFY_TYPE 0xD   /* Immediate notify entry. */
 734        uint8_t entry_count;    /* Entry count. */
 735        uint8_t reserved_1;
 736        uint8_t entry_status;   /* Entry Status. */
 737        __le32 reserved_2;
 738        uint8_t lun;
 739        uint8_t initiator_id;
 740        uint8_t reserved_3;
 741        uint8_t target_id;
 742        __le32 option_flags;
 743        uint8_t status;
 744        uint8_t reserved_4;
 745        uint8_t tag_value;      /* Received queue tag message value */
 746        uint8_t tag_type;       /* Received queue tag message type */
 747        /* entries allocated. */
 748        __le16 seq_id;
 749        uint8_t scsi_msg[8];    /* SCSI message not handled by ISP */
 750        __le16 reserved_5[8];
 751        uint8_t sense_data[18];
 752};
 753
 754/*
 755 * ISP queue - notify acknowledge entry structure definition.
 756 */
 757struct nack_entry {
 758        uint8_t entry_type;     /* Entry type. */
 759#define NOTIFY_ACK_TYPE 0xE     /* Notify acknowledge entry. */
 760        uint8_t entry_count;    /* Entry count. */
 761        uint8_t reserved_1;
 762        uint8_t entry_status;   /* Entry Status. */
 763        __le32 reserved_2;
 764        uint8_t lun;
 765        uint8_t initiator_id;
 766        uint8_t reserved_3;
 767        uint8_t target_id;
 768        __le32 option_flags;
 769        uint8_t status;
 770        uint8_t event;
 771        __le16 seq_id;
 772        __le16 reserved_4[22];
 773};
 774
 775/*
 776 * ISP queue - Accept Target I/O (ATIO) entry structure definition.
 777 */
 778struct atio_entry {
 779        uint8_t entry_type;     /* Entry type. */
 780#define ACCEPT_TGT_IO_TYPE 6    /* Accept target I/O entry. */
 781        uint8_t entry_count;    /* Entry count. */
 782        uint8_t reserved_1;
 783        uint8_t entry_status;   /* Entry Status. */
 784        __le32 reserved_2;
 785        uint8_t lun;
 786        uint8_t initiator_id;
 787        uint8_t cdb_len;
 788        uint8_t target_id;
 789        __le32 option_flags;
 790        uint8_t status;
 791        uint8_t scsi_status;
 792        uint8_t tag_value;      /* Received queue tag message value */
 793        uint8_t tag_type;       /* Received queue tag message type */
 794        uint8_t cdb[26];
 795        uint8_t sense_data[18];
 796};
 797
 798/*
 799 * ISP queue - Continue Target I/O (CTIO) entry structure definition.
 800 */
 801struct ctio_entry {
 802        uint8_t entry_type;     /* Entry type. */
 803#define CONTINUE_TGT_IO_TYPE 7  /* CTIO entry */
 804        uint8_t entry_count;    /* Entry count. */
 805        uint8_t reserved_1;
 806        uint8_t entry_status;   /* Entry Status. */
 807        __le32 reserved_2;
 808        uint8_t lun;            /* SCSI LUN */
 809        uint8_t initiator_id;
 810        uint8_t reserved_3;
 811        uint8_t target_id;
 812        __le32 option_flags;
 813        uint8_t status;
 814        uint8_t scsi_status;
 815        uint8_t tag_value;      /* Received queue tag message value */
 816        uint8_t tag_type;       /* Received queue tag message type */
 817        __le32 transfer_length;
 818        __le32 residual;
 819        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 820        __le16 dseg_count;      /* Data segment count. */
 821        __le32 dseg_0_address;  /* Data segment 0 address. */
 822        __le32 dseg_0_length;   /* Data segment 0 length. */
 823        __le32 dseg_1_address;  /* Data segment 1 address. */
 824        __le32 dseg_1_length;   /* Data segment 1 length. */
 825        __le32 dseg_2_address;  /* Data segment 2 address. */
 826        __le32 dseg_2_length;   /* Data segment 2 length. */
 827        __le32 dseg_3_address;  /* Data segment 3 address. */
 828        __le32 dseg_3_length;   /* Data segment 3 length. */
 829};
 830
 831/*
 832 * ISP queue - CTIO returned entry structure definition.
 833 */
 834struct ctio_ret_entry {
 835        uint8_t entry_type;     /* Entry type. */
 836#define CTIO_RET_TYPE   7       /* CTIO return entry */
 837        uint8_t entry_count;    /* Entry count. */
 838        uint8_t reserved_1;
 839        uint8_t entry_status;   /* Entry Status. */
 840        __le32 reserved_2;
 841        uint8_t lun;            /* SCSI LUN */
 842        uint8_t initiator_id;
 843        uint8_t reserved_3;
 844        uint8_t target_id;
 845        __le32 option_flags;
 846        uint8_t status;
 847        uint8_t scsi_status;
 848        uint8_t tag_value;      /* Received queue tag message value */
 849        uint8_t tag_type;       /* Received queue tag message type */
 850        __le32 transfer_length;
 851        __le32 residual;
 852        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 853        __le16 dseg_count;      /* Data segment count. */
 854        __le32 dseg_0_address;  /* Data segment 0 address. */
 855        __le32 dseg_0_length;   /* Data segment 0 length. */
 856        __le32 dseg_1_address;  /* Data segment 1 address. */
 857        __le16 dseg_1_length;   /* Data segment 1 length. */
 858        uint8_t sense_data[18];
 859};
 860
 861/*
 862 * ISP queue - CTIO A64 entry structure definition.
 863 */
 864struct ctio_a64_entry {
 865        uint8_t entry_type;     /* Entry type. */
 866#define CTIO_A64_TYPE 0xF       /* CTIO A64 entry */
 867        uint8_t entry_count;    /* Entry count. */
 868        uint8_t reserved_1;
 869        uint8_t entry_status;   /* Entry Status. */
 870        __le32 reserved_2;
 871        uint8_t lun;            /* SCSI LUN */
 872        uint8_t initiator_id;
 873        uint8_t reserved_3;
 874        uint8_t target_id;
 875        __le32 option_flags;
 876        uint8_t status;
 877        uint8_t scsi_status;
 878        uint8_t tag_value;      /* Received queue tag message value */
 879        uint8_t tag_type;       /* Received queue tag message type */
 880        __le32 transfer_length;
 881        __le32 residual;
 882        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 883        __le16 dseg_count;      /* Data segment count. */
 884        __le32 reserved_4[2];
 885        __le32 dseg_0_address[2];/* Data segment 0 address. */
 886        __le32 dseg_0_length;   /* Data segment 0 length. */
 887        __le32 dseg_1_address[2];/* Data segment 1 address. */
 888        __le32 dseg_1_length;   /* Data segment 1 length. */
 889};
 890
 891/*
 892 * ISP queue - CTIO returned entry structure definition.
 893 */
 894struct ctio_a64_ret_entry {
 895        uint8_t entry_type;     /* Entry type. */
 896#define CTIO_A64_RET_TYPE 0xF   /* CTIO A64 returned entry */
 897        uint8_t entry_count;    /* Entry count. */
 898        uint8_t reserved_1;
 899        uint8_t entry_status;   /* Entry Status. */
 900        __le32 reserved_2;
 901        uint8_t lun;            /* SCSI LUN */
 902        uint8_t initiator_id;
 903        uint8_t reserved_3;
 904        uint8_t target_id;
 905        __le32 option_flags;
 906        uint8_t status;
 907        uint8_t scsi_status;
 908        uint8_t tag_value;      /* Received queue tag message value */
 909        uint8_t tag_type;       /* Received queue tag message type */
 910        __le32 transfer_length;
 911        __le32 residual;
 912        __le16 timeout;         /* 0 = 30 seconds, 0xFFFF = disable */
 913        __le16 dseg_count;      /* Data segment count. */
 914        __le16 reserved_4[7];
 915        uint8_t sense_data[18];
 916};
 917
 918/*
 919 * ISP request and response queue entry sizes
 920 */
 921#define RESPONSE_ENTRY_SIZE     (sizeof(struct response))
 922#define REQUEST_ENTRY_SIZE      (sizeof(request_t))
 923
 924/*
 925 * ISP status entry - completion status definitions.
 926 */
 927#define CS_COMPLETE         0x0 /* No errors */
 928#define CS_INCOMPLETE       0x1 /* Incomplete transfer of cmd. */
 929#define CS_DMA              0x2 /* A DMA direction error. */
 930#define CS_TRANSPORT        0x3 /* Transport error. */
 931#define CS_RESET            0x4 /* SCSI bus reset occurred */
 932#define CS_ABORTED          0x5 /* System aborted command. */
 933#define CS_TIMEOUT          0x6 /* Timeout error. */
 934#define CS_DATA_OVERRUN     0x7 /* Data overrun. */
 935#define CS_COMMAND_OVERRUN  0x8 /* Command Overrun. */
 936#define CS_STATUS_OVERRUN   0x9 /* Status Overrun. */
 937#define CS_BAD_MSG          0xA /* Bad msg after status phase. */
 938#define CS_NO_MSG_OUT       0xB /* No msg out after selection. */
 939#define CS_EXTENDED_ID      0xC /* Extended ID failed. */
 940#define CS_IDE_MSG          0xD /* Target rejected IDE msg. */
 941#define CS_ABORT_MSG        0xE /* Target rejected abort msg. */
 942#define CS_REJECT_MSG       0xF /* Target rejected reject msg. */
 943#define CS_NOP_MSG          0x10        /* Target rejected NOP msg. */
 944#define CS_PARITY_MSG       0x11        /* Target rejected parity msg. */
 945#define CS_DEV_RESET_MSG    0x12        /* Target rejected dev rst msg. */
 946#define CS_ID_MSG           0x13        /* Target rejected ID msg. */
 947#define CS_FREE             0x14        /* Unexpected bus free. */
 948#define CS_DATA_UNDERRUN    0x15        /* Data Underrun. */
 949#define CS_TRANACTION_1     0x18        /* Transaction error 1 */
 950#define CS_TRANACTION_2     0x19        /* Transaction error 2 */
 951#define CS_TRANACTION_3     0x1a        /* Transaction error 3 */
 952#define CS_INV_ENTRY_TYPE   0x1b        /* Invalid entry type */
 953#define CS_DEV_QUEUE_FULL   0x1c        /* Device queue full */
 954#define CS_PHASED_SKIPPED   0x1d        /* SCSI phase skipped */
 955#define CS_ARS_FAILED       0x1e        /* ARS failed */
 956#define CS_LVD_BUS_ERROR    0x21        /* LVD bus error */
 957#define CS_BAD_PAYLOAD      0x80        /* Driver defined */
 958#define CS_UNKNOWN          0x81        /* Driver defined */
 959#define CS_RETRY            0x82        /* Driver defined */
 960
 961/*
 962 * ISP target entries - Option flags bit definitions.
 963 */
 964#define OF_ENABLE_TAG       BIT_1       /* Tagged queue action enable */
 965#define OF_DATA_IN          BIT_6       /* Data in to initiator */
 966                                        /*  (data from target to initiator) */
 967#define OF_DATA_OUT         BIT_7       /* Data out from initiator */
 968                                        /*  (data from initiator to target) */
 969#define OF_NO_DATA          (BIT_7 | BIT_6)
 970#define OF_DISC_DISABLED    BIT_15      /* Disconnects disabled */
 971#define OF_DISABLE_SDP      BIT_24      /* Disable sending save data ptr */
 972#define OF_SEND_RDP         BIT_26      /* Send restore data pointers msg */
 973#define OF_FORCE_DISC       BIT_30      /* Disconnects mandatory */
 974#define OF_SSTS             BIT_31      /* Send SCSI status */
 975
 976
 977/*
 978 * BUS parameters/settings structure - UNUSED
 979 */
 980struct bus_param {
 981        uint8_t id;             /* Host adapter SCSI id */
 982        uint8_t bus_reset_delay;        /* SCSI bus reset delay. */
 983        uint8_t failed_reset_count;     /* number of time reset failed */
 984        uint8_t unused;
 985        uint16_t device_enables;        /* Device enable bits. */
 986        uint16_t lun_disables;  /* LUN disable bits. */
 987        uint16_t qtag_enables;  /* Tag queue enables. */
 988        uint16_t hiwat;         /* High water mark per device. */
 989        uint8_t reset_marker:1;
 990        uint8_t disable_scsi_reset:1;
 991        uint8_t scsi_bus_dead:1;        /* SCSI Bus is Dead, when 5 back to back resets failed */
 992};
 993
 994
 995struct qla_driver_setup {
 996        uint32_t no_sync:1;
 997        uint32_t no_wide:1;
 998        uint32_t no_ppr:1;
 999        uint32_t no_nvram:1;
1000        uint16_t sync_mask;
1001        uint16_t wide_mask;
1002        uint16_t ppr_mask;
1003};
1004
1005
1006/*
1007 * Linux Host Adapter structure
1008 */
1009struct scsi_qla_host {
1010        /* Linux adapter configuration data */
1011        struct Scsi_Host *host; /* pointer to host data */
1012        struct scsi_qla_host *next;
1013        struct device_reg __iomem *iobase;      /* Base Memory-mapped I/O address */
1014
1015        unsigned char __iomem *mmpbase; /* memory mapped address */
1016        unsigned long host_no;
1017        struct pci_dev *pdev;
1018        uint8_t devnum;
1019        uint8_t revision;
1020        uint8_t ports;
1021
1022        unsigned long actthreads;
1023        unsigned long isr_count;        /* Interrupt count */
1024        unsigned long spurious_int;
1025
1026        /* Outstandings ISP commands. */
1027        struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
1028
1029        /* BUS configuration data */
1030        struct bus_param bus_settings[MAX_BUSES];
1031
1032        /* Received ISP mailbox data. */
1033        volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1034
1035        dma_addr_t request_dma;         /* Physical Address */
1036        request_t *request_ring;        /* Base virtual address */
1037        request_t *request_ring_ptr;    /* Current address. */
1038        uint16_t req_ring_index;        /* Current index. */
1039        uint16_t req_q_cnt;             /* Number of available entries. */
1040
1041        dma_addr_t response_dma;        /* Physical address. */
1042        struct response *response_ring; /* Base virtual address */
1043        struct response *response_ring_ptr;     /* Current address. */
1044        uint16_t rsp_ring_index;        /* Current index. */
1045
1046        struct list_head done_q;        /* Done queue */
1047
1048        struct completion *mailbox_wait;
1049        struct timer_list mailbox_timer;
1050
1051        volatile struct {
1052                uint32_t online:1;                      /* 0 */
1053                uint32_t reset_marker:1;                /* 1 */
1054                uint32_t disable_host_adapter:1;        /* 2 */
1055                uint32_t reset_active:1;                /* 3 */
1056                uint32_t abort_isp_active:1;            /* 4 */
1057                uint32_t disable_risc_code_load:1;      /* 5 */
1058        } flags;
1059
1060        struct nvram nvram;
1061        int nvram_valid;
1062
1063        /* Firmware Info */
1064        unsigned short fwstart; /* start address for F/W   */
1065        unsigned char fwver1;   /* F/W version first char  */
1066        unsigned char fwver2;   /* F/W version second char */
1067        unsigned char fwver3;   /* F/W version third char  */
1068};
1069
1070#endif /* _QLA1280_H */
1071